1//===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the ARM VFP instruction set. 10// 11//===----------------------------------------------------------------------===// 12 13def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>; 14def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>, 15 SDTCisSameAs<1, 2>]>; 16def SDT_VMOVRRD : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 17 SDTCisVT<2, f64>]>; 18 19def SDT_VMOVSR : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i32>]>; 20 21def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>; 22def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>; 23def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>; 24def arm_cmpfpe : SDNode<"ARMISD::CMPFPE", SDT_ARMCmp, [SDNPOutGlue]>; 25def arm_cmpfpe0: SDNode<"ARMISD::CMPFPEw0",SDT_CMPFP0, [SDNPOutGlue]>; 26def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>; 27def arm_fmrrd : SDNode<"ARMISD::VMOVRRD", SDT_VMOVRRD>; 28def arm_vmovsr : SDNode<"ARMISD::VMOVSR", SDT_VMOVSR>; 29 30def SDT_VMOVhr : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, i32>] >; 31def SDT_VMOVrh : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisFP<1>] >; 32def arm_vmovhr : SDNode<"ARMISD::VMOVhr", SDT_VMOVhr>; 33def arm_vmovrh : SDNode<"ARMISD::VMOVrh", SDT_VMOVrh>; 34 35//===----------------------------------------------------------------------===// 36// Operand Definitions. 37// 38 39// 8-bit floating-point immediate encodings. 40def FPImmOperand : AsmOperandClass { 41 let Name = "FPImm"; 42 let ParserMethod = "parseFPImm"; 43} 44 45def vfp_f16imm : Operand<f16>, 46 PatLeaf<(f16 fpimm), [{ 47 return ARM_AM::getFP16Imm(N->getValueAPF()) != -1; 48 }], SDNodeXForm<fpimm, [{ 49 APFloat InVal = N->getValueAPF(); 50 uint32_t enc = ARM_AM::getFP16Imm(InVal); 51 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 52 }]>> { 53 let PrintMethod = "printFPImmOperand"; 54 let ParserMatchClass = FPImmOperand; 55} 56 57def vfp_f32f16imm_xform : SDNodeXForm<fpimm, [{ 58 APFloat InVal = N->getValueAPF(); 59 uint32_t enc = ARM_AM::getFP32FP16Imm(InVal); 60 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 61 }]>; 62 63def vfp_f32f16imm : PatLeaf<(f32 fpimm), [{ 64 return ARM_AM::getFP32FP16Imm(N->getValueAPF()) != -1; 65 }], vfp_f32f16imm_xform>; 66 67def vfp_f32imm_xform : SDNodeXForm<fpimm, [{ 68 APFloat InVal = N->getValueAPF(); 69 uint32_t enc = ARM_AM::getFP32Imm(InVal); 70 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 71 }]>; 72 73def gi_vfp_f32imm : GICustomOperandRenderer<"renderVFPF32Imm">, 74 GISDNodeXFormEquiv<vfp_f32imm_xform>; 75 76def vfp_f32imm : Operand<f32>, 77 PatLeaf<(f32 fpimm), [{ 78 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1; 79 }], vfp_f32imm_xform> { 80 let PrintMethod = "printFPImmOperand"; 81 let ParserMatchClass = FPImmOperand; 82 let GISelPredicateCode = [{ 83 const auto &MO = MI.getOperand(1); 84 if (!MO.isFPImm()) 85 return false; 86 return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1; 87 }]; 88} 89 90def vfp_f64imm_xform : SDNodeXForm<fpimm, [{ 91 APFloat InVal = N->getValueAPF(); 92 uint32_t enc = ARM_AM::getFP64Imm(InVal); 93 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 94 }]>; 95 96def gi_vfp_f64imm : GICustomOperandRenderer<"renderVFPF64Imm">, 97 GISDNodeXFormEquiv<vfp_f64imm_xform>; 98 99def vfp_f64imm : Operand<f64>, 100 PatLeaf<(f64 fpimm), [{ 101 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1; 102 }], vfp_f64imm_xform> { 103 let PrintMethod = "printFPImmOperand"; 104 let ParserMatchClass = FPImmOperand; 105 let GISelPredicateCode = [{ 106 const auto &MO = MI.getOperand(1); 107 if (!MO.isFPImm()) 108 return false; 109 return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1; 110 }]; 111} 112 113def alignedload16 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 114 return cast<LoadSDNode>(N)->getAlignment() >= 2; 115}]>; 116 117def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 118 return cast<LoadSDNode>(N)->getAlignment() >= 4; 119}]>; 120 121def alignedstore16 : PatFrag<(ops node:$val, node:$ptr), 122 (store node:$val, node:$ptr), [{ 123 return cast<StoreSDNode>(N)->getAlignment() >= 2; 124}]>; 125 126def alignedstore32 : PatFrag<(ops node:$val, node:$ptr), 127 (store node:$val, node:$ptr), [{ 128 return cast<StoreSDNode>(N)->getAlignment() >= 4; 129}]>; 130 131// The VCVT to/from fixed-point instructions encode the 'fbits' operand 132// (the number of fixed bits) differently than it appears in the assembly 133// source. It's encoded as "Size - fbits" where Size is the size of the 134// fixed-point representation (32 or 16) and fbits is the value appearing 135// in the assembly source, an integer in [0,16] or (0,32], depending on size. 136def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; } 137def fbits32 : Operand<i32> { 138 let PrintMethod = "printFBits32"; 139 let ParserMatchClass = fbits32_asm_operand; 140} 141 142def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; } 143def fbits16 : Operand<i32> { 144 let PrintMethod = "printFBits16"; 145 let ParserMatchClass = fbits16_asm_operand; 146} 147 148//===----------------------------------------------------------------------===// 149// Load / store Instructions. 150// 151 152let canFoldAsLoad = 1, isReMaterializable = 1 in { 153 154def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), 155 IIC_fpLoad64, "vldr", "\t$Dd, $addr", 156 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>, 157 Requires<[HasFPRegs]>; 158 159def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), 160 IIC_fpLoad32, "vldr", "\t$Sd, $addr", 161 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]>, 162 Requires<[HasFPRegs]> { 163 // Some single precision VFP instructions may be executed on both NEON and VFP 164 // pipelines. 165 let D = VFPNeonDomain; 166} 167 168let isUnpredicable = 1 in 169def VLDRH : AHI5<0b1101, 0b01, (outs HPR:$Sd), (ins addrmode5fp16:$addr), 170 IIC_fpLoad16, "vldr", ".16\t$Sd, $addr", 171 [(set HPR:$Sd, (f16 (alignedload16 addrmode5fp16:$addr)))]>, 172 Requires<[HasFPRegs16]>; 173 174} // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in' 175 176def : Pat<(bf16 (alignedload16 addrmode5fp16:$addr)), 177 (VLDRH addrmode5fp16:$addr)> { 178 let Predicates = [HasFPRegs16]; 179} 180def : Pat<(bf16 (alignedload16 addrmode3:$addr)), 181 (COPY_TO_REGCLASS (LDRH addrmode3:$addr), HPR)> { 182 let Predicates = [HasNoFPRegs16, IsARM]; 183} 184def : Pat<(bf16 (alignedload16 t2addrmode_imm12:$addr)), 185 (COPY_TO_REGCLASS (t2LDRHi12 t2addrmode_imm12:$addr), HPR)> { 186 let Predicates = [HasNoFPRegs16, IsThumb]; 187} 188 189def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr), 190 IIC_fpStore64, "vstr", "\t$Dd, $addr", 191 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>, 192 Requires<[HasFPRegs]>; 193 194def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), 195 IIC_fpStore32, "vstr", "\t$Sd, $addr", 196 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]>, 197 Requires<[HasFPRegs]> { 198 // Some single precision VFP instructions may be executed on both NEON and VFP 199 // pipelines. 200 let D = VFPNeonDomain; 201} 202 203let isUnpredicable = 1 in 204def VSTRH : AHI5<0b1101, 0b00, (outs), (ins HPR:$Sd, addrmode5fp16:$addr), 205 IIC_fpStore16, "vstr", ".16\t$Sd, $addr", 206 [(alignedstore16 (f16 HPR:$Sd), addrmode5fp16:$addr)]>, 207 Requires<[HasFPRegs16]>; 208 209def : Pat<(alignedstore16 (bf16 HPR:$Sd), addrmode5fp16:$addr), 210 (VSTRH (bf16 HPR:$Sd), addrmode5fp16:$addr)> { 211 let Predicates = [HasFPRegs16]; 212} 213def : Pat<(alignedstore16 (bf16 HPR:$Sd), addrmode3:$addr), 214 (STRH (COPY_TO_REGCLASS $Sd, GPR), addrmode3:$addr)> { 215 let Predicates = [HasNoFPRegs16, IsARM]; 216} 217def : Pat<(alignedstore16 (bf16 HPR:$Sd), t2addrmode_imm12:$addr), 218 (t2STRHi12 (COPY_TO_REGCLASS $Sd, GPR), t2addrmode_imm12:$addr)> { 219 let Predicates = [HasNoFPRegs16, IsThumb]; 220} 221 222//===----------------------------------------------------------------------===// 223// Load / store multiple Instructions. 224// 225 226multiclass vfp_ldst_mult<string asm, bit L_bit, 227 InstrItinClass itin, InstrItinClass itin_upd> { 228 let Predicates = [HasFPRegs] in { 229 // Double Precision 230 def DIA : 231 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 232 IndexModeNone, itin, 233 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 234 let Inst{24-23} = 0b01; // Increment After 235 let Inst{21} = 0; // No writeback 236 let Inst{20} = L_bit; 237 } 238 def DIA_UPD : 239 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 240 variable_ops), 241 IndexModeUpd, itin_upd, 242 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 243 let Inst{24-23} = 0b01; // Increment After 244 let Inst{21} = 1; // Writeback 245 let Inst{20} = L_bit; 246 } 247 def DDB_UPD : 248 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 249 variable_ops), 250 IndexModeUpd, itin_upd, 251 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 252 let Inst{24-23} = 0b10; // Decrement Before 253 let Inst{21} = 1; // Writeback 254 let Inst{20} = L_bit; 255 } 256 257 // Single Precision 258 def SIA : 259 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops), 260 IndexModeNone, itin, 261 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 262 let Inst{24-23} = 0b01; // Increment After 263 let Inst{21} = 0; // No writeback 264 let Inst{20} = L_bit; 265 266 // Some single precision VFP instructions may be executed on both NEON and 267 // VFP pipelines. 268 let D = VFPNeonDomain; 269 } 270 def SIA_UPD : 271 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 272 variable_ops), 273 IndexModeUpd, itin_upd, 274 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 275 let Inst{24-23} = 0b01; // Increment After 276 let Inst{21} = 1; // Writeback 277 let Inst{20} = L_bit; 278 279 // Some single precision VFP instructions may be executed on both NEON and 280 // VFP pipelines. 281 let D = VFPNeonDomain; 282 } 283 def SDB_UPD : 284 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 285 variable_ops), 286 IndexModeUpd, itin_upd, 287 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 288 let Inst{24-23} = 0b10; // Decrement Before 289 let Inst{21} = 1; // Writeback 290 let Inst{20} = L_bit; 291 292 // Some single precision VFP instructions may be executed on both NEON and 293 // VFP pipelines. 294 let D = VFPNeonDomain; 295 } 296 } 297} 298 299let hasSideEffects = 0 in { 300 301let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 302defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>; 303 304let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 305defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>; 306 307} // hasSideEffects 308 309def : MnemonicAlias<"vldm", "vldmia">; 310def : MnemonicAlias<"vstm", "vstmia">; 311 312 313//===----------------------------------------------------------------------===// 314// Lazy load / store multiple Instructions 315// 316def VLLDM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone, 317 NoItinerary, "vlldm${p}\t$Rn", "", []>, 318 Requires<[HasV8MMainline, Has8MSecExt]> { 319 let Inst{24-23} = 0b00; 320 let Inst{22} = 0; 321 let Inst{21} = 1; 322 let Inst{20} = 1; 323 let Inst{15-12} = 0; 324 let Inst{7-0} = 0; 325 let mayLoad = 1; 326 let Defs = [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, VPR, FPSCR, FPSCR_NZCV]; 327} 328 329def VLSTM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone, 330 NoItinerary, "vlstm${p}\t$Rn", "", []>, 331 Requires<[HasV8MMainline, Has8MSecExt]> { 332 let Inst{24-23} = 0b00; 333 let Inst{22} = 0; 334 let Inst{21} = 1; 335 let Inst{20} = 0; 336 let Inst{15-12} = 0; 337 let Inst{7-0} = 0; 338 let mayStore = 1; 339} 340 341def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r), 0>, 342 Requires<[HasFPRegs]>; 343def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r), 0>, 344 Requires<[HasFPRegs]>; 345def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r), 0>, 346 Requires<[HasFPRegs]>; 347def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r), 0>, 348 Requires<[HasFPRegs]>; 349defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 350 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>; 351defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 352 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>; 353defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 354 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>; 355defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 356 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>; 357 358// FLDMX, FSTMX - Load and store multiple unknown precision registers for 359// pre-armv6 cores. 360// These instruction are deprecated so we don't want them to get selected. 361// However, there is no UAL syntax for them, so we keep them around for 362// (dis)assembly only. 363multiclass vfp_ldstx_mult<string asm, bit L_bit> { 364 let Predicates = [HasFPRegs], hasNoSchedulingInfo = 1 in { 365 // Unknown precision 366 def XIA : 367 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 368 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> { 369 let Inst{24-23} = 0b01; // Increment After 370 let Inst{21} = 0; // No writeback 371 let Inst{20} = L_bit; 372 } 373 def XIA_UPD : 374 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 375 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 376 let Inst{24-23} = 0b01; // Increment After 377 let Inst{21} = 1; // Writeback 378 let Inst{20} = L_bit; 379 } 380 def XDB_UPD : 381 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 382 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 383 let Inst{24-23} = 0b10; // Decrement Before 384 let Inst{21} = 1; // Writeback 385 let Inst{20} = L_bit; 386 } 387 } 388} 389 390defm FLDM : vfp_ldstx_mult<"fldm", 1>; 391defm FSTM : vfp_ldstx_mult<"fstm", 0>; 392 393def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">; 394def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">; 395 396def : VFP2MnemonicAlias<"fstmeax", "fstmiax">; 397def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">; 398 399//===----------------------------------------------------------------------===// 400// FP Binary Operations. 401// 402 403let TwoOperandAliasConstraint = "$Dn = $Dd" in 404def VADDD : ADbI<0b11100, 0b11, 0, 0, 405 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 406 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", 407 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>, 408 Sched<[WriteFPALU64]>; 409 410let TwoOperandAliasConstraint = "$Sn = $Sd" in 411def VADDS : ASbIn<0b11100, 0b11, 0, 0, 412 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 413 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", 414 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>, 415 Sched<[WriteFPALU32]> { 416 // Some single precision VFP instructions may be executed on both NEON and 417 // VFP pipelines on A8. 418 let D = VFPNeonA8Domain; 419} 420 421let TwoOperandAliasConstraint = "$Sn = $Sd" in 422def VADDH : AHbI<0b11100, 0b11, 0, 0, 423 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 424 IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm", 425 [(set (f16 HPR:$Sd), (fadd (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, 426 Sched<[WriteFPALU32]>; 427 428let TwoOperandAliasConstraint = "$Dn = $Dd" in 429def VSUBD : ADbI<0b11100, 0b11, 1, 0, 430 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 431 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", 432 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>, 433 Sched<[WriteFPALU64]>; 434 435let TwoOperandAliasConstraint = "$Sn = $Sd" in 436def VSUBS : ASbIn<0b11100, 0b11, 1, 0, 437 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 438 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", 439 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>, 440 Sched<[WriteFPALU32]>{ 441 // Some single precision VFP instructions may be executed on both NEON and 442 // VFP pipelines on A8. 443 let D = VFPNeonA8Domain; 444} 445 446let TwoOperandAliasConstraint = "$Sn = $Sd" in 447def VSUBH : AHbI<0b11100, 0b11, 1, 0, 448 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 449 IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm", 450 [(set (f16 HPR:$Sd), (fsub (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, 451 Sched<[WriteFPALU32]>; 452 453let TwoOperandAliasConstraint = "$Dn = $Dd" in 454def VDIVD : ADbI<0b11101, 0b00, 0, 0, 455 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 456 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", 457 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>, 458 Sched<[WriteFPDIV64]>; 459 460let TwoOperandAliasConstraint = "$Sn = $Sd" in 461def VDIVS : ASbI<0b11101, 0b00, 0, 0, 462 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 463 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm", 464 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>, 465 Sched<[WriteFPDIV32]>; 466 467let TwoOperandAliasConstraint = "$Sn = $Sd" in 468def VDIVH : AHbI<0b11101, 0b00, 0, 0, 469 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 470 IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm", 471 [(set (f16 HPR:$Sd), (fdiv (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, 472 Sched<[WriteFPDIV32]>; 473 474let TwoOperandAliasConstraint = "$Dn = $Dd" in 475def VMULD : ADbI<0b11100, 0b10, 0, 0, 476 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 477 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm", 478 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>, 479 Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>; 480 481let TwoOperandAliasConstraint = "$Sn = $Sd" in 482def VMULS : ASbIn<0b11100, 0b10, 0, 0, 483 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 484 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm", 485 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>, 486 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]> { 487 // Some single precision VFP instructions may be executed on both NEON and 488 // VFP pipelines on A8. 489 let D = VFPNeonA8Domain; 490} 491 492let TwoOperandAliasConstraint = "$Sn = $Sd" in 493def VMULH : AHbI<0b11100, 0b10, 0, 0, 494 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 495 IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm", 496 [(set (f16 HPR:$Sd), (fmul (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, 497 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>; 498 499def VNMULD : ADbI<0b11100, 0b10, 1, 0, 500 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 501 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm", 502 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>, 503 Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>; 504 505def VNMULS : ASbI<0b11100, 0b10, 1, 0, 506 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 507 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm", 508 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>, 509 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]> { 510 // Some single precision VFP instructions may be executed on both NEON and 511 // VFP pipelines on A8. 512 let D = VFPNeonA8Domain; 513} 514 515def VNMULH : AHbI<0b11100, 0b10, 1, 0, 516 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 517 IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm", 518 [(set (f16 HPR:$Sd), (fneg (fmul (f16 HPR:$Sn), (f16 HPR:$Sm))))]>, 519 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>; 520 521multiclass vsel_inst<string op, bits<2> opc, int CC> { 522 let DecoderNamespace = "VFPV8", PostEncoderMethod = "", 523 Uses = [CPSR], AddedComplexity = 4, isUnpredicable = 1 in { 524 def H : AHbInp<0b11100, opc, 0, 525 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 526 NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"), 527 [(set (f16 HPR:$Sd), (ARMcmov (f16 HPR:$Sm), (f16 HPR:$Sn), CC))]>, 528 Requires<[HasFullFP16]>; 529 530 def S : ASbInp<0b11100, opc, 0, 531 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 532 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"), 533 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>, 534 Requires<[HasFPARMv8]>; 535 536 def D : ADbInp<0b11100, opc, 0, 537 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 538 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"), 539 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>, 540 Requires<[HasFPARMv8, HasDPVFP]>; 541 } 542} 543 544// The CC constants here match ARMCC::CondCodes. 545defm VSELGT : vsel_inst<"gt", 0b11, 12>; 546defm VSELGE : vsel_inst<"ge", 0b10, 10>; 547defm VSELEQ : vsel_inst<"eq", 0b00, 0>; 548defm VSELVS : vsel_inst<"vs", 0b01, 6>; 549 550multiclass vmaxmin_inst<string op, bit opc, SDNode SD> { 551 let DecoderNamespace = "VFPV8", PostEncoderMethod = "", 552 isUnpredicable = 1 in { 553 def H : AHbInp<0b11101, 0b00, opc, 554 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 555 NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"), 556 [(set (f16 HPR:$Sd), (SD (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, 557 Requires<[HasFullFP16]>; 558 559 def S : ASbInp<0b11101, 0b00, opc, 560 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 561 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"), 562 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>, 563 Requires<[HasFPARMv8]>; 564 565 def D : ADbInp<0b11101, 0b00, opc, 566 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 567 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"), 568 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>, 569 Requires<[HasFPARMv8, HasDPVFP]>; 570 } 571} 572 573defm VFP_VMAXNM : vmaxmin_inst<"vmaxnm", 0, fmaxnum>; 574defm VFP_VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>; 575 576// Match reassociated forms only if not sign dependent rounding. 577def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)), 578 (VNMULD DPR:$a, DPR:$b)>, 579 Requires<[NoHonorSignDependentRounding,HasDPVFP]>; 580def : Pat<(fmul (fneg SPR:$a), SPR:$b), 581 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>; 582 583// These are encoded as unary instructions. 584let Defs = [FPSCR_NZCV] in { 585def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, 586 (outs), (ins DPR:$Dd, DPR:$Dm), 587 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", 588 [(arm_cmpfpe DPR:$Dd, (f64 DPR:$Dm))]>; 589 590def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, 591 (outs), (ins SPR:$Sd, SPR:$Sm), 592 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", 593 [(arm_cmpfpe SPR:$Sd, SPR:$Sm)]> { 594 // Some single precision VFP instructions may be executed on both NEON and 595 // VFP pipelines on A8. 596 let D = VFPNeonA8Domain; 597} 598 599def VCMPEH : AHuI<0b11101, 0b11, 0b0100, 0b11, 0, 600 (outs), (ins HPR:$Sd, HPR:$Sm), 601 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm", 602 [(arm_cmpfpe (f16 HPR:$Sd), (f16 HPR:$Sm))]>; 603 604def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, 605 (outs), (ins DPR:$Dd, DPR:$Dm), 606 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", 607 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>; 608 609def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, 610 (outs), (ins SPR:$Sd, SPR:$Sm), 611 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", 612 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> { 613 // Some single precision VFP instructions may be executed on both NEON and 614 // VFP pipelines on A8. 615 let D = VFPNeonA8Domain; 616} 617 618def VCMPH : AHuI<0b11101, 0b11, 0b0100, 0b01, 0, 619 (outs), (ins HPR:$Sd, HPR:$Sm), 620 IIC_fpCMP16, "vcmp", ".f16\t$Sd, $Sm", 621 [(arm_cmpfp (f16 HPR:$Sd), (f16 HPR:$Sm))]>; 622} // Defs = [FPSCR_NZCV] 623 624//===----------------------------------------------------------------------===// 625// FP Unary Operations. 626// 627 628def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, 629 (outs DPR:$Dd), (ins DPR:$Dm), 630 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm", 631 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>; 632 633def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0, 634 (outs SPR:$Sd), (ins SPR:$Sm), 635 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm", 636 [(set SPR:$Sd, (fabs SPR:$Sm))]> { 637 // Some single precision VFP instructions may be executed on both NEON and 638 // VFP pipelines on A8. 639 let D = VFPNeonA8Domain; 640} 641 642def VABSH : AHuI<0b11101, 0b11, 0b0000, 0b11, 0, 643 (outs HPR:$Sd), (ins HPR:$Sm), 644 IIC_fpUNA16, "vabs", ".f16\t$Sd, $Sm", 645 [(set (f16 HPR:$Sd), (fabs (f16 HPR:$Sm)))]>; 646 647let Defs = [FPSCR_NZCV] in { 648def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, 649 (outs), (ins DPR:$Dd), 650 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", 651 [(arm_cmpfpe0 (f64 DPR:$Dd))]> { 652 let Inst{3-0} = 0b0000; 653 let Inst{5} = 0; 654} 655 656def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, 657 (outs), (ins SPR:$Sd), 658 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", 659 [(arm_cmpfpe0 SPR:$Sd)]> { 660 let Inst{3-0} = 0b0000; 661 let Inst{5} = 0; 662 663 // Some single precision VFP instructions may be executed on both NEON and 664 // VFP pipelines on A8. 665 let D = VFPNeonA8Domain; 666} 667 668def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0, 669 (outs), (ins HPR:$Sd), 670 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, #0", 671 [(arm_cmpfpe0 (f16 HPR:$Sd))]> { 672 let Inst{3-0} = 0b0000; 673 let Inst{5} = 0; 674} 675 676def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, 677 (outs), (ins DPR:$Dd), 678 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", 679 [(arm_cmpfp0 (f64 DPR:$Dd))]> { 680 let Inst{3-0} = 0b0000; 681 let Inst{5} = 0; 682} 683 684def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, 685 (outs), (ins SPR:$Sd), 686 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", 687 [(arm_cmpfp0 SPR:$Sd)]> { 688 let Inst{3-0} = 0b0000; 689 let Inst{5} = 0; 690 691 // Some single precision VFP instructions may be executed on both NEON and 692 // VFP pipelines on A8. 693 let D = VFPNeonA8Domain; 694} 695 696def VCMPZH : AHuI<0b11101, 0b11, 0b0101, 0b01, 0, 697 (outs), (ins HPR:$Sd), 698 IIC_fpCMP16, "vcmp", ".f16\t$Sd, #0", 699 [(arm_cmpfp0 (f16 HPR:$Sd))]> { 700 let Inst{3-0} = 0b0000; 701 let Inst{5} = 0; 702} 703} // Defs = [FPSCR_NZCV] 704 705def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, 706 (outs DPR:$Dd), (ins SPR:$Sm), 707 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm", 708 [(set DPR:$Dd, (fpextend SPR:$Sm))]>, 709 Sched<[WriteFPCVT]> { 710 // Instruction operands. 711 bits<5> Dd; 712 bits<5> Sm; 713 714 // Encode instruction operands. 715 let Inst{3-0} = Sm{4-1}; 716 let Inst{5} = Sm{0}; 717 let Inst{15-12} = Dd{3-0}; 718 let Inst{22} = Dd{4}; 719 720 let Predicates = [HasVFP2, HasDPVFP]; 721 let hasSideEffects = 0; 722} 723 724// Special case encoding: bits 11-8 is 0b1011. 725def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm, 726 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", 727 [(set SPR:$Sd, (fpround DPR:$Dm))]>, 728 Sched<[WriteFPCVT]> { 729 // Instruction operands. 730 bits<5> Sd; 731 bits<5> Dm; 732 733 // Encode instruction operands. 734 let Inst{3-0} = Dm{3-0}; 735 let Inst{5} = Dm{4}; 736 let Inst{15-12} = Sd{4-1}; 737 let Inst{22} = Sd{0}; 738 739 let Inst{27-23} = 0b11101; 740 let Inst{21-16} = 0b110111; 741 let Inst{11-8} = 0b1011; 742 let Inst{7-6} = 0b11; 743 let Inst{4} = 0; 744 745 let Predicates = [HasVFP2, HasDPVFP]; 746 let hasSideEffects = 0; 747} 748 749// Between half, single and double-precision. 750let hasSideEffects = 0 in 751def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 752 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", 753 [/* Intentionally left blank, see patterns below */]>, 754 Requires<[HasFP16]>, 755 Sched<[WriteFPCVT]>; 756 757def : FP16Pat<(f32 (fpextend (f16 HPR:$Sm))), 758 (VCVTBHS (COPY_TO_REGCLASS (f16 HPR:$Sm), SPR))>; 759def : FP16Pat<(f16_to_fp GPR:$a), 760 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; 761 762let hasSideEffects = 0 in 763def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 764 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", 765 [/* Intentionally left blank, see patterns below */]>, 766 Requires<[HasFP16]>, 767 Sched<[WriteFPCVT]>; 768 769def : FP16Pat<(f16 (fpround SPR:$Sm)), 770 (COPY_TO_REGCLASS (VCVTBSH SPR:$Sm), HPR)>; 771def : FP16Pat<(fp_to_f16 SPR:$a), 772 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>; 773def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane), 774 (v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1), (VCVTBSH SPR:$src2), 775 (SSubReg_f16_reg imm:$lane)))>; 776def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane), 777 (v4f16 (INSERT_SUBREG (v4f16 DPR:$src1), (VCVTBSH SPR:$src2), 778 (SSubReg_f16_reg imm:$lane)))>; 779 780let hasSideEffects = 0 in 781def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 782 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", 783 [/* Intentionally left blank, see patterns below */]>, 784 Requires<[HasFP16]>, 785 Sched<[WriteFPCVT]>; 786 787def : FP16Pat<(f32 (fpextend (extractelt (v8f16 MQPR:$src), imm_odd:$lane))), 788 (VCVTTHS (EXTRACT_SUBREG MQPR:$src, (SSubReg_f16_reg imm_odd:$lane)))>; 789def : FP16Pat<(f32 (fpextend (extractelt (v4f16 DPR:$src), imm_odd:$lane))), 790 (VCVTTHS (EXTRACT_SUBREG 791 (v2f32 (COPY_TO_REGCLASS (v4f16 DPR:$src), DPR_VFP2)), 792 (SSubReg_f16_reg imm_odd:$lane)))>; 793 794let hasSideEffects = 0 in 795def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 796 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", 797 [/* Intentionally left blank, see patterns below */]>, 798 Requires<[HasFP16]>, 799 Sched<[WriteFPCVT]>; 800 801def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane), 802 (v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1), (VCVTTSH SPR:$src2), 803 (SSubReg_f16_reg imm:$lane)))>; 804def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane), 805 (v4f16 (INSERT_SUBREG (v4f16 DPR:$src1), (VCVTTSH SPR:$src2), 806 (SSubReg_f16_reg imm:$lane)))>; 807 808def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0, 809 (outs DPR:$Dd), (ins SPR:$Sm), 810 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm", 811 [/* Intentionally left blank, see patterns below */]>, 812 Requires<[HasFPARMv8, HasDPVFP]>, 813 Sched<[WriteFPCVT]> { 814 // Instruction operands. 815 bits<5> Sm; 816 817 // Encode instruction operands. 818 let Inst{3-0} = Sm{4-1}; 819 let Inst{5} = Sm{0}; 820 821 let hasSideEffects = 0; 822} 823 824def : FullFP16Pat<(f64 (fpextend (f16 HPR:$Sm))), 825 (VCVTBHD (COPY_TO_REGCLASS (f16 HPR:$Sm), SPR))>, 826 Requires<[HasFPARMv8, HasDPVFP]>; 827def : FP16Pat<(f64 (f16_to_fp GPR:$a)), 828 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>, 829 Requires<[HasFPARMv8, HasDPVFP]>; 830 831def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0, 832 (outs SPR:$Sd), (ins DPR:$Dm), 833 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm", 834 [/* Intentionally left blank, see patterns below */]>, 835 Requires<[HasFPARMv8, HasDPVFP]> { 836 // Instruction operands. 837 bits<5> Sd; 838 bits<5> Dm; 839 840 // Encode instruction operands. 841 let Inst{3-0} = Dm{3-0}; 842 let Inst{5} = Dm{4}; 843 let Inst{15-12} = Sd{4-1}; 844 let Inst{22} = Sd{0}; 845 846 let hasSideEffects = 0; 847} 848 849def : FullFP16Pat<(f16 (fpround DPR:$Dm)), 850 (COPY_TO_REGCLASS (VCVTBDH DPR:$Dm), HPR)>, 851 Requires<[HasFPARMv8, HasDPVFP]>; 852def : FP16Pat<(fp_to_f16 (f64 DPR:$a)), 853 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>, 854 Requires<[HasFPARMv8, HasDPVFP]>; 855 856def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0, 857 (outs DPR:$Dd), (ins SPR:$Sm), 858 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm", 859 []>, Requires<[HasFPARMv8, HasDPVFP]> { 860 // Instruction operands. 861 bits<5> Sm; 862 863 // Encode instruction operands. 864 let Inst{3-0} = Sm{4-1}; 865 let Inst{5} = Sm{0}; 866 867 let hasSideEffects = 0; 868} 869 870def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0, 871 (outs SPR:$Sd), (ins DPR:$Dm), 872 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm", 873 []>, Requires<[HasFPARMv8, HasDPVFP]> { 874 // Instruction operands. 875 bits<5> Sd; 876 bits<5> Dm; 877 878 // Encode instruction operands. 879 let Inst{15-12} = Sd{4-1}; 880 let Inst{22} = Sd{0}; 881 let Inst{3-0} = Dm{3-0}; 882 let Inst{5} = Dm{4}; 883 884 let hasSideEffects = 0; 885} 886 887multiclass vcvt_inst<string opc, bits<2> rm, 888 SDPatternOperator node = null_frag> { 889 let PostEncoderMethod = "", DecoderNamespace = "VFPV8", hasSideEffects = 0 in { 890 def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0, 891 (outs SPR:$Sd), (ins HPR:$Sm), 892 NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"), 893 []>, 894 Requires<[HasFullFP16]> { 895 let Inst{17-16} = rm; 896 } 897 898 def UH : AHuInp<0b11101, 0b11, 0b1100, 0b01, 0, 899 (outs SPR:$Sd), (ins HPR:$Sm), 900 NoItinerary, !strconcat("vcvt", opc, ".u32.f16\t$Sd, $Sm"), 901 []>, 902 Requires<[HasFullFP16]> { 903 let Inst{17-16} = rm; 904 } 905 906 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, 907 (outs SPR:$Sd), (ins SPR:$Sm), 908 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"), 909 []>, 910 Requires<[HasFPARMv8]> { 911 let Inst{17-16} = rm; 912 } 913 914 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, 915 (outs SPR:$Sd), (ins SPR:$Sm), 916 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"), 917 []>, 918 Requires<[HasFPARMv8]> { 919 let Inst{17-16} = rm; 920 } 921 922 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, 923 (outs SPR:$Sd), (ins DPR:$Dm), 924 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"), 925 []>, 926 Requires<[HasFPARMv8, HasDPVFP]> { 927 bits<5> Dm; 928 929 let Inst{17-16} = rm; 930 931 // Encode instruction operands. 932 let Inst{3-0} = Dm{3-0}; 933 let Inst{5} = Dm{4}; 934 let Inst{8} = 1; 935 } 936 937 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, 938 (outs SPR:$Sd), (ins DPR:$Dm), 939 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"), 940 []>, 941 Requires<[HasFPARMv8, HasDPVFP]> { 942 bits<5> Dm; 943 944 let Inst{17-16} = rm; 945 946 // Encode instruction operands 947 let Inst{3-0} = Dm{3-0}; 948 let Inst{5} = Dm{4}; 949 let Inst{8} = 1; 950 } 951 } 952 953 let Predicates = [HasFPARMv8] in { 954 let Predicates = [HasFullFP16] in { 955 def : Pat<(i32 (fp_to_sint (node (f16 HPR:$a)))), 956 (COPY_TO_REGCLASS 957 (!cast<Instruction>(NAME#"SH") (f16 HPR:$a)), 958 GPR)>; 959 960 def : Pat<(i32 (fp_to_uint (node (f16 HPR:$a)))), 961 (COPY_TO_REGCLASS 962 (!cast<Instruction>(NAME#"UH") (f16 HPR:$a)), 963 GPR)>; 964 } 965 def : Pat<(i32 (fp_to_sint (node SPR:$a))), 966 (COPY_TO_REGCLASS 967 (!cast<Instruction>(NAME#"SS") SPR:$a), 968 GPR)>; 969 def : Pat<(i32 (fp_to_uint (node SPR:$a))), 970 (COPY_TO_REGCLASS 971 (!cast<Instruction>(NAME#"US") SPR:$a), 972 GPR)>; 973 } 974 let Predicates = [HasFPARMv8, HasDPVFP] in { 975 def : Pat<(i32 (fp_to_sint (node (f64 DPR:$a)))), 976 (COPY_TO_REGCLASS 977 (!cast<Instruction>(NAME#"SD") DPR:$a), 978 GPR)>; 979 def : Pat<(i32 (fp_to_uint (node (f64 DPR:$a)))), 980 (COPY_TO_REGCLASS 981 (!cast<Instruction>(NAME#"UD") DPR:$a), 982 GPR)>; 983 } 984} 985 986defm VCVTA : vcvt_inst<"a", 0b00, fround>; 987defm VCVTN : vcvt_inst<"n", 0b01>; 988defm VCVTP : vcvt_inst<"p", 0b10, fceil>; 989defm VCVTM : vcvt_inst<"m", 0b11, ffloor>; 990 991def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, 992 (outs DPR:$Dd), (ins DPR:$Dm), 993 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", 994 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>; 995 996def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0, 997 (outs SPR:$Sd), (ins SPR:$Sm), 998 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", 999 [(set SPR:$Sd, (fneg SPR:$Sm))]> { 1000 // Some single precision VFP instructions may be executed on both NEON and 1001 // VFP pipelines on A8. 1002 let D = VFPNeonA8Domain; 1003} 1004 1005def VNEGH : AHuI<0b11101, 0b11, 0b0001, 0b01, 0, 1006 (outs HPR:$Sd), (ins HPR:$Sm), 1007 IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm", 1008 [(set (f16 HPR:$Sd), (fneg (f16 HPR:$Sm)))]>; 1009 1010multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> { 1011 def H : AHuI<0b11101, 0b11, 0b0110, 0b11, 0, 1012 (outs HPR:$Sd), (ins HPR:$Sm), 1013 NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm", 1014 [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>, 1015 Requires<[HasFullFP16]> { 1016 let Inst{7} = op2; 1017 let Inst{16} = op; 1018 } 1019 1020 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0, 1021 (outs SPR:$Sd), (ins SPR:$Sm), 1022 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm", 1023 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>, 1024 Requires<[HasFPARMv8]> { 1025 let Inst{7} = op2; 1026 let Inst{16} = op; 1027 } 1028 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0, 1029 (outs DPR:$Dd), (ins DPR:$Dm), 1030 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm", 1031 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>, 1032 Requires<[HasFPARMv8, HasDPVFP]> { 1033 let Inst{7} = op2; 1034 let Inst{16} = op; 1035 } 1036 1037 def : InstAlias<!strconcat("vrint", opc, "$p.f16.f16\t$Sd, $Sm"), 1038 (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>, 1039 Requires<[HasFullFP16]>; 1040 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"), 1041 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p), 0>, 1042 Requires<[HasFPARMv8]>; 1043 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"), 1044 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p), 0>, 1045 Requires<[HasFPARMv8,HasDPVFP]>; 1046} 1047 1048defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc>; 1049defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint>; 1050defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>; 1051 1052multiclass vrint_inst_anpm<string opc, bits<2> rm, 1053 SDPatternOperator node = null_frag> { 1054 let PostEncoderMethod = "", DecoderNamespace = "VFPV8", 1055 isUnpredicable = 1 in { 1056 def H : AHuInp<0b11101, 0b11, 0b1000, 0b01, 0, 1057 (outs HPR:$Sd), (ins HPR:$Sm), 1058 NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"), 1059 [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>, 1060 Requires<[HasFullFP16]> { 1061 let Inst{17-16} = rm; 1062 } 1063 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0, 1064 (outs SPR:$Sd), (ins SPR:$Sm), 1065 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"), 1066 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>, 1067 Requires<[HasFPARMv8]> { 1068 let Inst{17-16} = rm; 1069 } 1070 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0, 1071 (outs DPR:$Dd), (ins DPR:$Dm), 1072 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"), 1073 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>, 1074 Requires<[HasFPARMv8, HasDPVFP]> { 1075 let Inst{17-16} = rm; 1076 } 1077 } 1078 1079 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"), 1080 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>, 1081 Requires<[HasFPARMv8]>; 1082 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"), 1083 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm), 0>, 1084 Requires<[HasFPARMv8,HasDPVFP]>; 1085} 1086 1087defm VRINTA : vrint_inst_anpm<"a", 0b00, fround>; 1088defm VRINTN : vrint_inst_anpm<"n", 0b01, int_arm_neon_vrintn>; 1089defm VRINTP : vrint_inst_anpm<"p", 0b10, fceil>; 1090defm VRINTM : vrint_inst_anpm<"m", 0b11, ffloor>; 1091 1092def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, 1093 (outs DPR:$Dd), (ins DPR:$Dm), 1094 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", 1095 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>, 1096 Sched<[WriteFPSQRT64]>; 1097 1098def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, 1099 (outs SPR:$Sd), (ins SPR:$Sm), 1100 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", 1101 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>, 1102 Sched<[WriteFPSQRT32]>; 1103 1104def VSQRTH : AHuI<0b11101, 0b11, 0b0001, 0b11, 0, 1105 (outs HPR:$Sd), (ins HPR:$Sm), 1106 IIC_fpSQRT16, "vsqrt", ".f16\t$Sd, $Sm", 1107 [(set (f16 HPR:$Sd), (fsqrt (f16 HPR:$Sm)))]>; 1108 1109let hasSideEffects = 0 in { 1110let isMoveReg = 1 in { 1111def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0, 1112 (outs DPR:$Dd), (ins DPR:$Dm), 1113 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>, 1114 Requires<[HasFPRegs64]>; 1115 1116def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0, 1117 (outs SPR:$Sd), (ins SPR:$Sm), 1118 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>, 1119 Requires<[HasFPRegs]>; 1120} // isMoveReg 1121 1122let PostEncoderMethod = "", DecoderNamespace = "VFPV8", isUnpredicable = 1 in { 1123def VMOVH : ASuInp<0b11101, 0b11, 0b0000, 0b01, 0, 1124 (outs SPR:$Sd), (ins SPR:$Sm), 1125 IIC_fpUNA16, "vmovx.f16\t$Sd, $Sm", []>, 1126 Requires<[HasFullFP16]>; 1127 1128def VINSH : ASuInp<0b11101, 0b11, 0b0000, 0b11, 0, 1129 (outs SPR:$Sd), (ins SPR:$Sm), 1130 IIC_fpUNA16, "vins.f16\t$Sd, $Sm", []>, 1131 Requires<[HasFullFP16]>; 1132} // PostEncoderMethod 1133} // hasSideEffects 1134 1135//===----------------------------------------------------------------------===// 1136// FP <-> GPR Copies. Int <-> FP Conversions. 1137// 1138 1139let isMoveReg = 1 in { 1140def VMOVRS : AVConv2I<0b11100001, 0b1010, 1141 (outs GPR:$Rt), (ins SPR:$Sn), 1142 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn", 1143 [(set GPR:$Rt, (bitconvert SPR:$Sn))]>, 1144 Requires<[HasFPRegs]>, 1145 Sched<[WriteFPMOV]> { 1146 // Instruction operands. 1147 bits<4> Rt; 1148 bits<5> Sn; 1149 1150 // Encode instruction operands. 1151 let Inst{19-16} = Sn{4-1}; 1152 let Inst{7} = Sn{0}; 1153 let Inst{15-12} = Rt; 1154 1155 let Inst{6-5} = 0b00; 1156 let Inst{3-0} = 0b0000; 1157 1158 // Some single precision VFP instructions may be executed on both NEON and VFP 1159 // pipelines. 1160 let D = VFPNeonDomain; 1161} 1162 1163// Bitcast i32 -> f32. NEON prefers to use VMOVDRR. 1164def VMOVSR : AVConv4I<0b11100000, 0b1010, 1165 (outs SPR:$Sn), (ins GPR:$Rt), 1166 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt", 1167 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>, 1168 Requires<[HasFPRegs, UseVMOVSR]>, 1169 Sched<[WriteFPMOV]> { 1170 // Instruction operands. 1171 bits<5> Sn; 1172 bits<4> Rt; 1173 1174 // Encode instruction operands. 1175 let Inst{19-16} = Sn{4-1}; 1176 let Inst{7} = Sn{0}; 1177 let Inst{15-12} = Rt; 1178 1179 let Inst{6-5} = 0b00; 1180 let Inst{3-0} = 0b0000; 1181 1182 // Some single precision VFP instructions may be executed on both NEON and VFP 1183 // pipelines. 1184 let D = VFPNeonDomain; 1185} 1186} // isMoveReg 1187def : Pat<(arm_vmovsr GPR:$Rt), (VMOVSR GPR:$Rt)>, Requires<[HasVFP2, UseVMOVSR]>; 1188 1189let hasSideEffects = 0 in { 1190def VMOVRRD : AVConv3I<0b11000101, 0b1011, 1191 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm), 1192 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm", 1193 [(set GPR:$Rt, GPR:$Rt2, (arm_fmrrd DPR:$Dm))]>, 1194 Requires<[HasFPRegs]>, 1195 Sched<[WriteFPMOV]> { 1196 // Instruction operands. 1197 bits<5> Dm; 1198 bits<4> Rt; 1199 bits<4> Rt2; 1200 1201 // Encode instruction operands. 1202 let Inst{3-0} = Dm{3-0}; 1203 let Inst{5} = Dm{4}; 1204 let Inst{15-12} = Rt; 1205 let Inst{19-16} = Rt2; 1206 1207 let Inst{7-6} = 0b00; 1208 1209 // Some single precision VFP instructions may be executed on both NEON and VFP 1210 // pipelines. 1211 let D = VFPNeonDomain; 1212 1213 // This instruction is equivalent to 1214 // $Rt = EXTRACT_SUBREG $Dm, ssub_0 1215 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1 1216 let isExtractSubreg = 1; 1217} 1218 1219def VMOVRRS : AVConv3I<0b11000101, 0b1010, 1220 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2), 1221 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2", 1222 [/* For disassembly only; pattern left blank */]>, 1223 Requires<[HasFPRegs]>, 1224 Sched<[WriteFPMOV]> { 1225 bits<5> src1; 1226 bits<4> Rt; 1227 bits<4> Rt2; 1228 1229 // Encode instruction operands. 1230 let Inst{3-0} = src1{4-1}; 1231 let Inst{5} = src1{0}; 1232 let Inst{15-12} = Rt; 1233 let Inst{19-16} = Rt2; 1234 1235 let Inst{7-6} = 0b00; 1236 1237 // Some single precision VFP instructions may be executed on both NEON and VFP 1238 // pipelines. 1239 let D = VFPNeonDomain; 1240 let DecoderMethod = "DecodeVMOVRRS"; 1241} 1242} // hasSideEffects 1243 1244// FMDHR: GPR -> SPR 1245// FMDLR: GPR -> SPR 1246 1247def VMOVDRR : AVConv5I<0b11000100, 0b1011, 1248 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2), 1249 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2", 1250 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]>, 1251 Requires<[HasFPRegs]>, 1252 Sched<[WriteFPMOV]> { 1253 // Instruction operands. 1254 bits<5> Dm; 1255 bits<4> Rt; 1256 bits<4> Rt2; 1257 1258 // Encode instruction operands. 1259 let Inst{3-0} = Dm{3-0}; 1260 let Inst{5} = Dm{4}; 1261 let Inst{15-12} = Rt; 1262 let Inst{19-16} = Rt2; 1263 1264 let Inst{7-6} = 0b00; 1265 1266 // Some single precision VFP instructions may be executed on both NEON and VFP 1267 // pipelines. 1268 let D = VFPNeonDomain; 1269 1270 // This instruction is equivalent to 1271 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1 1272 let isRegSequence = 1; 1273} 1274 1275// Hoist an fabs or a fneg of a value coming from integer registers 1276// and do the fabs/fneg on the integer value. This is never a lose 1277// and could enable the conversion to float to be removed completely. 1278def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)), 1279 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>, 1280 Requires<[IsARM, HasV6T2]>; 1281def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)), 1282 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>, 1283 Requires<[IsThumb2, HasV6T2]>; 1284def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)), 1285 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>, 1286 Requires<[IsARM]>; 1287def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)), 1288 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>, 1289 Requires<[IsThumb2]>; 1290 1291let hasSideEffects = 0 in 1292def VMOVSRR : AVConv5I<0b11000100, 0b1010, 1293 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2), 1294 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2", 1295 [/* For disassembly only; pattern left blank */]>, 1296 Requires<[HasFPRegs]>, 1297 Sched<[WriteFPMOV]> { 1298 // Instruction operands. 1299 bits<5> dst1; 1300 bits<4> src1; 1301 bits<4> src2; 1302 1303 // Encode instruction operands. 1304 let Inst{3-0} = dst1{4-1}; 1305 let Inst{5} = dst1{0}; 1306 let Inst{15-12} = src1; 1307 let Inst{19-16} = src2; 1308 1309 let Inst{7-6} = 0b00; 1310 1311 // Some single precision VFP instructions may be executed on both NEON and VFP 1312 // pipelines. 1313 let D = VFPNeonDomain; 1314 1315 let DecoderMethod = "DecodeVMOVSRR"; 1316} 1317 1318// Move H->R, clearing top 16 bits 1319def VMOVRH : AVConv2I<0b11100001, 0b1001, 1320 (outs rGPR:$Rt), (ins HPR:$Sn), 1321 IIC_fpMOVSI, "vmov", ".f16\t$Rt, $Sn", 1322 []>, 1323 Requires<[HasFPRegs16]>, 1324 Sched<[WriteFPMOV]> { 1325 // Instruction operands. 1326 bits<4> Rt; 1327 bits<5> Sn; 1328 1329 // Encode instruction operands. 1330 let Inst{19-16} = Sn{4-1}; 1331 let Inst{7} = Sn{0}; 1332 let Inst{15-12} = Rt; 1333 1334 let Inst{6-5} = 0b00; 1335 let Inst{3-0} = 0b0000; 1336 1337 let isUnpredicable = 1; 1338} 1339 1340// Move R->H, clearing top 16 bits 1341def VMOVHR : AVConv4I<0b11100000, 0b1001, 1342 (outs HPR:$Sn), (ins rGPR:$Rt), 1343 IIC_fpMOVIS, "vmov", ".f16\t$Sn, $Rt", 1344 []>, 1345 Requires<[HasFPRegs16]>, 1346 Sched<[WriteFPMOV]> { 1347 // Instruction operands. 1348 bits<5> Sn; 1349 bits<4> Rt; 1350 1351 // Encode instruction operands. 1352 let Inst{19-16} = Sn{4-1}; 1353 let Inst{7} = Sn{0}; 1354 let Inst{15-12} = Rt; 1355 1356 let Inst{6-5} = 0b00; 1357 let Inst{3-0} = 0b0000; 1358 1359 let isUnpredicable = 1; 1360} 1361 1362def : FPRegs16Pat<(arm_vmovrh (f16 HPR:$Sn)), (VMOVRH (f16 HPR:$Sn))>; 1363def : FPRegs16Pat<(arm_vmovrh (bf16 HPR:$Sn)), (VMOVRH (bf16 HPR:$Sn))>; 1364def : FPRegs16Pat<(f16 (arm_vmovhr rGPR:$Rt)), (VMOVHR rGPR:$Rt)>; 1365def : FPRegs16Pat<(bf16 (arm_vmovhr rGPR:$Rt)), (VMOVHR rGPR:$Rt)>; 1366 1367// FMRDH: SPR -> GPR 1368// FMRDL: SPR -> GPR 1369// FMRRS: SPR -> GPR 1370// FMRX: SPR system reg -> GPR 1371// FMSRR: GPR -> SPR 1372// FMXR: GPR -> VFP system reg 1373 1374 1375// Int -> FP: 1376 1377class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1378 bits<4> opcod4, dag oops, dag iops, 1379 InstrItinClass itin, string opc, string asm, 1380 list<dag> pattern> 1381 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1382 pattern> { 1383 // Instruction operands. 1384 bits<5> Dd; 1385 bits<5> Sm; 1386 1387 // Encode instruction operands. 1388 let Inst{3-0} = Sm{4-1}; 1389 let Inst{5} = Sm{0}; 1390 let Inst{15-12} = Dd{3-0}; 1391 let Inst{22} = Dd{4}; 1392 1393 let Predicates = [HasVFP2, HasDPVFP]; 1394 let hasSideEffects = 0; 1395} 1396 1397class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1398 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin, 1399 string opc, string asm, list<dag> pattern> 1400 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1401 pattern> { 1402 // Instruction operands. 1403 bits<5> Sd; 1404 bits<5> Sm; 1405 1406 // Encode instruction operands. 1407 let Inst{3-0} = Sm{4-1}; 1408 let Inst{5} = Sm{0}; 1409 let Inst{15-12} = Sd{4-1}; 1410 let Inst{22} = Sd{0}; 1411 1412 let hasSideEffects = 0; 1413} 1414 1415class AVConv1IHs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1416 bits<4> opcod4, dag oops, dag iops, 1417 InstrItinClass itin, string opc, string asm, 1418 list<dag> pattern> 1419 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1420 pattern> { 1421 // Instruction operands. 1422 bits<5> Sd; 1423 bits<5> Sm; 1424 1425 // Encode instruction operands. 1426 let Inst{3-0} = Sm{4-1}; 1427 let Inst{5} = Sm{0}; 1428 let Inst{15-12} = Sd{4-1}; 1429 let Inst{22} = Sd{0}; 1430 1431 let Predicates = [HasFullFP16]; 1432 let hasSideEffects = 0; 1433} 1434 1435def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 1436 (outs DPR:$Dd), (ins SPR:$Sm), 1437 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm", 1438 []>, 1439 Sched<[WriteFPCVT]> { 1440 let Inst{7} = 1; // s32 1441} 1442 1443let Predicates=[HasVFP2, HasDPVFP] in { 1444 def : VFPPat<(f64 (sint_to_fp GPR:$a)), 1445 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>; 1446 1447 def : VFPPat<(f64 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1448 (VSITOD (VLDRS addrmode5:$a))>; 1449} 1450 1451def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 1452 (outs SPR:$Sd),(ins SPR:$Sm), 1453 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm", 1454 []>, 1455 Sched<[WriteFPCVT]> { 1456 let Inst{7} = 1; // s32 1457 1458 // Some single precision VFP instructions may be executed on both NEON and 1459 // VFP pipelines on A8. 1460 let D = VFPNeonA8Domain; 1461} 1462 1463def : VFPNoNEONPat<(f32 (sint_to_fp GPR:$a)), 1464 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>; 1465 1466def : VFPNoNEONPat<(f32 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1467 (VSITOS (VLDRS addrmode5:$a))>; 1468 1469def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001, 1470 (outs HPR:$Sd), (ins SPR:$Sm), 1471 IIC_fpCVTIH, "vcvt", ".f16.s32\t$Sd, $Sm", 1472 []>, 1473 Sched<[WriteFPCVT]> { 1474 let Inst{7} = 1; // s32 1475 let isUnpredicable = 1; 1476} 1477 1478def : VFPNoNEONPat<(f16 (sint_to_fp GPR:$a)), 1479 (VSITOH (COPY_TO_REGCLASS GPR:$a, SPR))>; 1480 1481def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 1482 (outs DPR:$Dd), (ins SPR:$Sm), 1483 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm", 1484 []>, 1485 Sched<[WriteFPCVT]> { 1486 let Inst{7} = 0; // u32 1487} 1488 1489let Predicates=[HasVFP2, HasDPVFP] in { 1490 def : VFPPat<(f64 (uint_to_fp GPR:$a)), 1491 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>; 1492 1493 def : VFPPat<(f64 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1494 (VUITOD (VLDRS addrmode5:$a))>; 1495} 1496 1497def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 1498 (outs SPR:$Sd), (ins SPR:$Sm), 1499 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm", 1500 []>, 1501 Sched<[WriteFPCVT]> { 1502 let Inst{7} = 0; // u32 1503 1504 // Some single precision VFP instructions may be executed on both NEON and 1505 // VFP pipelines on A8. 1506 let D = VFPNeonA8Domain; 1507} 1508 1509def : VFPNoNEONPat<(f32 (uint_to_fp GPR:$a)), 1510 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>; 1511 1512def : VFPNoNEONPat<(f32 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1513 (VUITOS (VLDRS addrmode5:$a))>; 1514 1515def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001, 1516 (outs HPR:$Sd), (ins SPR:$Sm), 1517 IIC_fpCVTIH, "vcvt", ".f16.u32\t$Sd, $Sm", 1518 []>, 1519 Sched<[WriteFPCVT]> { 1520 let Inst{7} = 0; // u32 1521 let isUnpredicable = 1; 1522} 1523 1524def : VFPNoNEONPat<(f16 (uint_to_fp GPR:$a)), 1525 (VUITOH (COPY_TO_REGCLASS GPR:$a, SPR))>; 1526 1527// FP -> Int: 1528 1529class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1530 bits<4> opcod4, dag oops, dag iops, 1531 InstrItinClass itin, string opc, string asm, 1532 list<dag> pattern> 1533 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1534 pattern> { 1535 // Instruction operands. 1536 bits<5> Sd; 1537 bits<5> Dm; 1538 1539 // Encode instruction operands. 1540 let Inst{3-0} = Dm{3-0}; 1541 let Inst{5} = Dm{4}; 1542 let Inst{15-12} = Sd{4-1}; 1543 let Inst{22} = Sd{0}; 1544 1545 let Predicates = [HasVFP2, HasDPVFP]; 1546 let hasSideEffects = 0; 1547} 1548 1549class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1550 bits<4> opcod4, dag oops, dag iops, 1551 InstrItinClass itin, string opc, string asm, 1552 list<dag> pattern> 1553 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1554 pattern> { 1555 // Instruction operands. 1556 bits<5> Sd; 1557 bits<5> Sm; 1558 1559 // Encode instruction operands. 1560 let Inst{3-0} = Sm{4-1}; 1561 let Inst{5} = Sm{0}; 1562 let Inst{15-12} = Sd{4-1}; 1563 let Inst{22} = Sd{0}; 1564 1565 let hasSideEffects = 0; 1566} 1567 1568class AVConv1IsH_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1569 bits<4> opcod4, dag oops, dag iops, 1570 InstrItinClass itin, string opc, string asm, 1571 list<dag> pattern> 1572 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1573 pattern> { 1574 // Instruction operands. 1575 bits<5> Sd; 1576 bits<5> Sm; 1577 1578 // Encode instruction operands. 1579 let Inst{3-0} = Sm{4-1}; 1580 let Inst{5} = Sm{0}; 1581 let Inst{15-12} = Sd{4-1}; 1582 let Inst{22} = Sd{0}; 1583 1584 let Predicates = [HasFullFP16]; 1585 let hasSideEffects = 0; 1586} 1587 1588// Always set Z bit in the instruction, i.e. "round towards zero" variants. 1589def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 1590 (outs SPR:$Sd), (ins DPR:$Dm), 1591 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm", 1592 []>, 1593 Sched<[WriteFPCVT]> { 1594 let Inst{7} = 1; // Z bit 1595} 1596 1597let Predicates=[HasVFP2, HasDPVFP] in { 1598 def : VFPPat<(i32 (fp_to_sint (f64 DPR:$a))), 1599 (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>; 1600 1601 def : VFPPat<(alignedstore32 (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr), 1602 (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>; 1603} 1604 1605def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 1606 (outs SPR:$Sd), (ins SPR:$Sm), 1607 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm", 1608 []>, 1609 Sched<[WriteFPCVT]> { 1610 let Inst{7} = 1; // Z bit 1611 1612 // Some single precision VFP instructions may be executed on both NEON and 1613 // VFP pipelines on A8. 1614 let D = VFPNeonA8Domain; 1615} 1616 1617def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)), 1618 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>; 1619 1620def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))), 1621 addrmode5:$ptr), 1622 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>; 1623 1624def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001, 1625 (outs SPR:$Sd), (ins HPR:$Sm), 1626 IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm", 1627 []>, 1628 Sched<[WriteFPCVT]> { 1629 let Inst{7} = 1; // Z bit 1630 let isUnpredicable = 1; 1631} 1632 1633def : VFPNoNEONPat<(i32 (fp_to_sint (f16 HPR:$a))), 1634 (COPY_TO_REGCLASS (VTOSIZH (f16 HPR:$a)), GPR)>; 1635 1636def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 1637 (outs SPR:$Sd), (ins DPR:$Dm), 1638 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm", 1639 []>, 1640 Sched<[WriteFPCVT]> { 1641 let Inst{7} = 1; // Z bit 1642} 1643 1644let Predicates=[HasVFP2, HasDPVFP] in { 1645 def : VFPPat<(i32 (fp_to_uint (f64 DPR:$a))), 1646 (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>; 1647 1648 def : VFPPat<(alignedstore32 (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr), 1649 (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>; 1650} 1651 1652def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 1653 (outs SPR:$Sd), (ins SPR:$Sm), 1654 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm", 1655 []>, 1656 Sched<[WriteFPCVT]> { 1657 let Inst{7} = 1; // Z bit 1658 1659 // Some single precision VFP instructions may be executed on both NEON and 1660 // VFP pipelines on A8. 1661 let D = VFPNeonA8Domain; 1662} 1663 1664def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)), 1665 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>; 1666 1667def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))), 1668 addrmode5:$ptr), 1669 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>; 1670 1671def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001, 1672 (outs SPR:$Sd), (ins HPR:$Sm), 1673 IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm", 1674 []>, 1675 Sched<[WriteFPCVT]> { 1676 let Inst{7} = 1; // Z bit 1677 let isUnpredicable = 1; 1678} 1679 1680def : VFPNoNEONPat<(i32 (fp_to_uint (f16 HPR:$a))), 1681 (COPY_TO_REGCLASS (VTOUIZH (f16 HPR:$a)), GPR)>; 1682 1683// And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR. 1684let Uses = [FPSCR] in { 1685def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 1686 (outs SPR:$Sd), (ins DPR:$Dm), 1687 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm", 1688 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>, 1689 Sched<[WriteFPCVT]> { 1690 let Inst{7} = 0; // Z bit 1691} 1692 1693def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 1694 (outs SPR:$Sd), (ins SPR:$Sm), 1695 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm", 1696 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]>, 1697 Sched<[WriteFPCVT]> { 1698 let Inst{7} = 0; // Z bit 1699} 1700 1701def VTOSIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001, 1702 (outs SPR:$Sd), (ins SPR:$Sm), 1703 IIC_fpCVTHI, "vcvtr", ".s32.f16\t$Sd, $Sm", 1704 []>, 1705 Sched<[WriteFPCVT]> { 1706 let Inst{7} = 0; // Z bit 1707 let isUnpredicable = 1; 1708} 1709 1710def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 1711 (outs SPR:$Sd), (ins DPR:$Dm), 1712 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm", 1713 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>, 1714 Sched<[WriteFPCVT]> { 1715 let Inst{7} = 0; // Z bit 1716} 1717 1718def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 1719 (outs SPR:$Sd), (ins SPR:$Sm), 1720 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm", 1721 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]>, 1722 Sched<[WriteFPCVT]> { 1723 let Inst{7} = 0; // Z bit 1724} 1725 1726def VTOUIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001, 1727 (outs SPR:$Sd), (ins SPR:$Sm), 1728 IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm", 1729 []>, 1730 Sched<[WriteFPCVT]> { 1731 let Inst{7} = 0; // Z bit 1732 let isUnpredicable = 1; 1733} 1734} 1735 1736// v8.3-a Javascript Convert to Signed fixed-point 1737def VJCVT : AVConv1IsD_Encode<0b11101, 0b11, 0b1001, 0b1011, 1738 (outs SPR:$Sd), (ins DPR:$Dm), 1739 IIC_fpCVTDI, "vjcvt", ".s32.f64\t$Sd, $Dm", 1740 []>, 1741 Requires<[HasFPARMv8, HasV8_3a]> { 1742 let Inst{7} = 1; // Z bit 1743} 1744 1745// Convert between floating-point and fixed-point 1746// Data type for fixed-point naming convention: 1747// S16 (U=0, sx=0) -> SH 1748// U16 (U=1, sx=0) -> UH 1749// S32 (U=0, sx=1) -> SL 1750// U32 (U=1, sx=1) -> UL 1751 1752let Constraints = "$a = $dst" in { 1753 1754// FP to Fixed-Point: 1755 1756// Single Precision register 1757class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 1758 bit op5, dag oops, dag iops, InstrItinClass itin, 1759 string opc, string asm, list<dag> pattern> 1760 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> { 1761 bits<5> dst; 1762 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 1763 let Inst{22} = dst{0}; 1764 let Inst{15-12} = dst{4-1}; 1765 1766 let hasSideEffects = 0; 1767} 1768 1769// Double Precision register 1770class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 1771 bit op5, dag oops, dag iops, InstrItinClass itin, 1772 string opc, string asm, list<dag> pattern> 1773 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> { 1774 bits<5> dst; 1775 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 1776 let Inst{22} = dst{4}; 1777 let Inst{15-12} = dst{3-0}; 1778 1779 let hasSideEffects = 0; 1780 let Predicates = [HasVFP2, HasDPVFP]; 1781} 1782 1783let isUnpredicable = 1 in { 1784 1785def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0, 1786 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1787 IIC_fpCVTHI, "vcvt", ".s16.f16\t$dst, $a, $fbits", []>, 1788 Requires<[HasFullFP16]>, 1789 Sched<[WriteFPCVT]>; 1790 1791def VTOUHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 0, 1792 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1793 IIC_fpCVTHI, "vcvt", ".u16.f16\t$dst, $a, $fbits", []>, 1794 Requires<[HasFullFP16]>, 1795 Sched<[WriteFPCVT]>; 1796 1797def VTOSLH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 1, 1798 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1799 IIC_fpCVTHI, "vcvt", ".s32.f16\t$dst, $a, $fbits", []>, 1800 Requires<[HasFullFP16]>, 1801 Sched<[WriteFPCVT]>; 1802 1803def VTOULH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 1, 1804 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1805 IIC_fpCVTHI, "vcvt", ".u32.f16\t$dst, $a, $fbits", []>, 1806 Requires<[HasFullFP16]>, 1807 Sched<[WriteFPCVT]>; 1808 1809} // End of 'let isUnpredicable = 1 in' 1810 1811def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0, 1812 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1813 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []>, 1814 Sched<[WriteFPCVT]> { 1815 // Some single precision VFP instructions may be executed on both NEON and 1816 // VFP pipelines on A8. 1817 let D = VFPNeonA8Domain; 1818} 1819 1820def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0, 1821 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1822 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []>, 1823 Sched<[WriteFPCVT]> { 1824 // Some single precision VFP instructions may be executed on both NEON and 1825 // VFP pipelines on A8. 1826 let D = VFPNeonA8Domain; 1827} 1828 1829def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1, 1830 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1831 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []>, 1832 Sched<[WriteFPCVT]> { 1833 // Some single precision VFP instructions may be executed on both NEON and 1834 // VFP pipelines on A8. 1835 let D = VFPNeonA8Domain; 1836} 1837 1838def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1, 1839 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1840 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []>, 1841 Sched<[WriteFPCVT]> { 1842 // Some single precision VFP instructions may be executed on both NEON and 1843 // VFP pipelines on A8. 1844 let D = VFPNeonA8Domain; 1845} 1846 1847def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0, 1848 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1849 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>, 1850 Sched<[WriteFPCVT]>; 1851 1852def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0, 1853 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1854 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>, 1855 Sched<[WriteFPCVT]>; 1856 1857def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1, 1858 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1859 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>, 1860 Sched<[WriteFPCVT]>; 1861 1862def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1, 1863 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1864 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>, 1865 Sched<[WriteFPCVT]>; 1866 1867// Fixed-Point to FP: 1868 1869let isUnpredicable = 1 in { 1870 1871def VSHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 0, 1872 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1873 IIC_fpCVTIH, "vcvt", ".f16.s16\t$dst, $a, $fbits", []>, 1874 Requires<[HasFullFP16]>, 1875 Sched<[WriteFPCVT]>; 1876 1877def VUHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 0, 1878 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1879 IIC_fpCVTIH, "vcvt", ".f16.u16\t$dst, $a, $fbits", []>, 1880 Requires<[HasFullFP16]>, 1881 Sched<[WriteFPCVT]>; 1882 1883def VSLTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 1, 1884 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1885 IIC_fpCVTIH, "vcvt", ".f16.s32\t$dst, $a, $fbits", []>, 1886 Requires<[HasFullFP16]>, 1887 Sched<[WriteFPCVT]>; 1888 1889def VULTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 1, 1890 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1891 IIC_fpCVTIH, "vcvt", ".f16.u32\t$dst, $a, $fbits", []>, 1892 Requires<[HasFullFP16]>, 1893 Sched<[WriteFPCVT]>; 1894 1895} // End of 'let isUnpredicable = 1 in' 1896 1897def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0, 1898 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1899 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []>, 1900 Sched<[WriteFPCVT]> { 1901 // Some single precision VFP instructions may be executed on both NEON and 1902 // VFP pipelines on A8. 1903 let D = VFPNeonA8Domain; 1904} 1905 1906def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0, 1907 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1908 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []>, 1909 Sched<[WriteFPCVT]> { 1910 // Some single precision VFP instructions may be executed on both NEON and 1911 // VFP pipelines on A8. 1912 let D = VFPNeonA8Domain; 1913} 1914 1915def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1, 1916 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1917 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []>, 1918 Sched<[WriteFPCVT]> { 1919 // Some single precision VFP instructions may be executed on both NEON and 1920 // VFP pipelines on A8. 1921 let D = VFPNeonA8Domain; 1922} 1923 1924def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1, 1925 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1926 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []>, 1927 Sched<[WriteFPCVT]> { 1928 // Some single precision VFP instructions may be executed on both NEON and 1929 // VFP pipelines on A8. 1930 let D = VFPNeonA8Domain; 1931} 1932 1933def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0, 1934 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1935 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>, 1936 Sched<[WriteFPCVT]>; 1937 1938def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0, 1939 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1940 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>, 1941 Sched<[WriteFPCVT]>; 1942 1943def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1, 1944 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1945 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>, 1946 Sched<[WriteFPCVT]>; 1947 1948def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1, 1949 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1950 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>, 1951 Sched<[WriteFPCVT]>; 1952 1953} // End of 'let Constraints = "$a = $dst" in' 1954 1955// BFloat16 - Single precision, unary, predicated 1956class BF16_VCVT<string opc, bits<2> op7_6> 1957 : VFPAI<(outs SPR:$Sd), (ins SPR:$dst, SPR:$Sm), 1958 VFPUnaryFrm, NoItinerary, 1959 opc, ".bf16.f32\t$Sd, $Sm", []>, 1960 RegConstraint<"$dst = $Sd">, 1961 Requires<[HasBF16]>, 1962 Sched<[]> { 1963 bits<5> Sd; 1964 bits<5> Sm; 1965 1966 // Encode instruction operands. 1967 let Inst{3-0} = Sm{4-1}; 1968 let Inst{5} = Sm{0}; 1969 let Inst{15-12} = Sd{4-1}; 1970 let Inst{22} = Sd{0}; 1971 1972 let Inst{27-23} = 0b11101; // opcode1 1973 let Inst{21-20} = 0b11; // opcode2 1974 let Inst{19-16} = 0b0011; // opcode3 1975 let Inst{11-8} = 0b1001; 1976 let Inst{7-6} = op7_6; 1977 let Inst{4} = 0; 1978 1979 let DecoderNamespace = "VFPV8"; 1980 let hasSideEffects = 0; 1981} 1982 1983def BF16_VCVTB : BF16_VCVT<"vcvtb", 0b01>; 1984def BF16_VCVTT : BF16_VCVT<"vcvtt", 0b11>; 1985 1986//===----------------------------------------------------------------------===// 1987// FP Multiply-Accumulate Operations. 1988// 1989 1990def VMLAD : ADbI<0b11100, 0b00, 0, 0, 1991 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1992 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm", 1993 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1994 (f64 DPR:$Ddin)))]>, 1995 RegConstraint<"$Ddin = $Dd">, 1996 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, 1997 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 1998 1999def VMLAS : ASbIn<0b11100, 0b00, 0, 0, 2000 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2001 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm", 2002 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 2003 SPR:$Sdin))]>, 2004 RegConstraint<"$Sdin = $Sd">, 2005 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>, 2006 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2007 // Some single precision VFP instructions may be executed on both NEON and 2008 // VFP pipelines on A8. 2009 let D = VFPNeonA8Domain; 2010} 2011 2012def VMLAH : AHbI<0b11100, 0b00, 0, 0, 2013 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2014 IIC_fpMAC16, "vmla", ".f16\t$Sd, $Sn, $Sm", 2015 [(set (f16 HPR:$Sd), (fadd_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), 2016 (f16 HPR:$Sdin)))]>, 2017 RegConstraint<"$Sdin = $Sd">, 2018 Requires<[HasFullFP16,UseFPVMLx]>; 2019 2020def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 2021 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 2022 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2023def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 2024 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 2025 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx]>; 2026def : Pat<(fadd_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)), 2027 (VMLAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2028 Requires<[HasFullFP16,DontUseNEONForFP, UseFPVMLx]>; 2029 2030 2031def VMLSD : ADbI<0b11100, 0b00, 1, 0, 2032 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2033 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm", 2034 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 2035 (f64 DPR:$Ddin)))]>, 2036 RegConstraint<"$Ddin = $Dd">, 2037 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, 2038 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2039 2040def VMLSS : ASbIn<0b11100, 0b00, 1, 0, 2041 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2042 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm", 2043 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 2044 SPR:$Sdin))]>, 2045 RegConstraint<"$Sdin = $Sd">, 2046 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>, 2047 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2048 // Some single precision VFP instructions may be executed on both NEON and 2049 // VFP pipelines on A8. 2050 let D = VFPNeonA8Domain; 2051} 2052 2053def VMLSH : AHbI<0b11100, 0b00, 1, 0, 2054 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2055 IIC_fpMAC16, "vmls", ".f16\t$Sd, $Sn, $Sm", 2056 [(set (f16 HPR:$Sd), (fadd_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))), 2057 (f16 HPR:$Sdin)))]>, 2058 RegConstraint<"$Sdin = $Sd">, 2059 Requires<[HasFullFP16,UseFPVMLx]>; 2060 2061def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 2062 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 2063 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2064def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 2065 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 2066 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; 2067def : Pat<(fsub_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)), 2068 (VMLSH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2069 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; 2070 2071def VNMLAD : ADbI<0b11100, 0b01, 1, 0, 2072 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2073 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm", 2074 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 2075 (f64 DPR:$Ddin)))]>, 2076 RegConstraint<"$Ddin = $Dd">, 2077 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, 2078 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2079 2080def VNMLAS : ASbI<0b11100, 0b01, 1, 0, 2081 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2082 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm", 2083 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 2084 SPR:$Sdin))]>, 2085 RegConstraint<"$Sdin = $Sd">, 2086 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>, 2087 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2088 // Some single precision VFP instructions may be executed on both NEON and 2089 // VFP pipelines on A8. 2090 let D = VFPNeonA8Domain; 2091} 2092 2093def VNMLAH : AHbI<0b11100, 0b01, 1, 0, 2094 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2095 IIC_fpMAC16, "vnmla", ".f16\t$Sd, $Sn, $Sm", 2096 [(set (f16 HPR:$Sd), (fsub_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))), 2097 (f16 HPR:$Sdin)))]>, 2098 RegConstraint<"$Sdin = $Sd">, 2099 Requires<[HasFullFP16,UseFPVMLx]>; 2100 2101// (-(a * b) - dst) -> -(dst + (a * b)) 2102def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 2103 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 2104 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2105def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 2106 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 2107 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; 2108def : Pat<(fsub_mlx (fneg (fmul_su (f16 HPR:$a), HPR:$b)), HPR:$dstin), 2109 (VNMLAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2110 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; 2111 2112// (-dst - (a * b)) -> -(dst + (a * b)) 2113def : Pat<(fsub_mlx (fneg DPR:$dstin), (fmul_su DPR:$a, (f64 DPR:$b))), 2114 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 2115 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2116def : Pat<(fsub_mlx (fneg SPR:$dstin), (fmul_su SPR:$a, SPR:$b)), 2117 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 2118 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; 2119def : Pat<(fsub_mlx (fneg HPR:$dstin), (fmul_su (f16 HPR:$a), HPR:$b)), 2120 (VNMLAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2121 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; 2122 2123def VNMLSD : ADbI<0b11100, 0b01, 0, 0, 2124 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2125 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm", 2126 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 2127 (f64 DPR:$Ddin)))]>, 2128 RegConstraint<"$Ddin = $Dd">, 2129 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, 2130 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2131 2132def VNMLSS : ASbI<0b11100, 0b01, 0, 0, 2133 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2134 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm", 2135 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 2136 RegConstraint<"$Sdin = $Sd">, 2137 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>, 2138 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2139 // Some single precision VFP instructions may be executed on both NEON and 2140 // VFP pipelines on A8. 2141 let D = VFPNeonA8Domain; 2142} 2143 2144def VNMLSH : AHbI<0b11100, 0b01, 0, 0, 2145 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2146 IIC_fpMAC16, "vnmls", ".f16\t$Sd, $Sn, $Sm", 2147 [(set (f16 HPR:$Sd), (fsub_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), (f16 HPR:$Sdin)))]>, 2148 RegConstraint<"$Sdin = $Sd">, 2149 Requires<[HasFullFP16,UseFPVMLx]>; 2150 2151def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 2152 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 2153 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2154def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 2155 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 2156 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; 2157def : Pat<(fsub_mlx (fmul_su (f16 HPR:$a), HPR:$b), HPR:$dstin), 2158 (VNMLSH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2159 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; 2160 2161//===----------------------------------------------------------------------===// 2162// Fused FP Multiply-Accumulate Operations. 2163// 2164def VFMAD : ADbI<0b11101, 0b10, 0, 0, 2165 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2166 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm", 2167 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 2168 (f64 DPR:$Ddin)))]>, 2169 RegConstraint<"$Ddin = $Dd">, 2170 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, 2171 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2172 2173def VFMAS : ASbIn<0b11101, 0b10, 0, 0, 2174 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2175 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm", 2176 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 2177 SPR:$Sdin))]>, 2178 RegConstraint<"$Sdin = $Sd">, 2179 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>, 2180 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2181 // Some single precision VFP instructions may be executed on both NEON and 2182 // VFP pipelines. 2183} 2184 2185def VFMAH : AHbI<0b11101, 0b10, 0, 0, 2186 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2187 IIC_fpFMAC16, "vfma", ".f16\t$Sd, $Sn, $Sm", 2188 [(set (f16 HPR:$Sd), (fadd_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), 2189 (f16 HPR:$Sdin)))]>, 2190 RegConstraint<"$Sdin = $Sd">, 2191 Requires<[HasFullFP16,UseFusedMAC]>, 2192 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2193 2194def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 2195 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>, 2196 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 2197def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 2198 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>, 2199 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 2200def : Pat<(fadd_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)), 2201 (VFMAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2202 Requires<[HasFullFP16,DontUseNEONForFP,UseFusedMAC]>; 2203 2204// Match @llvm.fma.* intrinsics 2205// (fma x, y, z) -> (vfms z, x, y) 2206def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)), 2207 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2208 Requires<[HasVFP4,HasDPVFP]>; 2209def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)), 2210 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2211 Requires<[HasVFP4]>; 2212def : Pat<(f16 (fma HPR:$Sn, HPR:$Sm, (f16 HPR:$Sdin))), 2213 (VFMAH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2214 Requires<[HasFullFP16]>; 2215 2216def VFMSD : ADbI<0b11101, 0b10, 1, 0, 2217 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2218 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm", 2219 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 2220 (f64 DPR:$Ddin)))]>, 2221 RegConstraint<"$Ddin = $Dd">, 2222 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, 2223 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2224 2225def VFMSS : ASbIn<0b11101, 0b10, 1, 0, 2226 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2227 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm", 2228 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 2229 SPR:$Sdin))]>, 2230 RegConstraint<"$Sdin = $Sd">, 2231 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>, 2232 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2233 // Some single precision VFP instructions may be executed on both NEON and 2234 // VFP pipelines. 2235} 2236 2237def VFMSH : AHbI<0b11101, 0b10, 1, 0, 2238 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2239 IIC_fpFMAC16, "vfms", ".f16\t$Sd, $Sn, $Sm", 2240 [(set (f16 HPR:$Sd), (fadd_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))), 2241 (f16 HPR:$Sdin)))]>, 2242 RegConstraint<"$Sdin = $Sd">, 2243 Requires<[HasFullFP16,UseFusedMAC]>, 2244 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2245 2246def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 2247 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>, 2248 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 2249def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 2250 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>, 2251 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 2252def : Pat<(fsub_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)), 2253 (VFMSH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2254 Requires<[HasFullFP16,DontUseNEONForFP,UseFusedMAC]>; 2255 2256// Match @llvm.fma.* intrinsics 2257// (fma (fneg x), y, z) -> (vfms z, x, y) 2258def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)), 2259 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2260 Requires<[HasVFP4,HasDPVFP]>; 2261def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)), 2262 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2263 Requires<[HasVFP4]>; 2264def : Pat<(f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (f16 HPR:$Sdin))), 2265 (VFMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2266 Requires<[HasFullFP16]>; 2267 2268def VFNMAD : ADbI<0b11101, 0b01, 1, 0, 2269 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2270 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm", 2271 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 2272 (f64 DPR:$Ddin)))]>, 2273 RegConstraint<"$Ddin = $Dd">, 2274 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, 2275 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2276 2277def VFNMAS : ASbI<0b11101, 0b01, 1, 0, 2278 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2279 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm", 2280 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 2281 SPR:$Sdin))]>, 2282 RegConstraint<"$Sdin = $Sd">, 2283 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>, 2284 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2285 // Some single precision VFP instructions may be executed on both NEON and 2286 // VFP pipelines. 2287} 2288 2289def VFNMAH : AHbI<0b11101, 0b01, 1, 0, 2290 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2291 IIC_fpFMAC16, "vfnma", ".f16\t$Sd, $Sn, $Sm", 2292 [(set (f16 HPR:$Sd), (fsub_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))), 2293 (f16 HPR:$Sdin)))]>, 2294 RegConstraint<"$Sdin = $Sd">, 2295 Requires<[HasFullFP16,UseFusedMAC]>, 2296 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2297 2298def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 2299 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>, 2300 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 2301def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 2302 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>, 2303 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 2304 2305// Match @llvm.fma.* intrinsics 2306// (fneg (fma x, y, z)) -> (vfnma z, x, y) 2307def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))), 2308 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2309 Requires<[HasVFP4,HasDPVFP]>; 2310def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))), 2311 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2312 Requires<[HasVFP4]>; 2313def : Pat<(fneg (fma (f16 HPR:$Sn), (f16 HPR:$Sm), (f16 (f16 HPR:$Sdin)))), 2314 (VFNMAH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2315 Requires<[HasFullFP16]>; 2316// (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y) 2317def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))), 2318 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2319 Requires<[HasVFP4,HasDPVFP]>; 2320def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))), 2321 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2322 Requires<[HasVFP4]>; 2323def : Pat<(f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (fneg (f16 HPR:$Sdin)))), 2324 (VFNMAH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2325 Requires<[HasFullFP16]>; 2326 2327def VFNMSD : ADbI<0b11101, 0b01, 0, 0, 2328 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2329 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm", 2330 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 2331 (f64 DPR:$Ddin)))]>, 2332 RegConstraint<"$Ddin = $Dd">, 2333 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, 2334 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2335 2336def VFNMSS : ASbI<0b11101, 0b01, 0, 0, 2337 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2338 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm", 2339 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 2340 RegConstraint<"$Sdin = $Sd">, 2341 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>, 2342 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2343 // Some single precision VFP instructions may be executed on both NEON and 2344 // VFP pipelines. 2345} 2346 2347def VFNMSH : AHbI<0b11101, 0b01, 0, 0, 2348 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2349 IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm", 2350 [(set (f16 HPR:$Sd), (fsub_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), (f16 HPR:$Sdin)))]>, 2351 RegConstraint<"$Sdin = $Sd">, 2352 Requires<[HasFullFP16,UseFusedMAC]>, 2353 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2354 2355def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 2356 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>, 2357 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 2358def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 2359 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>, 2360 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 2361 2362// Match @llvm.fma.* intrinsics 2363 2364// (fma x, y, (fneg z)) -> (vfnms z, x, y)) 2365def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))), 2366 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2367 Requires<[HasVFP4,HasDPVFP]>; 2368def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))), 2369 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2370 Requires<[HasVFP4]>; 2371def : Pat<(f16 (fma (f16 HPR:$Sn), (f16 HPR:$Sm), (fneg (f16 HPR:$Sdin)))), 2372 (VFNMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2373 Requires<[HasFullFP16]>; 2374// (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y) 2375def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))), 2376 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2377 Requires<[HasVFP4,HasDPVFP]>; 2378def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))), 2379 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2380 Requires<[HasVFP4]>; 2381def : Pat<(fneg (f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (f16 HPR:$Sdin)))), 2382 (VFNMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2383 Requires<[HasFullFP16]>; 2384 2385//===----------------------------------------------------------------------===// 2386// FP Conditional moves. 2387// 2388 2389let hasSideEffects = 0 in { 2390def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p), 2391 IIC_fpUNA64, 2392 [(set (f64 DPR:$Dd), 2393 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>, 2394 RegConstraint<"$Dn = $Dd">, Requires<[HasFPRegs64]>; 2395 2396def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p), 2397 IIC_fpUNA32, 2398 [(set (f32 SPR:$Sd), 2399 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>, 2400 RegConstraint<"$Sn = $Sd">, Requires<[HasFPRegs]>; 2401 2402def VMOVHcc : PseudoInst<(outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm, cmovpred:$p), 2403 IIC_fpUNA16, 2404 [(set (f16 HPR:$Sd), 2405 (ARMcmov (f16 HPR:$Sn), (f16 HPR:$Sm), cmovpred:$p))]>, 2406 RegConstraint<"$Sd = $Sn">, Requires<[HasFPRegs]>; 2407} // hasSideEffects 2408 2409//===----------------------------------------------------------------------===// 2410// Move from VFP System Register to ARM core register. 2411// 2412 2413class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 2414 list<dag> pattern>: 2415 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { 2416 2417 // Instruction operand. 2418 bits<4> Rt; 2419 2420 let Inst{27-20} = 0b11101111; 2421 let Inst{19-16} = opc19_16; 2422 let Inst{15-12} = Rt; 2423 let Inst{11-8} = 0b1010; 2424 let Inst{7} = 0; 2425 let Inst{6-5} = 0b00; 2426 let Inst{4} = 1; 2427 let Inst{3-0} = 0b0000; 2428 let Unpredictable{7-5} = 0b111; 2429 let Unpredictable{3-0} = 0b1111; 2430} 2431 2432let DecoderMethod = "DecodeForVMRSandVMSR" in { 2433 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags 2434 // to APSR. 2435 let Defs = [CPSR], Uses = [FPSCR_NZCV], Predicates = [HasFPRegs], 2436 Rt = 0b1111 /* apsr_nzcv */ in 2437 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins), 2438 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>; 2439 2440 // Application level FPSCR -> GPR 2441 let hasSideEffects = 1, Uses = [FPSCR], Predicates = [HasFPRegs] in 2442 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPRnopc:$Rt), (ins), 2443 "vmrs", "\t$Rt, fpscr", 2444 [(set GPRnopc:$Rt, (int_arm_get_fpscr))]>; 2445 2446 // System level FPEXC, FPSID -> GPR 2447 let Uses = [FPSCR] in { 2448 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPRnopc:$Rt), (ins), 2449 "vmrs", "\t$Rt, fpexc", []>; 2450 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPRnopc:$Rt), (ins), 2451 "vmrs", "\t$Rt, fpsid", []>; 2452 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPRnopc:$Rt), (ins), 2453 "vmrs", "\t$Rt, mvfr0", []>; 2454 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPRnopc:$Rt), (ins), 2455 "vmrs", "\t$Rt, mvfr1", []>; 2456 let Predicates = [HasFPARMv8] in { 2457 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPRnopc:$Rt), (ins), 2458 "vmrs", "\t$Rt, mvfr2", []>; 2459 } 2460 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPRnopc:$Rt), (ins), 2461 "vmrs", "\t$Rt, fpinst", []>; 2462 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPRnopc:$Rt), 2463 (ins), "vmrs", "\t$Rt, fpinst2", []>; 2464 let Predicates = [HasV8_1MMainline, HasFPRegs] in { 2465 // System level FPSCR_NZCVQC -> GPR 2466 def VMRS_FPSCR_NZCVQC 2467 : MovFromVFP<0b0010 /* fpscr_nzcvqc */, 2468 (outs GPR:$Rt), (ins cl_FPSCR_NZCV:$fpscr_in), 2469 "vmrs", "\t$Rt, fpscr_nzcvqc", []>; 2470 } 2471 } 2472 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2473 // System level FPSCR -> GPR, with context saving for security extensions 2474 def VMRS_FPCXTNS : MovFromVFP<0b1110 /* fpcxtns */, (outs GPR:$Rt), (ins), 2475 "vmrs", "\t$Rt, fpcxtns", []>; 2476 } 2477 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2478 // System level FPSCR -> GPR, with context saving for security extensions 2479 def VMRS_FPCXTS : MovFromVFP<0b1111 /* fpcxts */, (outs GPR:$Rt), (ins), 2480 "vmrs", "\t$Rt, fpcxts", []>; 2481 } 2482 2483 let Predicates = [HasV8_1MMainline, HasMVEInt] in { 2484 // System level VPR/P0 -> GPR 2485 let Uses = [VPR] in 2486 def VMRS_VPR : MovFromVFP<0b1100 /* vpr */, (outs GPR:$Rt), (ins), 2487 "vmrs", "\t$Rt, vpr", []>; 2488 2489 def VMRS_P0 : MovFromVFP<0b1101 /* p0 */, (outs GPR:$Rt), (ins VCCR:$cond), 2490 "vmrs", "\t$Rt, p0", []>; 2491 } 2492} 2493 2494//===----------------------------------------------------------------------===// 2495// Move from ARM core register to VFP System Register. 2496// 2497 2498class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 2499 list<dag> pattern>: 2500 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { 2501 2502 // Instruction operand. 2503 bits<4> Rt; 2504 2505 let Inst{27-20} = 0b11101110; 2506 let Inst{19-16} = opc19_16; 2507 let Inst{15-12} = Rt; 2508 let Inst{11-8} = 0b1010; 2509 let Inst{7} = 0; 2510 let Inst{6-5} = 0b00; 2511 let Inst{4} = 1; 2512 let Inst{3-0} = 0b0000; 2513 let Predicates = [HasVFP2]; 2514 let Unpredictable{7-5} = 0b111; 2515 let Unpredictable{3-0} = 0b1111; 2516} 2517 2518let DecoderMethod = "DecodeForVMRSandVMSR" in { 2519 let Defs = [FPSCR] in { 2520 let Predicates = [HasFPRegs] in 2521 // Application level GPR -> FPSCR 2522 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPRnopc:$Rt), 2523 "vmsr", "\tfpscr, $Rt", 2524 [(int_arm_set_fpscr GPRnopc:$Rt)]>; 2525 // System level GPR -> FPEXC 2526 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPRnopc:$Rt), 2527 "vmsr", "\tfpexc, $Rt", []>; 2528 // System level GPR -> FPSID 2529 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPRnopc:$Rt), 2530 "vmsr", "\tfpsid, $Rt", []>; 2531 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPRnopc:$Rt), 2532 "vmsr", "\tfpinst, $Rt", []>; 2533 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPRnopc:$Rt), 2534 "vmsr", "\tfpinst2, $Rt", []>; 2535 } 2536 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2537 // System level GPR -> FPSCR with context saving for security extensions 2538 def VMSR_FPCXTNS : MovToVFP<0b1110 /* fpcxtns */, (outs), (ins GPR:$Rt), 2539 "vmsr", "\tfpcxtns, $Rt", []>; 2540 } 2541 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2542 // System level GPR -> FPSCR with context saving for security extensions 2543 def VMSR_FPCXTS : MovToVFP<0b1111 /* fpcxts */, (outs), (ins GPR:$Rt), 2544 "vmsr", "\tfpcxts, $Rt", []>; 2545 } 2546 let Predicates = [HasV8_1MMainline, HasFPRegs] in { 2547 // System level GPR -> FPSCR_NZCVQC 2548 def VMSR_FPSCR_NZCVQC 2549 : MovToVFP<0b0010 /* fpscr_nzcvqc */, 2550 (outs cl_FPSCR_NZCV:$fpscr_out), (ins GPR:$Rt), 2551 "vmsr", "\tfpscr_nzcvqc, $Rt", []>; 2552 } 2553 2554 let Predicates = [HasV8_1MMainline, HasMVEInt] in { 2555 // System level GPR -> VPR/P0 2556 let Defs = [VPR] in 2557 def VMSR_VPR : MovToVFP<0b1100 /* vpr */, (outs), (ins GPR:$Rt), 2558 "vmsr", "\tvpr, $Rt", []>; 2559 2560 def VMSR_P0 : MovToVFP<0b1101 /* p0 */, (outs VCCR:$cond), (ins GPR:$Rt), 2561 "vmsr", "\tp0, $Rt", []>; 2562 } 2563} 2564 2565//===----------------------------------------------------------------------===// 2566// Misc. 2567// 2568 2569// Materialize FP immediates. VFP3 only. 2570let isReMaterializable = 1 in { 2571def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm), 2572 VFPMiscFrm, IIC_fpUNA64, 2573 "vmov", ".f64\t$Dd, $imm", 2574 [(set DPR:$Dd, vfp_f64imm:$imm)]>, 2575 Requires<[HasVFP3,HasDPVFP]> { 2576 bits<5> Dd; 2577 bits<8> imm; 2578 2579 let Inst{27-23} = 0b11101; 2580 let Inst{22} = Dd{4}; 2581 let Inst{21-20} = 0b11; 2582 let Inst{19-16} = imm{7-4}; 2583 let Inst{15-12} = Dd{3-0}; 2584 let Inst{11-9} = 0b101; 2585 let Inst{8} = 1; // Double precision. 2586 let Inst{7-4} = 0b0000; 2587 let Inst{3-0} = imm{3-0}; 2588} 2589 2590def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm), 2591 VFPMiscFrm, IIC_fpUNA32, 2592 "vmov", ".f32\t$Sd, $imm", 2593 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> { 2594 bits<5> Sd; 2595 bits<8> imm; 2596 2597 let Inst{27-23} = 0b11101; 2598 let Inst{22} = Sd{0}; 2599 let Inst{21-20} = 0b11; 2600 let Inst{19-16} = imm{7-4}; 2601 let Inst{15-12} = Sd{4-1}; 2602 let Inst{11-9} = 0b101; 2603 let Inst{8} = 0; // Single precision. 2604 let Inst{7-4} = 0b0000; 2605 let Inst{3-0} = imm{3-0}; 2606} 2607 2608def FCONSTH : VFPAI<(outs HPR:$Sd), (ins vfp_f16imm:$imm), 2609 VFPMiscFrm, IIC_fpUNA16, 2610 "vmov", ".f16\t$Sd, $imm", 2611 [(set (f16 HPR:$Sd), vfp_f16imm:$imm)]>, 2612 Requires<[HasFullFP16]> { 2613 bits<5> Sd; 2614 bits<8> imm; 2615 2616 let Inst{27-23} = 0b11101; 2617 let Inst{22} = Sd{0}; 2618 let Inst{21-20} = 0b11; 2619 let Inst{19-16} = imm{7-4}; 2620 let Inst{15-12} = Sd{4-1}; 2621 let Inst{11-8} = 0b1001; // Half precision 2622 let Inst{7-4} = 0b0000; 2623 let Inst{3-0} = imm{3-0}; 2624 2625 let isUnpredicable = 1; 2626} 2627} 2628 2629def : Pat<(f32 (vfp_f32f16imm:$imm)), 2630 (f32 (COPY_TO_REGCLASS (f16 (FCONSTH (vfp_f32f16imm_xform (f32 $imm)))), SPR))> { 2631 let Predicates = [HasFullFP16]; 2632} 2633 2634//===----------------------------------------------------------------------===// 2635// Assembler aliases. 2636// 2637// A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to 2638// support them all, but supporting at least some of the basics is 2639// good to be friendly. 2640def : VFP2MnemonicAlias<"flds", "vldr">; 2641def : VFP2MnemonicAlias<"fldd", "vldr">; 2642def : VFP2MnemonicAlias<"fmrs", "vmov">; 2643def : VFP2MnemonicAlias<"fmsr", "vmov">; 2644def : VFP2MnemonicAlias<"fsqrts", "vsqrt">; 2645def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">; 2646def : VFP2MnemonicAlias<"fadds", "vadd.f32">; 2647def : VFP2MnemonicAlias<"faddd", "vadd.f64">; 2648def : VFP2MnemonicAlias<"fmrdd", "vmov">; 2649def : VFP2MnemonicAlias<"fmrds", "vmov">; 2650def : VFP2MnemonicAlias<"fmrrd", "vmov">; 2651def : VFP2MnemonicAlias<"fmdrr", "vmov">; 2652def : VFP2MnemonicAlias<"fmuls", "vmul.f32">; 2653def : VFP2MnemonicAlias<"fmuld", "vmul.f64">; 2654def : VFP2MnemonicAlias<"fnegs", "vneg.f32">; 2655def : VFP2MnemonicAlias<"fnegd", "vneg.f64">; 2656def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">; 2657def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">; 2658def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">; 2659def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">; 2660def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">; 2661def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">; 2662def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">; 2663def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">; 2664def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">; 2665def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">; 2666def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">; 2667def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">; 2668def : VFP2MnemonicAlias<"fsts", "vstr">; 2669def : VFP2MnemonicAlias<"fstd", "vstr">; 2670def : VFP2MnemonicAlias<"fmacd", "vmla.f64">; 2671def : VFP2MnemonicAlias<"fmacs", "vmla.f32">; 2672def : VFP2MnemonicAlias<"fcpys", "vmov.f32">; 2673def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">; 2674def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">; 2675def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">; 2676def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">; 2677def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">; 2678def : VFP2MnemonicAlias<"fmrx", "vmrs">; 2679def : VFP2MnemonicAlias<"fmxr", "vmsr">; 2680 2681// Be friendly and accept the old form of zero-compare 2682def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>; 2683def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>; 2684 2685 2686def : InstAlias<"fmstat${p}", (FMSTAT pred:$p), 0>, Requires<[HasFPRegs]>; 2687def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm", 2688 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 2689def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm", 2690 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 2691def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm", 2692 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 2693def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm", 2694 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 2695 2696// No need for the size suffix on VSQRT. It's implied by the register classes. 2697def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>; 2698def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>; 2699 2700// VLDR/VSTR accept an optional type suffix. 2701def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr", 2702 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 2703def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr", 2704 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 2705def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr", 2706 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 2707def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr", 2708 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 2709 2710// VMOV can accept optional 32-bit or less data type suffix suffix. 2711def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn", 2712 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 2713def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn", 2714 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 2715def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn", 2716 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 2717def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt", 2718 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 2719def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt", 2720 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 2721def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt", 2722 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 2723 2724def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn", 2725 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>; 2726def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2", 2727 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>; 2728 2729// VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way 2730// VMOVD does. 2731def : VFP2InstAlias<"vmov${p} $Sd, $Sm", 2732 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>; 2733 2734// FCONSTD/FCONSTS alias for vmov.f64/vmov.f32 2735// These aliases provide added functionality over vmov.f instructions by 2736// allowing users to write assembly containing encoded floating point constants 2737// (e.g. #0x70 vs #1.0). Without these alises there is no way for the 2738// assembler to accept encoded fp constants (but the equivalent fp-literal is 2739// accepted directly by vmovf). 2740def : VFP3InstAlias<"fconstd${p} $Dd, $val", 2741 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>; 2742def : VFP3InstAlias<"fconsts${p} $Sd, $val", 2743 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>; 2744 2745def VSCCLRMD : VFPXI<(outs), (ins pred:$p, fp_dreglist_with_vpr:$regs, variable_ops), 2746 AddrModeNone, 4, IndexModeNone, VFPMiscFrm, NoItinerary, 2747 "vscclrm{$p}\t$regs", "", []>, Sched<[]> { 2748 bits<13> regs; 2749 let Inst{31-23} = 0b111011001; 2750 let Inst{22} = regs{12}; 2751 let Inst{21-16} = 0b011111; 2752 let Inst{15-12} = regs{11-8}; 2753 let Inst{11-8} = 0b1011; 2754 let Inst{7-1} = regs{7-1}; 2755 let Inst{0} = 0; 2756 2757 let DecoderMethod = "DecodeVSCCLRM"; 2758 2759 list<Predicate> Predicates = [HasV8_1MMainline, Has8MSecExt]; 2760} 2761 2762def VSCCLRMS : VFPXI<(outs), (ins pred:$p, fp_sreglist_with_vpr:$regs, variable_ops), 2763 AddrModeNone, 4, IndexModeNone, VFPMiscFrm, NoItinerary, 2764 "vscclrm{$p}\t$regs", "", []>, Sched<[]> { 2765 bits<13> regs; 2766 let Inst{31-23} = 0b111011001; 2767 let Inst{22} = regs{8}; 2768 let Inst{21-16} = 0b011111; 2769 let Inst{15-12} = regs{12-9}; 2770 let Inst{11-8} = 0b1010; 2771 let Inst{7-0} = regs{7-0}; 2772 2773 let DecoderMethod = "DecodeVSCCLRM"; 2774 2775 list<Predicate> Predicates = [HasV8_1MMainline, Has8MSecExt]; 2776} 2777 2778//===----------------------------------------------------------------------===// 2779// Store VFP System Register to memory. 2780// 2781 2782class vfp_vstrldr<bit opc, bit P, bit W, bits<4> SysReg, string sysreg, 2783 dag oops, dag iops, IndexMode im, string Dest, string cstr> 2784 : VFPI<oops, iops, AddrModeT2_i7s4, 4, im, VFPLdStFrm, IIC_fpSTAT, 2785 !if(opc,"vldr","vstr"), !strconcat("\t", sysreg, ", ", Dest), cstr, []>, 2786 Sched<[]> { 2787 bits<12> addr; 2788 let Inst{27-25} = 0b110; 2789 let Inst{24} = P; 2790 let Inst{23} = addr{7}; 2791 let Inst{22} = SysReg{3}; 2792 let Inst{21} = W; 2793 let Inst{20} = opc; 2794 let Inst{19-16} = addr{11-8}; 2795 let Inst{15-13} = SysReg{2-0}; 2796 let Inst{12-7} = 0b011111; 2797 let Inst{6-0} = addr{6-0}; 2798 list<Predicate> Predicates = [HasFPRegs, HasV8_1MMainline]; 2799 let mayLoad = opc; 2800 let mayStore = !if(opc, 0b0, 0b1); 2801 let hasSideEffects = 1; 2802} 2803 2804multiclass vfp_vstrldr_sysreg<bit opc, bits<4> SysReg, string sysreg, 2805 dag oops=(outs), dag iops=(ins)> { 2806 def _off : 2807 vfp_vstrldr<opc, 1, 0, SysReg, sysreg, 2808 oops, !con(iops, (ins t2addrmode_imm7s4:$addr)), 2809 IndexModePost, "$addr", "" > { 2810 let DecoderMethod = "DecodeVSTRVLDR_SYSREG<false>"; 2811 } 2812 2813 def _pre : 2814 vfp_vstrldr<opc, 1, 1, SysReg, sysreg, 2815 !con(oops, (outs GPRnopc:$wb)), 2816 !con(iops, (ins t2addrmode_imm7s4_pre:$addr)), 2817 IndexModePre, "$addr!", "$addr.base = $wb"> { 2818 let DecoderMethod = "DecodeVSTRVLDR_SYSREG<true>"; 2819 } 2820 2821 def _post : 2822 vfp_vstrldr<opc, 0, 1, SysReg, sysreg, 2823 !con(oops, (outs GPRnopc:$wb)), 2824 !con(iops, (ins t2_addr_offset_none:$Rn, 2825 t2am_imm7s4_offset:$addr)), 2826 IndexModePost, "$Rn$addr", "$Rn.base = $wb"> { 2827 bits<4> Rn; 2828 let Inst{19-16} = Rn{3-0}; 2829 let DecoderMethod = "DecodeVSTRVLDR_SYSREG<true>"; 2830 } 2831} 2832 2833let Defs = [FPSCR] in { 2834 defm VSTR_FPSCR : vfp_vstrldr_sysreg<0b0,0b0001, "fpscr">; 2835 defm VSTR_FPSCR_NZCVQC : vfp_vstrldr_sysreg<0b0,0b0010, "fpscr_nzcvqc">; 2836 2837 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2838 defm VSTR_FPCXTNS : vfp_vstrldr_sysreg<0b0,0b1110, "fpcxtns">; 2839 defm VSTR_FPCXTS : vfp_vstrldr_sysreg<0b0,0b1111, "fpcxts">; 2840 } 2841} 2842 2843let Predicates = [HasV8_1MMainline, HasMVEInt] in { 2844 let Uses = [VPR] in { 2845 defm VSTR_VPR : vfp_vstrldr_sysreg<0b0,0b1100, "vpr">; 2846 } 2847 defm VSTR_P0 : vfp_vstrldr_sysreg<0b0,0b1101, "p0", 2848 (outs), (ins VCCR:$P0)>; 2849 2850 let Defs = [VPR] in { 2851 defm VLDR_VPR : vfp_vstrldr_sysreg<0b1,0b1100, "vpr">; 2852 } 2853 defm VLDR_P0 : vfp_vstrldr_sysreg<0b1,0b1101, "p0", 2854 (outs VCCR:$P0), (ins)>; 2855} 2856 2857let Uses = [FPSCR] in { 2858 defm VLDR_FPSCR : vfp_vstrldr_sysreg<0b1,0b0001, "fpscr">; 2859 defm VLDR_FPSCR_NZCVQC : vfp_vstrldr_sysreg<0b1,0b0010, "fpscr_nzcvqc">; 2860 2861 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2862 defm VLDR_FPCXTNS : vfp_vstrldr_sysreg<0b1,0b1110, "fpcxtns">; 2863 defm VLDR_FPCXTS : vfp_vstrldr_sysreg<0b1,0b1111, "fpcxts">; 2864 } 2865} 2866