1//===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the ARM VFP instruction set. 10// 11//===----------------------------------------------------------------------===// 12 13def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>; 14def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>, 15 SDTCisSameAs<1, 2>]>; 16def SDT_VMOVRRD : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 17 SDTCisVT<2, f64>]>; 18 19def SDT_VMOVSR : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i32>]>; 20 21def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>; 22def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>; 23def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>; 24def arm_cmpfpe : SDNode<"ARMISD::CMPFPE", SDT_ARMCmp, [SDNPOutGlue]>; 25def arm_cmpfpe0: SDNode<"ARMISD::CMPFPEw0",SDT_CMPFP0, [SDNPOutGlue]>; 26def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>; 27def arm_fmrrd : SDNode<"ARMISD::VMOVRRD", SDT_VMOVRRD>; 28def arm_vmovsr : SDNode<"ARMISD::VMOVSR", SDT_VMOVSR>; 29 30def SDT_VMOVhr : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, i32>] >; 31def SDT_VMOVrh : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisFP<1>] >; 32def arm_vmovhr : SDNode<"ARMISD::VMOVhr", SDT_VMOVhr>; 33def arm_vmovrh : SDNode<"ARMISD::VMOVrh", SDT_VMOVrh>; 34 35//===----------------------------------------------------------------------===// 36// Operand Definitions. 37// 38 39// 8-bit floating-point immediate encodings. 40def FPImmOperand : AsmOperandClass { 41 let Name = "FPImm"; 42 let ParserMethod = "parseFPImm"; 43} 44 45def vfp_f16imm : Operand<f16>, 46 PatLeaf<(f16 fpimm), [{ 47 return ARM_AM::getFP16Imm(N->getValueAPF()) != -1; 48 }], SDNodeXForm<fpimm, [{ 49 APFloat InVal = N->getValueAPF(); 50 uint32_t enc = ARM_AM::getFP16Imm(InVal); 51 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 52 }]>> { 53 let PrintMethod = "printFPImmOperand"; 54 let ParserMatchClass = FPImmOperand; 55} 56 57def vfp_f32f16imm_xform : SDNodeXForm<fpimm, [{ 58 APFloat InVal = N->getValueAPF(); 59 uint32_t enc = ARM_AM::getFP32FP16Imm(InVal); 60 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 61 }]>; 62 63def vfp_f32f16imm : PatLeaf<(f32 fpimm), [{ 64 return ARM_AM::getFP32FP16Imm(N->getValueAPF()) != -1; 65 }], vfp_f32f16imm_xform>; 66 67def vfp_f32imm_xform : SDNodeXForm<fpimm, [{ 68 APFloat InVal = N->getValueAPF(); 69 uint32_t enc = ARM_AM::getFP32Imm(InVal); 70 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 71 }]>; 72 73def gi_vfp_f32imm : GICustomOperandRenderer<"renderVFPF32Imm">, 74 GISDNodeXFormEquiv<vfp_f32imm_xform>; 75 76def vfp_f32imm : Operand<f32>, 77 PatLeaf<(f32 fpimm), [{ 78 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1; 79 }], vfp_f32imm_xform> { 80 let PrintMethod = "printFPImmOperand"; 81 let ParserMatchClass = FPImmOperand; 82 let GISelPredicateCode = [{ 83 const auto &MO = MI.getOperand(1); 84 if (!MO.isFPImm()) 85 return false; 86 return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1; 87 }]; 88} 89 90def vfp_f64imm_xform : SDNodeXForm<fpimm, [{ 91 APFloat InVal = N->getValueAPF(); 92 uint32_t enc = ARM_AM::getFP64Imm(InVal); 93 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 94 }]>; 95 96def gi_vfp_f64imm : GICustomOperandRenderer<"renderVFPF64Imm">, 97 GISDNodeXFormEquiv<vfp_f64imm_xform>; 98 99def vfp_f64imm : Operand<f64>, 100 PatLeaf<(f64 fpimm), [{ 101 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1; 102 }], vfp_f64imm_xform> { 103 let PrintMethod = "printFPImmOperand"; 104 let ParserMatchClass = FPImmOperand; 105 let GISelPredicateCode = [{ 106 const auto &MO = MI.getOperand(1); 107 if (!MO.isFPImm()) 108 return false; 109 return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1; 110 }]; 111} 112 113def alignedload16 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 114 return cast<LoadSDNode>(N)->getAlign() >= 2; 115}]>; 116 117def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 118 return cast<LoadSDNode>(N)->getAlign() >= 4; 119}]>; 120 121def alignedstore16 : PatFrag<(ops node:$val, node:$ptr), 122 (store node:$val, node:$ptr), [{ 123 return cast<StoreSDNode>(N)->getAlign() >= 2; 124}]>; 125 126def alignedstore32 : PatFrag<(ops node:$val, node:$ptr), 127 (store node:$val, node:$ptr), [{ 128 return cast<StoreSDNode>(N)->getAlign() >= 4; 129}]>; 130 131// The VCVT to/from fixed-point instructions encode the 'fbits' operand 132// (the number of fixed bits) differently than it appears in the assembly 133// source. It's encoded as "Size - fbits" where Size is the size of the 134// fixed-point representation (32 or 16) and fbits is the value appearing 135// in the assembly source, an integer in [0,16] or (0,32], depending on size. 136def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; } 137def fbits32 : Operand<i32> { 138 let PrintMethod = "printFBits32"; 139 let ParserMatchClass = fbits32_asm_operand; 140} 141 142def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; } 143def fbits16 : Operand<i32> { 144 let PrintMethod = "printFBits16"; 145 let ParserMatchClass = fbits16_asm_operand; 146} 147 148//===----------------------------------------------------------------------===// 149// Load / store Instructions. 150// 151 152let canFoldAsLoad = 1, isReMaterializable = 1 in { 153 154def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), 155 IIC_fpLoad64, "vldr", "\t$Dd, $addr", 156 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>, 157 Requires<[HasFPRegs]>; 158 159def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), 160 IIC_fpLoad32, "vldr", "\t$Sd, $addr", 161 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]>, 162 Requires<[HasFPRegs]> { 163 // Some single precision VFP instructions may be executed on both NEON and VFP 164 // pipelines. 165 let D = VFPNeonDomain; 166} 167 168let isUnpredicable = 1 in 169def VLDRH : AHI5<0b1101, 0b01, (outs HPR:$Sd), (ins addrmode5fp16:$addr), 170 IIC_fpLoad16, "vldr", ".16\t$Sd, $addr", 171 [(set HPR:$Sd, (f16 (alignedload16 addrmode5fp16:$addr)))]>, 172 Requires<[HasFPRegs16]>; 173 174} // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in' 175 176def : Pat<(bf16 (alignedload16 addrmode5fp16:$addr)), 177 (VLDRH addrmode5fp16:$addr)> { 178 let Predicates = [HasFPRegs16]; 179} 180def : Pat<(bf16 (alignedload16 addrmode3:$addr)), 181 (COPY_TO_REGCLASS (LDRH addrmode3:$addr), HPR)> { 182 let Predicates = [HasNoFPRegs16, IsARM]; 183} 184def : Pat<(bf16 (alignedload16 t2addrmode_imm12:$addr)), 185 (COPY_TO_REGCLASS (t2LDRHi12 t2addrmode_imm12:$addr), HPR)> { 186 let Predicates = [HasNoFPRegs16, IsThumb]; 187} 188 189def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr), 190 IIC_fpStore64, "vstr", "\t$Dd, $addr", 191 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>, 192 Requires<[HasFPRegs]>; 193 194def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), 195 IIC_fpStore32, "vstr", "\t$Sd, $addr", 196 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]>, 197 Requires<[HasFPRegs]> { 198 // Some single precision VFP instructions may be executed on both NEON and VFP 199 // pipelines. 200 let D = VFPNeonDomain; 201} 202 203let isUnpredicable = 1 in 204def VSTRH : AHI5<0b1101, 0b00, (outs), (ins HPR:$Sd, addrmode5fp16:$addr), 205 IIC_fpStore16, "vstr", ".16\t$Sd, $addr", 206 [(alignedstore16 (f16 HPR:$Sd), addrmode5fp16:$addr)]>, 207 Requires<[HasFPRegs16]>; 208 209def : Pat<(alignedstore16 (bf16 HPR:$Sd), addrmode5fp16:$addr), 210 (VSTRH (bf16 HPR:$Sd), addrmode5fp16:$addr)> { 211 let Predicates = [HasFPRegs16]; 212} 213def : Pat<(alignedstore16 (bf16 HPR:$Sd), addrmode3:$addr), 214 (STRH (COPY_TO_REGCLASS $Sd, GPR), addrmode3:$addr)> { 215 let Predicates = [HasNoFPRegs16, IsARM]; 216} 217def : Pat<(alignedstore16 (bf16 HPR:$Sd), t2addrmode_imm12:$addr), 218 (t2STRHi12 (COPY_TO_REGCLASS $Sd, GPR), t2addrmode_imm12:$addr)> { 219 let Predicates = [HasNoFPRegs16, IsThumb]; 220} 221 222//===----------------------------------------------------------------------===// 223// Load / store multiple Instructions. 224// 225 226multiclass vfp_ldst_mult<string asm, bit L_bit, 227 InstrItinClass itin, InstrItinClass itin_upd> { 228 let Predicates = [HasFPRegs] in { 229 // Double Precision 230 def DIA : 231 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 232 IndexModeNone, itin, 233 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 234 let Inst{24-23} = 0b01; // Increment After 235 let Inst{21} = 0; // No writeback 236 let Inst{20} = L_bit; 237 } 238 def DIA_UPD : 239 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 240 variable_ops), 241 IndexModeUpd, itin_upd, 242 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 243 let Inst{24-23} = 0b01; // Increment After 244 let Inst{21} = 1; // Writeback 245 let Inst{20} = L_bit; 246 } 247 def DDB_UPD : 248 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 249 variable_ops), 250 IndexModeUpd, itin_upd, 251 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 252 let Inst{24-23} = 0b10; // Decrement Before 253 let Inst{21} = 1; // Writeback 254 let Inst{20} = L_bit; 255 } 256 257 // Single Precision 258 def SIA : 259 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops), 260 IndexModeNone, itin, 261 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 262 let Inst{24-23} = 0b01; // Increment After 263 let Inst{21} = 0; // No writeback 264 let Inst{20} = L_bit; 265 266 // Some single precision VFP instructions may be executed on both NEON and 267 // VFP pipelines. 268 let D = VFPNeonDomain; 269 } 270 def SIA_UPD : 271 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 272 variable_ops), 273 IndexModeUpd, itin_upd, 274 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 275 let Inst{24-23} = 0b01; // Increment After 276 let Inst{21} = 1; // Writeback 277 let Inst{20} = L_bit; 278 279 // Some single precision VFP instructions may be executed on both NEON and 280 // VFP pipelines. 281 let D = VFPNeonDomain; 282 } 283 def SDB_UPD : 284 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 285 variable_ops), 286 IndexModeUpd, itin_upd, 287 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 288 let Inst{24-23} = 0b10; // Decrement Before 289 let Inst{21} = 1; // Writeback 290 let Inst{20} = L_bit; 291 292 // Some single precision VFP instructions may be executed on both NEON and 293 // VFP pipelines. 294 let D = VFPNeonDomain; 295 } 296 } 297} 298 299let hasSideEffects = 0 in { 300 301let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 302defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>; 303 304let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 305defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>; 306 307} // hasSideEffects 308 309def : MnemonicAlias<"vldm", "vldmia">; 310def : MnemonicAlias<"vstm", "vstmia">; 311 312 313//===----------------------------------------------------------------------===// 314// Lazy load / store multiple Instructions 315// 316def VLLDM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone, 317 NoItinerary, "vlldm${p}\t$Rn", "", []>, 318 Requires<[HasV8MMainline, Has8MSecExt]> { 319 let Inst{24-23} = 0b00; 320 let Inst{22} = 0; 321 let Inst{21} = 1; 322 let Inst{20} = 1; 323 let Inst{15-12} = 0; 324 let Inst{7-0} = 0; 325 let mayLoad = 1; 326 let Defs = [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, VPR, FPSCR, FPSCR_NZCV]; 327} 328 329def VLSTM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone, 330 NoItinerary, "vlstm${p}\t$Rn", "", []>, 331 Requires<[HasV8MMainline, Has8MSecExt]> { 332 let Inst{24-23} = 0b00; 333 let Inst{22} = 0; 334 let Inst{21} = 1; 335 let Inst{20} = 0; 336 let Inst{15-12} = 0; 337 let Inst{7-0} = 0; 338 let mayStore = 1; 339} 340 341def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r), 0>, 342 Requires<[HasFPRegs]>; 343def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r), 0>, 344 Requires<[HasFPRegs]>; 345def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r), 0>, 346 Requires<[HasFPRegs]>; 347def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r), 0>, 348 Requires<[HasFPRegs]>; 349defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 350 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>; 351defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 352 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>; 353defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 354 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>; 355defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 356 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>; 357 358// FLDMX, FSTMX - Load and store multiple unknown precision registers for 359// pre-armv6 cores. 360// These instruction are deprecated so we don't want them to get selected. 361// However, there is no UAL syntax for them, so we keep them around for 362// (dis)assembly only. 363multiclass vfp_ldstx_mult<string asm, bit L_bit> { 364 let Predicates = [HasFPRegs], hasNoSchedulingInfo = 1 in { 365 // Unknown precision 366 def XIA : 367 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 368 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> { 369 let Inst{24-23} = 0b01; // Increment After 370 let Inst{21} = 0; // No writeback 371 let Inst{20} = L_bit; 372 } 373 def XIA_UPD : 374 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 375 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 376 let Inst{24-23} = 0b01; // Increment After 377 let Inst{21} = 1; // Writeback 378 let Inst{20} = L_bit; 379 } 380 def XDB_UPD : 381 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 382 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 383 let Inst{24-23} = 0b10; // Decrement Before 384 let Inst{21} = 1; // Writeback 385 let Inst{20} = L_bit; 386 } 387 } 388} 389 390defm FLDM : vfp_ldstx_mult<"fldm", 1>; 391defm FSTM : vfp_ldstx_mult<"fstm", 0>; 392 393def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">; 394def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">; 395 396def : VFP2MnemonicAlias<"fstmeax", "fstmiax">; 397def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">; 398 399//===----------------------------------------------------------------------===// 400// FP Binary Operations. 401// 402 403let TwoOperandAliasConstraint = "$Dn = $Dd" in 404def VADDD : ADbI<0b11100, 0b11, 0, 0, 405 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 406 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", 407 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>, 408 Sched<[WriteFPALU64]>; 409 410let TwoOperandAliasConstraint = "$Sn = $Sd" in 411def VADDS : ASbIn<0b11100, 0b11, 0, 0, 412 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 413 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", 414 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>, 415 Sched<[WriteFPALU32]> { 416 // Some single precision VFP instructions may be executed on both NEON and 417 // VFP pipelines on A8. 418 let D = VFPNeonA8Domain; 419} 420 421let TwoOperandAliasConstraint = "$Sn = $Sd" in 422def VADDH : AHbI<0b11100, 0b11, 0, 0, 423 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 424 IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm", 425 [(set (f16 HPR:$Sd), (fadd (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, 426 Sched<[WriteFPALU32]>; 427 428let TwoOperandAliasConstraint = "$Dn = $Dd" in 429def VSUBD : ADbI<0b11100, 0b11, 1, 0, 430 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 431 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", 432 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>, 433 Sched<[WriteFPALU64]>; 434 435let TwoOperandAliasConstraint = "$Sn = $Sd" in 436def VSUBS : ASbIn<0b11100, 0b11, 1, 0, 437 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 438 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", 439 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>, 440 Sched<[WriteFPALU32]>{ 441 // Some single precision VFP instructions may be executed on both NEON and 442 // VFP pipelines on A8. 443 let D = VFPNeonA8Domain; 444} 445 446let TwoOperandAliasConstraint = "$Sn = $Sd" in 447def VSUBH : AHbI<0b11100, 0b11, 1, 0, 448 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 449 IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm", 450 [(set (f16 HPR:$Sd), (fsub (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, 451 Sched<[WriteFPALU32]>; 452 453let TwoOperandAliasConstraint = "$Dn = $Dd" in 454def VDIVD : ADbI<0b11101, 0b00, 0, 0, 455 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 456 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", 457 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>, 458 Sched<[WriteFPDIV64]>; 459 460let TwoOperandAliasConstraint = "$Sn = $Sd" in 461def VDIVS : ASbI<0b11101, 0b00, 0, 0, 462 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 463 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm", 464 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>, 465 Sched<[WriteFPDIV32]>; 466 467let TwoOperandAliasConstraint = "$Sn = $Sd" in 468def VDIVH : AHbI<0b11101, 0b00, 0, 0, 469 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 470 IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm", 471 [(set (f16 HPR:$Sd), (fdiv (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, 472 Sched<[WriteFPDIV32]>; 473 474let TwoOperandAliasConstraint = "$Dn = $Dd" in 475def VMULD : ADbI<0b11100, 0b10, 0, 0, 476 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 477 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm", 478 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>, 479 Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>; 480 481let TwoOperandAliasConstraint = "$Sn = $Sd" in 482def VMULS : ASbIn<0b11100, 0b10, 0, 0, 483 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 484 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm", 485 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>, 486 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]> { 487 // Some single precision VFP instructions may be executed on both NEON and 488 // VFP pipelines on A8. 489 let D = VFPNeonA8Domain; 490} 491 492let TwoOperandAliasConstraint = "$Sn = $Sd" in 493def VMULH : AHbI<0b11100, 0b10, 0, 0, 494 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 495 IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm", 496 [(set (f16 HPR:$Sd), (fmul (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, 497 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>; 498 499let TwoOperandAliasConstraint = "$Dn = $Dd" in 500def VNMULD : ADbI<0b11100, 0b10, 1, 0, 501 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 502 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm", 503 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>, 504 Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>; 505 506let TwoOperandAliasConstraint = "$Sn = $Sd" in 507def VNMULS : ASbI<0b11100, 0b10, 1, 0, 508 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 509 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm", 510 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>, 511 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]> { 512 // Some single precision VFP instructions may be executed on both NEON and 513 // VFP pipelines on A8. 514 let D = VFPNeonA8Domain; 515} 516 517let TwoOperandAliasConstraint = "$Sn = $Sd" in 518def VNMULH : AHbI<0b11100, 0b10, 1, 0, 519 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 520 IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm", 521 [(set (f16 HPR:$Sd), (fneg (fmul (f16 HPR:$Sn), (f16 HPR:$Sm))))]>, 522 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>; 523 524multiclass vsel_inst<string op, bits<2> opc, int CC> { 525 let DecoderNamespace = "VFPV8", PostEncoderMethod = "", 526 Uses = [CPSR], AddedComplexity = 4, isUnpredicable = 1 in { 527 def H : AHbInp<0b11100, opc, 0, 528 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 529 NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"), 530 [(set (f16 HPR:$Sd), (ARMcmov (f16 HPR:$Sm), (f16 HPR:$Sn), CC))]>, 531 Requires<[HasFullFP16]>; 532 533 def S : ASbInp<0b11100, opc, 0, 534 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 535 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"), 536 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>, 537 Requires<[HasFPARMv8]>; 538 539 def D : ADbInp<0b11100, opc, 0, 540 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 541 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"), 542 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>, 543 Requires<[HasFPARMv8, HasDPVFP]>; 544 } 545} 546 547// The CC constants here match ARMCC::CondCodes. 548defm VSELGT : vsel_inst<"gt", 0b11, 12>; 549defm VSELGE : vsel_inst<"ge", 0b10, 10>; 550defm VSELEQ : vsel_inst<"eq", 0b00, 0>; 551defm VSELVS : vsel_inst<"vs", 0b01, 6>; 552 553multiclass vmaxmin_inst<string op, bit opc, SDNode SD> { 554 let DecoderNamespace = "VFPV8", PostEncoderMethod = "", 555 isUnpredicable = 1 in { 556 def H : AHbInp<0b11101, 0b00, opc, 557 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 558 NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"), 559 [(set (f16 HPR:$Sd), (SD (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, 560 Requires<[HasFullFP16]>; 561 562 def S : ASbInp<0b11101, 0b00, opc, 563 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 564 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"), 565 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>, 566 Requires<[HasFPARMv8]>; 567 568 def D : ADbInp<0b11101, 0b00, opc, 569 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 570 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"), 571 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>, 572 Requires<[HasFPARMv8, HasDPVFP]>; 573 } 574} 575 576defm VFP_VMAXNM : vmaxmin_inst<"vmaxnm", 0, fmaxnum>; 577defm VFP_VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>; 578 579// Match reassociated forms only if not sign dependent rounding. 580def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)), 581 (VNMULD DPR:$a, DPR:$b)>, 582 Requires<[NoHonorSignDependentRounding,HasDPVFP]>; 583def : Pat<(fmul (fneg SPR:$a), SPR:$b), 584 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>; 585 586// These are encoded as unary instructions. 587let Defs = [FPSCR_NZCV] in { 588def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, 589 (outs), (ins DPR:$Dd, DPR:$Dm), 590 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", "", 591 [(arm_cmpfpe DPR:$Dd, (f64 DPR:$Dm))]>; 592 593def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, 594 (outs), (ins SPR:$Sd, SPR:$Sm), 595 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", "", 596 [(arm_cmpfpe SPR:$Sd, SPR:$Sm)]> { 597 // Some single precision VFP instructions may be executed on both NEON and 598 // VFP pipelines on A8. 599 let D = VFPNeonA8Domain; 600} 601 602def VCMPEH : AHuI<0b11101, 0b11, 0b0100, 0b11, 0, 603 (outs), (ins HPR:$Sd, HPR:$Sm), 604 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm", 605 [(arm_cmpfpe (f16 HPR:$Sd), (f16 HPR:$Sm))]>; 606 607def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, 608 (outs), (ins DPR:$Dd, DPR:$Dm), 609 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", "", 610 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>; 611 612def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, 613 (outs), (ins SPR:$Sd, SPR:$Sm), 614 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", "", 615 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> { 616 // Some single precision VFP instructions may be executed on both NEON and 617 // VFP pipelines on A8. 618 let D = VFPNeonA8Domain; 619} 620 621def VCMPH : AHuI<0b11101, 0b11, 0b0100, 0b01, 0, 622 (outs), (ins HPR:$Sd, HPR:$Sm), 623 IIC_fpCMP16, "vcmp", ".f16\t$Sd, $Sm", 624 [(arm_cmpfp (f16 HPR:$Sd), (f16 HPR:$Sm))]>; 625} // Defs = [FPSCR_NZCV] 626 627//===----------------------------------------------------------------------===// 628// FP Unary Operations. 629// 630 631def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, 632 (outs DPR:$Dd), (ins DPR:$Dm), 633 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm", "", 634 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>; 635 636def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0, 637 (outs SPR:$Sd), (ins SPR:$Sm), 638 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm", 639 [(set SPR:$Sd, (fabs SPR:$Sm))]> { 640 // Some single precision VFP instructions may be executed on both NEON and 641 // VFP pipelines on A8. 642 let D = VFPNeonA8Domain; 643} 644 645def VABSH : AHuI<0b11101, 0b11, 0b0000, 0b11, 0, 646 (outs HPR:$Sd), (ins HPR:$Sm), 647 IIC_fpUNA16, "vabs", ".f16\t$Sd, $Sm", 648 [(set (f16 HPR:$Sd), (fabs (f16 HPR:$Sm)))]>; 649 650let Defs = [FPSCR_NZCV] in { 651def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, 652 (outs), (ins DPR:$Dd), 653 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", "", 654 [(arm_cmpfpe0 (f64 DPR:$Dd))]> { 655 let Inst{3-0} = 0b0000; 656 let Inst{5} = 0; 657} 658 659def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, 660 (outs), (ins SPR:$Sd), 661 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", "", 662 [(arm_cmpfpe0 SPR:$Sd)]> { 663 let Inst{3-0} = 0b0000; 664 let Inst{5} = 0; 665 666 // Some single precision VFP instructions may be executed on both NEON and 667 // VFP pipelines on A8. 668 let D = VFPNeonA8Domain; 669} 670 671def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0, 672 (outs), (ins HPR:$Sd), 673 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, #0", 674 [(arm_cmpfpe0 (f16 HPR:$Sd))]> { 675 let Inst{3-0} = 0b0000; 676 let Inst{5} = 0; 677} 678 679def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, 680 (outs), (ins DPR:$Dd), 681 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", "", 682 [(arm_cmpfp0 (f64 DPR:$Dd))]> { 683 let Inst{3-0} = 0b0000; 684 let Inst{5} = 0; 685} 686 687def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, 688 (outs), (ins SPR:$Sd), 689 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", "", 690 [(arm_cmpfp0 SPR:$Sd)]> { 691 let Inst{3-0} = 0b0000; 692 let Inst{5} = 0; 693 694 // Some single precision VFP instructions may be executed on both NEON and 695 // VFP pipelines on A8. 696 let D = VFPNeonA8Domain; 697} 698 699def VCMPZH : AHuI<0b11101, 0b11, 0b0101, 0b01, 0, 700 (outs), (ins HPR:$Sd), 701 IIC_fpCMP16, "vcmp", ".f16\t$Sd, #0", 702 [(arm_cmpfp0 (f16 HPR:$Sd))]> { 703 let Inst{3-0} = 0b0000; 704 let Inst{5} = 0; 705} 706} // Defs = [FPSCR_NZCV] 707 708def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, 709 (outs DPR:$Dd), (ins SPR:$Sm), 710 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm", "", 711 [(set DPR:$Dd, (fpextend SPR:$Sm))]>, 712 Sched<[WriteFPCVT]> { 713 // Instruction operands. 714 bits<5> Dd; 715 bits<5> Sm; 716 717 // Encode instruction operands. 718 let Inst{3-0} = Sm{4-1}; 719 let Inst{5} = Sm{0}; 720 let Inst{15-12} = Dd{3-0}; 721 let Inst{22} = Dd{4}; 722 723 let Predicates = [HasVFP2, HasDPVFP]; 724 let hasSideEffects = 0; 725} 726 727// Special case encoding: bits 11-8 is 0b1011. 728def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm, 729 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", "", 730 [(set SPR:$Sd, (fpround DPR:$Dm))]>, 731 Sched<[WriteFPCVT]> { 732 // Instruction operands. 733 bits<5> Sd; 734 bits<5> Dm; 735 736 // Encode instruction operands. 737 let Inst{3-0} = Dm{3-0}; 738 let Inst{5} = Dm{4}; 739 let Inst{15-12} = Sd{4-1}; 740 let Inst{22} = Sd{0}; 741 742 let Inst{27-23} = 0b11101; 743 let Inst{21-16} = 0b110111; 744 let Inst{11-8} = 0b1011; 745 let Inst{7-6} = 0b11; 746 let Inst{4} = 0; 747 748 let Predicates = [HasVFP2, HasDPVFP]; 749 let hasSideEffects = 0; 750} 751 752// Between half, single and double-precision. 753let hasSideEffects = 0 in 754def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 755 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", "", 756 [/* Intentionally left blank, see patterns below */]>, 757 Requires<[HasFP16]>, 758 Sched<[WriteFPCVT]>; 759 760def : FP16Pat<(f32 (fpextend (f16 HPR:$Sm))), 761 (VCVTBHS (COPY_TO_REGCLASS (f16 HPR:$Sm), SPR))>; 762def : FP16Pat<(f16_to_fp GPR:$a), 763 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; 764 765let hasSideEffects = 0 in 766def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm), 767 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", "$Sd = $Sda", 768 [/* Intentionally left blank, see patterns below */]>, 769 Requires<[HasFP16]>, 770 Sched<[WriteFPCVT]>; 771 772def : FP16Pat<(f16 (fpround SPR:$Sm)), 773 (COPY_TO_REGCLASS (VCVTBSH (IMPLICIT_DEF), SPR:$Sm), HPR)>; 774def : FP16Pat<(fp_to_f16 SPR:$a), 775 (i32 (COPY_TO_REGCLASS (VCVTBSH (IMPLICIT_DEF), SPR:$a), GPR))>; 776def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane), 777 (v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1), 778 (VCVTBSH (EXTRACT_SUBREG (v8f16 MQPR:$src1), (SSubReg_f16_reg imm:$lane)), 779 SPR:$src2), 780 (SSubReg_f16_reg imm:$lane)))>; 781def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane), 782 (v4f16 (INSERT_SUBREG (v4f16 DPR:$src1), 783 (VCVTBSH (EXTRACT_SUBREG (v4f16 DPR:$src1), (SSubReg_f16_reg imm:$lane)), 784 SPR:$src2), 785 (SSubReg_f16_reg imm:$lane)))>; 786 787let hasSideEffects = 0 in 788def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 789 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", "", 790 [/* Intentionally left blank, see patterns below */]>, 791 Requires<[HasFP16]>, 792 Sched<[WriteFPCVT]>; 793 794def : FP16Pat<(f32 (fpextend (extractelt (v8f16 MQPR:$src), imm_odd:$lane))), 795 (VCVTTHS (EXTRACT_SUBREG MQPR:$src, (SSubReg_f16_reg imm_odd:$lane)))>; 796def : FP16Pat<(f32 (fpextend (extractelt (v4f16 DPR:$src), imm_odd:$lane))), 797 (VCVTTHS (EXTRACT_SUBREG 798 (v2f32 (COPY_TO_REGCLASS (v4f16 DPR:$src), DPR_VFP2)), 799 (SSubReg_f16_reg imm_odd:$lane)))>; 800 801let hasSideEffects = 0 in 802def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm), 803 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", "$Sd = $Sda", 804 [/* Intentionally left blank, see patterns below */]>, 805 Requires<[HasFP16]>, 806 Sched<[WriteFPCVT]>; 807 808def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane), 809 (v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1), 810 (VCVTTSH (EXTRACT_SUBREG (v8f16 MQPR:$src1), (SSubReg_f16_reg imm:$lane)), 811 SPR:$src2), 812 (SSubReg_f16_reg imm:$lane)))>; 813def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane), 814 (v4f16 (INSERT_SUBREG (v4f16 DPR:$src1), 815 (VCVTTSH (EXTRACT_SUBREG (v4f16 DPR:$src1), (SSubReg_f16_reg imm:$lane)), 816 SPR:$src2), 817 (SSubReg_f16_reg imm:$lane)))>; 818 819def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0, 820 (outs DPR:$Dd), (ins SPR:$Sm), 821 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm", "", 822 [/* Intentionally left blank, see patterns below */]>, 823 Requires<[HasFPARMv8, HasDPVFP]>, 824 Sched<[WriteFPCVT]> { 825 // Instruction operands. 826 bits<5> Sm; 827 828 // Encode instruction operands. 829 let Inst{3-0} = Sm{4-1}; 830 let Inst{5} = Sm{0}; 831 832 let hasSideEffects = 0; 833} 834 835def : FullFP16Pat<(f64 (fpextend (f16 HPR:$Sm))), 836 (VCVTBHD (COPY_TO_REGCLASS (f16 HPR:$Sm), SPR))>, 837 Requires<[HasFPARMv8, HasDPVFP]>; 838def : FP16Pat<(f64 (f16_to_fp GPR:$a)), 839 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>, 840 Requires<[HasFPARMv8, HasDPVFP]>; 841 842def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0, 843 (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm), 844 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm", "$Sd = $Sda", 845 [/* Intentionally left blank, see patterns below */]>, 846 Requires<[HasFPARMv8, HasDPVFP]> { 847 // Instruction operands. 848 bits<5> Sd; 849 bits<5> Dm; 850 851 // Encode instruction operands. 852 let Inst{3-0} = Dm{3-0}; 853 let Inst{5} = Dm{4}; 854 let Inst{15-12} = Sd{4-1}; 855 let Inst{22} = Sd{0}; 856 857 let hasSideEffects = 0; 858} 859 860def : FullFP16Pat<(f16 (fpround DPR:$Dm)), 861 (COPY_TO_REGCLASS (VCVTBDH (IMPLICIT_DEF), DPR:$Dm), HPR)>, 862 Requires<[HasFPARMv8, HasDPVFP]>; 863def : FP16Pat<(fp_to_f16 (f64 DPR:$a)), 864 (i32 (COPY_TO_REGCLASS (VCVTBDH (IMPLICIT_DEF), DPR:$a), GPR))>, 865 Requires<[HasFPARMv8, HasDPVFP]>; 866 867def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0, 868 (outs DPR:$Dd), (ins SPR:$Sm), 869 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm", "", 870 []>, Requires<[HasFPARMv8, HasDPVFP]> { 871 // Instruction operands. 872 bits<5> Sm; 873 874 // Encode instruction operands. 875 let Inst{3-0} = Sm{4-1}; 876 let Inst{5} = Sm{0}; 877 878 let hasSideEffects = 0; 879} 880 881def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0, 882 (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm), 883 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm", "$Sd = $Sda", 884 []>, Requires<[HasFPARMv8, HasDPVFP]> { 885 // Instruction operands. 886 bits<5> Sd; 887 bits<5> Dm; 888 889 // Encode instruction operands. 890 let Inst{15-12} = Sd{4-1}; 891 let Inst{22} = Sd{0}; 892 let Inst{3-0} = Dm{3-0}; 893 let Inst{5} = Dm{4}; 894 895 let hasSideEffects = 0; 896} 897 898multiclass vcvt_inst<string opc, bits<2> rm, 899 SDPatternOperator node = null_frag> { 900 let PostEncoderMethod = "", DecoderNamespace = "VFPV8", hasSideEffects = 0 in { 901 def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0, 902 (outs SPR:$Sd), (ins HPR:$Sm), 903 NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"), 904 []>, 905 Requires<[HasFullFP16]> { 906 let Inst{17-16} = rm; 907 } 908 909 def UH : AHuInp<0b11101, 0b11, 0b1100, 0b01, 0, 910 (outs SPR:$Sd), (ins HPR:$Sm), 911 NoItinerary, !strconcat("vcvt", opc, ".u32.f16\t$Sd, $Sm"), 912 []>, 913 Requires<[HasFullFP16]> { 914 let Inst{17-16} = rm; 915 } 916 917 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, 918 (outs SPR:$Sd), (ins SPR:$Sm), 919 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"), 920 []>, 921 Requires<[HasFPARMv8]> { 922 let Inst{17-16} = rm; 923 } 924 925 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, 926 (outs SPR:$Sd), (ins SPR:$Sm), 927 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"), 928 []>, 929 Requires<[HasFPARMv8]> { 930 let Inst{17-16} = rm; 931 } 932 933 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, 934 (outs SPR:$Sd), (ins DPR:$Dm), 935 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"), 936 []>, 937 Requires<[HasFPARMv8, HasDPVFP]> { 938 bits<5> Dm; 939 940 let Inst{17-16} = rm; 941 942 // Encode instruction operands. 943 let Inst{3-0} = Dm{3-0}; 944 let Inst{5} = Dm{4}; 945 let Inst{8} = 1; 946 } 947 948 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, 949 (outs SPR:$Sd), (ins DPR:$Dm), 950 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"), 951 []>, 952 Requires<[HasFPARMv8, HasDPVFP]> { 953 bits<5> Dm; 954 955 let Inst{17-16} = rm; 956 957 // Encode instruction operands 958 let Inst{3-0} = Dm{3-0}; 959 let Inst{5} = Dm{4}; 960 let Inst{8} = 1; 961 } 962 } 963 964 let Predicates = [HasFPARMv8] in { 965 let Predicates = [HasFullFP16] in { 966 def : Pat<(i32 (fp_to_sint (node (f16 HPR:$a)))), 967 (COPY_TO_REGCLASS 968 (!cast<Instruction>(NAME#"SH") (f16 HPR:$a)), 969 GPR)>; 970 971 def : Pat<(i32 (fp_to_uint (node (f16 HPR:$a)))), 972 (COPY_TO_REGCLASS 973 (!cast<Instruction>(NAME#"UH") (f16 HPR:$a)), 974 GPR)>; 975 } 976 def : Pat<(i32 (fp_to_sint (node SPR:$a))), 977 (COPY_TO_REGCLASS 978 (!cast<Instruction>(NAME#"SS") SPR:$a), 979 GPR)>; 980 def : Pat<(i32 (fp_to_uint (node SPR:$a))), 981 (COPY_TO_REGCLASS 982 (!cast<Instruction>(NAME#"US") SPR:$a), 983 GPR)>; 984 } 985 let Predicates = [HasFPARMv8, HasDPVFP] in { 986 def : Pat<(i32 (fp_to_sint (node (f64 DPR:$a)))), 987 (COPY_TO_REGCLASS 988 (!cast<Instruction>(NAME#"SD") DPR:$a), 989 GPR)>; 990 def : Pat<(i32 (fp_to_uint (node (f64 DPR:$a)))), 991 (COPY_TO_REGCLASS 992 (!cast<Instruction>(NAME#"UD") DPR:$a), 993 GPR)>; 994 } 995} 996 997defm VCVTA : vcvt_inst<"a", 0b00, fround>; 998defm VCVTN : vcvt_inst<"n", 0b01>; 999defm VCVTP : vcvt_inst<"p", 0b10, fceil>; 1000defm VCVTM : vcvt_inst<"m", 0b11, ffloor>; 1001 1002def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, 1003 (outs DPR:$Dd), (ins DPR:$Dm), 1004 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", "", 1005 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>; 1006 1007def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0, 1008 (outs SPR:$Sd), (ins SPR:$Sm), 1009 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", 1010 [(set SPR:$Sd, (fneg SPR:$Sm))]> { 1011 // Some single precision VFP instructions may be executed on both NEON and 1012 // VFP pipelines on A8. 1013 let D = VFPNeonA8Domain; 1014} 1015 1016def VNEGH : AHuI<0b11101, 0b11, 0b0001, 0b01, 0, 1017 (outs HPR:$Sd), (ins HPR:$Sm), 1018 IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm", 1019 [(set (f16 HPR:$Sd), (fneg (f16 HPR:$Sm)))]>; 1020 1021multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> { 1022 def H : AHuI<0b11101, 0b11, 0b0110, 0b11, 0, 1023 (outs HPR:$Sd), (ins HPR:$Sm), 1024 NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm", 1025 [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>, 1026 Requires<[HasFullFP16]> { 1027 let Inst{7} = op2; 1028 let Inst{16} = op; 1029 } 1030 1031 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0, 1032 (outs SPR:$Sd), (ins SPR:$Sm), 1033 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm", "", 1034 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>, 1035 Requires<[HasFPARMv8]> { 1036 let Inst{7} = op2; 1037 let Inst{16} = op; 1038 } 1039 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0, 1040 (outs DPR:$Dd), (ins DPR:$Dm), 1041 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm", "", 1042 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>, 1043 Requires<[HasFPARMv8, HasDPVFP]> { 1044 let Inst{7} = op2; 1045 let Inst{16} = op; 1046 } 1047 1048 def : InstAlias<!strconcat("vrint", opc, "$p.f16.f16\t$Sd, $Sm"), 1049 (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>, 1050 Requires<[HasFullFP16]>; 1051 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"), 1052 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p), 0>, 1053 Requires<[HasFPARMv8]>; 1054 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"), 1055 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p), 0>, 1056 Requires<[HasFPARMv8,HasDPVFP]>; 1057} 1058 1059defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc>; 1060defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint>; 1061defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>; 1062 1063multiclass vrint_inst_anpm<string opc, bits<2> rm, 1064 SDPatternOperator node = null_frag> { 1065 let PostEncoderMethod = "", DecoderNamespace = "VFPV8", 1066 isUnpredicable = 1 in { 1067 def H : AHuInp<0b11101, 0b11, 0b1000, 0b01, 0, 1068 (outs HPR:$Sd), (ins HPR:$Sm), 1069 NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"), 1070 [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>, 1071 Requires<[HasFullFP16]> { 1072 let Inst{17-16} = rm; 1073 } 1074 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0, 1075 (outs SPR:$Sd), (ins SPR:$Sm), 1076 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"), 1077 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>, 1078 Requires<[HasFPARMv8]> { 1079 let Inst{17-16} = rm; 1080 } 1081 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0, 1082 (outs DPR:$Dd), (ins DPR:$Dm), 1083 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"), 1084 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>, 1085 Requires<[HasFPARMv8, HasDPVFP]> { 1086 let Inst{17-16} = rm; 1087 } 1088 } 1089 1090 def : InstAlias<!strconcat("vrint", opc, ".f16.f16\t$Sd, $Sm"), 1091 (!cast<Instruction>(NAME#"H") HPR:$Sd, HPR:$Sm), 0>, 1092 Requires<[HasFullFP16]>; 1093 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"), 1094 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>, 1095 Requires<[HasFPARMv8]>; 1096 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"), 1097 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm), 0>, 1098 Requires<[HasFPARMv8,HasDPVFP]>; 1099} 1100 1101defm VRINTA : vrint_inst_anpm<"a", 0b00, fround>; 1102defm VRINTN : vrint_inst_anpm<"n", 0b01, int_arm_neon_vrintn>; 1103defm VRINTP : vrint_inst_anpm<"p", 0b10, fceil>; 1104defm VRINTM : vrint_inst_anpm<"m", 0b11, ffloor>; 1105 1106def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, 1107 (outs DPR:$Dd), (ins DPR:$Dm), 1108 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", "", 1109 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>, 1110 Sched<[WriteFPSQRT64]>; 1111 1112def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, 1113 (outs SPR:$Sd), (ins SPR:$Sm), 1114 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", "", 1115 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>, 1116 Sched<[WriteFPSQRT32]>; 1117 1118def VSQRTH : AHuI<0b11101, 0b11, 0b0001, 0b11, 0, 1119 (outs HPR:$Sd), (ins HPR:$Sm), 1120 IIC_fpSQRT16, "vsqrt", ".f16\t$Sd, $Sm", 1121 [(set (f16 HPR:$Sd), (fsqrt (f16 HPR:$Sm)))]>; 1122 1123let hasSideEffects = 0 in { 1124let isMoveReg = 1 in { 1125def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0, 1126 (outs DPR:$Dd), (ins DPR:$Dm), 1127 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", "", []>, 1128 Requires<[HasFPRegs64]>; 1129 1130def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0, 1131 (outs SPR:$Sd), (ins SPR:$Sm), 1132 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", "", []>, 1133 Requires<[HasFPRegs]>; 1134} // isMoveReg 1135 1136let PostEncoderMethod = "", DecoderNamespace = "VFPV8", isUnpredicable = 1 in { 1137def VMOVH : ASuInp<0b11101, 0b11, 0b0000, 0b01, 0, 1138 (outs SPR:$Sd), (ins SPR:$Sm), 1139 IIC_fpUNA16, "vmovx.f16\t$Sd, $Sm", []>, 1140 Requires<[HasFullFP16]>; 1141 1142def VINSH : ASuInp<0b11101, 0b11, 0b0000, 0b11, 0, 1143 (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm), 1144 IIC_fpUNA16, "vins.f16\t$Sd, $Sm", []>, 1145 Requires<[HasFullFP16]> { 1146 let Constraints = "$Sd = $Sda"; 1147} 1148 1149} // PostEncoderMethod 1150} // hasSideEffects 1151 1152//===----------------------------------------------------------------------===// 1153// FP <-> GPR Copies. Int <-> FP Conversions. 1154// 1155 1156let isMoveReg = 1 in { 1157def VMOVRS : AVConv2I<0b11100001, 0b1010, 1158 (outs GPR:$Rt), (ins SPR:$Sn), 1159 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn", 1160 [(set GPR:$Rt, (bitconvert SPR:$Sn))]>, 1161 Requires<[HasFPRegs]>, 1162 Sched<[WriteFPMOV]> { 1163 // Instruction operands. 1164 bits<4> Rt; 1165 bits<5> Sn; 1166 1167 // Encode instruction operands. 1168 let Inst{19-16} = Sn{4-1}; 1169 let Inst{7} = Sn{0}; 1170 let Inst{15-12} = Rt; 1171 1172 let Inst{6-5} = 0b00; 1173 let Inst{3-0} = 0b0000; 1174 1175 // Some single precision VFP instructions may be executed on both NEON and VFP 1176 // pipelines. 1177 let D = VFPNeonDomain; 1178} 1179 1180// Bitcast i32 -> f32. NEON prefers to use VMOVDRR. 1181def VMOVSR : AVConv4I<0b11100000, 0b1010, 1182 (outs SPR:$Sn), (ins GPR:$Rt), 1183 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt", 1184 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>, 1185 Requires<[HasFPRegs, UseVMOVSR]>, 1186 Sched<[WriteFPMOV]> { 1187 // Instruction operands. 1188 bits<5> Sn; 1189 bits<4> Rt; 1190 1191 // Encode instruction operands. 1192 let Inst{19-16} = Sn{4-1}; 1193 let Inst{7} = Sn{0}; 1194 let Inst{15-12} = Rt; 1195 1196 let Inst{6-5} = 0b00; 1197 let Inst{3-0} = 0b0000; 1198 1199 // Some single precision VFP instructions may be executed on both NEON and VFP 1200 // pipelines. 1201 let D = VFPNeonDomain; 1202} 1203} // isMoveReg 1204def : Pat<(arm_vmovsr GPR:$Rt), (VMOVSR GPR:$Rt)>, Requires<[HasFPRegs, UseVMOVSR]>; 1205 1206let hasSideEffects = 0 in { 1207def VMOVRRD : AVConv3I<0b11000101, 0b1011, 1208 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm), 1209 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm", 1210 [(set GPR:$Rt, GPR:$Rt2, (arm_fmrrd DPR:$Dm))]>, 1211 Requires<[HasFPRegs]>, 1212 Sched<[WriteFPMOV]> { 1213 // Instruction operands. 1214 bits<5> Dm; 1215 bits<4> Rt; 1216 bits<4> Rt2; 1217 1218 // Encode instruction operands. 1219 let Inst{3-0} = Dm{3-0}; 1220 let Inst{5} = Dm{4}; 1221 let Inst{15-12} = Rt; 1222 let Inst{19-16} = Rt2; 1223 1224 let Inst{7-6} = 0b00; 1225 1226 // Some single precision VFP instructions may be executed on both NEON and VFP 1227 // pipelines. 1228 let D = VFPNeonDomain; 1229 1230 // This instruction is equivalent to 1231 // $Rt = EXTRACT_SUBREG $Dm, ssub_0 1232 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1 1233 let isExtractSubreg = 1; 1234} 1235 1236def VMOVRRS : AVConv3I<0b11000101, 0b1010, 1237 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2), 1238 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2", 1239 [/* For disassembly only; pattern left blank */]>, 1240 Requires<[HasFPRegs]>, 1241 Sched<[WriteFPMOV]> { 1242 bits<5> src1; 1243 bits<4> Rt; 1244 bits<4> Rt2; 1245 1246 // Encode instruction operands. 1247 let Inst{3-0} = src1{4-1}; 1248 let Inst{5} = src1{0}; 1249 let Inst{15-12} = Rt; 1250 let Inst{19-16} = Rt2; 1251 1252 let Inst{7-6} = 0b00; 1253 1254 // Some single precision VFP instructions may be executed on both NEON and VFP 1255 // pipelines. 1256 let D = VFPNeonDomain; 1257 let DecoderMethod = "DecodeVMOVRRS"; 1258} 1259} // hasSideEffects 1260 1261// FMDHR: GPR -> SPR 1262// FMDLR: GPR -> SPR 1263 1264def VMOVDRR : AVConv5I<0b11000100, 0b1011, 1265 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2), 1266 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2", 1267 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]>, 1268 Requires<[HasFPRegs]>, 1269 Sched<[WriteFPMOV]> { 1270 // Instruction operands. 1271 bits<5> Dm; 1272 bits<4> Rt; 1273 bits<4> Rt2; 1274 1275 // Encode instruction operands. 1276 let Inst{3-0} = Dm{3-0}; 1277 let Inst{5} = Dm{4}; 1278 let Inst{15-12} = Rt; 1279 let Inst{19-16} = Rt2; 1280 1281 let Inst{7-6} = 0b00; 1282 1283 // Some single precision VFP instructions may be executed on both NEON and VFP 1284 // pipelines. 1285 let D = VFPNeonDomain; 1286 1287 // This instruction is equivalent to 1288 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1 1289 let isRegSequence = 1; 1290} 1291 1292// Hoist an fabs or a fneg of a value coming from integer registers 1293// and do the fabs/fneg on the integer value. This is never a lose 1294// and could enable the conversion to float to be removed completely. 1295def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)), 1296 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>, 1297 Requires<[IsARM, HasV6T2]>; 1298def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)), 1299 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>, 1300 Requires<[IsThumb2, HasV6T2]>; 1301def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)), 1302 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>, 1303 Requires<[IsARM]>; 1304def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)), 1305 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>, 1306 Requires<[IsThumb2]>; 1307 1308let hasSideEffects = 0 in 1309def VMOVSRR : AVConv5I<0b11000100, 0b1010, 1310 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2), 1311 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2", 1312 [/* For disassembly only; pattern left blank */]>, 1313 Requires<[HasFPRegs]>, 1314 Sched<[WriteFPMOV]> { 1315 // Instruction operands. 1316 bits<5> dst1; 1317 bits<4> src1; 1318 bits<4> src2; 1319 1320 // Encode instruction operands. 1321 let Inst{3-0} = dst1{4-1}; 1322 let Inst{5} = dst1{0}; 1323 let Inst{15-12} = src1; 1324 let Inst{19-16} = src2; 1325 1326 let Inst{7-6} = 0b00; 1327 1328 // Some single precision VFP instructions may be executed on both NEON and VFP 1329 // pipelines. 1330 let D = VFPNeonDomain; 1331 1332 let DecoderMethod = "DecodeVMOVSRR"; 1333} 1334 1335// Move H->R, clearing top 16 bits 1336def VMOVRH : AVConv2I<0b11100001, 0b1001, 1337 (outs rGPR:$Rt), (ins HPR:$Sn), 1338 IIC_fpMOVSI, "vmov", ".f16\t$Rt, $Sn", 1339 []>, 1340 Requires<[HasFPRegs16]>, 1341 Sched<[WriteFPMOV]> { 1342 // Instruction operands. 1343 bits<4> Rt; 1344 bits<5> Sn; 1345 1346 // Encode instruction operands. 1347 let Inst{19-16} = Sn{4-1}; 1348 let Inst{7} = Sn{0}; 1349 let Inst{15-12} = Rt; 1350 1351 let Inst{6-5} = 0b00; 1352 let Inst{3-0} = 0b0000; 1353 1354 let isUnpredicable = 1; 1355} 1356 1357// Move R->H, clearing top 16 bits 1358def VMOVHR : AVConv4I<0b11100000, 0b1001, 1359 (outs HPR:$Sn), (ins rGPR:$Rt), 1360 IIC_fpMOVIS, "vmov", ".f16\t$Sn, $Rt", 1361 []>, 1362 Requires<[HasFPRegs16]>, 1363 Sched<[WriteFPMOV]> { 1364 // Instruction operands. 1365 bits<5> Sn; 1366 bits<4> Rt; 1367 1368 // Encode instruction operands. 1369 let Inst{19-16} = Sn{4-1}; 1370 let Inst{7} = Sn{0}; 1371 let Inst{15-12} = Rt; 1372 1373 let Inst{6-5} = 0b00; 1374 let Inst{3-0} = 0b0000; 1375 1376 let isUnpredicable = 1; 1377} 1378 1379def : FPRegs16Pat<(arm_vmovrh (f16 HPR:$Sn)), (VMOVRH (f16 HPR:$Sn))>; 1380def : FPRegs16Pat<(arm_vmovrh (bf16 HPR:$Sn)), (VMOVRH (bf16 HPR:$Sn))>; 1381def : FPRegs16Pat<(f16 (arm_vmovhr rGPR:$Rt)), (VMOVHR rGPR:$Rt)>; 1382def : FPRegs16Pat<(bf16 (arm_vmovhr rGPR:$Rt)), (VMOVHR rGPR:$Rt)>; 1383 1384// FMRDH: SPR -> GPR 1385// FMRDL: SPR -> GPR 1386// FMRRS: SPR -> GPR 1387// FMRX: SPR system reg -> GPR 1388// FMSRR: GPR -> SPR 1389// FMXR: GPR -> VFP system reg 1390 1391 1392// Int -> FP: 1393 1394class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1395 bits<4> opcod4, dag oops, dag iops, 1396 InstrItinClass itin, string opc, string asm, 1397 list<dag> pattern> 1398 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1399 pattern> { 1400 // Instruction operands. 1401 bits<5> Dd; 1402 bits<5> Sm; 1403 1404 // Encode instruction operands. 1405 let Inst{3-0} = Sm{4-1}; 1406 let Inst{5} = Sm{0}; 1407 let Inst{15-12} = Dd{3-0}; 1408 let Inst{22} = Dd{4}; 1409 1410 let Predicates = [HasVFP2, HasDPVFP]; 1411 let hasSideEffects = 0; 1412} 1413 1414class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1415 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin, 1416 string opc, string asm, list<dag> pattern> 1417 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1418 pattern> { 1419 // Instruction operands. 1420 bits<5> Sd; 1421 bits<5> Sm; 1422 1423 // Encode instruction operands. 1424 let Inst{3-0} = Sm{4-1}; 1425 let Inst{5} = Sm{0}; 1426 let Inst{15-12} = Sd{4-1}; 1427 let Inst{22} = Sd{0}; 1428 1429 let hasSideEffects = 0; 1430} 1431 1432class AVConv1IHs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1433 bits<4> opcod4, dag oops, dag iops, 1434 InstrItinClass itin, string opc, string asm, 1435 list<dag> pattern> 1436 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1437 pattern> { 1438 // Instruction operands. 1439 bits<5> Sd; 1440 bits<5> Sm; 1441 1442 // Encode instruction operands. 1443 let Inst{3-0} = Sm{4-1}; 1444 let Inst{5} = Sm{0}; 1445 let Inst{15-12} = Sd{4-1}; 1446 let Inst{22} = Sd{0}; 1447 1448 let Predicates = [HasFullFP16]; 1449 let hasSideEffects = 0; 1450} 1451 1452def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 1453 (outs DPR:$Dd), (ins SPR:$Sm), 1454 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm", 1455 []>, 1456 Sched<[WriteFPCVT]> { 1457 let Inst{7} = 1; // s32 1458} 1459 1460let Predicates=[HasVFP2, HasDPVFP] in { 1461 def : VFPPat<(f64 (sint_to_fp GPR:$a)), 1462 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>; 1463 1464 def : VFPPat<(f64 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1465 (VSITOD (VLDRS addrmode5:$a))>; 1466} 1467 1468def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 1469 (outs SPR:$Sd),(ins SPR:$Sm), 1470 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm", 1471 []>, 1472 Sched<[WriteFPCVT]> { 1473 let Inst{7} = 1; // s32 1474 1475 // Some single precision VFP instructions may be executed on both NEON and 1476 // VFP pipelines on A8. 1477 let D = VFPNeonA8Domain; 1478} 1479 1480def : VFPNoNEONPat<(f32 (sint_to_fp GPR:$a)), 1481 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>; 1482 1483def : VFPNoNEONPat<(f32 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1484 (VSITOS (VLDRS addrmode5:$a))>; 1485 1486def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001, 1487 (outs HPR:$Sd), (ins SPR:$Sm), 1488 IIC_fpCVTIH, "vcvt", ".f16.s32\t$Sd, $Sm", 1489 []>, 1490 Sched<[WriteFPCVT]> { 1491 let Inst{7} = 1; // s32 1492 let isUnpredicable = 1; 1493} 1494 1495def : VFPNoNEONPat<(f16 (sint_to_fp GPR:$a)), 1496 (VSITOH (COPY_TO_REGCLASS GPR:$a, SPR))>; 1497 1498def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 1499 (outs DPR:$Dd), (ins SPR:$Sm), 1500 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm", 1501 []>, 1502 Sched<[WriteFPCVT]> { 1503 let Inst{7} = 0; // u32 1504} 1505 1506let Predicates=[HasVFP2, HasDPVFP] in { 1507 def : VFPPat<(f64 (uint_to_fp GPR:$a)), 1508 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>; 1509 1510 def : VFPPat<(f64 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1511 (VUITOD (VLDRS addrmode5:$a))>; 1512} 1513 1514def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 1515 (outs SPR:$Sd), (ins SPR:$Sm), 1516 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm", 1517 []>, 1518 Sched<[WriteFPCVT]> { 1519 let Inst{7} = 0; // u32 1520 1521 // Some single precision VFP instructions may be executed on both NEON and 1522 // VFP pipelines on A8. 1523 let D = VFPNeonA8Domain; 1524} 1525 1526def : VFPNoNEONPat<(f32 (uint_to_fp GPR:$a)), 1527 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>; 1528 1529def : VFPNoNEONPat<(f32 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1530 (VUITOS (VLDRS addrmode5:$a))>; 1531 1532def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001, 1533 (outs HPR:$Sd), (ins SPR:$Sm), 1534 IIC_fpCVTIH, "vcvt", ".f16.u32\t$Sd, $Sm", 1535 []>, 1536 Sched<[WriteFPCVT]> { 1537 let Inst{7} = 0; // u32 1538 let isUnpredicable = 1; 1539} 1540 1541def : VFPNoNEONPat<(f16 (uint_to_fp GPR:$a)), 1542 (VUITOH (COPY_TO_REGCLASS GPR:$a, SPR))>; 1543 1544// FP -> Int: 1545 1546class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1547 bits<4> opcod4, dag oops, dag iops, 1548 InstrItinClass itin, string opc, string asm, 1549 list<dag> pattern> 1550 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1551 pattern> { 1552 // Instruction operands. 1553 bits<5> Sd; 1554 bits<5> Dm; 1555 1556 // Encode instruction operands. 1557 let Inst{3-0} = Dm{3-0}; 1558 let Inst{5} = Dm{4}; 1559 let Inst{15-12} = Sd{4-1}; 1560 let Inst{22} = Sd{0}; 1561 1562 let Predicates = [HasVFP2, HasDPVFP]; 1563 let hasSideEffects = 0; 1564} 1565 1566class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1567 bits<4> opcod4, dag oops, dag iops, 1568 InstrItinClass itin, string opc, string asm, 1569 list<dag> pattern> 1570 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1571 pattern> { 1572 // Instruction operands. 1573 bits<5> Sd; 1574 bits<5> Sm; 1575 1576 // Encode instruction operands. 1577 let Inst{3-0} = Sm{4-1}; 1578 let Inst{5} = Sm{0}; 1579 let Inst{15-12} = Sd{4-1}; 1580 let Inst{22} = Sd{0}; 1581 1582 let hasSideEffects = 0; 1583} 1584 1585class AVConv1IsH_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1586 bits<4> opcod4, dag oops, dag iops, 1587 InstrItinClass itin, string opc, string asm, 1588 list<dag> pattern> 1589 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1590 pattern> { 1591 // Instruction operands. 1592 bits<5> Sd; 1593 bits<5> Sm; 1594 1595 // Encode instruction operands. 1596 let Inst{3-0} = Sm{4-1}; 1597 let Inst{5} = Sm{0}; 1598 let Inst{15-12} = Sd{4-1}; 1599 let Inst{22} = Sd{0}; 1600 1601 let Predicates = [HasFullFP16]; 1602 let hasSideEffects = 0; 1603} 1604 1605// Always set Z bit in the instruction, i.e. "round towards zero" variants. 1606def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 1607 (outs SPR:$Sd), (ins DPR:$Dm), 1608 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm", 1609 []>, 1610 Sched<[WriteFPCVT]> { 1611 let Inst{7} = 1; // Z bit 1612} 1613 1614let Predicates=[HasVFP2, HasDPVFP] in { 1615 def : VFPPat<(i32 (fp_to_sint (f64 DPR:$a))), 1616 (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>; 1617 def : VFPPat<(i32 (fp_to_sint_sat (f64 DPR:$a), i32)), 1618 (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>; 1619 1620 def : VFPPat<(alignedstore32 (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr), 1621 (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>; 1622 def : VFPPat<(alignedstore32 (i32 (fp_to_sint_sat (f64 DPR:$a), i32)), addrmode5:$ptr), 1623 (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>; 1624} 1625 1626def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 1627 (outs SPR:$Sd), (ins SPR:$Sm), 1628 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm", 1629 []>, 1630 Sched<[WriteFPCVT]> { 1631 let Inst{7} = 1; // Z bit 1632 1633 // Some single precision VFP instructions may be executed on both NEON and 1634 // VFP pipelines on A8. 1635 let D = VFPNeonA8Domain; 1636} 1637 1638def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)), 1639 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>; 1640def : VFPPat<(i32 (fp_to_sint_sat SPR:$a, i32)), 1641 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>; 1642 1643def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))), 1644 addrmode5:$ptr), 1645 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>; 1646def : VFPPat<(alignedstore32 (i32 (fp_to_sint_sat (f32 SPR:$a), i32)), 1647 addrmode5:$ptr), 1648 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>; 1649 1650def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001, 1651 (outs SPR:$Sd), (ins HPR:$Sm), 1652 IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm", 1653 []>, 1654 Sched<[WriteFPCVT]> { 1655 let Inst{7} = 1; // Z bit 1656 let isUnpredicable = 1; 1657} 1658 1659def : VFPNoNEONPat<(i32 (fp_to_sint (f16 HPR:$a))), 1660 (COPY_TO_REGCLASS (VTOSIZH (f16 HPR:$a)), GPR)>; 1661def : VFPPat<(i32 (fp_to_sint_sat (f16 HPR:$a), i32)), 1662 (COPY_TO_REGCLASS (VTOSIZH (f16 HPR:$a)), GPR)>; 1663 1664def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 1665 (outs SPR:$Sd), (ins DPR:$Dm), 1666 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm", 1667 []>, 1668 Sched<[WriteFPCVT]> { 1669 let Inst{7} = 1; // Z bit 1670} 1671 1672let Predicates=[HasVFP2, HasDPVFP] in { 1673 def : VFPPat<(i32 (fp_to_uint (f64 DPR:$a))), 1674 (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>; 1675 def : VFPPat<(i32 (fp_to_uint_sat (f64 DPR:$a), i32)), 1676 (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>; 1677 1678 def : VFPPat<(alignedstore32 (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr), 1679 (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>; 1680 def : VFPPat<(alignedstore32 (i32 (fp_to_uint_sat (f64 DPR:$a), i32)), addrmode5:$ptr), 1681 (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>; 1682} 1683 1684def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 1685 (outs SPR:$Sd), (ins SPR:$Sm), 1686 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm", 1687 []>, 1688 Sched<[WriteFPCVT]> { 1689 let Inst{7} = 1; // Z bit 1690 1691 // Some single precision VFP instructions may be executed on both NEON and 1692 // VFP pipelines on A8. 1693 let D = VFPNeonA8Domain; 1694} 1695 1696def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)), 1697 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>; 1698def : VFPPat<(i32 (fp_to_uint_sat SPR:$a, i32)), 1699 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>; 1700 1701def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))), 1702 addrmode5:$ptr), 1703 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>; 1704def : VFPPat<(alignedstore32 (i32 (fp_to_uint_sat (f32 SPR:$a), i32)), 1705 addrmode5:$ptr), 1706 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>; 1707 1708def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001, 1709 (outs SPR:$Sd), (ins HPR:$Sm), 1710 IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm", 1711 []>, 1712 Sched<[WriteFPCVT]> { 1713 let Inst{7} = 1; // Z bit 1714 let isUnpredicable = 1; 1715} 1716 1717def : VFPNoNEONPat<(i32 (fp_to_uint (f16 HPR:$a))), 1718 (COPY_TO_REGCLASS (VTOUIZH (f16 HPR:$a)), GPR)>; 1719def : VFPPat<(i32 (fp_to_uint_sat (f16 HPR:$a), i32)), 1720 (COPY_TO_REGCLASS (VTOUIZH (f16 HPR:$a)), GPR)>; 1721 1722// And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR. 1723let Uses = [FPSCR] in { 1724def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 1725 (outs SPR:$Sd), (ins DPR:$Dm), 1726 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm", 1727 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>, 1728 Sched<[WriteFPCVT]> { 1729 let Inst{7} = 0; // Z bit 1730} 1731 1732def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 1733 (outs SPR:$Sd), (ins SPR:$Sm), 1734 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm", 1735 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]>, 1736 Sched<[WriteFPCVT]> { 1737 let Inst{7} = 0; // Z bit 1738} 1739 1740def VTOSIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001, 1741 (outs SPR:$Sd), (ins SPR:$Sm), 1742 IIC_fpCVTHI, "vcvtr", ".s32.f16\t$Sd, $Sm", 1743 []>, 1744 Sched<[WriteFPCVT]> { 1745 let Inst{7} = 0; // Z bit 1746 let isUnpredicable = 1; 1747} 1748 1749def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 1750 (outs SPR:$Sd), (ins DPR:$Dm), 1751 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm", 1752 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>, 1753 Sched<[WriteFPCVT]> { 1754 let Inst{7} = 0; // Z bit 1755} 1756 1757def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 1758 (outs SPR:$Sd), (ins SPR:$Sm), 1759 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm", 1760 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]>, 1761 Sched<[WriteFPCVT]> { 1762 let Inst{7} = 0; // Z bit 1763} 1764 1765def VTOUIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001, 1766 (outs SPR:$Sd), (ins SPR:$Sm), 1767 IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm", 1768 []>, 1769 Sched<[WriteFPCVT]> { 1770 let Inst{7} = 0; // Z bit 1771 let isUnpredicable = 1; 1772} 1773} 1774 1775// v8.3-a Javascript Convert to Signed fixed-point 1776def VJCVT : AVConv1IsD_Encode<0b11101, 0b11, 0b1001, 0b1011, 1777 (outs SPR:$Sd), (ins DPR:$Dm), 1778 IIC_fpCVTDI, "vjcvt", ".s32.f64\t$Sd, $Dm", 1779 []>, 1780 Requires<[HasFPARMv8, HasV8_3a]> { 1781 let Inst{7} = 1; // Z bit 1782} 1783 1784// Convert between floating-point and fixed-point 1785// Data type for fixed-point naming convention: 1786// S16 (U=0, sx=0) -> SH 1787// U16 (U=1, sx=0) -> UH 1788// S32 (U=0, sx=1) -> SL 1789// U32 (U=1, sx=1) -> UL 1790 1791let Constraints = "$a = $dst" in { 1792 1793// FP to Fixed-Point: 1794 1795// Single Precision register 1796class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 1797 bit op5, dag oops, dag iops, InstrItinClass itin, 1798 string opc, string asm, list<dag> pattern> 1799 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> { 1800 bits<5> dst; 1801 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 1802 let Inst{22} = dst{0}; 1803 let Inst{15-12} = dst{4-1}; 1804 1805 let hasSideEffects = 0; 1806} 1807 1808// Double Precision register 1809class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 1810 bit op5, dag oops, dag iops, InstrItinClass itin, 1811 string opc, string asm, list<dag> pattern> 1812 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> { 1813 bits<5> dst; 1814 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 1815 let Inst{22} = dst{4}; 1816 let Inst{15-12} = dst{3-0}; 1817 1818 let hasSideEffects = 0; 1819 let Predicates = [HasVFP2, HasDPVFP]; 1820} 1821 1822let isUnpredicable = 1 in { 1823 1824def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0, 1825 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1826 IIC_fpCVTHI, "vcvt", ".s16.f16\t$dst, $a, $fbits", []>, 1827 Requires<[HasFullFP16]>, 1828 Sched<[WriteFPCVT]>; 1829 1830def VTOUHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 0, 1831 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1832 IIC_fpCVTHI, "vcvt", ".u16.f16\t$dst, $a, $fbits", []>, 1833 Requires<[HasFullFP16]>, 1834 Sched<[WriteFPCVT]>; 1835 1836def VTOSLH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 1, 1837 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1838 IIC_fpCVTHI, "vcvt", ".s32.f16\t$dst, $a, $fbits", []>, 1839 Requires<[HasFullFP16]>, 1840 Sched<[WriteFPCVT]>; 1841 1842def VTOULH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 1, 1843 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1844 IIC_fpCVTHI, "vcvt", ".u32.f16\t$dst, $a, $fbits", []>, 1845 Requires<[HasFullFP16]>, 1846 Sched<[WriteFPCVT]>; 1847 1848} // End of 'let isUnpredicable = 1 in' 1849 1850def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0, 1851 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1852 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []>, 1853 Sched<[WriteFPCVT]> { 1854 // Some single precision VFP instructions may be executed on both NEON and 1855 // VFP pipelines on A8. 1856 let D = VFPNeonA8Domain; 1857} 1858 1859def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0, 1860 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1861 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []>, 1862 Sched<[WriteFPCVT]> { 1863 // Some single precision VFP instructions may be executed on both NEON and 1864 // VFP pipelines on A8. 1865 let D = VFPNeonA8Domain; 1866} 1867 1868def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1, 1869 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1870 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []>, 1871 Sched<[WriteFPCVT]> { 1872 // Some single precision VFP instructions may be executed on both NEON and 1873 // VFP pipelines on A8. 1874 let D = VFPNeonA8Domain; 1875} 1876 1877def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1, 1878 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1879 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []>, 1880 Sched<[WriteFPCVT]> { 1881 // Some single precision VFP instructions may be executed on both NEON and 1882 // VFP pipelines on A8. 1883 let D = VFPNeonA8Domain; 1884} 1885 1886def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0, 1887 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1888 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>, 1889 Sched<[WriteFPCVT]>; 1890 1891def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0, 1892 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1893 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>, 1894 Sched<[WriteFPCVT]>; 1895 1896def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1, 1897 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1898 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>, 1899 Sched<[WriteFPCVT]>; 1900 1901def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1, 1902 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1903 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>, 1904 Sched<[WriteFPCVT]>; 1905 1906// Fixed-Point to FP: 1907 1908let isUnpredicable = 1 in { 1909 1910def VSHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 0, 1911 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1912 IIC_fpCVTIH, "vcvt", ".f16.s16\t$dst, $a, $fbits", []>, 1913 Requires<[HasFullFP16]>, 1914 Sched<[WriteFPCVT]>; 1915 1916def VUHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 0, 1917 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1918 IIC_fpCVTIH, "vcvt", ".f16.u16\t$dst, $a, $fbits", []>, 1919 Requires<[HasFullFP16]>, 1920 Sched<[WriteFPCVT]>; 1921 1922def VSLTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 1, 1923 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1924 IIC_fpCVTIH, "vcvt", ".f16.s32\t$dst, $a, $fbits", []>, 1925 Requires<[HasFullFP16]>, 1926 Sched<[WriteFPCVT]>; 1927 1928def VULTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 1, 1929 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1930 IIC_fpCVTIH, "vcvt", ".f16.u32\t$dst, $a, $fbits", []>, 1931 Requires<[HasFullFP16]>, 1932 Sched<[WriteFPCVT]>; 1933 1934} // End of 'let isUnpredicable = 1 in' 1935 1936def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0, 1937 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1938 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []>, 1939 Sched<[WriteFPCVT]> { 1940 // Some single precision VFP instructions may be executed on both NEON and 1941 // VFP pipelines on A8. 1942 let D = VFPNeonA8Domain; 1943} 1944 1945def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0, 1946 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1947 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []>, 1948 Sched<[WriteFPCVT]> { 1949 // Some single precision VFP instructions may be executed on both NEON and 1950 // VFP pipelines on A8. 1951 let D = VFPNeonA8Domain; 1952} 1953 1954def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1, 1955 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1956 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []>, 1957 Sched<[WriteFPCVT]> { 1958 // Some single precision VFP instructions may be executed on both NEON and 1959 // VFP pipelines on A8. 1960 let D = VFPNeonA8Domain; 1961} 1962 1963def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1, 1964 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1965 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []>, 1966 Sched<[WriteFPCVT]> { 1967 // Some single precision VFP instructions may be executed on both NEON and 1968 // VFP pipelines on A8. 1969 let D = VFPNeonA8Domain; 1970} 1971 1972def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0, 1973 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1974 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>, 1975 Sched<[WriteFPCVT]>; 1976 1977def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0, 1978 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1979 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>, 1980 Sched<[WriteFPCVT]>; 1981 1982def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1, 1983 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1984 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>, 1985 Sched<[WriteFPCVT]>; 1986 1987def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1, 1988 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1989 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>, 1990 Sched<[WriteFPCVT]>; 1991 1992} // End of 'let Constraints = "$a = $dst" in' 1993 1994// BFloat16 - Single precision, unary, predicated 1995class BF16_VCVT<string opc, bits<2> op7_6> 1996 : VFPAI<(outs SPR:$Sd), (ins SPR:$dst, SPR:$Sm), 1997 VFPUnaryFrm, NoItinerary, 1998 opc, ".bf16.f32\t$Sd, $Sm", "", []>, 1999 RegConstraint<"$dst = $Sd">, 2000 Requires<[HasBF16]>, 2001 Sched<[]> { 2002 bits<5> Sd; 2003 bits<5> Sm; 2004 2005 // Encode instruction operands. 2006 let Inst{3-0} = Sm{4-1}; 2007 let Inst{5} = Sm{0}; 2008 let Inst{15-12} = Sd{4-1}; 2009 let Inst{22} = Sd{0}; 2010 2011 let Inst{27-23} = 0b11101; // opcode1 2012 let Inst{21-20} = 0b11; // opcode2 2013 let Inst{19-16} = 0b0011; // opcode3 2014 let Inst{11-8} = 0b1001; 2015 let Inst{7-6} = op7_6; 2016 let Inst{4} = 0; 2017 2018 let DecoderNamespace = "VFPV8"; 2019 let hasSideEffects = 0; 2020} 2021 2022def BF16_VCVTB : BF16_VCVT<"vcvtb", 0b01>; 2023def BF16_VCVTT : BF16_VCVT<"vcvtt", 0b11>; 2024 2025//===----------------------------------------------------------------------===// 2026// FP Multiply-Accumulate Operations. 2027// 2028 2029def VMLAD : ADbI<0b11100, 0b00, 0, 0, 2030 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2031 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm", 2032 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 2033 (f64 DPR:$Ddin)))]>, 2034 RegConstraint<"$Ddin = $Dd">, 2035 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, 2036 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2037 2038def VMLAS : ASbIn<0b11100, 0b00, 0, 0, 2039 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2040 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm", 2041 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 2042 SPR:$Sdin))]>, 2043 RegConstraint<"$Sdin = $Sd">, 2044 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>, 2045 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2046 // Some single precision VFP instructions may be executed on both NEON and 2047 // VFP pipelines on A8. 2048 let D = VFPNeonA8Domain; 2049} 2050 2051def VMLAH : AHbI<0b11100, 0b00, 0, 0, 2052 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2053 IIC_fpMAC16, "vmla", ".f16\t$Sd, $Sn, $Sm", 2054 [(set (f16 HPR:$Sd), (fadd_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), 2055 (f16 HPR:$Sdin)))]>, 2056 RegConstraint<"$Sdin = $Sd">, 2057 Requires<[HasFullFP16,UseFPVMLx]>; 2058 2059def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 2060 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 2061 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2062def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 2063 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 2064 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx]>; 2065def : Pat<(fadd_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)), 2066 (VMLAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2067 Requires<[HasFullFP16,DontUseNEONForFP, UseFPVMLx]>; 2068 2069 2070def VMLSD : ADbI<0b11100, 0b00, 1, 0, 2071 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2072 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm", 2073 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 2074 (f64 DPR:$Ddin)))]>, 2075 RegConstraint<"$Ddin = $Dd">, 2076 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, 2077 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2078 2079def VMLSS : ASbIn<0b11100, 0b00, 1, 0, 2080 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2081 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm", 2082 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 2083 SPR:$Sdin))]>, 2084 RegConstraint<"$Sdin = $Sd">, 2085 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>, 2086 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2087 // Some single precision VFP instructions may be executed on both NEON and 2088 // VFP pipelines on A8. 2089 let D = VFPNeonA8Domain; 2090} 2091 2092def VMLSH : AHbI<0b11100, 0b00, 1, 0, 2093 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2094 IIC_fpMAC16, "vmls", ".f16\t$Sd, $Sn, $Sm", 2095 [(set (f16 HPR:$Sd), (fadd_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))), 2096 (f16 HPR:$Sdin)))]>, 2097 RegConstraint<"$Sdin = $Sd">, 2098 Requires<[HasFullFP16,UseFPVMLx]>; 2099 2100def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 2101 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 2102 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2103def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 2104 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 2105 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; 2106def : Pat<(fsub_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)), 2107 (VMLSH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2108 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; 2109 2110def VNMLAD : ADbI<0b11100, 0b01, 1, 0, 2111 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2112 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm", 2113 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 2114 (f64 DPR:$Ddin)))]>, 2115 RegConstraint<"$Ddin = $Dd">, 2116 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, 2117 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2118 2119def VNMLAS : ASbI<0b11100, 0b01, 1, 0, 2120 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2121 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm", 2122 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 2123 SPR:$Sdin))]>, 2124 RegConstraint<"$Sdin = $Sd">, 2125 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>, 2126 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2127 // Some single precision VFP instructions may be executed on both NEON and 2128 // VFP pipelines on A8. 2129 let D = VFPNeonA8Domain; 2130} 2131 2132def VNMLAH : AHbI<0b11100, 0b01, 1, 0, 2133 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2134 IIC_fpMAC16, "vnmla", ".f16\t$Sd, $Sn, $Sm", 2135 [(set (f16 HPR:$Sd), (fsub_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))), 2136 (f16 HPR:$Sdin)))]>, 2137 RegConstraint<"$Sdin = $Sd">, 2138 Requires<[HasFullFP16,UseFPVMLx]>; 2139 2140// (-(a * b) - dst) -> -(dst + (a * b)) 2141def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 2142 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 2143 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2144def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 2145 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 2146 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; 2147def : Pat<(fsub_mlx (fneg (fmul_su (f16 HPR:$a), HPR:$b)), HPR:$dstin), 2148 (VNMLAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2149 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; 2150 2151// (-dst - (a * b)) -> -(dst + (a * b)) 2152def : Pat<(fsub_mlx (fneg DPR:$dstin), (fmul_su DPR:$a, (f64 DPR:$b))), 2153 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 2154 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2155def : Pat<(fsub_mlx (fneg SPR:$dstin), (fmul_su SPR:$a, SPR:$b)), 2156 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 2157 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; 2158def : Pat<(fsub_mlx (fneg HPR:$dstin), (fmul_su (f16 HPR:$a), HPR:$b)), 2159 (VNMLAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2160 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; 2161 2162def VNMLSD : ADbI<0b11100, 0b01, 0, 0, 2163 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2164 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm", 2165 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 2166 (f64 DPR:$Ddin)))]>, 2167 RegConstraint<"$Ddin = $Dd">, 2168 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, 2169 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2170 2171def VNMLSS : ASbI<0b11100, 0b01, 0, 0, 2172 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2173 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm", 2174 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 2175 RegConstraint<"$Sdin = $Sd">, 2176 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>, 2177 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2178 // Some single precision VFP instructions may be executed on both NEON and 2179 // VFP pipelines on A8. 2180 let D = VFPNeonA8Domain; 2181} 2182 2183def VNMLSH : AHbI<0b11100, 0b01, 0, 0, 2184 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2185 IIC_fpMAC16, "vnmls", ".f16\t$Sd, $Sn, $Sm", 2186 [(set (f16 HPR:$Sd), (fsub_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), (f16 HPR:$Sdin)))]>, 2187 RegConstraint<"$Sdin = $Sd">, 2188 Requires<[HasFullFP16,UseFPVMLx]>; 2189 2190def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 2191 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 2192 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2193def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 2194 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 2195 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; 2196def : Pat<(fsub_mlx (fmul_su (f16 HPR:$a), HPR:$b), HPR:$dstin), 2197 (VNMLSH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2198 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; 2199 2200//===----------------------------------------------------------------------===// 2201// Fused FP Multiply-Accumulate Operations. 2202// 2203def VFMAD : ADbI<0b11101, 0b10, 0, 0, 2204 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2205 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm", 2206 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 2207 (f64 DPR:$Ddin)))]>, 2208 RegConstraint<"$Ddin = $Dd">, 2209 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, 2210 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2211 2212def VFMAS : ASbIn<0b11101, 0b10, 0, 0, 2213 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2214 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm", 2215 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 2216 SPR:$Sdin))]>, 2217 RegConstraint<"$Sdin = $Sd">, 2218 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>, 2219 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2220 // Some single precision VFP instructions may be executed on both NEON and 2221 // VFP pipelines. 2222} 2223 2224def VFMAH : AHbI<0b11101, 0b10, 0, 0, 2225 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2226 IIC_fpFMAC16, "vfma", ".f16\t$Sd, $Sn, $Sm", 2227 [(set (f16 HPR:$Sd), (fadd_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), 2228 (f16 HPR:$Sdin)))]>, 2229 RegConstraint<"$Sdin = $Sd">, 2230 Requires<[HasFullFP16,UseFusedMAC]>, 2231 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2232 2233def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 2234 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>, 2235 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 2236def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 2237 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>, 2238 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 2239def : Pat<(fadd_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)), 2240 (VFMAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2241 Requires<[HasFullFP16,DontUseNEONForFP,UseFusedMAC]>; 2242 2243// Match @llvm.fma.* intrinsics 2244// (fma x, y, z) -> (vfms z, x, y) 2245def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)), 2246 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2247 Requires<[HasVFP4,HasDPVFP]>; 2248def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)), 2249 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2250 Requires<[HasVFP4]>; 2251def : Pat<(f16 (fma HPR:$Sn, HPR:$Sm, (f16 HPR:$Sdin))), 2252 (VFMAH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2253 Requires<[HasFullFP16]>; 2254 2255def VFMSD : ADbI<0b11101, 0b10, 1, 0, 2256 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2257 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm", 2258 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 2259 (f64 DPR:$Ddin)))]>, 2260 RegConstraint<"$Ddin = $Dd">, 2261 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, 2262 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2263 2264def VFMSS : ASbIn<0b11101, 0b10, 1, 0, 2265 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2266 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm", 2267 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 2268 SPR:$Sdin))]>, 2269 RegConstraint<"$Sdin = $Sd">, 2270 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>, 2271 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2272 // Some single precision VFP instructions may be executed on both NEON and 2273 // VFP pipelines. 2274} 2275 2276def VFMSH : AHbI<0b11101, 0b10, 1, 0, 2277 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2278 IIC_fpFMAC16, "vfms", ".f16\t$Sd, $Sn, $Sm", 2279 [(set (f16 HPR:$Sd), (fadd_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))), 2280 (f16 HPR:$Sdin)))]>, 2281 RegConstraint<"$Sdin = $Sd">, 2282 Requires<[HasFullFP16,UseFusedMAC]>, 2283 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2284 2285def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 2286 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>, 2287 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 2288def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 2289 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>, 2290 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 2291def : Pat<(fsub_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)), 2292 (VFMSH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2293 Requires<[HasFullFP16,DontUseNEONForFP,UseFusedMAC]>; 2294 2295// Match @llvm.fma.* intrinsics 2296// (fma (fneg x), y, z) -> (vfms z, x, y) 2297def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)), 2298 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2299 Requires<[HasVFP4,HasDPVFP]>; 2300def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)), 2301 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2302 Requires<[HasVFP4]>; 2303def : Pat<(f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (f16 HPR:$Sdin))), 2304 (VFMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2305 Requires<[HasFullFP16]>; 2306 2307def VFNMAD : ADbI<0b11101, 0b01, 1, 0, 2308 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2309 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm", 2310 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 2311 (f64 DPR:$Ddin)))]>, 2312 RegConstraint<"$Ddin = $Dd">, 2313 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, 2314 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2315 2316def VFNMAS : ASbI<0b11101, 0b01, 1, 0, 2317 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2318 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm", 2319 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 2320 SPR:$Sdin))]>, 2321 RegConstraint<"$Sdin = $Sd">, 2322 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>, 2323 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2324 // Some single precision VFP instructions may be executed on both NEON and 2325 // VFP pipelines. 2326} 2327 2328def VFNMAH : AHbI<0b11101, 0b01, 1, 0, 2329 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2330 IIC_fpFMAC16, "vfnma", ".f16\t$Sd, $Sn, $Sm", 2331 [(set (f16 HPR:$Sd), (fsub_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))), 2332 (f16 HPR:$Sdin)))]>, 2333 RegConstraint<"$Sdin = $Sd">, 2334 Requires<[HasFullFP16,UseFusedMAC]>, 2335 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2336 2337def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 2338 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>, 2339 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 2340def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 2341 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>, 2342 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 2343 2344// Match @llvm.fma.* intrinsics 2345// (fneg (fma x, y, z)) -> (vfnma z, x, y) 2346def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))), 2347 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2348 Requires<[HasVFP4,HasDPVFP]>; 2349def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))), 2350 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2351 Requires<[HasVFP4]>; 2352def : Pat<(fneg (fma (f16 HPR:$Sn), (f16 HPR:$Sm), (f16 (f16 HPR:$Sdin)))), 2353 (VFNMAH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2354 Requires<[HasFullFP16]>; 2355// (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y) 2356def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))), 2357 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2358 Requires<[HasVFP4,HasDPVFP]>; 2359def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))), 2360 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2361 Requires<[HasVFP4]>; 2362def : Pat<(f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (fneg (f16 HPR:$Sdin)))), 2363 (VFNMAH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2364 Requires<[HasFullFP16]>; 2365 2366def VFNMSD : ADbI<0b11101, 0b01, 0, 0, 2367 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2368 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm", 2369 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 2370 (f64 DPR:$Ddin)))]>, 2371 RegConstraint<"$Ddin = $Dd">, 2372 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, 2373 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2374 2375def VFNMSS : ASbI<0b11101, 0b01, 0, 0, 2376 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2377 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm", 2378 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 2379 RegConstraint<"$Sdin = $Sd">, 2380 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>, 2381 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2382 // Some single precision VFP instructions may be executed on both NEON and 2383 // VFP pipelines. 2384} 2385 2386def VFNMSH : AHbI<0b11101, 0b01, 0, 0, 2387 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2388 IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm", 2389 [(set (f16 HPR:$Sd), (fsub_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), (f16 HPR:$Sdin)))]>, 2390 RegConstraint<"$Sdin = $Sd">, 2391 Requires<[HasFullFP16,UseFusedMAC]>, 2392 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2393 2394def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 2395 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>, 2396 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 2397def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 2398 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>, 2399 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 2400 2401// Match @llvm.fma.* intrinsics 2402 2403// (fma x, y, (fneg z)) -> (vfnms z, x, y)) 2404def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))), 2405 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2406 Requires<[HasVFP4,HasDPVFP]>; 2407def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))), 2408 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2409 Requires<[HasVFP4]>; 2410def : Pat<(f16 (fma (f16 HPR:$Sn), (f16 HPR:$Sm), (fneg (f16 HPR:$Sdin)))), 2411 (VFNMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2412 Requires<[HasFullFP16]>; 2413// (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y) 2414def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))), 2415 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2416 Requires<[HasVFP4,HasDPVFP]>; 2417def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))), 2418 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2419 Requires<[HasVFP4]>; 2420def : Pat<(fneg (f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (f16 HPR:$Sdin)))), 2421 (VFNMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2422 Requires<[HasFullFP16]>; 2423 2424//===----------------------------------------------------------------------===// 2425// FP Conditional moves. 2426// 2427 2428let hasSideEffects = 0 in { 2429def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p), 2430 IIC_fpUNA64, 2431 [(set (f64 DPR:$Dd), 2432 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>, 2433 RegConstraint<"$Dn = $Dd">, Requires<[HasFPRegs64]>; 2434 2435def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p), 2436 IIC_fpUNA32, 2437 [(set (f32 SPR:$Sd), 2438 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>, 2439 RegConstraint<"$Sn = $Sd">, Requires<[HasFPRegs]>; 2440 2441def VMOVHcc : PseudoInst<(outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm, cmovpred:$p), 2442 IIC_fpUNA16, 2443 [(set (f16 HPR:$Sd), 2444 (ARMcmov (f16 HPR:$Sn), (f16 HPR:$Sm), cmovpred:$p))]>, 2445 RegConstraint<"$Sd = $Sn">, Requires<[HasFPRegs]>; 2446} // hasSideEffects 2447 2448//===----------------------------------------------------------------------===// 2449// Move from VFP System Register to ARM core register. 2450// 2451 2452class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 2453 list<dag> pattern>: 2454 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, "", pattern> { 2455 2456 // Instruction operand. 2457 bits<4> Rt; 2458 2459 let Inst{27-20} = 0b11101111; 2460 let Inst{19-16} = opc19_16; 2461 let Inst{15-12} = Rt; 2462 let Inst{11-8} = 0b1010; 2463 let Inst{7} = 0; 2464 let Inst{6-5} = 0b00; 2465 let Inst{4} = 1; 2466 let Inst{3-0} = 0b0000; 2467 let Unpredictable{7-5} = 0b111; 2468 let Unpredictable{3-0} = 0b1111; 2469} 2470 2471let DecoderMethod = "DecodeForVMRSandVMSR" in { 2472 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags 2473 // to APSR. 2474 let Defs = [CPSR], Uses = [FPSCR_NZCV], Predicates = [HasFPRegs], 2475 Rt = 0b1111 /* apsr_nzcv */ in 2476 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins), 2477 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>; 2478 2479 // Application level FPSCR -> GPR 2480 let hasSideEffects = 1, Uses = [FPSCR], Predicates = [HasFPRegs] in 2481 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPRnopc:$Rt), (ins), 2482 "vmrs", "\t$Rt, fpscr", 2483 [(set GPRnopc:$Rt, (int_arm_get_fpscr))]>; 2484 2485 // System level FPEXC, FPSID -> GPR 2486 let Uses = [FPSCR] in { 2487 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPRnopc:$Rt), (ins), 2488 "vmrs", "\t$Rt, fpexc", []>; 2489 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPRnopc:$Rt), (ins), 2490 "vmrs", "\t$Rt, fpsid", []>; 2491 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPRnopc:$Rt), (ins), 2492 "vmrs", "\t$Rt, mvfr0", []>; 2493 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPRnopc:$Rt), (ins), 2494 "vmrs", "\t$Rt, mvfr1", []>; 2495 let Predicates = [HasFPARMv8] in { 2496 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPRnopc:$Rt), (ins), 2497 "vmrs", "\t$Rt, mvfr2", []>; 2498 } 2499 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPRnopc:$Rt), (ins), 2500 "vmrs", "\t$Rt, fpinst", []>; 2501 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPRnopc:$Rt), 2502 (ins), "vmrs", "\t$Rt, fpinst2", []>; 2503 let Predicates = [HasV8_1MMainline, HasFPRegs] in { 2504 // System level FPSCR_NZCVQC -> GPR 2505 def VMRS_FPSCR_NZCVQC 2506 : MovFromVFP<0b0010 /* fpscr_nzcvqc */, 2507 (outs GPR:$Rt), (ins cl_FPSCR_NZCV:$fpscr_in), 2508 "vmrs", "\t$Rt, fpscr_nzcvqc", []>; 2509 } 2510 } 2511 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2512 // System level FPSCR -> GPR, with context saving for security extensions 2513 def VMRS_FPCXTNS : MovFromVFP<0b1110 /* fpcxtns */, (outs GPR:$Rt), (ins), 2514 "vmrs", "\t$Rt, fpcxtns", []>; 2515 } 2516 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2517 // System level FPSCR -> GPR, with context saving for security extensions 2518 def VMRS_FPCXTS : MovFromVFP<0b1111 /* fpcxts */, (outs GPR:$Rt), (ins), 2519 "vmrs", "\t$Rt, fpcxts", []>; 2520 } 2521 2522 let Predicates = [HasV8_1MMainline, HasMVEInt] in { 2523 // System level VPR/P0 -> GPR 2524 let Uses = [VPR] in 2525 def VMRS_VPR : MovFromVFP<0b1100 /* vpr */, (outs GPR:$Rt), (ins), 2526 "vmrs", "\t$Rt, vpr", []>; 2527 2528 def VMRS_P0 : MovFromVFP<0b1101 /* p0 */, (outs GPR:$Rt), (ins VCCR:$cond), 2529 "vmrs", "\t$Rt, p0", []>; 2530 } 2531} 2532 2533//===----------------------------------------------------------------------===// 2534// Move from ARM core register to VFP System Register. 2535// 2536 2537class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 2538 list<dag> pattern>: 2539 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, "", pattern> { 2540 2541 // Instruction operand. 2542 bits<4> Rt; 2543 2544 let Inst{27-20} = 0b11101110; 2545 let Inst{19-16} = opc19_16; 2546 let Inst{15-12} = Rt; 2547 let Inst{11-8} = 0b1010; 2548 let Inst{7} = 0; 2549 let Inst{6-5} = 0b00; 2550 let Inst{4} = 1; 2551 let Inst{3-0} = 0b0000; 2552 let Predicates = [HasVFP2]; 2553 let Unpredictable{7-5} = 0b111; 2554 let Unpredictable{3-0} = 0b1111; 2555} 2556 2557let DecoderMethod = "DecodeForVMRSandVMSR" in { 2558 let Defs = [FPSCR] in { 2559 let Predicates = [HasFPRegs] in 2560 // Application level GPR -> FPSCR 2561 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPRnopc:$Rt), 2562 "vmsr", "\tfpscr, $Rt", 2563 [(int_arm_set_fpscr GPRnopc:$Rt)]>; 2564 // System level GPR -> FPEXC 2565 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPRnopc:$Rt), 2566 "vmsr", "\tfpexc, $Rt", []>; 2567 // System level GPR -> FPSID 2568 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPRnopc:$Rt), 2569 "vmsr", "\tfpsid, $Rt", []>; 2570 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPRnopc:$Rt), 2571 "vmsr", "\tfpinst, $Rt", []>; 2572 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPRnopc:$Rt), 2573 "vmsr", "\tfpinst2, $Rt", []>; 2574 } 2575 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2576 // System level GPR -> FPSCR with context saving for security extensions 2577 def VMSR_FPCXTNS : MovToVFP<0b1110 /* fpcxtns */, (outs), (ins GPR:$Rt), 2578 "vmsr", "\tfpcxtns, $Rt", []>; 2579 } 2580 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2581 // System level GPR -> FPSCR with context saving for security extensions 2582 def VMSR_FPCXTS : MovToVFP<0b1111 /* fpcxts */, (outs), (ins GPR:$Rt), 2583 "vmsr", "\tfpcxts, $Rt", []>; 2584 } 2585 let Predicates = [HasV8_1MMainline, HasFPRegs] in { 2586 // System level GPR -> FPSCR_NZCVQC 2587 def VMSR_FPSCR_NZCVQC 2588 : MovToVFP<0b0010 /* fpscr_nzcvqc */, 2589 (outs cl_FPSCR_NZCV:$fpscr_out), (ins GPR:$Rt), 2590 "vmsr", "\tfpscr_nzcvqc, $Rt", []>; 2591 } 2592 2593 let Predicates = [HasV8_1MMainline, HasMVEInt] in { 2594 // System level GPR -> VPR/P0 2595 let Defs = [VPR] in 2596 def VMSR_VPR : MovToVFP<0b1100 /* vpr */, (outs), (ins GPR:$Rt), 2597 "vmsr", "\tvpr, $Rt", []>; 2598 2599 def VMSR_P0 : MovToVFP<0b1101 /* p0 */, (outs VCCR:$cond), (ins GPR:$Rt), 2600 "vmsr", "\tp0, $Rt", []>; 2601 } 2602} 2603 2604//===----------------------------------------------------------------------===// 2605// Misc. 2606// 2607 2608// Materialize FP immediates. VFP3 only. 2609let isReMaterializable = 1 in { 2610def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm), 2611 VFPMiscFrm, IIC_fpUNA64, 2612 "vmov", ".f64\t$Dd, $imm", "", 2613 [(set DPR:$Dd, vfp_f64imm:$imm)]>, 2614 Requires<[HasVFP3,HasDPVFP]> { 2615 bits<5> Dd; 2616 bits<8> imm; 2617 2618 let Inst{27-23} = 0b11101; 2619 let Inst{22} = Dd{4}; 2620 let Inst{21-20} = 0b11; 2621 let Inst{19-16} = imm{7-4}; 2622 let Inst{15-12} = Dd{3-0}; 2623 let Inst{11-9} = 0b101; 2624 let Inst{8} = 1; // Double precision. 2625 let Inst{7-4} = 0b0000; 2626 let Inst{3-0} = imm{3-0}; 2627} 2628 2629def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm), 2630 VFPMiscFrm, IIC_fpUNA32, 2631 "vmov", ".f32\t$Sd, $imm", "", 2632 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> { 2633 bits<5> Sd; 2634 bits<8> imm; 2635 2636 let Inst{27-23} = 0b11101; 2637 let Inst{22} = Sd{0}; 2638 let Inst{21-20} = 0b11; 2639 let Inst{19-16} = imm{7-4}; 2640 let Inst{15-12} = Sd{4-1}; 2641 let Inst{11-9} = 0b101; 2642 let Inst{8} = 0; // Single precision. 2643 let Inst{7-4} = 0b0000; 2644 let Inst{3-0} = imm{3-0}; 2645} 2646 2647def FCONSTH : VFPAI<(outs HPR:$Sd), (ins vfp_f16imm:$imm), 2648 VFPMiscFrm, IIC_fpUNA16, 2649 "vmov", ".f16\t$Sd, $imm", "", 2650 [(set (f16 HPR:$Sd), vfp_f16imm:$imm)]>, 2651 Requires<[HasFullFP16]> { 2652 bits<5> Sd; 2653 bits<8> imm; 2654 2655 let Inst{27-23} = 0b11101; 2656 let Inst{22} = Sd{0}; 2657 let Inst{21-20} = 0b11; 2658 let Inst{19-16} = imm{7-4}; 2659 let Inst{15-12} = Sd{4-1}; 2660 let Inst{11-8} = 0b1001; // Half precision 2661 let Inst{7-4} = 0b0000; 2662 let Inst{3-0} = imm{3-0}; 2663 2664 let isUnpredicable = 1; 2665} 2666} 2667 2668def : Pat<(f32 (vfp_f32f16imm:$imm)), 2669 (f32 (COPY_TO_REGCLASS (f16 (FCONSTH (vfp_f32f16imm_xform (f32 $imm)))), SPR))> { 2670 let Predicates = [HasFullFP16]; 2671} 2672 2673//===----------------------------------------------------------------------===// 2674// Assembler aliases. 2675// 2676// A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to 2677// support them all, but supporting at least some of the basics is 2678// good to be friendly. 2679def : VFP2MnemonicAlias<"flds", "vldr">; 2680def : VFP2MnemonicAlias<"fldd", "vldr">; 2681def : VFP2MnemonicAlias<"fmrs", "vmov">; 2682def : VFP2MnemonicAlias<"fmsr", "vmov">; 2683def : VFP2MnemonicAlias<"fsqrts", "vsqrt">; 2684def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">; 2685def : VFP2MnemonicAlias<"fadds", "vadd.f32">; 2686def : VFP2MnemonicAlias<"faddd", "vadd.f64">; 2687def : VFP2MnemonicAlias<"fmrdd", "vmov">; 2688def : VFP2MnemonicAlias<"fmrds", "vmov">; 2689def : VFP2MnemonicAlias<"fmrrd", "vmov">; 2690def : VFP2MnemonicAlias<"fmdrr", "vmov">; 2691def : VFP2MnemonicAlias<"fmuls", "vmul.f32">; 2692def : VFP2MnemonicAlias<"fmuld", "vmul.f64">; 2693def : VFP2MnemonicAlias<"fnegs", "vneg.f32">; 2694def : VFP2MnemonicAlias<"fnegd", "vneg.f64">; 2695def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">; 2696def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">; 2697def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">; 2698def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">; 2699def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">; 2700def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">; 2701def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">; 2702def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">; 2703def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">; 2704def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">; 2705def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">; 2706def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">; 2707def : VFP2MnemonicAlias<"fsts", "vstr">; 2708def : VFP2MnemonicAlias<"fstd", "vstr">; 2709def : VFP2MnemonicAlias<"fmacd", "vmla.f64">; 2710def : VFP2MnemonicAlias<"fmacs", "vmla.f32">; 2711def : VFP2MnemonicAlias<"fcpys", "vmov.f32">; 2712def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">; 2713def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">; 2714def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">; 2715def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">; 2716def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">; 2717def : VFP2MnemonicAlias<"fmrx", "vmrs">; 2718def : VFP2MnemonicAlias<"fmxr", "vmsr">; 2719 2720// Be friendly and accept the old form of zero-compare 2721def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>; 2722def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>; 2723 2724 2725def : InstAlias<"fmstat${p}", (FMSTAT pred:$p), 0>, Requires<[HasFPRegs]>; 2726def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm", 2727 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 2728def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm", 2729 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 2730def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm", 2731 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 2732def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm", 2733 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 2734 2735// No need for the size suffix on VSQRT. It's implied by the register classes. 2736def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>; 2737def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>; 2738 2739// VLDR/VSTR accept an optional type suffix. 2740def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr", 2741 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 2742def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr", 2743 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 2744def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr", 2745 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 2746def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr", 2747 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 2748 2749// VMOV can accept optional 32-bit or less data type suffix suffix. 2750def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn", 2751 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 2752def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn", 2753 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 2754def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn", 2755 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 2756def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt", 2757 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 2758def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt", 2759 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 2760def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt", 2761 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 2762 2763def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn", 2764 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>; 2765def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2", 2766 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>; 2767 2768// VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way 2769// VMOVD does. 2770def : VFP2InstAlias<"vmov${p} $Sd, $Sm", 2771 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>; 2772 2773// FCONSTD/FCONSTS alias for vmov.f64/vmov.f32 2774// These aliases provide added functionality over vmov.f instructions by 2775// allowing users to write assembly containing encoded floating point constants 2776// (e.g. #0x70 vs #1.0). Without these alises there is no way for the 2777// assembler to accept encoded fp constants (but the equivalent fp-literal is 2778// accepted directly by vmovf). 2779def : VFP3InstAlias<"fconstd${p} $Dd, $val", 2780 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>; 2781def : VFP3InstAlias<"fconsts${p} $Sd, $val", 2782 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>; 2783 2784def VSCCLRMD : VFPXI<(outs), (ins pred:$p, fp_dreglist_with_vpr:$regs, variable_ops), 2785 AddrModeNone, 4, IndexModeNone, VFPMiscFrm, NoItinerary, 2786 "vscclrm{$p}\t$regs", "", []>, Sched<[]> { 2787 bits<13> regs; 2788 let Inst{31-23} = 0b111011001; 2789 let Inst{22} = regs{12}; 2790 let Inst{21-16} = 0b011111; 2791 let Inst{15-12} = regs{11-8}; 2792 let Inst{11-8} = 0b1011; 2793 let Inst{7-1} = regs{7-1}; 2794 let Inst{0} = 0; 2795 2796 let DecoderMethod = "DecodeVSCCLRM"; 2797 2798 list<Predicate> Predicates = [HasV8_1MMainline, Has8MSecExt]; 2799} 2800 2801def VSCCLRMS : VFPXI<(outs), (ins pred:$p, fp_sreglist_with_vpr:$regs, variable_ops), 2802 AddrModeNone, 4, IndexModeNone, VFPMiscFrm, NoItinerary, 2803 "vscclrm{$p}\t$regs", "", []>, Sched<[]> { 2804 bits<13> regs; 2805 let Inst{31-23} = 0b111011001; 2806 let Inst{22} = regs{8}; 2807 let Inst{21-16} = 0b011111; 2808 let Inst{15-12} = regs{12-9}; 2809 let Inst{11-8} = 0b1010; 2810 let Inst{7-0} = regs{7-0}; 2811 2812 let DecoderMethod = "DecodeVSCCLRM"; 2813 2814 list<Predicate> Predicates = [HasV8_1MMainline, Has8MSecExt]; 2815} 2816 2817//===----------------------------------------------------------------------===// 2818// Store VFP System Register to memory. 2819// 2820 2821class vfp_vstrldr<bit opc, bit P, bit W, bits<4> SysReg, string sysreg, 2822 dag oops, dag iops, IndexMode im, string Dest, string cstr> 2823 : VFPI<oops, iops, AddrModeT2_i7s4, 4, im, VFPLdStFrm, IIC_fpSTAT, 2824 !if(opc,"vldr","vstr"), !strconcat("\t", sysreg, ", ", Dest), cstr, []>, 2825 Sched<[]> { 2826 bits<12> addr; 2827 let Inst{27-25} = 0b110; 2828 let Inst{24} = P; 2829 let Inst{23} = addr{7}; 2830 let Inst{22} = SysReg{3}; 2831 let Inst{21} = W; 2832 let Inst{20} = opc; 2833 let Inst{19-16} = addr{11-8}; 2834 let Inst{15-13} = SysReg{2-0}; 2835 let Inst{12-7} = 0b011111; 2836 let Inst{6-0} = addr{6-0}; 2837 list<Predicate> Predicates = [HasFPRegs, HasV8_1MMainline]; 2838 let mayLoad = opc; 2839 let mayStore = !if(opc, 0b0, 0b1); 2840 let hasSideEffects = 1; 2841} 2842 2843multiclass vfp_vstrldr_sysreg<bit opc, bits<4> SysReg, string sysreg, 2844 dag oops=(outs), dag iops=(ins)> { 2845 def _off : 2846 vfp_vstrldr<opc, 1, 0, SysReg, sysreg, 2847 oops, !con(iops, (ins t2addrmode_imm7s4:$addr)), 2848 IndexModePost, "$addr", "" > { 2849 let DecoderMethod = "DecodeVSTRVLDR_SYSREG<false>"; 2850 } 2851 2852 def _pre : 2853 vfp_vstrldr<opc, 1, 1, SysReg, sysreg, 2854 !con(oops, (outs GPRnopc:$wb)), 2855 !con(iops, (ins t2addrmode_imm7s4_pre:$addr)), 2856 IndexModePre, "$addr!", "$addr.base = $wb"> { 2857 let DecoderMethod = "DecodeVSTRVLDR_SYSREG<true>"; 2858 } 2859 2860 def _post : 2861 vfp_vstrldr<opc, 0, 1, SysReg, sysreg, 2862 !con(oops, (outs GPRnopc:$wb)), 2863 !con(iops, (ins t2_addr_offset_none:$Rn, 2864 t2am_imm7s4_offset:$addr)), 2865 IndexModePost, "$Rn$addr", "$Rn.base = $wb"> { 2866 bits<4> Rn; 2867 let Inst{19-16} = Rn{3-0}; 2868 let DecoderMethod = "DecodeVSTRVLDR_SYSREG<true>"; 2869 } 2870} 2871 2872let Defs = [FPSCR] in { 2873 defm VSTR_FPSCR : vfp_vstrldr_sysreg<0b0,0b0001, "fpscr">; 2874 defm VSTR_FPSCR_NZCVQC : vfp_vstrldr_sysreg<0b0,0b0010, "fpscr_nzcvqc">; 2875 2876 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2877 defm VSTR_FPCXTNS : vfp_vstrldr_sysreg<0b0,0b1110, "fpcxtns">; 2878 defm VSTR_FPCXTS : vfp_vstrldr_sysreg<0b0,0b1111, "fpcxts">; 2879 } 2880} 2881 2882let Predicates = [HasV8_1MMainline, HasMVEInt] in { 2883 let Uses = [VPR] in { 2884 defm VSTR_VPR : vfp_vstrldr_sysreg<0b0,0b1100, "vpr">; 2885 } 2886 defm VSTR_P0 : vfp_vstrldr_sysreg<0b0,0b1101, "p0", 2887 (outs), (ins VCCR:$P0)>; 2888 2889 let Defs = [VPR] in { 2890 defm VLDR_VPR : vfp_vstrldr_sysreg<0b1,0b1100, "vpr">; 2891 } 2892 defm VLDR_P0 : vfp_vstrldr_sysreg<0b1,0b1101, "p0", 2893 (outs VCCR:$P0), (ins)>; 2894} 2895 2896let Uses = [FPSCR] in { 2897 defm VLDR_FPSCR : vfp_vstrldr_sysreg<0b1,0b0001, "fpscr">; 2898 defm VLDR_FPSCR_NZCVQC : vfp_vstrldr_sysreg<0b1,0b0010, "fpscr_nzcvqc">; 2899 2900 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2901 defm VLDR_FPCXTNS : vfp_vstrldr_sysreg<0b1,0b1110, "fpcxtns">; 2902 defm VLDR_FPCXTS : vfp_vstrldr_sysreg<0b1,0b1111, "fpcxts">; 2903 } 2904} 2905