1//===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the Thumb2 instruction set. 10// 11//===----------------------------------------------------------------------===// 12 13// IT block predicate field 14def it_pred_asmoperand : AsmOperandClass { 15 let Name = "ITCondCode"; 16 let ParserMethod = "parseITCondCode"; 17} 18def it_pred : Operand<i32> { 19 let PrintMethod = "printMandatoryPredicateOperand"; 20 let ParserMatchClass = it_pred_asmoperand; 21} 22 23// IT block condition mask 24def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; } 25def it_mask : Operand<i32> { 26 let PrintMethod = "printThumbITMask"; 27 let ParserMatchClass = it_mask_asmoperand; 28 let EncoderMethod = "getITMaskOpValue"; 29} 30 31// t2_shift_imm: An integer that encodes a shift amount and the type of shift 32// (asr or lsl). The 6-bit immediate encodes as: 33// {5} 0 ==> lsl 34// 1 asr 35// {4-0} imm5 shift amount. 36// asr #32 not allowed 37def t2_shift_imm : Operand<i32> { 38 let PrintMethod = "printShiftImmOperand"; 39 let ParserMatchClass = ShifterImmAsmOperand; 40 let DecoderMethod = "DecodeT2ShifterImmOperand"; 41} 42 43def mve_shift_imm : AsmOperandClass { 44 let Name = "MVELongShift"; 45 let RenderMethod = "addImmOperands"; 46 let DiagnosticString = "operand must be an immediate in the range [1,32]"; 47} 48def long_shift : Operand<i32>, 49 ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]> { 50 let ParserMatchClass = mve_shift_imm; 51 let DecoderMethod = "DecodeLongShiftOperand"; 52} 53 54// Shifted operands. No register controlled shifts for Thumb2. 55// Note: We do not support rrx shifted operands yet. 56def t2_so_reg : Operand<i32>, // reg imm 57 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 58 [shl,srl,sra,rotr]> { 59 let EncoderMethod = "getT2SORegOpValue"; 60 let PrintMethod = "printT2SOOperand"; 61 let DecoderMethod = "DecodeSORegImmOperand"; 62 let ParserMatchClass = ShiftedImmAsmOperand; 63 let MIOperandInfo = (ops rGPR, i32imm); 64} 65 66// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value 67def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ 68 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N), 69 MVT::i32); 70}]>; 71 72// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value 73def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ 74 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), SDLoc(N), 75 MVT::i32); 76}]>; 77 78// so_imm_notSext_XFORM - Return a so_imm value packed into the format 79// described for so_imm_notSext def below, with sign extension from 16 80// bits. 81def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{ 82 APInt apIntN = N->getAPIntValue(); 83 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue(); 84 return CurDAG->getTargetConstant(~N16bitSignExt, SDLoc(N), MVT::i32); 85}]>; 86 87// t2_so_imm - Match a 32-bit immediate operand, which is an 88// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit 89// immediate splatted into multiple bytes of the word. 90def t2_so_imm_asmoperand : AsmOperandClass { 91 let Name = "T2SOImm"; 92 let RenderMethod = "addImmOperands"; 93 94} 95def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{ 96 return ARM_AM::getT2SOImmVal(Imm) != -1; 97 }]> { 98 let ParserMatchClass = t2_so_imm_asmoperand; 99 let EncoderMethod = "getT2SOImmOpValue"; 100 let DecoderMethod = "DecodeT2SOImm"; 101} 102 103// t2_so_imm_not - Match an immediate that is a complement 104// of a t2_so_imm. 105// Note: this pattern doesn't require an encoder method and such, as it's 106// only used on aliases (Pat<> and InstAlias<>). The actual encoding 107// is handled by the destination instructions, which use t2_so_imm. 108def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; } 109def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{ 110 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1; 111}], t2_so_imm_not_XFORM> { 112 let ParserMatchClass = t2_so_imm_not_asmoperand; 113} 114 115// t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm 116// if the upper 16 bits are zero. 117def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{ 118 APInt apIntN = N->getAPIntValue(); 119 if (!apIntN.isIntN(16)) return false; 120 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue(); 121 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1; 122 }], t2_so_imm_notSext16_XFORM> { 123 let ParserMatchClass = t2_so_imm_not_asmoperand; 124} 125 126// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. 127def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; } 128def t2_so_imm_neg : Operand<i32>, ImmLeaf<i32, [{ 129 return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1; 130}], t2_so_imm_neg_XFORM> { 131 let ParserMatchClass = t2_so_imm_neg_asmoperand; 132} 133 134/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0,4095]. 135def imm0_4095_asmoperand: ImmAsmOperand<0,4095> { let Name = "Imm0_4095"; } 136def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{ 137 return Imm >= 0 && Imm < 4096; 138}]> { 139 let ParserMatchClass = imm0_4095_asmoperand; 140} 141 142def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; } 143def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{ 144 return (uint32_t)(-N->getZExtValue()) < 4096; 145}], imm_neg_XFORM> { 146 let ParserMatchClass = imm0_4095_neg_asmoperand; 147} 148 149def imm1_255_neg : PatLeaf<(i32 imm), [{ 150 uint32_t Val = -N->getZExtValue(); 151 return (Val > 0 && Val < 255); 152}], imm_neg_XFORM>; 153 154def imm0_255_not : PatLeaf<(i32 imm), [{ 155 return (uint32_t)(~N->getZExtValue()) < 255; 156}], imm_not_XFORM>; 157 158def lo5AllOne : PatLeaf<(i32 imm), [{ 159 // Returns true if all low 5-bits are 1. 160 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL; 161}]>; 162 163// Define Thumb2 specific addressing modes. 164 165// t2_addr_offset_none := reg 166def MemNoOffsetT2AsmOperand 167 : AsmOperandClass { let Name = "MemNoOffsetT2"; } 168def t2_addr_offset_none : MemOperand { 169 let PrintMethod = "printAddrMode7Operand"; 170 let DecoderMethod = "DecodeGPRnopcRegisterClass"; 171 let ParserMatchClass = MemNoOffsetT2AsmOperand; 172 let MIOperandInfo = (ops GPRnopc:$base); 173} 174 175// t2_nosp_addr_offset_none := reg 176def MemNoOffsetT2NoSpAsmOperand 177 : AsmOperandClass { let Name = "MemNoOffsetT2NoSp"; } 178def t2_nosp_addr_offset_none : MemOperand { 179 let PrintMethod = "printAddrMode7Operand"; 180 let DecoderMethod = "DecoderGPRRegisterClass"; 181 let ParserMatchClass = MemNoOffsetT2NoSpAsmOperand; 182 let MIOperandInfo = (ops rGPR:$base); 183} 184 185// t2addrmode_imm12 := reg + imm12 186def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";} 187def t2addrmode_imm12 : MemOperand, 188 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> { 189 let PrintMethod = "printAddrModeImm12Operand<false>"; 190 let EncoderMethod = "getAddrModeImm12OpValue"; 191 let DecoderMethod = "DecodeT2AddrModeImm12"; 192 let ParserMatchClass = t2addrmode_imm12_asmoperand; 193 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 194} 195 196// t2ldrlabel := imm12 197def t2ldrlabel : Operand<i32> { 198 let EncoderMethod = "getAddrModeImm12OpValue"; 199 let PrintMethod = "printThumbLdrLabelOperand"; 200} 201 202def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";} 203def t2ldr_pcrel_imm12 : Operand<i32> { 204 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand; 205 // used for assembler pseudo instruction and maps to t2ldrlabel, so 206 // doesn't need encoder or print methods of its own. 207} 208 209// ADR instruction labels. 210def t2adrlabel : Operand<i32> { 211 let EncoderMethod = "getT2AdrLabelOpValue"; 212 let PrintMethod = "printAdrLabelOperand<0>"; 213} 214 215// t2addrmode_posimm8 := reg + imm8 216def MemPosImm8OffsetAsmOperand : AsmOperandClass { 217 let Name="MemPosImm8Offset"; 218 let RenderMethod = "addMemImmOffsetOperands"; 219} 220def t2addrmode_posimm8 : MemOperand { 221 let PrintMethod = "printT2AddrModeImm8Operand<false>"; 222 let EncoderMethod = "getT2AddrModeImmOpValue<8,0>"; 223 let DecoderMethod = "DecodeT2AddrModeImm8"; 224 let ParserMatchClass = MemPosImm8OffsetAsmOperand; 225 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 226} 227 228// t2addrmode_negimm8 := reg - imm8 229def MemNegImm8OffsetAsmOperand : AsmOperandClass { 230 let Name="MemNegImm8Offset"; 231 let RenderMethod = "addMemImmOffsetOperands"; 232} 233def t2addrmode_negimm8 : MemOperand, 234 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 235 let PrintMethod = "printT2AddrModeImm8Operand<false>"; 236 let EncoderMethod = "getT2AddrModeImmOpValue<8,0>"; 237 let DecoderMethod = "DecodeT2AddrModeImm8"; 238 let ParserMatchClass = MemNegImm8OffsetAsmOperand; 239 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 240} 241 242// t2addrmode_imm8 := reg +/- imm8 243def MemImm8OffsetAsmOperand : AsmOperandClass { 244 let Name = "MemImm8Offset"; 245 let RenderMethod = "addMemImmOffsetOperands"; 246} 247class T2AddrMode_Imm8 : MemOperand, 248 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 249 let EncoderMethod = "getT2AddrModeImmOpValue<8,0>"; 250 let DecoderMethod = "DecodeT2AddrModeImm8"; 251 let ParserMatchClass = MemImm8OffsetAsmOperand; 252 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 253} 254 255def t2addrmode_imm8 : T2AddrMode_Imm8 { 256 let PrintMethod = "printT2AddrModeImm8Operand<false>"; 257} 258 259def t2addrmode_imm8_pre : T2AddrMode_Imm8 { 260 let PrintMethod = "printT2AddrModeImm8Operand<true>"; 261} 262 263def t2am_imm8_offset : MemOperand, 264 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", 265 [], [SDNPWantRoot]> { 266 let PrintMethod = "printT2AddrModeImm8OffsetOperand"; 267 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue"; 268 let DecoderMethod = "DecodeT2Imm8"; 269} 270 271// t2addrmode_imm8s4 := reg +/- (imm8 << 2) 272def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";} 273class T2AddrMode_Imm8s4 : MemOperand, 274 ComplexPattern<i32, 2, "SelectT2AddrModeImm8<2>", []> { 275 let EncoderMethod = "getT2AddrModeImm8s4OpValue"; 276 let DecoderMethod = "DecodeT2AddrModeImm8s4"; 277 let ParserMatchClass = MemImm8s4OffsetAsmOperand; 278 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 279} 280 281def t2addrmode_imm8s4 : T2AddrMode_Imm8s4 { 282 let PrintMethod = "printT2AddrModeImm8s4Operand<false>"; 283} 284 285def t2addrmode_imm8s4_pre : T2AddrMode_Imm8s4 { 286 let PrintMethod = "printT2AddrModeImm8s4Operand<true>"; 287} 288 289def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; } 290def t2am_imm8s4_offset : MemOperand { 291 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand"; 292 let EncoderMethod = "getT2ScaledImmOpValue<8,2>"; 293 let DecoderMethod = "DecodeT2Imm8S4"; 294} 295 296// t2addrmode_imm7s4 := reg +/- (imm7 << 2) 297def MemImm7s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm7s4Offset";} 298class T2AddrMode_Imm7s4 : MemOperand { 299 let EncoderMethod = "getT2AddrModeImm7s4OpValue"; 300 let DecoderMethod = "DecodeT2AddrModeImm7<2,0>"; 301 let ParserMatchClass = MemImm7s4OffsetAsmOperand; 302 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm); 303} 304 305def t2addrmode_imm7s4 : T2AddrMode_Imm7s4 { 306 // They are printed the same way as the imm8 version 307 let PrintMethod = "printT2AddrModeImm8s4Operand<false>"; 308} 309 310def t2addrmode_imm7s4_pre : T2AddrMode_Imm7s4 { 311 // They are printed the same way as the imm8 version 312 let PrintMethod = "printT2AddrModeImm8s4Operand<true>"; 313} 314 315def t2am_imm7s4_offset_asmoperand : AsmOperandClass { let Name = "Imm7s4"; } 316def t2am_imm7s4_offset : MemOperand { 317 // They are printed the same way as the imm8 version 318 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand"; 319 let ParserMatchClass = t2am_imm7s4_offset_asmoperand; 320 let EncoderMethod = "getT2ScaledImmOpValue<7,2>"; 321 let DecoderMethod = "DecodeT2Imm7S4"; 322} 323 324// t2addrmode_imm0_1020s4 := reg + (imm8 << 2) 325def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass { 326 let Name = "MemImm0_1020s4Offset"; 327} 328def t2addrmode_imm0_1020s4 : MemOperand, 329 ComplexPattern<i32, 2, "SelectT2AddrModeExclusive"> { 330 let PrintMethod = "printT2AddrModeImm0_1020s4Operand"; 331 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue"; 332 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4"; 333 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand; 334 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm); 335} 336 337// t2addrmode_so_reg := reg + (reg << imm2) 338def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";} 339def t2addrmode_so_reg : MemOperand, 340 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { 341 let PrintMethod = "printT2AddrModeSoRegOperand"; 342 let EncoderMethod = "getT2AddrModeSORegOpValue"; 343 let DecoderMethod = "DecodeT2AddrModeSOReg"; 344 let ParserMatchClass = t2addrmode_so_reg_asmoperand; 345 let MIOperandInfo = (ops GPRnopc:$base, rGPR:$offsreg, i32imm:$offsimm); 346} 347 348// Addresses for the TBB/TBH instructions. 349def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; } 350def addrmode_tbb : MemOperand { 351 let PrintMethod = "printAddrModeTBB"; 352 let ParserMatchClass = addrmode_tbb_asmoperand; 353 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm); 354} 355def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; } 356def addrmode_tbh : MemOperand { 357 let PrintMethod = "printAddrModeTBH"; 358 let ParserMatchClass = addrmode_tbh_asmoperand; 359 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm); 360} 361 362// Define ARMv8.1-M specific addressing modes. 363 364// Label operands for BF/BFL/WLS/DLS/LE 365class BFLabelOp<string signed, string isNeg, string zeroPermitted, string size, 366 string fixup> 367 : Operand<OtherVT> { 368 let EncoderMethod = !strconcat("getBFTargetOpValue<", isNeg, ", ", 369 fixup, ">"); 370 let OperandType = "OPERAND_PCREL"; 371 let DecoderMethod = !strconcat("DecodeBFLabelOperand<", signed, ", ", 372 isNeg, ", ", zeroPermitted, ", ", size, ">"); 373} 374def bflabel_u4 : BFLabelOp<"false", "false", "false", "4", "ARM::fixup_bf_branch">; 375def bflabel_s12 : BFLabelOp<"true", "false", "true", "12", "ARM::fixup_bfc_target">; 376def bflabel_s16 : BFLabelOp<"true", "false", "true", "16", "ARM::fixup_bf_target">; 377def bflabel_s18 : BFLabelOp<"true", "false", "true", "18", "ARM::fixup_bfl_target">; 378 379def wlslabel_u11_asmoperand : AsmOperandClass { 380 let Name = "WLSLabel"; 381 let RenderMethod = "addImmOperands"; 382 let PredicateMethod = "isUnsignedOffset<11, 1>"; 383 let DiagnosticString = 384 "loop end is out of range or not a positive multiple of 2"; 385} 386def wlslabel_u11 : BFLabelOp<"false", "false", "true", "11", "ARM::fixup_wls"> { 387 let ParserMatchClass = wlslabel_u11_asmoperand; 388} 389def lelabel_u11_asmoperand : AsmOperandClass { 390 let Name = "LELabel"; 391 let RenderMethod = "addImmOperands"; 392 let PredicateMethod = "isLEOffset"; 393 let DiagnosticString = 394 "loop start is out of range or not a negative multiple of 2"; 395} 396def lelabel_u11 : BFLabelOp<"false", "true", "true", "11", "ARM::fixup_le"> { 397 let ParserMatchClass = lelabel_u11_asmoperand; 398} 399 400def bfafter_target : Operand<OtherVT> { 401 let EncoderMethod = "getBFAfterTargetOpValue"; 402 let OperandType = "OPERAND_PCREL"; 403 let DecoderMethod = "DecodeBFAfterTargetOperand"; 404} 405 406// pred operand excluding AL 407def pred_noal_asmoperand : AsmOperandClass { 408 let Name = "CondCodeNoAL"; 409 let RenderMethod = "addITCondCodeOperands"; 410 let PredicateMethod = "isITCondCodeNoAL"; 411 let ParserMethod = "parseITCondCode"; 412} 413def pred_noal : Operand<i32> { 414 let PrintMethod = "printMandatoryPredicateOperand"; 415 let ParserMatchClass = pred_noal_asmoperand; 416 let DecoderMethod = "DecodePredNoALOperand"; 417} 418 419 420// CSEL aliases inverted predicate 421def pred_noal_inv_asmoperand : AsmOperandClass { 422 let Name = "CondCodeNoALInv"; 423 let RenderMethod = "addITCondCodeInvOperands"; 424 let PredicateMethod = "isITCondCodeNoAL"; 425 let ParserMethod = "parseITCondCode"; 426} 427def pred_noal_inv : Operand<i32> { 428 let PrintMethod = "printMandatoryInvertedPredicateOperand"; 429 let ParserMatchClass = pred_noal_inv_asmoperand; 430} 431//===----------------------------------------------------------------------===// 432// Multiclass helpers... 433// 434 435 436class T2OneRegImm<dag oops, dag iops, InstrItinClass itin, 437 string opc, string asm, list<dag> pattern> 438 : T2I<oops, iops, itin, opc, asm, pattern> { 439 bits<4> Rd; 440 bits<12> imm; 441 442 let Inst{11-8} = Rd; 443 let Inst{26} = imm{11}; 444 let Inst{14-12} = imm{10-8}; 445 let Inst{7-0} = imm{7-0}; 446} 447 448 449class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin, 450 string opc, string asm, list<dag> pattern> 451 : T2sI<oops, iops, itin, opc, asm, pattern> { 452 bits<4> Rd; 453 bits<4> Rn; 454 bits<12> imm; 455 456 let Inst{11-8} = Rd; 457 let Inst{26} = imm{11}; 458 let Inst{14-12} = imm{10-8}; 459 let Inst{7-0} = imm{7-0}; 460} 461 462class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin, 463 string opc, string asm, list<dag> pattern> 464 : T2I<oops, iops, itin, opc, asm, pattern> { 465 bits<4> Rn; 466 bits<12> imm; 467 468 let Inst{19-16} = Rn; 469 let Inst{26} = imm{11}; 470 let Inst{14-12} = imm{10-8}; 471 let Inst{7-0} = imm{7-0}; 472} 473 474 475class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 476 string opc, string asm, list<dag> pattern> 477 : T2I<oops, iops, itin, opc, asm, pattern> { 478 bits<4> Rd; 479 bits<12> ShiftedRm; 480 481 let Inst{11-8} = Rd; 482 let Inst{3-0} = ShiftedRm{3-0}; 483 let Inst{5-4} = ShiftedRm{6-5}; 484 let Inst{14-12} = ShiftedRm{11-9}; 485 let Inst{7-6} = ShiftedRm{8-7}; 486} 487 488class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 489 string opc, string asm, list<dag> pattern> 490 : T2sI<oops, iops, itin, opc, asm, pattern> { 491 bits<4> Rd; 492 bits<12> ShiftedRm; 493 494 let Inst{11-8} = Rd; 495 let Inst{3-0} = ShiftedRm{3-0}; 496 let Inst{5-4} = ShiftedRm{6-5}; 497 let Inst{14-12} = ShiftedRm{11-9}; 498 let Inst{7-6} = ShiftedRm{8-7}; 499} 500 501class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin, 502 string opc, string asm, list<dag> pattern> 503 : T2I<oops, iops, itin, opc, asm, pattern> { 504 bits<4> Rn; 505 bits<12> ShiftedRm; 506 507 let Inst{19-16} = Rn; 508 let Inst{3-0} = ShiftedRm{3-0}; 509 let Inst{5-4} = ShiftedRm{6-5}; 510 let Inst{14-12} = ShiftedRm{11-9}; 511 let Inst{7-6} = ShiftedRm{8-7}; 512} 513 514class T2TwoReg<dag oops, dag iops, InstrItinClass itin, 515 string opc, string asm, list<dag> pattern> 516 : T2I<oops, iops, itin, opc, asm, pattern> { 517 bits<4> Rd; 518 bits<4> Rm; 519 520 let Inst{11-8} = Rd; 521 let Inst{3-0} = Rm; 522} 523 524class T2sTwoReg<dag oops, dag iops, InstrItinClass itin, 525 string opc, string asm, list<dag> pattern> 526 : T2sI<oops, iops, itin, opc, asm, pattern> { 527 bits<4> Rd; 528 bits<4> Rm; 529 530 let Inst{11-8} = Rd; 531 let Inst{3-0} = Rm; 532} 533 534class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin, 535 string opc, string asm, list<dag> pattern> 536 : T2I<oops, iops, itin, opc, asm, pattern> { 537 bits<4> Rn; 538 bits<4> Rm; 539 540 let Inst{19-16} = Rn; 541 let Inst{3-0} = Rm; 542} 543 544 545class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin, 546 string opc, string asm, list<dag> pattern> 547 : T2I<oops, iops, itin, opc, asm, pattern> { 548 bits<4> Rd; 549 bits<4> Rn; 550 bits<12> imm; 551 552 let Inst{11-8} = Rd; 553 let Inst{19-16} = Rn; 554 let Inst{26} = imm{11}; 555 let Inst{14-12} = imm{10-8}; 556 let Inst{7-0} = imm{7-0}; 557} 558 559class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin, 560 string opc, string asm, list<dag> pattern> 561 : T2sI<oops, iops, itin, opc, asm, pattern> { 562 bits<4> Rd; 563 bits<4> Rn; 564 bits<12> imm; 565 566 let Inst{11-8} = Rd; 567 let Inst{19-16} = Rn; 568 let Inst{26} = imm{11}; 569 let Inst{14-12} = imm{10-8}; 570 let Inst{7-0} = imm{7-0}; 571} 572 573class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin, 574 string opc, string asm, list<dag> pattern> 575 : T2I<oops, iops, itin, opc, asm, pattern> { 576 bits<4> Rd; 577 bits<4> Rm; 578 bits<5> imm; 579 580 let Inst{11-8} = Rd; 581 let Inst{3-0} = Rm; 582 let Inst{14-12} = imm{4-2}; 583 let Inst{7-6} = imm{1-0}; 584} 585 586class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin, 587 string opc, string asm, list<dag> pattern> 588 : T2sI<oops, iops, itin, opc, asm, pattern> { 589 bits<4> Rd; 590 bits<4> Rm; 591 bits<5> imm; 592 593 let Inst{11-8} = Rd; 594 let Inst{3-0} = Rm; 595 let Inst{14-12} = imm{4-2}; 596 let Inst{7-6} = imm{1-0}; 597} 598 599class T2ThreeReg<dag oops, dag iops, InstrItinClass itin, 600 string opc, string asm, list<dag> pattern> 601 : T2I<oops, iops, itin, opc, asm, pattern> { 602 bits<4> Rd; 603 bits<4> Rn; 604 bits<4> Rm; 605 606 let Inst{11-8} = Rd; 607 let Inst{19-16} = Rn; 608 let Inst{3-0} = Rm; 609} 610 611class T2ThreeRegNoP<dag oops, dag iops, InstrItinClass itin, 612 string asm, list<dag> pattern> 613 : T2XI<oops, iops, itin, asm, pattern> { 614 bits<4> Rd; 615 bits<4> Rn; 616 bits<4> Rm; 617 618 let Inst{11-8} = Rd; 619 let Inst{19-16} = Rn; 620 let Inst{3-0} = Rm; 621} 622 623class T2sThreeReg<dag oops, dag iops, InstrItinClass itin, 624 string opc, string asm, list<dag> pattern> 625 : T2sI<oops, iops, itin, opc, asm, pattern> { 626 bits<4> Rd; 627 bits<4> Rn; 628 bits<4> Rm; 629 630 let Inst{11-8} = Rd; 631 let Inst{19-16} = Rn; 632 let Inst{3-0} = Rm; 633} 634 635class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 636 string opc, string asm, list<dag> pattern> 637 : T2I<oops, iops, itin, opc, asm, pattern> { 638 bits<4> Rd; 639 bits<4> Rn; 640 bits<12> ShiftedRm; 641 642 let Inst{11-8} = Rd; 643 let Inst{19-16} = Rn; 644 let Inst{3-0} = ShiftedRm{3-0}; 645 let Inst{5-4} = ShiftedRm{6-5}; 646 let Inst{14-12} = ShiftedRm{11-9}; 647 let Inst{7-6} = ShiftedRm{8-7}; 648} 649 650class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 651 string opc, string asm, list<dag> pattern> 652 : T2sI<oops, iops, itin, opc, asm, pattern> { 653 bits<4> Rd; 654 bits<4> Rn; 655 bits<12> ShiftedRm; 656 657 let Inst{11-8} = Rd; 658 let Inst{19-16} = Rn; 659 let Inst{3-0} = ShiftedRm{3-0}; 660 let Inst{5-4} = ShiftedRm{6-5}; 661 let Inst{14-12} = ShiftedRm{11-9}; 662 let Inst{7-6} = ShiftedRm{8-7}; 663} 664 665class T2FourReg<dag oops, dag iops, InstrItinClass itin, 666 string opc, string asm, list<dag> pattern> 667 : T2I<oops, iops, itin, opc, asm, pattern> { 668 bits<4> Rd; 669 bits<4> Rn; 670 bits<4> Rm; 671 bits<4> Ra; 672 673 let Inst{19-16} = Rn; 674 let Inst{15-12} = Ra; 675 let Inst{11-8} = Rd; 676 let Inst{3-0} = Rm; 677} 678 679class T2MulLong<bits<3> opc22_20, bits<4> opc7_4, 680 string opc, list<dag> pattern> 681 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64, 682 opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern>, 683 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]> { 684 bits<4> RdLo; 685 bits<4> RdHi; 686 bits<4> Rn; 687 bits<4> Rm; 688 689 let Inst{31-23} = 0b111110111; 690 let Inst{22-20} = opc22_20; 691 let Inst{19-16} = Rn; 692 let Inst{15-12} = RdLo; 693 let Inst{11-8} = RdHi; 694 let Inst{7-4} = opc7_4; 695 let Inst{3-0} = Rm; 696} 697class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4, string opc> 698 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), 699 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64, 700 opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>, 701 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 702 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> { 703 bits<4> RdLo; 704 bits<4> RdHi; 705 bits<4> Rn; 706 bits<4> Rm; 707 708 let Inst{31-23} = 0b111110111; 709 let Inst{22-20} = opc22_20; 710 let Inst{19-16} = Rn; 711 let Inst{15-12} = RdLo; 712 let Inst{11-8} = RdHi; 713 let Inst{7-4} = opc7_4; 714 let Inst{3-0} = Rm; 715} 716 717 718/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 719/// binary operation that produces a value. These are predicable and can be 720/// changed to modify CPSR. 721multiclass T2I_bin_irs<bits<4> opcod, string opc, 722 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 723 SDPatternOperator opnode, bit Commutable = 0, 724 string wide = ""> { 725 // shifted imm 726 def ri : T2sTwoRegImm< 727 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii, 728 opc, "\t$Rd, $Rn, $imm", 729 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>, 730 Sched<[WriteALU, ReadALU]> { 731 let Inst{31-27} = 0b11110; 732 let Inst{25} = 0; 733 let Inst{24-21} = opcod; 734 let Inst{15} = 0; 735 } 736 // register 737 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir, 738 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"), 739 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>, 740 Sched<[WriteALU, ReadALU, ReadALU]> { 741 let isCommutable = Commutable; 742 let Inst{31-27} = 0b11101; 743 let Inst{26-25} = 0b01; 744 let Inst{24-21} = opcod; 745 let Inst{15} = 0b0; 746 // In most of these instructions, and most versions of the Arm 747 // architecture, bit 15 of this encoding is listed as (0) rather 748 // than 0, i.e. setting it to 1 is UNPREDICTABLE or a soft-fail 749 // rather than a hard failure. In v8.1-M, this requirement is 750 // upgraded to a hard one for ORR, so that the encodings with 1 751 // in this bit can be reused for other instructions (such as 752 // CSEL). Setting Unpredictable{15} = 1 here would reintroduce 753 // that encoding clash in the auto- generated MC decoder, so I 754 // comment it out. 755 let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1); 756 let Inst{14-12} = 0b000; // imm3 757 let Inst{7-6} = 0b00; // imm2 758 let Inst{5-4} = 0b00; // type 759 } 760 // shifted register 761 def rs : T2sTwoRegShiftedReg< 762 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis, 763 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"), 764 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>, 765 Sched<[WriteALUsi, ReadALU]> { 766 let Inst{31-27} = 0b11101; 767 let Inst{26-25} = 0b01; 768 let Inst{24-21} = opcod; 769 let Inst{15} = 0; 770 let Unpredictable{15} = !if(!eq(opcod, 0b0010), 0b0, 0b1); // see above 771 } 772 // Assembly aliases for optional destination operand when it's the same 773 // as the source operand. 774 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"), 775 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, 776 t2_so_imm:$imm, pred:$p, 777 cc_out:$s)>; 778 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"), 779 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, 780 rGPR:$Rm, pred:$p, 781 cc_out:$s)>; 782 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"), 783 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, 784 t2_so_reg:$shift, pred:$p, 785 cc_out:$s)>; 786} 787 788/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need 789// the ".w" suffix to indicate that they are wide. 790multiclass T2I_bin_w_irs<bits<4> opcod, string opc, 791 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 792 SDPatternOperator opnode, bit Commutable = 0> : 793 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> { 794 // Assembler aliases w/ the ".w" suffix. 795 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"), 796 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, 797 cc_out:$s)>; 798 // Assembler aliases w/o the ".w" suffix. 799 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"), 800 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, 801 cc_out:$s)>; 802 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"), 803 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift, 804 pred:$p, cc_out:$s)>; 805 806 // and with the optional destination operand, too. 807 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"), 808 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, 809 pred:$p, cc_out:$s)>; 810 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"), 811 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, 812 cc_out:$s)>; 813 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"), 814 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift, 815 pred:$p, cc_out:$s)>; 816} 817 818/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are 819/// reversed. The 'rr' form is only defined for the disassembler; for codegen 820/// it is equivalent to the T2I_bin_irs counterpart. 821multiclass T2I_rbin_irs<bits<4> opcod, string opc, SDNode opnode> { 822 // shifted imm 823 def ri : T2sTwoRegImm< 824 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, 825 opc, ".w\t$Rd, $Rn, $imm", 826 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>, 827 Sched<[WriteALU, ReadALU]> { 828 let Inst{31-27} = 0b11110; 829 let Inst{25} = 0; 830 let Inst{24-21} = opcod; 831 let Inst{15} = 0; 832 } 833 // register 834 def rr : T2sThreeReg< 835 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, 836 opc, "\t$Rd, $Rn, $Rm", 837 [/* For disassembly only; pattern left blank */]>, 838 Sched<[WriteALU, ReadALU, ReadALU]> { 839 let Inst{31-27} = 0b11101; 840 let Inst{26-25} = 0b01; 841 let Inst{24-21} = opcod; 842 let Inst{14-12} = 0b000; // imm3 843 let Inst{7-6} = 0b00; // imm2 844 let Inst{5-4} = 0b00; // type 845 } 846 // shifted register 847 def rs : T2sTwoRegShiftedReg< 848 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), 849 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm", 850 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>, 851 Sched<[WriteALUsi, ReadALU]> { 852 let Inst{31-27} = 0b11101; 853 let Inst{26-25} = 0b01; 854 let Inst{24-21} = opcod; 855 } 856} 857 858/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the 859/// instruction modifies the CPSR register. 860/// 861/// These opcodes will be converted to the real non-S opcodes by 862/// AdjustInstrPostInstrSelection after giving then an optional CPSR operand. 863let hasPostISelHook = 1, Defs = [CPSR] in { 864multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 865 InstrItinClass iis, SDNode opnode, 866 bit Commutable = 0> { 867 // shifted imm 868 def ri : t2PseudoInst<(outs rGPR:$Rd), 869 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p), 870 4, iii, 871 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, 872 t2_so_imm:$imm))]>, 873 Sched<[WriteALU, ReadALU]>; 874 // register 875 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p), 876 4, iir, 877 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, 878 rGPR:$Rm))]>, 879 Sched<[WriteALU, ReadALU, ReadALU]> { 880 let isCommutable = Commutable; 881 } 882 // shifted register 883 def rs : t2PseudoInst<(outs rGPR:$Rd), 884 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p), 885 4, iis, 886 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, 887 t2_so_reg:$ShiftedRm))]>, 888 Sched<[WriteALUsi, ReadALUsr]>; 889} 890} 891 892/// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG 893/// operands are reversed. 894let hasPostISelHook = 1, Defs = [CPSR] in { 895multiclass T2I_rbin_s_is<SDNode opnode> { 896 // shifted imm 897 def ri : t2PseudoInst<(outs rGPR:$Rd), 898 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p), 899 4, IIC_iALUi, 900 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, 901 rGPR:$Rn))]>, 902 Sched<[WriteALU, ReadALU]>; 903 // shifted register 904 def rs : t2PseudoInst<(outs rGPR:$Rd), 905 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p), 906 4, IIC_iALUsi, 907 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, 908 rGPR:$Rn))]>, 909 Sched<[WriteALUsi, ReadALU]>; 910} 911} 912 913/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) 914/// patterns for a binary operation that produces a value. 915multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, SDNode opnode, 916 bit Commutable = 0> { 917 // shifted imm 918 // The register-immediate version is re-materializable. This is useful 919 // in particular for taking the address of a local. 920 let isReMaterializable = 1 in { 921 def spImm : T2sTwoRegImm< 922 (outs GPRsp:$Rd), (ins GPRsp:$Rn, t2_so_imm:$imm), IIC_iALUi, 923 opc, ".w\t$Rd, $Rn, $imm", 924 []>, 925 Sched<[WriteALU, ReadALU]> { 926 let Rn = 13; 927 let Rd = 13; 928 929 let Inst{31-27} = 0b11110; 930 let Inst{25-24} = 0b01; 931 let Inst{23-21} = op23_21; 932 let Inst{15} = 0; 933 934 let DecoderMethod = "DecodeT2AddSubSPImm"; 935 } 936 937 def ri : T2sTwoRegImm< 938 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi, 939 opc, ".w\t$Rd, $Rn, $imm", 940 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>, 941 Sched<[WriteALU, ReadALU]> { 942 let Inst{31-27} = 0b11110; 943 let Inst{25} = 0; 944 let Inst{24} = 1; 945 let Inst{23-21} = op23_21; 946 let Inst{15} = 0; 947 } 948 } 949 // 12-bit imm 950 def ri12 : T2I< 951 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi, 952 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm", 953 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>, 954 Sched<[WriteALU, ReadALU]> { 955 bits<4> Rd; 956 bits<4> Rn; 957 bits<12> imm; 958 let Inst{31-27} = 0b11110; 959 let Inst{26} = imm{11}; 960 let Inst{25-24} = 0b10; 961 let Inst{23-21} = op23_21; 962 let Inst{20} = 0; // The S bit. 963 let Inst{19-16} = Rn; 964 let Inst{15} = 0; 965 let Inst{14-12} = imm{10-8}; 966 let Inst{11-8} = Rd; 967 let Inst{7-0} = imm{7-0}; 968 } 969 def spImm12 : T2I< 970 (outs GPRsp:$Rd), (ins GPRsp:$Rn, imm0_4095:$imm), IIC_iALUi, 971 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm", 972 []>, 973 Sched<[WriteALU, ReadALU]> { 974 bits<4> Rd = 13; 975 bits<4> Rn = 13; 976 bits<12> imm; 977 let Inst{31-27} = 0b11110; 978 let Inst{26} = imm{11}; 979 let Inst{25-24} = 0b10; 980 let Inst{23-21} = op23_21; 981 let Inst{20} = 0; // The S bit. 982 let Inst{19-16} = Rn; 983 let Inst{15} = 0; 984 let Inst{14-12} = imm{10-8}; 985 let Inst{11-8} = Rd; 986 let Inst{7-0} = imm{7-0}; 987 let DecoderMethod = "DecodeT2AddSubSPImm"; 988 } 989 // register 990 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), 991 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm", 992 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>, 993 Sched<[WriteALU, ReadALU, ReadALU]> { 994 let isCommutable = Commutable; 995 let Inst{31-27} = 0b11101; 996 let Inst{26-25} = 0b01; 997 let Inst{24} = 1; 998 let Inst{23-21} = op23_21; 999 let Inst{14-12} = 0b000; // imm3 1000 let Inst{7-6} = 0b00; // imm2 1001 let Inst{5-4} = 0b00; // type 1002 } 1003 // shifted register 1004 def rs : T2sTwoRegShiftedReg< 1005 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), 1006 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", 1007 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>, 1008 Sched<[WriteALUsi, ReadALU]> { 1009 let Inst{31-27} = 0b11101; 1010 let Inst{26-25} = 0b01; 1011 let Inst{24} = 1; 1012 let Inst{23-21} = op23_21; 1013 } 1014} 1015 1016/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns 1017/// for a binary operation that produces a value and use the carry 1018/// bit. It's not predicable. 1019let Defs = [CPSR], Uses = [CPSR] in { 1020multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode, 1021 bit Commutable = 0> { 1022 // shifted imm 1023 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), 1024 IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1025 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>, 1026 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> { 1027 let Inst{31-27} = 0b11110; 1028 let Inst{25} = 0; 1029 let Inst{24-21} = opcod; 1030 let Inst{15} = 0; 1031 } 1032 // register 1033 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, 1034 opc, ".w\t$Rd, $Rn, $Rm", 1035 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>, 1036 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> { 1037 let isCommutable = Commutable; 1038 let Inst{31-27} = 0b11101; 1039 let Inst{26-25} = 0b01; 1040 let Inst{24-21} = opcod; 1041 let Inst{14-12} = 0b000; // imm3 1042 let Inst{7-6} = 0b00; // imm2 1043 let Inst{5-4} = 0b00; // type 1044 } 1045 // shifted register 1046 def rs : T2sTwoRegShiftedReg< 1047 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), 1048 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", 1049 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>, 1050 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> { 1051 let Inst{31-27} = 0b11101; 1052 let Inst{26-25} = 0b01; 1053 let Inst{24-21} = opcod; 1054 } 1055} 1056} 1057 1058/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift / 1059// rotate operation that produces a value. 1060multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, SDNode opnode> { 1061 // 5-bit imm 1062 def ri : T2sTwoRegShiftImm< 1063 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi, 1064 opc, ".w\t$Rd, $Rm, $imm", 1065 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>, 1066 Sched<[WriteALU]> { 1067 let Inst{31-27} = 0b11101; 1068 let Inst{26-21} = 0b010010; 1069 let Inst{19-16} = 0b1111; // Rn 1070 let Inst{15} = 0b0; 1071 let Inst{5-4} = opcod; 1072 } 1073 // register 1074 def rr : T2sThreeReg< 1075 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr, 1076 opc, ".w\t$Rd, $Rn, $Rm", 1077 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>, 1078 Sched<[WriteALU]> { 1079 let Inst{31-27} = 0b11111; 1080 let Inst{26-23} = 0b0100; 1081 let Inst{22-21} = opcod; 1082 let Inst{15-12} = 0b1111; 1083 let Inst{7-4} = 0b0000; 1084 } 1085 1086 // Optional destination register 1087 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"), 1088 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p, 1089 cc_out:$s)>; 1090 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"), 1091 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, 1092 cc_out:$s)>; 1093 1094 // Assembler aliases w/o the ".w" suffix. 1095 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"), 1096 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p, 1097 cc_out:$s)>; 1098 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"), 1099 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, 1100 cc_out:$s)>; 1101 1102 // and with the optional destination operand, too. 1103 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"), 1104 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p, 1105 cc_out:$s)>; 1106 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"), 1107 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, 1108 cc_out:$s)>; 1109} 1110 1111/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 1112/// patterns. Similar to T2I_bin_irs except the instruction does not produce 1113/// a explicit result, only implicitly set CPSR. 1114multiclass T2I_cmp_irs<bits<4> opcod, string opc, RegisterClass LHSGPR, 1115 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1116 SDPatternOperator opnode> { 1117let isCompare = 1, Defs = [CPSR] in { 1118 // shifted imm 1119 def ri : T2OneRegCmpImm< 1120 (outs), (ins LHSGPR:$Rn, t2_so_imm:$imm), iii, 1121 opc, ".w\t$Rn, $imm", 1122 [(opnode LHSGPR:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> { 1123 let Inst{31-27} = 0b11110; 1124 let Inst{25} = 0; 1125 let Inst{24-21} = opcod; 1126 let Inst{20} = 1; // The S bit. 1127 let Inst{15} = 0; 1128 let Inst{11-8} = 0b1111; // Rd 1129 } 1130 // register 1131 def rr : T2TwoRegCmp< 1132 (outs), (ins LHSGPR:$Rn, rGPR:$Rm), iir, 1133 opc, ".w\t$Rn, $Rm", 1134 [(opnode LHSGPR:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> { 1135 let Inst{31-27} = 0b11101; 1136 let Inst{26-25} = 0b01; 1137 let Inst{24-21} = opcod; 1138 let Inst{20} = 1; // The S bit. 1139 let Inst{14-12} = 0b000; // imm3 1140 let Inst{11-8} = 0b1111; // Rd 1141 let Inst{7-6} = 0b00; // imm2 1142 let Inst{5-4} = 0b00; // type 1143 } 1144 // shifted register 1145 def rs : T2OneRegCmpShiftedReg< 1146 (outs), (ins LHSGPR:$Rn, t2_so_reg:$ShiftedRm), iis, 1147 opc, ".w\t$Rn, $ShiftedRm", 1148 [(opnode LHSGPR:$Rn, t2_so_reg:$ShiftedRm)]>, 1149 Sched<[WriteCMPsi]> { 1150 let Inst{31-27} = 0b11101; 1151 let Inst{26-25} = 0b01; 1152 let Inst{24-21} = opcod; 1153 let Inst{20} = 1; // The S bit. 1154 let Inst{11-8} = 0b1111; // Rd 1155 } 1156} 1157 1158 // Assembler aliases w/o the ".w" suffix. 1159 // No alias here for 'rr' version as not all instantiations of this 1160 // multiclass want one (CMP in particular, does not). 1161 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"), 1162 (!cast<Instruction>(NAME#"ri") LHSGPR:$Rn, t2_so_imm:$imm, pred:$p)>; 1163 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"), 1164 (!cast<Instruction>(NAME#"rs") LHSGPR:$Rn, t2_so_reg:$shift, pred:$p)>; 1165} 1166 1167/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. 1168multiclass T2I_ld<bit signed, bits<2> opcod, string opc, 1169 InstrItinClass iii, InstrItinClass iis, RegisterClass target, 1170 PatFrag opnode> { 1171 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii, 1172 opc, ".w\t$Rt, $addr", 1173 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]>, 1174 Sched<[WriteLd]> { 1175 bits<4> Rt; 1176 bits<17> addr; 1177 let Inst{31-25} = 0b1111100; 1178 let Inst{24} = signed; 1179 let Inst{23} = 1; 1180 let Inst{22-21} = opcod; 1181 let Inst{20} = 1; // load 1182 let Inst{19-16} = addr{16-13}; // Rn 1183 let Inst{15-12} = Rt; 1184 let Inst{11-0} = addr{11-0}; // imm 1185 1186 let DecoderMethod = "DecodeT2LoadImm12"; 1187 } 1188 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii, 1189 opc, "\t$Rt, $addr", 1190 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]>, 1191 Sched<[WriteLd]> { 1192 bits<4> Rt; 1193 bits<13> addr; 1194 let Inst{31-27} = 0b11111; 1195 let Inst{26-25} = 0b00; 1196 let Inst{24} = signed; 1197 let Inst{23} = 0; 1198 let Inst{22-21} = opcod; 1199 let Inst{20} = 1; // load 1200 let Inst{19-16} = addr{12-9}; // Rn 1201 let Inst{15-12} = Rt; 1202 let Inst{11} = 1; 1203 // Offset: index==TRUE, wback==FALSE 1204 let Inst{10} = 1; // The P bit. 1205 let Inst{9} = addr{8}; // U 1206 let Inst{8} = 0; // The W bit. 1207 let Inst{7-0} = addr{7-0}; // imm 1208 1209 let DecoderMethod = "DecodeT2LoadImm8"; 1210 } 1211 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis, 1212 opc, ".w\t$Rt, $addr", 1213 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]>, 1214 Sched<[WriteLd]> { 1215 let Inst{31-27} = 0b11111; 1216 let Inst{26-25} = 0b00; 1217 let Inst{24} = signed; 1218 let Inst{23} = 0; 1219 let Inst{22-21} = opcod; 1220 let Inst{20} = 1; // load 1221 let Inst{11-6} = 0b000000; 1222 1223 bits<4> Rt; 1224 let Inst{15-12} = Rt; 1225 1226 bits<10> addr; 1227 let Inst{19-16} = addr{9-6}; // Rn 1228 let Inst{3-0} = addr{5-2}; // Rm 1229 let Inst{5-4} = addr{1-0}; // imm 1230 1231 let DecoderMethod = "DecodeT2LoadShift"; 1232 } 1233 1234 // pci variant is very similar to i12, but supports negative offsets 1235 // from the PC. 1236 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii, 1237 opc, ".w\t$Rt, $addr", 1238 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]>, 1239 Sched<[WriteLd]> { 1240 let isReMaterializable = 1; 1241 let Inst{31-27} = 0b11111; 1242 let Inst{26-25} = 0b00; 1243 let Inst{24} = signed; 1244 let Inst{22-21} = opcod; 1245 let Inst{20} = 1; // load 1246 let Inst{19-16} = 0b1111; // Rn 1247 1248 bits<4> Rt; 1249 let Inst{15-12} = Rt{3-0}; 1250 1251 bits<13> addr; 1252 let Inst{23} = addr{12}; // add = (U == '1') 1253 let Inst{11-0} = addr{11-0}; 1254 1255 let DecoderMethod = "DecodeT2LoadLabel"; 1256 } 1257} 1258 1259/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. 1260multiclass T2I_st<bits<2> opcod, string opc, 1261 InstrItinClass iii, InstrItinClass iis, RegisterClass target, 1262 PatFrag opnode> { 1263 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii, 1264 opc, ".w\t$Rt, $addr", 1265 [(opnode target:$Rt, t2addrmode_imm12:$addr)]>, 1266 Sched<[WriteST]> { 1267 let Inst{31-27} = 0b11111; 1268 let Inst{26-23} = 0b0001; 1269 let Inst{22-21} = opcod; 1270 let Inst{20} = 0; // !load 1271 1272 bits<4> Rt; 1273 let Inst{15-12} = Rt; 1274 1275 bits<17> addr; 1276 let addr{12} = 1; // add = TRUE 1277 let Inst{19-16} = addr{16-13}; // Rn 1278 let Inst{23} = addr{12}; // U 1279 let Inst{11-0} = addr{11-0}; // imm 1280 } 1281 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii, 1282 opc, "\t$Rt, $addr", 1283 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]>, 1284 Sched<[WriteST]> { 1285 let Inst{31-27} = 0b11111; 1286 let Inst{26-23} = 0b0000; 1287 let Inst{22-21} = opcod; 1288 let Inst{20} = 0; // !load 1289 let Inst{11} = 1; 1290 // Offset: index==TRUE, wback==FALSE 1291 let Inst{10} = 1; // The P bit. 1292 let Inst{8} = 0; // The W bit. 1293 1294 bits<4> Rt; 1295 let Inst{15-12} = Rt; 1296 1297 bits<13> addr; 1298 let Inst{19-16} = addr{12-9}; // Rn 1299 let Inst{9} = addr{8}; // U 1300 let Inst{7-0} = addr{7-0}; // imm 1301 } 1302 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis, 1303 opc, ".w\t$Rt, $addr", 1304 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]>, 1305 Sched<[WriteST]> { 1306 let Inst{31-27} = 0b11111; 1307 let Inst{26-23} = 0b0000; 1308 let Inst{22-21} = opcod; 1309 let Inst{20} = 0; // !load 1310 let Inst{11-6} = 0b000000; 1311 1312 bits<4> Rt; 1313 let Inst{15-12} = Rt; 1314 1315 bits<10> addr; 1316 let Inst{19-16} = addr{9-6}; // Rn 1317 let Inst{3-0} = addr{5-2}; // Rm 1318 let Inst{5-4} = addr{1-0}; // imm 1319 } 1320} 1321 1322/// T2I_ext_rrot - A unary operation with two forms: one whose operand is a 1323/// register and one whose operand is a register rotated by 8/16/24. 1324class T2I_ext_rrot_base<bits<3> opcod, dag iops, dag oops, 1325 string opc, string oprs, 1326 list<dag> pattern> 1327 : T2TwoReg<iops, oops, IIC_iEXTr, opc, oprs, pattern> { 1328 bits<2> rot; 1329 let Inst{31-27} = 0b11111; 1330 let Inst{26-23} = 0b0100; 1331 let Inst{22-20} = opcod; 1332 let Inst{19-16} = 0b1111; // Rn 1333 let Inst{15-12} = 0b1111; 1334 let Inst{7} = 1; 1335 let Inst{5-4} = rot; // rotate 1336} 1337 1338class T2I_ext_rrot<bits<3> opcod, string opc> 1339 : T2I_ext_rrot_base<opcod, 1340 (outs rGPR:$Rd), 1341 (ins rGPR:$Rm, rot_imm:$rot), 1342 opc, ".w\t$Rd, $Rm$rot", []>, 1343 Requires<[IsThumb2]>, 1344 Sched<[WriteALU, ReadALU]>; 1345 1346// UXTB16, SXTB16 - Requires HasDSP, does not need the .w qualifier. 1347class T2I_ext_rrot_xtb16<bits<3> opcod, string opc> 1348 : T2I_ext_rrot_base<opcod, 1349 (outs rGPR:$Rd), 1350 (ins rGPR:$Rm, rot_imm:$rot), 1351 opc, "\t$Rd, $Rm$rot", []>, 1352 Requires<[HasDSP, IsThumb2]>, 1353 Sched<[WriteALU, ReadALU]>; 1354 1355/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a 1356/// register and one whose operand is a register rotated by 8/16/24. 1357class T2I_exta_rrot<bits<3> opcod, string opc> 1358 : T2ThreeReg<(outs rGPR:$Rd), 1359 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot), 1360 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1361 Requires<[HasDSP, IsThumb2]>, 1362 Sched<[WriteALU, ReadALU]> { 1363 bits<2> rot; 1364 let Inst{31-27} = 0b11111; 1365 let Inst{26-23} = 0b0100; 1366 let Inst{22-20} = opcod; 1367 let Inst{15-12} = 0b1111; 1368 let Inst{7} = 1; 1369 let Inst{5-4} = rot; 1370} 1371 1372//===----------------------------------------------------------------------===// 1373// Instructions 1374//===----------------------------------------------------------------------===// 1375 1376//===----------------------------------------------------------------------===// 1377// Miscellaneous Instructions. 1378// 1379 1380class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin, 1381 string asm, list<dag> pattern> 1382 : T2XI<oops, iops, itin, asm, pattern> { 1383 bits<4> Rd; 1384 bits<12> label; 1385 1386 let Inst{11-8} = Rd; 1387 let Inst{26} = label{11}; 1388 let Inst{14-12} = label{10-8}; 1389 let Inst{7-0} = label{7-0}; 1390} 1391 1392// LEApcrel - Load a pc-relative address into a register without offending the 1393// assembler. 1394def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd), 1395 (ins t2adrlabel:$addr, pred:$p), 1396 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>, 1397 Sched<[WriteALU, ReadALU]> { 1398 let Inst{31-27} = 0b11110; 1399 let Inst{25-24} = 0b10; 1400 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE) 1401 let Inst{22} = 0; 1402 let Inst{20} = 0; 1403 let Inst{19-16} = 0b1111; // Rn 1404 let Inst{15} = 0; 1405 1406 bits<4> Rd; 1407 bits<13> addr; 1408 let Inst{11-8} = Rd; 1409 let Inst{23} = addr{12}; 1410 let Inst{21} = addr{12}; 1411 let Inst{26} = addr{11}; 1412 let Inst{14-12} = addr{10-8}; 1413 let Inst{7-0} = addr{7-0}; 1414 1415 let DecoderMethod = "DecodeT2Adr"; 1416} 1417 1418let hasSideEffects = 0, isReMaterializable = 1 in 1419def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), 1420 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 1421let hasSideEffects = 1 in 1422def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd), 1423 (ins i32imm:$label, pred:$p), 1424 4, IIC_iALUi, 1425 []>, Sched<[WriteALU, ReadALU]>; 1426 1427 1428//===----------------------------------------------------------------------===// 1429// Load / store Instructions. 1430// 1431 1432// Load 1433let canFoldAsLoad = 1, isReMaterializable = 1 in 1434defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, load>; 1435 1436// Loads with zero extension 1437defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1438 GPRnopc, zextloadi16>; 1439defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1440 GPRnopc, zextloadi8>; 1441 1442// Loads with sign extension 1443defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1444 GPRnopc, sextloadi16>; 1445defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1446 GPRnopc, sextloadi8>; 1447 1448let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { 1449// Load doubleword 1450def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2), 1451 (ins t2addrmode_imm8s4:$addr), 1452 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", 1453 [(set rGPR:$Rt, rGPR:$Rt2, (ARMldrd t2addrmode_imm8s4:$addr))]>, 1454 Sched<[WriteLd]>; 1455} // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 1456 1457// zextload i1 -> zextload i8 1458def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr), 1459 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1460def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr), 1461 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1462def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr), 1463 (t2LDRBs t2addrmode_so_reg:$addr)>; 1464def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)), 1465 (t2LDRBpci tconstpool:$addr)>; 1466 1467// extload -> zextload 1468// FIXME: Reduce the number of patterns by legalizing extload to zextload 1469// earlier? 1470def : T2Pat<(extloadi1 t2addrmode_imm12:$addr), 1471 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1472def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr), 1473 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1474def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr), 1475 (t2LDRBs t2addrmode_so_reg:$addr)>; 1476def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)), 1477 (t2LDRBpci tconstpool:$addr)>; 1478 1479def : T2Pat<(extloadi8 t2addrmode_imm12:$addr), 1480 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1481def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr), 1482 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1483def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr), 1484 (t2LDRBs t2addrmode_so_reg:$addr)>; 1485def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)), 1486 (t2LDRBpci tconstpool:$addr)>; 1487 1488def : T2Pat<(extloadi16 t2addrmode_imm12:$addr), 1489 (t2LDRHi12 t2addrmode_imm12:$addr)>; 1490def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr), 1491 (t2LDRHi8 t2addrmode_negimm8:$addr)>; 1492def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr), 1493 (t2LDRHs t2addrmode_so_reg:$addr)>; 1494def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)), 1495 (t2LDRHpci tconstpool:$addr)>; 1496 1497// FIXME: The destination register of the loads and stores can't be PC, but 1498// can be SP. We need another regclass (similar to rGPR) to represent 1499// that. Not a pressing issue since these are selected manually, 1500// not via pattern. 1501 1502// Indexed loads 1503 1504let mayLoad = 1, hasSideEffects = 0 in { 1505def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1506 (ins t2addrmode_imm8_pre:$addr), 1507 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu, 1508 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>, 1509 Sched<[WriteLd]>; 1510 1511def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1512 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1513 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu, 1514 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>, 1515 Sched<[WriteLd]>; 1516 1517def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1518 (ins t2addrmode_imm8_pre:$addr), 1519 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1520 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>, 1521 Sched<[WriteLd]>; 1522 1523def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1524 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1525 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1526 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>, 1527 Sched<[WriteLd]>; 1528 1529def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1530 (ins t2addrmode_imm8_pre:$addr), 1531 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1532 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>, 1533 Sched<[WriteLd]>; 1534 1535def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1536 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1537 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1538 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>, 1539 Sched<[WriteLd]>; 1540 1541def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1542 (ins t2addrmode_imm8_pre:$addr), 1543 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1544 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", 1545 []>, Sched<[WriteLd]>; 1546 1547def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1548 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1549 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1550 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>, 1551 Sched<[WriteLd]>; 1552 1553def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1554 (ins t2addrmode_imm8_pre:$addr), 1555 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1556 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", 1557 []>, Sched<[WriteLd]>; 1558 1559def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1560 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1561 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1562 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>, 1563 Sched<[WriteLd]>; 1564} // mayLoad = 1, hasSideEffects = 0 1565 1566// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110). 1567// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4 1568class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii> 1569 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc, 1570 "\t$Rt, $addr", []>, Sched<[WriteLd]> { 1571 bits<4> Rt; 1572 bits<13> addr; 1573 let Inst{31-27} = 0b11111; 1574 let Inst{26-25} = 0b00; 1575 let Inst{24} = signed; 1576 let Inst{23} = 0; 1577 let Inst{22-21} = type; 1578 let Inst{20} = 1; // load 1579 let Inst{19-16} = addr{12-9}; 1580 let Inst{15-12} = Rt; 1581 let Inst{11} = 1; 1582 let Inst{10-8} = 0b110; // PUW. 1583 let Inst{7-0} = addr{7-0}; 1584 1585 let DecoderMethod = "DecodeT2LoadT"; 1586} 1587 1588def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>; 1589def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>; 1590def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>; 1591def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>; 1592def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>; 1593 1594class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops, 1595 string opc, string asm, list<dag> pattern> 1596 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, 1597 opc, asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]> { 1598 bits<4> Rt; 1599 bits<4> addr; 1600 1601 let Inst{31-27} = 0b11101; 1602 let Inst{26-24} = 0b000; 1603 let Inst{23-20} = bits23_20; 1604 let Inst{11-6} = 0b111110; 1605 let Inst{5-4} = bit54; 1606 let Inst{3-0} = 0b1111; 1607 1608 // Encode instruction operands 1609 let Inst{19-16} = addr; 1610 let Inst{15-12} = Rt; 1611} 1612 1613def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt), 1614 (ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>, 1615 Sched<[WriteLd]>; 1616def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt), 1617 (ins addr_offset_none:$addr), "ldab", "\t$Rt, $addr", []>, 1618 Sched<[WriteLd]>; 1619def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt), 1620 (ins addr_offset_none:$addr), "ldah", "\t$Rt, $addr", []>, 1621 Sched<[WriteLd]>; 1622 1623// Store 1624defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR, store>; 1625defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si, 1626 rGPR, truncstorei8>; 1627defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si, 1628 rGPR, truncstorei16>; 1629 1630// Store doubleword 1631let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in 1632def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs), 1633 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr), 1634 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", 1635 [(ARMstrd rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr)]>, 1636 Sched<[WriteST]>; 1637 1638// Indexed stores 1639 1640let mayStore = 1, hasSideEffects = 0 in { 1641def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb), 1642 (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr), 1643 AddrModeT2_i8, IndexModePre, IIC_iStore_iu, 1644 "str", "\t$Rt, $addr!", 1645 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>, 1646 Sched<[WriteST]>; 1647 1648def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb), 1649 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr), 1650 AddrModeT2_i8, IndexModePre, IIC_iStore_iu, 1651 "strh", "\t$Rt, $addr!", 1652 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>, 1653 Sched<[WriteST]>; 1654 1655def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb), 1656 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr), 1657 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu, 1658 "strb", "\t$Rt, $addr!", 1659 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>, 1660 Sched<[WriteST]>; 1661} // mayStore = 1, hasSideEffects = 0 1662 1663def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb), 1664 (ins GPRnopc:$Rt, addr_offset_none:$Rn, 1665 t2am_imm8_offset:$offset), 1666 AddrModeT2_i8, IndexModePost, IIC_iStore_iu, 1667 "str", "\t$Rt, $Rn$offset", 1668 "$Rn = $Rn_wb,@earlyclobber $Rn_wb", 1669 [(set GPRnopc:$Rn_wb, 1670 (post_store GPRnopc:$Rt, addr_offset_none:$Rn, 1671 t2am_imm8_offset:$offset))]>, 1672 Sched<[WriteST]>; 1673 1674def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb), 1675 (ins rGPR:$Rt, addr_offset_none:$Rn, 1676 t2am_imm8_offset:$offset), 1677 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu, 1678 "strh", "\t$Rt, $Rn$offset", 1679 "$Rn = $Rn_wb,@earlyclobber $Rn_wb", 1680 [(set GPRnopc:$Rn_wb, 1681 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn, 1682 t2am_imm8_offset:$offset))]>, 1683 Sched<[WriteST]>; 1684 1685def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb), 1686 (ins rGPR:$Rt, addr_offset_none:$Rn, 1687 t2am_imm8_offset:$offset), 1688 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu, 1689 "strb", "\t$Rt, $Rn$offset", 1690 "$Rn = $Rn_wb,@earlyclobber $Rn_wb", 1691 [(set GPRnopc:$Rn_wb, 1692 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn, 1693 t2am_imm8_offset:$offset))]>, 1694 Sched<[WriteST]>; 1695 1696// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 1697// put the patterns on the instruction definitions directly as ISel wants 1698// the address base and offset to be separate operands, not a single 1699// complex operand like we represent the instructions themselves. The 1700// pseudos map between the two. 1701let usesCustomInserter = 1, 1702 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 1703def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb), 1704 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p), 1705 4, IIC_iStore_ru, 1706 [(set GPRnopc:$Rn_wb, 1707 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>, 1708 Sched<[WriteST]>; 1709def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb), 1710 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p), 1711 4, IIC_iStore_ru, 1712 [(set GPRnopc:$Rn_wb, 1713 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>, 1714 Sched<[WriteST]>; 1715def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb), 1716 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p), 1717 4, IIC_iStore_ru, 1718 [(set GPRnopc:$Rn_wb, 1719 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>, 1720 Sched<[WriteST]>; 1721} 1722 1723// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly 1724// only. 1725// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4 1726class T2IstT<bits<2> type, string opc, InstrItinClass ii> 1727 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc, 1728 "\t$Rt, $addr", []>, Sched<[WriteST]> { 1729 let Inst{31-27} = 0b11111; 1730 let Inst{26-25} = 0b00; 1731 let Inst{24} = 0; // not signed 1732 let Inst{23} = 0; 1733 let Inst{22-21} = type; 1734 let Inst{20} = 0; // store 1735 let Inst{11} = 1; 1736 let Inst{10-8} = 0b110; // PUW 1737 1738 bits<4> Rt; 1739 bits<13> addr; 1740 let Inst{15-12} = Rt; 1741 let Inst{19-16} = addr{12-9}; 1742 let Inst{7-0} = addr{7-0}; 1743} 1744 1745def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>; 1746def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>; 1747def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>; 1748 1749// ldrd / strd pre / post variants 1750 1751let mayLoad = 1, hasSideEffects = 0 in 1752def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb), 1753 (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru, 1754 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>, 1755 Sched<[WriteLd]> { 1756 let DecoderMethod = "DecodeT2LDRDPreInstruction"; 1757} 1758 1759let mayLoad = 1, hasSideEffects = 0 in 1760def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb), 1761 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm), 1762 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm", 1763 "$addr.base = $wb", []>, Sched<[WriteLd]>; 1764 1765let mayStore = 1, hasSideEffects = 0 in 1766def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb), 1767 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr), 1768 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!", 1769 "$addr.base = $wb", []>, Sched<[WriteST]> { 1770 let DecoderMethod = "DecodeT2STRDPreInstruction"; 1771} 1772 1773let mayStore = 1, hasSideEffects = 0 in 1774def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb), 1775 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr, 1776 t2am_imm8s4_offset:$imm), 1777 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm", 1778 "$addr.base = $wb", []>, Sched<[WriteST]>; 1779 1780class T2Istrrel<bits<2> bit54, dag oops, dag iops, 1781 string opc, string asm, list<dag> pattern> 1782 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc, 1783 asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]>, 1784 Sched<[WriteST]> { 1785 bits<4> Rt; 1786 bits<4> addr; 1787 1788 let Inst{31-27} = 0b11101; 1789 let Inst{26-20} = 0b0001100; 1790 let Inst{11-6} = 0b111110; 1791 let Inst{5-4} = bit54; 1792 let Inst{3-0} = 0b1111; 1793 1794 // Encode instruction operands 1795 let Inst{19-16} = addr; 1796 let Inst{15-12} = Rt; 1797} 1798 1799def t2STL : T2Istrrel<0b10, (outs), (ins rGPR:$Rt, addr_offset_none:$addr), 1800 "stl", "\t$Rt, $addr", []>; 1801def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr), 1802 "stlb", "\t$Rt, $addr", []>; 1803def t2STLH : T2Istrrel<0b01, (outs), (ins rGPR:$Rt, addr_offset_none:$addr), 1804 "stlh", "\t$Rt, $addr", []>; 1805 1806// T2Ipl (Preload Data/Instruction) signals the memory system of possible future 1807// data/instruction access. 1808// instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0), 1809// (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1). 1810multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> { 1811 1812 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc, 1813 "\t$addr", 1814 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>, 1815 Sched<[WritePreLd]> { 1816 let Inst{31-25} = 0b1111100; 1817 let Inst{24} = instr; 1818 let Inst{23} = 1; 1819 let Inst{22} = 0; 1820 let Inst{21} = write; 1821 let Inst{20} = 1; 1822 let Inst{15-12} = 0b1111; 1823 1824 bits<17> addr; 1825 let Inst{19-16} = addr{16-13}; // Rn 1826 let Inst{11-0} = addr{11-0}; // imm12 1827 1828 let DecoderMethod = "DecodeT2LoadImm12"; 1829 } 1830 1831 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc, 1832 "\t$addr", 1833 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>, 1834 Sched<[WritePreLd]> { 1835 let Inst{31-25} = 0b1111100; 1836 let Inst{24} = instr; 1837 let Inst{23} = 0; // U = 0 1838 let Inst{22} = 0; 1839 let Inst{21} = write; 1840 let Inst{20} = 1; 1841 let Inst{15-12} = 0b1111; 1842 let Inst{11-8} = 0b1100; 1843 1844 bits<13> addr; 1845 let Inst{19-16} = addr{12-9}; // Rn 1846 let Inst{7-0} = addr{7-0}; // imm8 1847 1848 let DecoderMethod = "DecodeT2LoadImm8"; 1849 } 1850 1851 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc, 1852 "\t$addr", 1853 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>, 1854 Sched<[WritePreLd]> { 1855 let Inst{31-25} = 0b1111100; 1856 let Inst{24} = instr; 1857 let Inst{23} = 0; // add = TRUE for T1 1858 let Inst{22} = 0; 1859 let Inst{21} = write; 1860 let Inst{20} = 1; 1861 let Inst{15-12} = 0b1111; 1862 let Inst{11-6} = 0b000000; 1863 1864 bits<10> addr; 1865 let Inst{19-16} = addr{9-6}; // Rn 1866 let Inst{3-0} = addr{5-2}; // Rm 1867 let Inst{5-4} = addr{1-0}; // imm2 1868 1869 let DecoderMethod = "DecodeT2LoadShift"; 1870 } 1871} 1872 1873defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>; 1874defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>; 1875defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>; 1876 1877// PLD/PLDW/PLI aliases w/ the optional .w suffix 1878def : t2InstAlias<"pld${p}.w\t$addr", 1879 (t2PLDi12 t2addrmode_imm12:$addr, pred:$p)>; 1880def : t2InstAlias<"pld${p}.w\t$addr", 1881 (t2PLDi8 t2addrmode_negimm8:$addr, pred:$p)>; 1882def : t2InstAlias<"pld${p}.w\t$addr", 1883 (t2PLDs t2addrmode_so_reg:$addr, pred:$p)>; 1884 1885def : InstAlias<"pldw${p}.w\t$addr", 1886 (t2PLDWi12 t2addrmode_imm12:$addr, pred:$p), 0>, 1887 Requires<[IsThumb2,HasV7,HasMP]>; 1888def : InstAlias<"pldw${p}.w\t$addr", 1889 (t2PLDWi8 t2addrmode_negimm8:$addr, pred:$p), 0>, 1890 Requires<[IsThumb2,HasV7,HasMP]>; 1891def : InstAlias<"pldw${p}.w\t$addr", 1892 (t2PLDWs t2addrmode_so_reg:$addr, pred:$p), 0>, 1893 Requires<[IsThumb2,HasV7,HasMP]>; 1894 1895def : InstAlias<"pli${p}.w\t$addr", 1896 (t2PLIi12 t2addrmode_imm12:$addr, pred:$p), 0>, 1897 Requires<[IsThumb2,HasV7]>; 1898def : InstAlias<"pli${p}.w\t$addr", 1899 (t2PLIi8 t2addrmode_negimm8:$addr, pred:$p), 0>, 1900 Requires<[IsThumb2,HasV7]>; 1901def : InstAlias<"pli${p}.w\t$addr", 1902 (t2PLIs t2addrmode_so_reg:$addr, pred:$p), 0>, 1903 Requires<[IsThumb2,HasV7]>; 1904 1905// pci variant is very similar to i12, but supports negative offsets 1906// from the PC. Only PLD and PLI have pci variants (not PLDW) 1907class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr), 1908 IIC_Preload, opc, "\t$addr", 1909 [(ARMPreload (ARMWrapper tconstpool:$addr), 1910 (i32 0), (i32 inst))]>, Sched<[WritePreLd]> { 1911 let Inst{31-25} = 0b1111100; 1912 let Inst{24} = inst; 1913 let Inst{22-20} = 0b001; 1914 let Inst{19-16} = 0b1111; 1915 let Inst{15-12} = 0b1111; 1916 1917 bits<13> addr; 1918 let Inst{23} = addr{12}; // add = (U == '1') 1919 let Inst{11-0} = addr{11-0}; // imm12 1920 1921 let DecoderMethod = "DecodeT2LoadLabel"; 1922} 1923 1924def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>; 1925def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>; 1926 1927def : t2InstAlias<"pld${p}.w $addr", 1928 (t2PLDpci t2ldrlabel:$addr, pred:$p)>; 1929def : InstAlias<"pli${p}.w $addr", 1930 (t2PLIpci t2ldrlabel:$addr, pred:$p), 0>, 1931 Requires<[IsThumb2,HasV7]>; 1932 1933// PLD/PLI with alternate literal form. 1934def : t2InstAlias<"pld${p} $addr", 1935 (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>; 1936def : InstAlias<"pli${p} $addr", 1937 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>, 1938 Requires<[IsThumb2,HasV7]>; 1939def : t2InstAlias<"pld${p}.w $addr", 1940 (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>; 1941def : InstAlias<"pli${p}.w $addr", 1942 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>, 1943 Requires<[IsThumb2,HasV7]>; 1944 1945//===----------------------------------------------------------------------===// 1946// Load / store multiple Instructions. 1947// 1948 1949multiclass thumb2_ld_mult<string asm, InstrItinClass itin, 1950 InstrItinClass itin_upd, bit L_bit> { 1951 def IA : 1952 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1953 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> { 1954 bits<4> Rn; 1955 bits<16> regs; 1956 1957 let Inst{31-27} = 0b11101; 1958 let Inst{26-25} = 0b00; 1959 let Inst{24-23} = 0b01; // Increment After 1960 let Inst{22} = 0; 1961 let Inst{21} = 0; // No writeback 1962 let Inst{20} = L_bit; 1963 let Inst{19-16} = Rn; 1964 let Inst{15-0} = regs; 1965 } 1966 def IA_UPD : 1967 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1968 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> { 1969 bits<4> Rn; 1970 bits<16> regs; 1971 1972 let Inst{31-27} = 0b11101; 1973 let Inst{26-25} = 0b00; 1974 let Inst{24-23} = 0b01; // Increment After 1975 let Inst{22} = 0; 1976 let Inst{21} = 1; // Writeback 1977 let Inst{20} = L_bit; 1978 let Inst{19-16} = Rn; 1979 let Inst{15-0} = regs; 1980 } 1981 def DB : 1982 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1983 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> { 1984 bits<4> Rn; 1985 bits<16> regs; 1986 1987 let Inst{31-27} = 0b11101; 1988 let Inst{26-25} = 0b00; 1989 let Inst{24-23} = 0b10; // Decrement Before 1990 let Inst{22} = 0; 1991 let Inst{21} = 0; // No writeback 1992 let Inst{20} = L_bit; 1993 let Inst{19-16} = Rn; 1994 let Inst{15-0} = regs; 1995 } 1996 def DB_UPD : 1997 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1998 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 1999 bits<4> Rn; 2000 bits<16> regs; 2001 2002 let Inst{31-27} = 0b11101; 2003 let Inst{26-25} = 0b00; 2004 let Inst{24-23} = 0b10; // Decrement Before 2005 let Inst{22} = 0; 2006 let Inst{21} = 1; // Writeback 2007 let Inst{20} = L_bit; 2008 let Inst{19-16} = Rn; 2009 let Inst{15-0} = regs; 2010 } 2011} 2012 2013let hasSideEffects = 0 in { 2014 2015let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in 2016defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>; 2017 2018multiclass thumb2_st_mult<string asm, InstrItinClass itin, 2019 InstrItinClass itin_upd, bit L_bit> { 2020 def IA : 2021 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2022 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> { 2023 bits<4> Rn; 2024 bits<16> regs; 2025 2026 let Inst{31-27} = 0b11101; 2027 let Inst{26-25} = 0b00; 2028 let Inst{24-23} = 0b01; // Increment After 2029 let Inst{22} = 0; 2030 let Inst{21} = 0; // No writeback 2031 let Inst{20} = L_bit; 2032 let Inst{19-16} = Rn; 2033 let Inst{15} = 0; 2034 let Inst{14} = regs{14}; 2035 let Inst{13} = 0; 2036 let Inst{12-0} = regs{12-0}; 2037 } 2038 def IA_UPD : 2039 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2040 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> { 2041 bits<4> Rn; 2042 bits<16> regs; 2043 2044 let Inst{31-27} = 0b11101; 2045 let Inst{26-25} = 0b00; 2046 let Inst{24-23} = 0b01; // Increment After 2047 let Inst{22} = 0; 2048 let Inst{21} = 1; // Writeback 2049 let Inst{20} = L_bit; 2050 let Inst{19-16} = Rn; 2051 let Inst{15} = 0; 2052 let Inst{14} = regs{14}; 2053 let Inst{13} = 0; 2054 let Inst{12-0} = regs{12-0}; 2055 } 2056 def DB : 2057 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2058 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> { 2059 bits<4> Rn; 2060 bits<16> regs; 2061 2062 let Inst{31-27} = 0b11101; 2063 let Inst{26-25} = 0b00; 2064 let Inst{24-23} = 0b10; // Decrement Before 2065 let Inst{22} = 0; 2066 let Inst{21} = 0; // No writeback 2067 let Inst{20} = L_bit; 2068 let Inst{19-16} = Rn; 2069 let Inst{15} = 0; 2070 let Inst{14} = regs{14}; 2071 let Inst{13} = 0; 2072 let Inst{12-0} = regs{12-0}; 2073 } 2074 def DB_UPD : 2075 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2076 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 2077 bits<4> Rn; 2078 bits<16> regs; 2079 2080 let Inst{31-27} = 0b11101; 2081 let Inst{26-25} = 0b00; 2082 let Inst{24-23} = 0b10; // Decrement Before 2083 let Inst{22} = 0; 2084 let Inst{21} = 1; // Writeback 2085 let Inst{20} = L_bit; 2086 let Inst{19-16} = Rn; 2087 let Inst{15} = 0; 2088 let Inst{14} = regs{14}; 2089 let Inst{13} = 0; 2090 let Inst{12-0} = regs{12-0}; 2091 } 2092} 2093 2094 2095let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 2096defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>; 2097 2098} // hasSideEffects 2099 2100 2101//===----------------------------------------------------------------------===// 2102// Move Instructions. 2103// 2104 2105let hasSideEffects = 0 in 2106def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rm), IIC_iMOVr, 2107 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> { 2108 let Inst{31-27} = 0b11101; 2109 let Inst{26-25} = 0b01; 2110 let Inst{24-21} = 0b0010; 2111 let Inst{19-16} = 0b1111; // Rn 2112 let Inst{15} = 0b0; 2113 let Inst{14-12} = 0b000; 2114 let Inst{7-4} = 0b0000; 2115} 2116def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, 2117 pred:$p, zero_reg)>; 2118def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, 2119 pred:$p, CPSR)>; 2120def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, 2121 pred:$p, CPSR)>; 2122 2123// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16. 2124let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, 2125 AddedComplexity = 1 in 2126def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi, 2127 "mov", ".w\t$Rd, $imm", 2128 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> { 2129 let Inst{31-27} = 0b11110; 2130 let Inst{25} = 0; 2131 let Inst{24-21} = 0b0010; 2132 let Inst{19-16} = 0b1111; // Rn 2133 let Inst{15} = 0; 2134} 2135 2136// cc_out is handled as part of the explicit mnemonic in the parser for 'mov'. 2137// Use aliases to get that to play nice here. 2138def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 2139 pred:$p, CPSR)>; 2140def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 2141 pred:$p, CPSR)>; 2142 2143def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 2144 pred:$p, zero_reg)>; 2145def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 2146 pred:$p, zero_reg)>; 2147 2148let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 2149def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi, 2150 "movw", "\t$Rd, $imm", 2151 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]>, 2152 Requires<[IsThumb, HasV8MBaseline]> { 2153 let Inst{31-27} = 0b11110; 2154 let Inst{25} = 1; 2155 let Inst{24-21} = 0b0010; 2156 let Inst{20} = 0; // The S bit. 2157 let Inst{15} = 0; 2158 2159 bits<4> Rd; 2160 bits<16> imm; 2161 2162 let Inst{11-8} = Rd; 2163 let Inst{19-16} = imm{15-12}; 2164 let Inst{26} = imm{11}; 2165 let Inst{14-12} = imm{10-8}; 2166 let Inst{7-0} = imm{7-0}; 2167 let DecoderMethod = "DecodeT2MOVTWInstruction"; 2168} 2169 2170def : InstAlias<"mov${p} $Rd, $imm", 2171 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p), 0>, 2172 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteALU]>; 2173 2174def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd), 2175 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 2176 Sched<[WriteALU]>; 2177 2178let Constraints = "$src = $Rd" in { 2179def t2MOVTi16 : T2I<(outs rGPR:$Rd), 2180 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi, 2181 "movt", "\t$Rd, $imm", 2182 [(set rGPR:$Rd, 2183 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>, 2184 Sched<[WriteALU]>, 2185 Requires<[IsThumb, HasV8MBaseline]> { 2186 let Inst{31-27} = 0b11110; 2187 let Inst{25} = 1; 2188 let Inst{24-21} = 0b0110; 2189 let Inst{20} = 0; // The S bit. 2190 let Inst{15} = 0; 2191 2192 bits<4> Rd; 2193 bits<16> imm; 2194 2195 let Inst{11-8} = Rd; 2196 let Inst{19-16} = imm{15-12}; 2197 let Inst{26} = imm{11}; 2198 let Inst{14-12} = imm{10-8}; 2199 let Inst{7-0} = imm{7-0}; 2200 let DecoderMethod = "DecodeT2MOVTWInstruction"; 2201} 2202 2203def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd), 2204 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 2205 Sched<[WriteALU]>, Requires<[IsThumb, HasV8MBaseline]>; 2206} // Constraints 2207 2208def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>; 2209 2210//===----------------------------------------------------------------------===// 2211// Extend Instructions. 2212// 2213 2214// Sign extenders 2215 2216def t2SXTB : T2I_ext_rrot<0b100, "sxtb">; 2217def t2SXTH : T2I_ext_rrot<0b000, "sxth">; 2218def t2SXTB16 : T2I_ext_rrot_xtb16<0b010, "sxtb16">; 2219 2220def t2SXTAB : T2I_exta_rrot<0b100, "sxtab">; 2221def t2SXTAH : T2I_exta_rrot<0b000, "sxtah">; 2222def t2SXTAB16 : T2I_exta_rrot<0b010, "sxtab16">; 2223 2224def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i8), 2225 (t2SXTB rGPR:$Rn, rot_imm:$rot)>; 2226def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i16), 2227 (t2SXTH rGPR:$Rn, rot_imm:$rot)>; 2228def : Thumb2DSPPat<(add rGPR:$Rn, 2229 (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i8)), 2230 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2231def : Thumb2DSPPat<(add rGPR:$Rn, 2232 (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i16)), 2233 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2234def : Thumb2DSPPat<(int_arm_sxtb16 rGPR:$Rn), 2235 (t2SXTB16 rGPR:$Rn, 0)>; 2236def : Thumb2DSPPat<(int_arm_sxtab16 rGPR:$Rn, rGPR:$Rm), 2237 (t2SXTAB16 rGPR:$Rn, rGPR:$Rm, 0)>; 2238def : Thumb2DSPPat<(int_arm_sxtb16 (rotr rGPR:$Rn, rot_imm:$rot)), 2239 (t2SXTB16 rGPR:$Rn, rot_imm:$rot)>; 2240def : Thumb2DSPPat<(int_arm_sxtab16 rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)), 2241 (t2SXTAB16 rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2242 2243 2244// A simple right-shift can also be used in most cases (the exception is the 2245// SXTH operations with a rotate of 24: there the non-contiguous bits are 2246// relevant). 2247def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg 2248 (srl rGPR:$Rm, rot_imm:$rot), i8)), 2249 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2250def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg 2251 (srl rGPR:$Rm, imm8_or_16:$rot), i16)), 2252 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2253def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg 2254 (rotr rGPR:$Rm, (i32 24)), i16)), 2255 (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>; 2256def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg 2257 (or (srl rGPR:$Rm, (i32 24)), 2258 (shl rGPR:$Rm, (i32 8))), i16)), 2259 (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>; 2260 2261// Zero extenders 2262 2263let AddedComplexity = 16 in { 2264def t2UXTB : T2I_ext_rrot<0b101, "uxtb">; 2265def t2UXTH : T2I_ext_rrot<0b001, "uxth">; 2266def t2UXTB16 : T2I_ext_rrot_xtb16<0b011, "uxtb16">; 2267 2268def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x000000FF), 2269 (t2UXTB rGPR:$Rm, rot_imm:$rot)>; 2270def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x0000FFFF), 2271 (t2UXTH rGPR:$Rm, rot_imm:$rot)>; 2272def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x00FF00FF), 2273 (t2UXTB16 rGPR:$Rm, rot_imm:$rot)>; 2274 2275def : Thumb2DSPPat<(int_arm_uxtb16 rGPR:$Rm), 2276 (t2UXTB16 rGPR:$Rm, 0)>; 2277def : Thumb2DSPPat<(int_arm_uxtb16 (rotr rGPR:$Rn, rot_imm:$rot)), 2278 (t2UXTB16 rGPR:$Rn, rot_imm:$rot)>; 2279 2280// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 2281// The transformation should probably be done as a combiner action 2282// instead so we can include a check for masking back in the upper 2283// eight bits of the source into the lower eight bits of the result. 2284//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF), 2285// (t2UXTB16 rGPR:$Src, 3)>, 2286// Requires<[HasDSP, IsThumb2]>; 2287def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF), 2288 (t2UXTB16 rGPR:$Src, 1)>, 2289 Requires<[HasDSP, IsThumb2]>; 2290 2291def t2UXTAB : T2I_exta_rrot<0b101, "uxtab">; 2292def t2UXTAH : T2I_exta_rrot<0b001, "uxtah">; 2293def t2UXTAB16 : T2I_exta_rrot<0b011, "uxtab16">; 2294 2295def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot), 2296 0x00FF)), 2297 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2298def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot), 2299 0xFFFF)), 2300 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2301def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 2302 0xFF)), 2303 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2304def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 2305 0xFFFF)), 2306 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2307def : Thumb2DSPPat<(int_arm_uxtab16 rGPR:$Rn, rGPR:$Rm), 2308 (t2UXTAB16 rGPR:$Rn, rGPR:$Rm, 0)>; 2309def : Thumb2DSPPat<(int_arm_uxtab16 rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)), 2310 (t2UXTAB16 rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2311} 2312 2313 2314//===----------------------------------------------------------------------===// 2315// Arithmetic Instructions. 2316// 2317 2318let isAdd = 1 in 2319defm t2ADD : T2I_bin_ii12rs<0b000, "add", add, 1>; 2320defm t2SUB : T2I_bin_ii12rs<0b101, "sub", sub>; 2321 2322// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. 2323// 2324// Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the 2325// selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by 2326// AdjustInstrPostInstrSelection where we determine whether or not to 2327// set the "s" bit based on CPSR liveness. 2328// 2329// FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen 2330// support for an optional CPSR definition that corresponds to the DAG 2331// node's second value. We can then eliminate the implicit def of CPSR. 2332defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMaddc, 1>; 2333defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMsubc>; 2334 2335def : T2Pat<(ARMsubs GPRnopc:$Rn, t2_so_imm:$imm), 2336 (t2SUBSri $Rn, t2_so_imm:$imm)>; 2337def : T2Pat<(ARMsubs GPRnopc:$Rn, rGPR:$Rm), (t2SUBSrr $Rn, $Rm)>; 2338def : T2Pat<(ARMsubs GPRnopc:$Rn, t2_so_reg:$ShiftedRm), 2339 (t2SUBSrs $Rn, t2_so_reg:$ShiftedRm)>; 2340 2341let hasPostISelHook = 1 in { 2342defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", ARMadde, 1>; 2343defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", ARMsube>; 2344} 2345 2346def : t2InstSubst<"adc${s}${p} $rd, $rn, $imm", 2347 (t2SBCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>; 2348def : t2InstSubst<"sbc${s}${p} $rd, $rn, $imm", 2349 (t2ADCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>; 2350 2351def : t2InstSubst<"add${s}${p}.w $rd, $rn, $imm", 2352 (t2SUBri rGPR:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>; 2353def : t2InstSubst<"sub${s}${p}.w $rd, $rn, $imm", 2354 (t2ADDri rGPR:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>; 2355def : t2InstSubst<"subw${p} $Rd, $Rn, $imm", 2356 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>; 2357def : t2InstSubst<"sub${s}${p} $rd, $rn, $imm", 2358 (t2ADDri rGPR:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>; 2359def : t2InstSubst<"sub${p} $rd, $rn, $imm", 2360 (t2ADDri12 rGPR:$rd, GPR:$rn, imm0_4095_neg:$imm, pred:$p)>; 2361 2362// SP to SP alike 2363def : t2InstSubst<"add${s}${p}.w $rd, $rn, $imm", 2364 (t2SUBspImm GPRsp:$rd, GPRsp:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>; 2365def : t2InstSubst<"sub${s}${p}.w $rd, $rn, $imm", 2366 (t2ADDspImm GPRsp:$rd, GPRsp:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>; 2367def : t2InstSubst<"subw${p} $Rd, $Rn, $imm", 2368 (t2ADDspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095_neg:$imm, pred:$p)>; 2369def : t2InstSubst<"sub${s}${p} $rd, $rn, $imm", 2370 (t2ADDspImm GPRsp:$rd, GPRsp:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>; 2371def : t2InstSubst<"sub${p} $rd, $rn, $imm", 2372 (t2ADDspImm12 GPRsp:$rd, GPRsp:$rn, imm0_4095_neg:$imm, pred:$p)>; 2373 2374 2375// RSB 2376defm t2RSB : T2I_rbin_irs <0b1110, "rsb", sub>; 2377 2378// FIXME: Eliminate them if we can write def : Pat patterns which defines 2379// CPSR and the implicit def of CPSR is not needed. 2380defm t2RSBS : T2I_rbin_s_is <ARMsubc>; 2381 2382// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 2383// The assume-no-carry-in form uses the negation of the input since add/sub 2384// assume opposite meanings of the carry flag (i.e., carry == !borrow). 2385// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 2386// details. 2387// The AddedComplexity preferences the first variant over the others since 2388// it can be shrunk to a 16-bit wide encoding, while the others cannot. 2389let AddedComplexity = 1 in 2390def : T2Pat<(add rGPR:$src, imm1_255_neg:$imm), 2391 (t2SUBri rGPR:$src, imm1_255_neg:$imm)>; 2392def : T2Pat<(add rGPR:$src, t2_so_imm_neg:$imm), 2393 (t2SUBri rGPR:$src, t2_so_imm_neg:$imm)>; 2394def : T2Pat<(add rGPR:$src, imm0_4095_neg:$imm), 2395 (t2SUBri12 rGPR:$src, imm0_4095_neg:$imm)>; 2396def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm), 2397 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>; 2398 2399// Do the same for v8m targets since they support movw with a 16-bit value. 2400def : T1Pat<(add tGPR:$src, imm0_65535_neg:$imm), 2401 (tSUBrr tGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>, 2402 Requires<[HasV8MBaseline]>; 2403 2404let AddedComplexity = 1 in 2405def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm), 2406 (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>; 2407def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm), 2408 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>; 2409def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm), 2410 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>; 2411// The with-carry-in form matches bitwise not instead of the negation. 2412// Effectively, the inverse interpretation of the carry flag already accounts 2413// for part of the negation. 2414let AddedComplexity = 1 in 2415def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR), 2416 (t2SBCri rGPR:$src, imm0_255_not:$imm)>; 2417def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR), 2418 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>; 2419def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR), 2420 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>; 2421 2422def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 2423 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", 2424 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>, 2425 Requires<[IsThumb2, HasDSP]> { 2426 let Inst{31-27} = 0b11111; 2427 let Inst{26-24} = 0b010; 2428 let Inst{23} = 0b1; 2429 let Inst{22-20} = 0b010; 2430 let Inst{15-12} = 0b1111; 2431 let Inst{7} = 0b1; 2432 let Inst{6-4} = 0b000; 2433} 2434 2435// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned) 2436// And Miscellaneous operations -- for disassembly only 2437class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc, 2438 list<dag> pat, dag iops, string asm> 2439 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>, 2440 Requires<[IsThumb2, HasDSP]> { 2441 let Inst{31-27} = 0b11111; 2442 let Inst{26-23} = 0b0101; 2443 let Inst{22-20} = op22_20; 2444 let Inst{15-12} = 0b1111; 2445 let Inst{7-4} = op7_4; 2446 2447 bits<4> Rd; 2448 bits<4> Rn; 2449 bits<4> Rm; 2450 2451 let Inst{11-8} = Rd; 2452 let Inst{19-16} = Rn; 2453 let Inst{3-0} = Rm; 2454} 2455 2456class T2I_pam_intrinsics<bits<3> op22_20, bits<4> op7_4, string opc, 2457 Intrinsic intrinsic> 2458 : T2I_pam<op22_20, op7_4, opc, 2459 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm))], 2460 (ins rGPR:$Rn, rGPR:$Rm), "\t$Rd, $Rn, $Rm">; 2461 2462class T2I_pam_intrinsics_rev<bits<3> op22_20, bits<4> op7_4, string opc> 2463 : T2I_pam<op22_20, op7_4, opc, [], 2464 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 2465 2466// Saturating add/subtract 2467def t2QADD16 : T2I_pam_intrinsics<0b001, 0b0001, "qadd16", int_arm_qadd16>; 2468def t2QADD8 : T2I_pam_intrinsics<0b000, 0b0001, "qadd8", int_arm_qadd8>; 2469def t2QASX : T2I_pam_intrinsics<0b010, 0b0001, "qasx", int_arm_qasx>; 2470def t2UQSUB8 : T2I_pam_intrinsics<0b100, 0b0101, "uqsub8", int_arm_uqsub8>; 2471def t2QSAX : T2I_pam_intrinsics<0b110, 0b0001, "qsax", int_arm_qsax>; 2472def t2QSUB16 : T2I_pam_intrinsics<0b101, 0b0001, "qsub16", int_arm_qsub16>; 2473def t2QSUB8 : T2I_pam_intrinsics<0b100, 0b0001, "qsub8", int_arm_qsub8>; 2474def t2UQADD16 : T2I_pam_intrinsics<0b001, 0b0101, "uqadd16", int_arm_uqadd16>; 2475def t2UQADD8 : T2I_pam_intrinsics<0b000, 0b0101, "uqadd8", int_arm_uqadd8>; 2476def t2UQASX : T2I_pam_intrinsics<0b010, 0b0101, "uqasx", int_arm_uqasx>; 2477def t2UQSAX : T2I_pam_intrinsics<0b110, 0b0101, "uqsax", int_arm_uqsax>; 2478def t2UQSUB16 : T2I_pam_intrinsics<0b101, 0b0101, "uqsub16", int_arm_uqsub16>; 2479def t2QADD : T2I_pam_intrinsics_rev<0b000, 0b1000, "qadd">; 2480def t2QSUB : T2I_pam_intrinsics_rev<0b000, 0b1010, "qsub">; 2481def t2QDADD : T2I_pam_intrinsics_rev<0b000, 0b1001, "qdadd">; 2482def t2QDSUB : T2I_pam_intrinsics_rev<0b000, 0b1011, "qdsub">; 2483 2484def : Thumb2DSPPat<(int_arm_qadd rGPR:$Rm, rGPR:$Rn), 2485 (t2QADD rGPR:$Rm, rGPR:$Rn)>; 2486def : Thumb2DSPPat<(int_arm_qsub rGPR:$Rm, rGPR:$Rn), 2487 (t2QSUB rGPR:$Rm, rGPR:$Rn)>; 2488def : Thumb2DSPPat<(int_arm_qadd rGPR:$Rm, (int_arm_qadd rGPR:$Rn, rGPR:$Rn)), 2489 (t2QDADD rGPR:$Rm, rGPR:$Rn)>; 2490def : Thumb2DSPPat<(int_arm_qsub rGPR:$Rm, (int_arm_qadd rGPR:$Rn, rGPR:$Rn)), 2491 (t2QDSUB rGPR:$Rm, rGPR:$Rn)>; 2492 2493def : Thumb2DSPPat<(saddsat rGPR:$Rm, rGPR:$Rn), 2494 (t2QADD rGPR:$Rm, rGPR:$Rn)>; 2495def : Thumb2DSPPat<(ssubsat rGPR:$Rm, rGPR:$Rn), 2496 (t2QSUB rGPR:$Rm, rGPR:$Rn)>; 2497def : Thumb2DSPPat<(saddsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)), 2498 (t2QDADD rGPR:$Rm, rGPR:$Rn)>; 2499def : Thumb2DSPPat<(ssubsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)), 2500 (t2QDSUB rGPR:$Rm, rGPR:$Rn)>; 2501def : Thumb2DSPPat<(ARMqadd8b rGPR:$Rm, rGPR:$Rn), 2502 (t2QADD8 rGPR:$Rm, rGPR:$Rn)>; 2503def : Thumb2DSPPat<(ARMqsub8b rGPR:$Rm, rGPR:$Rn), 2504 (t2QSUB8 rGPR:$Rm, rGPR:$Rn)>; 2505def : Thumb2DSPPat<(ARMqadd16b rGPR:$Rm, rGPR:$Rn), 2506 (t2QADD16 rGPR:$Rm, rGPR:$Rn)>; 2507def : Thumb2DSPPat<(ARMqsub16b rGPR:$Rm, rGPR:$Rn), 2508 (t2QSUB16 rGPR:$Rm, rGPR:$Rn)>; 2509 2510// Signed/Unsigned add/subtract 2511 2512def t2SASX : T2I_pam_intrinsics<0b010, 0b0000, "sasx", int_arm_sasx>; 2513def t2SADD16 : T2I_pam_intrinsics<0b001, 0b0000, "sadd16", int_arm_sadd16>; 2514def t2SADD8 : T2I_pam_intrinsics<0b000, 0b0000, "sadd8", int_arm_sadd8>; 2515def t2SSAX : T2I_pam_intrinsics<0b110, 0b0000, "ssax", int_arm_ssax>; 2516def t2SSUB16 : T2I_pam_intrinsics<0b101, 0b0000, "ssub16", int_arm_ssub16>; 2517def t2SSUB8 : T2I_pam_intrinsics<0b100, 0b0000, "ssub8", int_arm_ssub8>; 2518def t2UASX : T2I_pam_intrinsics<0b010, 0b0100, "uasx", int_arm_uasx>; 2519def t2UADD16 : T2I_pam_intrinsics<0b001, 0b0100, "uadd16", int_arm_uadd16>; 2520def t2UADD8 : T2I_pam_intrinsics<0b000, 0b0100, "uadd8", int_arm_uadd8>; 2521def t2USAX : T2I_pam_intrinsics<0b110, 0b0100, "usax", int_arm_usax>; 2522def t2USUB16 : T2I_pam_intrinsics<0b101, 0b0100, "usub16", int_arm_usub16>; 2523def t2USUB8 : T2I_pam_intrinsics<0b100, 0b0100, "usub8", int_arm_usub8>; 2524 2525// Signed/Unsigned halving add/subtract 2526 2527def t2SHASX : T2I_pam_intrinsics<0b010, 0b0010, "shasx", int_arm_shasx>; 2528def t2SHADD16 : T2I_pam_intrinsics<0b001, 0b0010, "shadd16", int_arm_shadd16>; 2529def t2SHADD8 : T2I_pam_intrinsics<0b000, 0b0010, "shadd8", int_arm_shadd8>; 2530def t2SHSAX : T2I_pam_intrinsics<0b110, 0b0010, "shsax", int_arm_shsax>; 2531def t2SHSUB16 : T2I_pam_intrinsics<0b101, 0b0010, "shsub16", int_arm_shsub16>; 2532def t2SHSUB8 : T2I_pam_intrinsics<0b100, 0b0010, "shsub8", int_arm_shsub8>; 2533def t2UHASX : T2I_pam_intrinsics<0b010, 0b0110, "uhasx", int_arm_uhasx>; 2534def t2UHADD16 : T2I_pam_intrinsics<0b001, 0b0110, "uhadd16", int_arm_uhadd16>; 2535def t2UHADD8 : T2I_pam_intrinsics<0b000, 0b0110, "uhadd8", int_arm_uhadd8>; 2536def t2UHSAX : T2I_pam_intrinsics<0b110, 0b0110, "uhsax", int_arm_uhsax>; 2537def t2UHSUB16 : T2I_pam_intrinsics<0b101, 0b0110, "uhsub16", int_arm_uhsub16>; 2538def t2UHSUB8 : T2I_pam_intrinsics<0b100, 0b0110, "uhsub8", int_arm_uhsub8>; 2539 2540// Helper class for disassembly only 2541// A6.3.16 & A6.3.17 2542// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions. 2543class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, 2544 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 2545 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> { 2546 let Inst{31-27} = 0b11111; 2547 let Inst{26-24} = 0b011; 2548 let Inst{23} = long; 2549 let Inst{22-20} = op22_20; 2550 let Inst{7-4} = op7_4; 2551} 2552 2553class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, 2554 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 2555 : T2FourReg<oops, iops, itin, opc, asm, pattern> { 2556 let Inst{31-27} = 0b11111; 2557 let Inst{26-24} = 0b011; 2558 let Inst{23} = long; 2559 let Inst{22-20} = op22_20; 2560 let Inst{7-4} = op7_4; 2561} 2562 2563// Unsigned Sum of Absolute Differences [and Accumulate]. 2564def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd), 2565 (ins rGPR:$Rn, rGPR:$Rm), 2566 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", 2567 [(set rGPR:$Rd, (int_arm_usad8 rGPR:$Rn, rGPR:$Rm))]>, 2568 Requires<[IsThumb2, HasDSP]> { 2569 let Inst{15-12} = 0b1111; 2570} 2571def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd), 2572 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary, 2573 "usada8", "\t$Rd, $Rn, $Rm, $Ra", 2574 [(set rGPR:$Rd, (int_arm_usada8 rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>, 2575 Requires<[IsThumb2, HasDSP]>; 2576 2577// Signed/Unsigned saturate. 2578let hasSideEffects = 1 in 2579class T2SatI<dag iops, string opc, string asm> 2580 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, []> { 2581 bits<4> Rd; 2582 bits<4> Rn; 2583 bits<5> sat_imm; 2584 bits<6> sh; 2585 2586 let Inst{31-24} = 0b11110011; 2587 let Inst{21} = sh{5}; 2588 let Inst{20} = 0; 2589 let Inst{19-16} = Rn; 2590 let Inst{15} = 0; 2591 let Inst{14-12} = sh{4-2}; 2592 let Inst{11-8} = Rd; 2593 let Inst{7-6} = sh{1-0}; 2594 let Inst{5} = 0; 2595 let Inst{4-0} = sat_imm; 2596} 2597 2598def t2SSAT: T2SatI<(ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh), 2599 "ssat", "\t$Rd, $sat_imm, $Rn$sh">, 2600 Requires<[IsThumb2]>, Sched<[WriteALU]> { 2601 let Inst{23-22} = 0b00; 2602 let Inst{5} = 0; 2603} 2604 2605def t2SSAT16: T2SatI<(ins imm1_16:$sat_imm, rGPR:$Rn), 2606 "ssat16", "\t$Rd, $sat_imm, $Rn">, 2607 Requires<[IsThumb2, HasDSP]>, Sched<[WriteALU]> { 2608 let Inst{23-22} = 0b00; 2609 let sh = 0b100000; 2610 let Inst{4} = 0; 2611} 2612 2613def t2USAT: T2SatI<(ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh), 2614 "usat", "\t$Rd, $sat_imm, $Rn$sh">, 2615 Requires<[IsThumb2]>, Sched<[WriteALU]> { 2616 let Inst{23-22} = 0b10; 2617} 2618 2619def t2USAT16: T2SatI<(ins imm0_15:$sat_imm, rGPR:$Rn), 2620 "usat16", "\t$Rd, $sat_imm, $Rn">, 2621 Requires<[IsThumb2, HasDSP]>, Sched<[WriteALU]> { 2622 let Inst{23-22} = 0b10; 2623 let sh = 0b100000; 2624 let Inst{4} = 0; 2625} 2626 2627def : T2Pat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm), 2628 (t2SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 2629def : T2Pat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm), 2630 (t2USAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 2631def : T2Pat<(int_arm_ssat GPR:$a, imm1_32:$pos), 2632 (t2SSAT imm1_32:$pos, GPR:$a, 0)>; 2633def : T2Pat<(int_arm_usat GPR:$a, imm0_31:$pos), 2634 (t2USAT imm0_31:$pos, GPR:$a, 0)>; 2635def : T2Pat<(int_arm_ssat16 GPR:$a, imm1_16:$pos), 2636 (t2SSAT16 imm1_16:$pos, GPR:$a)>; 2637def : T2Pat<(int_arm_usat16 GPR:$a, imm0_15:$pos), 2638 (t2USAT16 imm0_15:$pos, GPR:$a)>; 2639 2640//===----------------------------------------------------------------------===// 2641// Shift and rotate Instructions. 2642// 2643 2644defm t2LSL : T2I_sh_ir<0b00, "lsl", imm1_31, shl>; 2645defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, srl>; 2646defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, sra>; 2647defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31, rotr>; 2648 2649// LSL #0 is actually MOV, and has slightly different permitted registers to 2650// LSL with non-zero shift 2651def : t2InstAlias<"lsl${s}${p} $Rd, $Rm, #0", 2652 (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>; 2653def : t2InstAlias<"lsl${s}${p}.w $Rd, $Rm, #0", 2654 (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>; 2655 2656// (rotr x, (and y, 0x...1f)) ==> (ROR x, y) 2657def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)), 2658 (t2RORrr rGPR:$lhs, rGPR:$rhs)>; 2659 2660let Uses = [CPSR] in { 2661def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 2662 "rrx", "\t$Rd, $Rm", 2663 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> { 2664 let Inst{31-27} = 0b11101; 2665 let Inst{26-25} = 0b01; 2666 let Inst{24-21} = 0b0010; 2667 let Inst{19-16} = 0b1111; // Rn 2668 let Inst{15} = 0b0; 2669 let Unpredictable{15} = 0b1; 2670 let Inst{14-12} = 0b000; 2671 let Inst{7-4} = 0b0011; 2672} 2673} 2674 2675let isCodeGenOnly = 1, Defs = [CPSR] in { 2676def t2MOVsrl_flag : T2TwoRegShiftImm< 2677 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 2678 "lsrs", ".w\t$Rd, $Rm, #1", 2679 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>, 2680 Sched<[WriteALU]> { 2681 let Inst{31-27} = 0b11101; 2682 let Inst{26-25} = 0b01; 2683 let Inst{24-21} = 0b0010; 2684 let Inst{20} = 1; // The S bit. 2685 let Inst{19-16} = 0b1111; // Rn 2686 let Inst{5-4} = 0b01; // Shift type. 2687 // Shift amount = Inst{14-12:7-6} = 1. 2688 let Inst{14-12} = 0b000; 2689 let Inst{7-6} = 0b01; 2690} 2691def t2MOVsra_flag : T2TwoRegShiftImm< 2692 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 2693 "asrs", ".w\t$Rd, $Rm, #1", 2694 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>, 2695 Sched<[WriteALU]> { 2696 let Inst{31-27} = 0b11101; 2697 let Inst{26-25} = 0b01; 2698 let Inst{24-21} = 0b0010; 2699 let Inst{20} = 1; // The S bit. 2700 let Inst{19-16} = 0b1111; // Rn 2701 let Inst{5-4} = 0b10; // Shift type. 2702 // Shift amount = Inst{14-12:7-6} = 1. 2703 let Inst{14-12} = 0b000; 2704 let Inst{7-6} = 0b01; 2705} 2706} 2707 2708//===----------------------------------------------------------------------===// 2709// Bitwise Instructions. 2710// 2711 2712defm t2AND : T2I_bin_w_irs<0b0000, "and", 2713 IIC_iBITi, IIC_iBITr, IIC_iBITsi, and, 1>; 2714defm t2ORR : T2I_bin_w_irs<0b0010, "orr", 2715 IIC_iBITi, IIC_iBITr, IIC_iBITsi, or, 1>; 2716defm t2EOR : T2I_bin_w_irs<0b0100, "eor", 2717 IIC_iBITi, IIC_iBITr, IIC_iBITsi, xor, 1>; 2718 2719defm t2BIC : T2I_bin_w_irs<0b0001, "bic", 2720 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2721 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 2722 2723class T2BitFI<dag oops, dag iops, InstrItinClass itin, 2724 string opc, string asm, list<dag> pattern> 2725 : T2I<oops, iops, itin, opc, asm, pattern> { 2726 bits<4> Rd; 2727 bits<5> msb; 2728 bits<5> lsb; 2729 2730 let Inst{11-8} = Rd; 2731 let Inst{4-0} = msb{4-0}; 2732 let Inst{14-12} = lsb{4-2}; 2733 let Inst{7-6} = lsb{1-0}; 2734} 2735 2736class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin, 2737 string opc, string asm, list<dag> pattern> 2738 : T2BitFI<oops, iops, itin, opc, asm, pattern> { 2739 bits<4> Rn; 2740 2741 let Inst{19-16} = Rn; 2742} 2743 2744let Constraints = "$src = $Rd" in 2745def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm), 2746 IIC_iUNAsi, "bfc", "\t$Rd, $imm", 2747 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]>, Sched<[WriteALU]> { 2748 let Inst{31-27} = 0b11110; 2749 let Inst{26} = 0; // should be 0. 2750 let Inst{25} = 1; 2751 let Inst{24-20} = 0b10110; 2752 let Inst{19-16} = 0b1111; // Rn 2753 let Inst{15} = 0; 2754 let Inst{5} = 0; // should be 0. 2755 2756 bits<10> imm; 2757 let msb{4-0} = imm{9-5}; 2758 let lsb{4-0} = imm{4-0}; 2759} 2760 2761def t2SBFX: T2TwoRegBitFI< 2762 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb), 2763 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> { 2764 let Inst{31-27} = 0b11110; 2765 let Inst{25} = 1; 2766 let Inst{24-20} = 0b10100; 2767 let Inst{15} = 0; 2768 2769 let hasSideEffects = 0; 2770} 2771 2772def t2UBFX: T2TwoRegBitFI< 2773 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb), 2774 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> { 2775 let Inst{31-27} = 0b11110; 2776 let Inst{25} = 1; 2777 let Inst{24-20} = 0b11100; 2778 let Inst{15} = 0; 2779 2780 let hasSideEffects = 0; 2781} 2782 2783// A8.8.247 UDF - Undefined (Encoding T2) 2784def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16", 2785 [(int_arm_undefined imm0_65535:$imm16)]> { 2786 bits<16> imm16; 2787 let Inst{31-29} = 0b111; 2788 let Inst{28-27} = 0b10; 2789 let Inst{26-20} = 0b1111111; 2790 let Inst{19-16} = imm16{15-12}; 2791 let Inst{15} = 0b1; 2792 let Inst{14-12} = 0b010; 2793 let Inst{11-0} = imm16{11-0}; 2794} 2795 2796// A8.6.18 BFI - Bitfield insert (Encoding T1) 2797let Constraints = "$src = $Rd" in { 2798 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd), 2799 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm), 2800 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm", 2801 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn, 2802 bf_inv_mask_imm:$imm))]>, Sched<[WriteALU]> { 2803 let Inst{31-27} = 0b11110; 2804 let Inst{26} = 0; // should be 0. 2805 let Inst{25} = 1; 2806 let Inst{24-20} = 0b10110; 2807 let Inst{15} = 0; 2808 let Inst{5} = 0; // should be 0. 2809 2810 bits<10> imm; 2811 let msb{4-0} = imm{9-5}; 2812 let lsb{4-0} = imm{4-0}; 2813 } 2814} 2815 2816defm t2ORN : T2I_bin_irs<0b0011, "orn", 2817 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2818 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">; 2819 2820/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 2821/// unary operation that produces a value. These are predicable and can be 2822/// changed to modify CPSR. 2823multiclass T2I_un_irs<bits<4> opcod, string opc, 2824 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 2825 PatFrag opnode, 2826 bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> { 2827 // shifted imm 2828 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii, 2829 opc, "\t$Rd, $imm", 2830 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> { 2831 let isAsCheapAsAMove = Cheap; 2832 let isReMaterializable = ReMat; 2833 let isMoveImm = MoveImm; 2834 let Inst{31-27} = 0b11110; 2835 let Inst{25} = 0; 2836 let Inst{24-21} = opcod; 2837 let Inst{19-16} = 0b1111; // Rn 2838 let Inst{15} = 0; 2839 } 2840 // register 2841 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir, 2842 opc, ".w\t$Rd, $Rm", 2843 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> { 2844 let Inst{31-27} = 0b11101; 2845 let Inst{26-25} = 0b01; 2846 let Inst{24-21} = opcod; 2847 let Inst{19-16} = 0b1111; // Rn 2848 let Inst{14-12} = 0b000; // imm3 2849 let Inst{7-6} = 0b00; // imm2 2850 let Inst{5-4} = 0b00; // type 2851 } 2852 // shifted register 2853 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis, 2854 opc, ".w\t$Rd, $ShiftedRm", 2855 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>, 2856 Sched<[WriteALU]> { 2857 let Inst{31-27} = 0b11101; 2858 let Inst{26-25} = 0b01; 2859 let Inst{24-21} = opcod; 2860 let Inst{19-16} = 0b1111; // Rn 2861 } 2862} 2863 2864// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version 2865let AddedComplexity = 1 in 2866defm t2MVN : T2I_un_irs <0b0011, "mvn", 2867 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi, 2868 not, 1, 1, 1>; 2869 2870let AddedComplexity = 1 in 2871def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm), 2872 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>; 2873 2874// top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise 2875def top16Zero: PatLeaf<(i32 rGPR:$src), [{ 2876 return !SDValue(N,0)->getValueType(0).isVector() && 2877 CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16)); 2878 }]>; 2879 2880// so_imm_notSext is needed instead of so_imm_not, as the value of imm 2881// will match the extended, not the original bitWidth for $src. 2882def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm), 2883 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>; 2884 2885 2886// FIXME: Disable this pattern on Darwin to workaround an assembler bug. 2887def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm), 2888 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>, 2889 Requires<[IsThumb2]>; 2890 2891def : T2Pat<(t2_so_imm_not:$src), 2892 (t2MVNi t2_so_imm_not:$src)>; 2893 2894// There are shorter Thumb encodings for ADD than ORR, so to increase 2895// Thumb2SizeReduction's chances later on we select a t2ADD for an or where 2896// possible. 2897def : T2Pat<(or AddLikeOrOp:$Rn, t2_so_imm:$imm), 2898 (t2ADDri rGPR:$Rn, t2_so_imm:$imm)>; 2899 2900def : T2Pat<(or AddLikeOrOp:$Rn, imm0_4095:$Rm), 2901 (t2ADDri12 rGPR:$Rn, imm0_4095:$Rm)>; 2902 2903def : T2Pat<(or AddLikeOrOp:$Rn, non_imm32:$Rm), 2904 (t2ADDrr $Rn, $Rm)>; 2905 2906//===----------------------------------------------------------------------===// 2907// Multiply Instructions. 2908// 2909let isCommutable = 1 in 2910def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, 2911 "mul", "\t$Rd, $Rn, $Rm", 2912 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]>, 2913 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 2914 let Inst{31-27} = 0b11111; 2915 let Inst{26-23} = 0b0110; 2916 let Inst{22-20} = 0b000; 2917 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2918 let Inst{7-4} = 0b0000; // Multiply 2919} 2920 2921class T2FourRegMLA<bits<4> op7_4, string opc, list<dag> pattern> 2922 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2923 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>, 2924 Requires<[IsThumb2, UseMulOps]>, 2925 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 2926 let Inst{31-27} = 0b11111; 2927 let Inst{26-23} = 0b0110; 2928 let Inst{22-20} = 0b000; 2929 let Inst{7-4} = op7_4; 2930} 2931 2932def t2MLA : T2FourRegMLA<0b0000, "mla", 2933 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), 2934 rGPR:$Ra))]>; 2935def t2MLS: T2FourRegMLA<0b0001, "mls", 2936 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, 2937 rGPR:$Rm)))]>; 2938 2939// Extra precision multiplies with low / high results 2940let hasSideEffects = 0 in { 2941let isCommutable = 1 in { 2942def t2SMULL : T2MulLong<0b000, 0b0000, "smull", 2943 [(set rGPR:$RdLo, rGPR:$RdHi, 2944 (smullohi rGPR:$Rn, rGPR:$Rm))]>; 2945def t2UMULL : T2MulLong<0b010, 0b0000, "umull", 2946 [(set rGPR:$RdLo, rGPR:$RdHi, 2947 (umullohi rGPR:$Rn, rGPR:$Rm))]>; 2948} // isCommutable 2949 2950// Multiply + accumulate 2951def t2SMLAL : T2MlaLong<0b100, 0b0000, "smlal">; 2952def t2UMLAL : T2MlaLong<0b110, 0b0000, "umlal">; 2953def t2UMAAL : T2MlaLong<0b110, 0b0110, "umaal">, Requires<[IsThumb2, HasDSP]>; 2954} // hasSideEffects 2955 2956// Rounding variants of the below included for disassembly only 2957 2958// Most significant word multiply 2959class T2SMMUL<bits<4> op7_4, string opc, list<dag> pattern> 2960 : T2ThreeReg<(outs rGPR:$Rd), 2961 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, 2962 opc, "\t$Rd, $Rn, $Rm", pattern>, 2963 Requires<[IsThumb2, HasDSP]>, 2964 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 2965 let Inst{31-27} = 0b11111; 2966 let Inst{26-23} = 0b0110; 2967 let Inst{22-20} = 0b101; 2968 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2969 let Inst{7-4} = op7_4; 2970} 2971def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn, 2972 rGPR:$Rm))]>; 2973def t2SMMULR : 2974 T2SMMUL<0b0001, "smmulr", 2975 [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, (i32 0)))]>; 2976 2977class T2FourRegSMMLA<bits<3> op22_20, bits<4> op7_4, string opc, 2978 list<dag> pattern> 2979 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2980 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>, 2981 Requires<[IsThumb2, HasDSP, UseMulOps]>, 2982 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 2983 let Inst{31-27} = 0b11111; 2984 let Inst{26-23} = 0b0110; 2985 let Inst{22-20} = op22_20; 2986 let Inst{7-4} = op7_4; 2987} 2988 2989def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla", 2990 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>; 2991def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar", 2992 [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>; 2993def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls", []>; 2994def t2SMMLSR: T2FourRegSMMLA<0b110, 0b0001, "smmlsr", 2995 [(set rGPR:$Rd, (ARMsmmlsr rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>; 2996 2997class T2ThreeRegSMUL<bits<3> op22_20, bits<2> op5_4, string opc, 2998 list<dag> pattern> 2999 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, opc, 3000 "\t$Rd, $Rn, $Rm", pattern>, 3001 Requires<[IsThumb2, HasDSP]>, 3002 Sched<[WriteMUL16, ReadMUL, ReadMUL]> { 3003 let Inst{31-27} = 0b11111; 3004 let Inst{26-23} = 0b0110; 3005 let Inst{22-20} = op22_20; 3006 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 3007 let Inst{7-6} = 0b00; 3008 let Inst{5-4} = op5_4; 3009} 3010 3011def t2SMULBB : T2ThreeRegSMUL<0b001, 0b00, "smulbb", 3012 [(set rGPR:$Rd, (bb_mul rGPR:$Rn, rGPR:$Rm))]>; 3013def t2SMULBT : T2ThreeRegSMUL<0b001, 0b01, "smulbt", 3014 [(set rGPR:$Rd, (bt_mul rGPR:$Rn, rGPR:$Rm))]>; 3015def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb", 3016 [(set rGPR:$Rd, (tb_mul rGPR:$Rn, rGPR:$Rm))]>; 3017def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt", 3018 [(set rGPR:$Rd, (tt_mul rGPR:$Rn, rGPR:$Rm))]>; 3019def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb", 3020 [(set rGPR:$Rd, (ARMsmulwb rGPR:$Rn, rGPR:$Rm))]>; 3021def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt", 3022 [(set rGPR:$Rd, (ARMsmulwt rGPR:$Rn, rGPR:$Rm))]>; 3023 3024def : Thumb2DSPPat<(mul sext_16_node:$Rn, (sext_bottom_16 rGPR:$Rm)), 3025 (t2SMULBB rGPR:$Rn, rGPR:$Rm)>; 3026def : Thumb2DSPPat<(mul sext_16_node:$Rn, (sext_top_16 rGPR:$Rm)), 3027 (t2SMULBT rGPR:$Rn, rGPR:$Rm)>; 3028def : Thumb2DSPPat<(mul (sext_top_16 rGPR:$Rn), sext_16_node:$Rm), 3029 (t2SMULTB rGPR:$Rn, rGPR:$Rm)>; 3030 3031def : Thumb2DSPPat<(int_arm_smulbb rGPR:$Rn, rGPR:$Rm), 3032 (t2SMULBB rGPR:$Rn, rGPR:$Rm)>; 3033def : Thumb2DSPPat<(int_arm_smulbt rGPR:$Rn, rGPR:$Rm), 3034 (t2SMULBT rGPR:$Rn, rGPR:$Rm)>; 3035def : Thumb2DSPPat<(int_arm_smultb rGPR:$Rn, rGPR:$Rm), 3036 (t2SMULTB rGPR:$Rn, rGPR:$Rm)>; 3037def : Thumb2DSPPat<(int_arm_smultt rGPR:$Rn, rGPR:$Rm), 3038 (t2SMULTT rGPR:$Rn, rGPR:$Rm)>; 3039def : Thumb2DSPPat<(int_arm_smulwb rGPR:$Rn, rGPR:$Rm), 3040 (t2SMULWB rGPR:$Rn, rGPR:$Rm)>; 3041def : Thumb2DSPPat<(int_arm_smulwt rGPR:$Rn, rGPR:$Rm), 3042 (t2SMULWT rGPR:$Rn, rGPR:$Rm)>; 3043 3044class T2FourRegSMLA<bits<3> op22_20, bits<2> op5_4, string opc, 3045 list<dag> pattern> 3046 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16, 3047 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>, 3048 Requires<[IsThumb2, HasDSP, UseMulOps]>, 3049 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]> { 3050 let Inst{31-27} = 0b11111; 3051 let Inst{26-23} = 0b0110; 3052 let Inst{22-20} = op22_20; 3053 let Inst{7-6} = 0b00; 3054 let Inst{5-4} = op5_4; 3055} 3056 3057def t2SMLABB : T2FourRegSMLA<0b001, 0b00, "smlabb", 3058 [(set rGPR:$Rd, (add rGPR:$Ra, (bb_mul rGPR:$Rn, rGPR:$Rm)))]>; 3059def t2SMLABT : T2FourRegSMLA<0b001, 0b01, "smlabt", 3060 [(set rGPR:$Rd, (add rGPR:$Ra, (bt_mul rGPR:$Rn, rGPR:$Rm)))]>; 3061def t2SMLATB : T2FourRegSMLA<0b001, 0b10, "smlatb", 3062 [(set rGPR:$Rd, (add rGPR:$Ra, (tb_mul rGPR:$Rn, rGPR:$Rm)))]>; 3063def t2SMLATT : T2FourRegSMLA<0b001, 0b11, "smlatt", 3064 [(set rGPR:$Rd, (add rGPR:$Ra, (tt_mul rGPR:$Rn, rGPR:$Rm)))]>; 3065def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb", 3066 [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwb rGPR:$Rn, rGPR:$Rm)))]>; 3067def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt", 3068 [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwt rGPR:$Rn, rGPR:$Rm)))]>; 3069 3070def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, sext_16_node:$Rm)), 3071 (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; 3072def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, 3073 (sext_bottom_16 rGPR:$Rm))), 3074 (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; 3075def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, 3076 (sext_top_16 rGPR:$Rm))), 3077 (t2SMLABT rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; 3078def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul (sext_top_16 rGPR:$Rn), 3079 sext_16_node:$Rm)), 3080 (t2SMLATB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; 3081 3082def : Thumb2DSPPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc), 3083 (t2SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 3084def : Thumb2DSPPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc), 3085 (t2SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 3086def : Thumb2DSPPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc), 3087 (t2SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 3088def : Thumb2DSPPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc), 3089 (t2SMLATT GPR:$a, GPR:$b, GPR:$acc)>; 3090def : Thumb2DSPPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc), 3091 (t2SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 3092def : Thumb2DSPPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc), 3093 (t2SMLAWT GPR:$a, GPR:$b, GPR:$acc)>; 3094 3095// Halfword multiple accumulate long: SMLAL<x><y> 3096def t2SMLALBB : T2MlaLong<0b100, 0b1000, "smlalbb">, 3097 Requires<[IsThumb2, HasDSP]>; 3098def t2SMLALBT : T2MlaLong<0b100, 0b1001, "smlalbt">, 3099 Requires<[IsThumb2, HasDSP]>; 3100def t2SMLALTB : T2MlaLong<0b100, 0b1010, "smlaltb">, 3101 Requires<[IsThumb2, HasDSP]>; 3102def t2SMLALTT : T2MlaLong<0b100, 0b1011, "smlaltt">, 3103 Requires<[IsThumb2, HasDSP]>; 3104 3105def : Thumb2DSPPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 3106 (t2SMLALBB $Rn, $Rm, $RLo, $RHi)>; 3107def : Thumb2DSPPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 3108 (t2SMLALBT $Rn, $Rm, $RLo, $RHi)>; 3109def : Thumb2DSPPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 3110 (t2SMLALTB $Rn, $Rm, $RLo, $RHi)>; 3111def : Thumb2DSPPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 3112 (t2SMLALTT $Rn, $Rm, $RLo, $RHi)>; 3113 3114class T2DualHalfMul<bits<3> op22_20, bits<4> op7_4, string opc, 3115 Intrinsic intrinsic> 3116 : T2ThreeReg_mac<0, op22_20, op7_4, 3117 (outs rGPR:$Rd), 3118 (ins rGPR:$Rn, rGPR:$Rm), 3119 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm", 3120 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm))]>, 3121 Requires<[IsThumb2, HasDSP]>, 3122 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 3123 let Inst{15-12} = 0b1111; 3124} 3125 3126// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 3127def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad", int_arm_smuad>; 3128def t2SMUADX: T2DualHalfMul<0b010, 0b0001, "smuadx", int_arm_smuadx>; 3129def t2SMUSD: T2DualHalfMul<0b100, 0b0000, "smusd", int_arm_smusd>; 3130def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx", int_arm_smusdx>; 3131 3132class T2DualHalfMulAdd<bits<3> op22_20, bits<4> op7_4, string opc, 3133 Intrinsic intrinsic> 3134 : T2FourReg_mac<0, op22_20, op7_4, 3135 (outs rGPR:$Rd), 3136 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), 3137 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm, $Ra", 3138 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>, 3139 Requires<[IsThumb2, HasDSP]>; 3140 3141def t2SMLAD : T2DualHalfMulAdd<0b010, 0b0000, "smlad", int_arm_smlad>; 3142def t2SMLADX : T2DualHalfMulAdd<0b010, 0b0001, "smladx", int_arm_smladx>; 3143def t2SMLSD : T2DualHalfMulAdd<0b100, 0b0000, "smlsd", int_arm_smlsd>; 3144def t2SMLSDX : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx", int_arm_smlsdx>; 3145 3146class T2DualHalfMulAddLong<bits<3> op22_20, bits<4> op7_4, string opc> 3147 : T2FourReg_mac<1, op22_20, op7_4, 3148 (outs rGPR:$Ra, rGPR:$Rd), 3149 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), 3150 IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>, 3151 RegConstraint<"$Ra = $RLo, $Rd = $RHi">, 3152 Requires<[IsThumb2, HasDSP]>, 3153 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 3154 3155def t2SMLALD : T2DualHalfMulAddLong<0b100, 0b1100, "smlald">; 3156def t2SMLALDX : T2DualHalfMulAddLong<0b100, 0b1101, "smlaldx">; 3157def t2SMLSLD : T2DualHalfMulAddLong<0b101, 0b1100, "smlsld">; 3158def t2SMLSLDX : T2DualHalfMulAddLong<0b101, 0b1101, "smlsldx">; 3159 3160def : Thumb2DSPPat<(ARMSmlald rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), 3161 (t2SMLALD rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>; 3162def : Thumb2DSPPat<(ARMSmlaldx rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), 3163 (t2SMLALDX rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>; 3164def : Thumb2DSPPat<(ARMSmlsld rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), 3165 (t2SMLSLD rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>; 3166def : Thumb2DSPPat<(ARMSmlsldx rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), 3167 (t2SMLSLDX rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>; 3168 3169//===----------------------------------------------------------------------===// 3170// Division Instructions. 3171// Signed and unsigned division on v7-M 3172// 3173def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV, 3174 "sdiv", "\t$Rd, $Rn, $Rm", 3175 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>, 3176 Requires<[HasDivideInThumb, IsThumb, HasV8MBaseline]>, 3177 Sched<[WriteDIV]> { 3178 let Inst{31-27} = 0b11111; 3179 let Inst{26-21} = 0b011100; 3180 let Inst{20} = 0b1; 3181 let Inst{15-12} = 0b1111; 3182 let Inst{7-4} = 0b1111; 3183} 3184 3185def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV, 3186 "udiv", "\t$Rd, $Rn, $Rm", 3187 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>, 3188 Requires<[HasDivideInThumb, IsThumb, HasV8MBaseline]>, 3189 Sched<[WriteDIV]> { 3190 let Inst{31-27} = 0b11111; 3191 let Inst{26-21} = 0b011101; 3192 let Inst{20} = 0b1; 3193 let Inst{15-12} = 0b1111; 3194 let Inst{7-4} = 0b1111; 3195} 3196 3197//===----------------------------------------------------------------------===// 3198// Misc. Arithmetic Instructions. 3199// 3200 3201class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops, 3202 InstrItinClass itin, string opc, string asm, list<dag> pattern> 3203 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> { 3204 let Inst{31-27} = 0b11111; 3205 let Inst{26-22} = 0b01010; 3206 let Inst{21-20} = op1; 3207 let Inst{15-12} = 0b1111; 3208 let Inst{7-6} = 0b10; 3209 let Inst{5-4} = op2; 3210 let Rn{3-0} = Rm; 3211} 3212 3213def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 3214 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>, 3215 Sched<[WriteALU]>; 3216 3217def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 3218 "rbit", "\t$Rd, $Rm", 3219 [(set rGPR:$Rd, (bitreverse rGPR:$Rm))]>, 3220 Sched<[WriteALU]>; 3221 3222def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 3223 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>, 3224 Sched<[WriteALU]>; 3225 3226def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 3227 "rev16", ".w\t$Rd, $Rm", 3228 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>, 3229 Sched<[WriteALU]>; 3230 3231def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 3232 "revsh", ".w\t$Rd, $Rm", 3233 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>, 3234 Sched<[WriteALU]>; 3235 3236def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)), 3237 (and (srl rGPR:$Rm, (i32 8)), 0xFF)), 3238 (t2REVSH rGPR:$Rm)>; 3239 3240def t2PKHBT : T2ThreeReg< 3241 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh), 3242 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 3243 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF), 3244 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh), 3245 0xFFFF0000)))]>, 3246 Requires<[HasDSP, IsThumb2]>, 3247 Sched<[WriteALUsi, ReadALU]> { 3248 let Inst{31-27} = 0b11101; 3249 let Inst{26-25} = 0b01; 3250 let Inst{24-20} = 0b01100; 3251 let Inst{5} = 0; // BT form 3252 let Inst{4} = 0; 3253 3254 bits<5> sh; 3255 let Inst{14-12} = sh{4-2}; 3256 let Inst{7-6} = sh{1-0}; 3257} 3258 3259// Alternate cases for PKHBT where identities eliminate some nodes. 3260def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)), 3261 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>, 3262 Requires<[HasDSP, IsThumb2]>; 3263def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)), 3264 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>, 3265 Requires<[HasDSP, IsThumb2]>; 3266 3267// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 3268// will match the pattern below. 3269def t2PKHTB : T2ThreeReg< 3270 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh), 3271 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 3272 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000), 3273 (and (sra rGPR:$Rm, pkh_asr_amt:$sh), 3274 0xFFFF)))]>, 3275 Requires<[HasDSP, IsThumb2]>, 3276 Sched<[WriteALUsi, ReadALU]> { 3277 let Inst{31-27} = 0b11101; 3278 let Inst{26-25} = 0b01; 3279 let Inst{24-20} = 0b01100; 3280 let Inst{5} = 1; // TB form 3281 let Inst{4} = 0; 3282 3283 bits<5> sh; 3284 let Inst{14-12} = sh{4-2}; 3285 let Inst{7-6} = sh{1-0}; 3286} 3287 3288// Alternate cases for PKHTB where identities eliminate some nodes. Note that 3289// a shift amount of 0 is *not legal* here, it is PKHBT instead. 3290// We also can not replace a srl (17..31) by an arithmetic shift we would use in 3291// pkhtb src1, src2, asr (17..31). 3292def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16:$sh)), 3293 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16:$sh)>, 3294 Requires<[HasDSP, IsThumb2]>; 3295def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (sra rGPR:$src2, imm16_31:$sh)), 3296 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>, 3297 Requires<[HasDSP, IsThumb2]>; 3298def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), 3299 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)), 3300 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>, 3301 Requires<[HasDSP, IsThumb2]>; 3302 3303//===----------------------------------------------------------------------===// 3304// CRC32 Instructions 3305// 3306// Polynomials: 3307// + CRC32{B,H,W} 0x04C11DB7 3308// + CRC32C{B,H,W} 0x1EDC6F41 3309// 3310 3311class T2I_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 3312 : T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary, 3313 !strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"), 3314 [(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>, 3315 Requires<[IsThumb2, HasV8, HasCRC]> { 3316 let Inst{31-27} = 0b11111; 3317 let Inst{26-21} = 0b010110; 3318 let Inst{20} = C; 3319 let Inst{15-12} = 0b1111; 3320 let Inst{7-6} = 0b10; 3321 let Inst{5-4} = sz; 3322} 3323 3324def t2CRC32B : T2I_crc32<0, 0b00, "b", int_arm_crc32b>; 3325def t2CRC32CB : T2I_crc32<1, 0b00, "cb", int_arm_crc32cb>; 3326def t2CRC32H : T2I_crc32<0, 0b01, "h", int_arm_crc32h>; 3327def t2CRC32CH : T2I_crc32<1, 0b01, "ch", int_arm_crc32ch>; 3328def t2CRC32W : T2I_crc32<0, 0b10, "w", int_arm_crc32w>; 3329def t2CRC32CW : T2I_crc32<1, 0b10, "cw", int_arm_crc32cw>; 3330 3331//===----------------------------------------------------------------------===// 3332// Comparison Instructions... 3333// 3334defm t2CMP : T2I_cmp_irs<0b1101, "cmp", GPRnopc, 3335 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, ARMcmp>; 3336 3337def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm), 3338 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>; 3339def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs), 3340 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>; 3341def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs), 3342 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>; 3343 3344let isCompare = 1, Defs = [CPSR] in { 3345 // shifted imm 3346 def t2CMNri : T2OneRegCmpImm< 3347 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi, 3348 "cmn", ".w\t$Rn, $imm", 3349 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>, 3350 Sched<[WriteCMP, ReadALU]> { 3351 let Inst{31-27} = 0b11110; 3352 let Inst{25} = 0; 3353 let Inst{24-21} = 0b1000; 3354 let Inst{20} = 1; // The S bit. 3355 let Inst{15} = 0; 3356 let Inst{11-8} = 0b1111; // Rd 3357 } 3358 // register 3359 def t2CMNzrr : T2TwoRegCmp< 3360 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr, 3361 "cmn", ".w\t$Rn, $Rm", 3362 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 3363 GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 3364 let Inst{31-27} = 0b11101; 3365 let Inst{26-25} = 0b01; 3366 let Inst{24-21} = 0b1000; 3367 let Inst{20} = 1; // The S bit. 3368 let Inst{14-12} = 0b000; // imm3 3369 let Inst{11-8} = 0b1111; // Rd 3370 let Inst{7-6} = 0b00; // imm2 3371 let Inst{5-4} = 0b00; // type 3372 } 3373 // shifted register 3374 def t2CMNzrs : T2OneRegCmpShiftedReg< 3375 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi, 3376 "cmn", ".w\t$Rn, $ShiftedRm", 3377 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 3378 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>, 3379 Sched<[WriteCMPsi, ReadALU, ReadALU]> { 3380 let Inst{31-27} = 0b11101; 3381 let Inst{26-25} = 0b01; 3382 let Inst{24-21} = 0b1000; 3383 let Inst{20} = 1; // The S bit. 3384 let Inst{11-8} = 0b1111; // Rd 3385 } 3386} 3387 3388// Assembler aliases w/o the ".w" suffix. 3389// No alias here for 'rr' version as not all instantiations of this multiclass 3390// want one (CMP in particular, does not). 3391def : t2InstAlias<"cmn${p} $Rn, $imm", 3392 (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>; 3393def : t2InstAlias<"cmn${p} $Rn, $shift", 3394 (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>; 3395 3396def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm), 3397 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 3398 3399def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm), 3400 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>; 3401 3402defm t2TST : T2I_cmp_irs<0b0000, "tst", rGPR, 3403 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi, 3404 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>; 3405defm t2TEQ : T2I_cmp_irs<0b0100, "teq", rGPR, 3406 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi, 3407 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>; 3408 3409// Conditional moves 3410let hasSideEffects = 0 in { 3411 3412let isCommutable = 1, isSelect = 1 in 3413def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd), 3414 (ins rGPR:$false, rGPR:$Rm, cmovpred:$p), 3415 4, IIC_iCMOVr, 3416 [(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, 3417 cmovpred:$p))]>, 3418 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 3419 3420let isMoveImm = 1 in 3421def t2MOVCCi 3422 : t2PseudoInst<(outs rGPR:$Rd), 3423 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p), 3424 4, IIC_iCMOVi, 3425 [(set rGPR:$Rd, (ARMcmov rGPR:$false,t2_so_imm:$imm, 3426 cmovpred:$p))]>, 3427 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 3428 3429let isCodeGenOnly = 1 in { 3430let isMoveImm = 1 in 3431def t2MOVCCi16 3432 : t2PseudoInst<(outs rGPR:$Rd), 3433 (ins rGPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 3434 4, IIC_iCMOVi, 3435 [(set rGPR:$Rd, (ARMcmov rGPR:$false, imm0_65535:$imm, 3436 cmovpred:$p))]>, 3437 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 3438 3439let isMoveImm = 1 in 3440def t2MVNCCi 3441 : t2PseudoInst<(outs rGPR:$Rd), 3442 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p), 3443 4, IIC_iCMOVi, 3444 [(set rGPR:$Rd, 3445 (ARMcmov rGPR:$false, t2_so_imm_not:$imm, 3446 cmovpred:$p))]>, 3447 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 3448 3449class MOVCCShPseudo<SDPatternOperator opnode, Operand ty> 3450 : t2PseudoInst<(outs rGPR:$Rd), 3451 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p), 3452 4, IIC_iCMOVsi, 3453 [(set rGPR:$Rd, (ARMcmov rGPR:$false, 3454 (opnode rGPR:$Rm, (i32 ty:$imm)), 3455 cmovpred:$p))]>, 3456 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 3457 3458def t2MOVCClsl : MOVCCShPseudo<shl, imm0_31>; 3459def t2MOVCClsr : MOVCCShPseudo<srl, imm_sr>; 3460def t2MOVCCasr : MOVCCShPseudo<sra, imm_sr>; 3461def t2MOVCCror : MOVCCShPseudo<rotr, imm0_31>; 3462 3463let isMoveImm = 1 in 3464def t2MOVCCi32imm 3465 : t2PseudoInst<(outs rGPR:$dst), 3466 (ins rGPR:$false, i32imm:$src, cmovpred:$p), 3467 8, IIC_iCMOVix2, 3468 [(set rGPR:$dst, (ARMcmov rGPR:$false, imm:$src, 3469 cmovpred:$p))]>, 3470 RegConstraint<"$false = $dst">; 3471} // isCodeGenOnly = 1 3472 3473} // hasSideEffects 3474 3475//===----------------------------------------------------------------------===// 3476// Atomic operations intrinsics 3477// 3478 3479// memory barriers protect the atomic sequences 3480let hasSideEffects = 1 in { 3481def t2DMB : T2I<(outs), (ins memb_opt:$opt), NoItinerary, 3482 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 3483 Requires<[IsThumb, HasDB]> { 3484 bits<4> opt; 3485 let Inst{31-4} = 0xf3bf8f5; 3486 let Inst{3-0} = opt; 3487} 3488 3489def t2DSB : T2I<(outs), (ins memb_opt:$opt), NoItinerary, 3490 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 3491 Requires<[IsThumb, HasDB]> { 3492 bits<4> opt; 3493 let Inst{31-4} = 0xf3bf8f4; 3494 let Inst{3-0} = opt; 3495} 3496 3497def t2ISB : T2I<(outs), (ins instsyncb_opt:$opt), NoItinerary, 3498 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 3499 Requires<[IsThumb, HasDB]> { 3500 bits<4> opt; 3501 let Inst{31-4} = 0xf3bf8f6; 3502 let Inst{3-0} = opt; 3503} 3504 3505let hasNoSchedulingInfo = 1 in 3506def t2TSB : T2I<(outs), (ins tsb_opt:$opt), NoItinerary, 3507 "tsb", "\t$opt", []>, Requires<[IsThumb, HasV8_4a]> { 3508 let Inst{31-0} = 0xf3af8012; 3509} 3510} 3511 3512// Armv8.5-A speculation barrier 3513def t2SB : Thumb2XI<(outs), (ins), AddrModeNone, 4, NoItinerary, "sb", "", []>, 3514 Requires<[IsThumb2, HasSB]>, Sched<[]> { 3515 let Inst{31-0} = 0xf3bf8f70; 3516 let Unpredictable = 0x000f2f0f; 3517 let hasSideEffects = 1; 3518} 3519 3520class T2I_ldrex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz, 3521 InstrItinClass itin, string opc, string asm, string cstr, 3522 list<dag> pattern, bits<4> rt2 = 0b1111> 3523 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 3524 let Inst{31-27} = 0b11101; 3525 let Inst{26-20} = 0b0001101; 3526 let Inst{11-8} = rt2; 3527 let Inst{7-4} = opcod; 3528 let Inst{3-0} = 0b1111; 3529 3530 bits<4> addr; 3531 bits<4> Rt; 3532 let Inst{19-16} = addr; 3533 let Inst{15-12} = Rt; 3534} 3535class T2I_strex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz, 3536 InstrItinClass itin, string opc, string asm, string cstr, 3537 list<dag> pattern, bits<4> rt2 = 0b1111> 3538 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 3539 let Inst{31-27} = 0b11101; 3540 let Inst{26-20} = 0b0001100; 3541 let Inst{11-8} = rt2; 3542 let Inst{7-4} = opcod; 3543 3544 bits<4> Rd; 3545 bits<4> addr; 3546 bits<4> Rt; 3547 let Inst{3-0} = Rd; 3548 let Inst{19-16} = addr; 3549 let Inst{15-12} = Rt; 3550} 3551 3552let mayLoad = 1 in { 3553def t2LDREXB : T2I_ldrex<0b0100, (outs rGPR:$Rt), (ins addr_offset_none:$addr), 3554 AddrModeNone, 4, NoItinerary, 3555 "ldrexb", "\t$Rt, $addr", "", 3556 [(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>, 3557 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteLd]>; 3558def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr), 3559 AddrModeNone, 4, NoItinerary, 3560 "ldrexh", "\t$Rt, $addr", "", 3561 [(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>, 3562 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteLd]>; 3563def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr), 3564 AddrModeT2_ldrex, 4, NoItinerary, 3565 "ldrex", "\t$Rt, $addr", "", 3566 [(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))]>, 3567 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteLd]> { 3568 bits<4> Rt; 3569 bits<12> addr; 3570 let Inst{31-27} = 0b11101; 3571 let Inst{26-20} = 0b0000101; 3572 let Inst{19-16} = addr{11-8}; 3573 let Inst{15-12} = Rt; 3574 let Inst{11-8} = 0b1111; 3575 let Inst{7-0} = addr{7-0}; 3576} 3577let hasExtraDefRegAllocReq = 1 in 3578def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2), 3579 (ins addr_offset_none:$addr), 3580 AddrModeNone, 4, NoItinerary, 3581 "ldrexd", "\t$Rt, $Rt2, $addr", "", 3582 [], {?, ?, ?, ?}>, 3583 Requires<[IsThumb2, IsNotMClass]>, Sched<[WriteLd]> { 3584 bits<4> Rt2; 3585 let Inst{11-8} = Rt2; 3586} 3587def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr), 3588 AddrModeNone, 4, NoItinerary, 3589 "ldaexb", "\t$Rt, $addr", "", 3590 [(set rGPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>, 3591 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>, Sched<[WriteLd]>; 3592def t2LDAEXH : T2I_ldrex<0b1101, (outs rGPR:$Rt), (ins addr_offset_none:$addr), 3593 AddrModeNone, 4, NoItinerary, 3594 "ldaexh", "\t$Rt, $addr", "", 3595 [(set rGPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>, 3596 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>, Sched<[WriteLd]>; 3597def t2LDAEX : Thumb2I<(outs rGPR:$Rt), (ins addr_offset_none:$addr), 3598 AddrModeNone, 4, NoItinerary, 3599 "ldaex", "\t$Rt, $addr", "", 3600 [(set rGPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>, 3601 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>, Sched<[WriteLd]> { 3602 bits<4> Rt; 3603 bits<4> addr; 3604 let Inst{31-27} = 0b11101; 3605 let Inst{26-20} = 0b0001101; 3606 let Inst{19-16} = addr; 3607 let Inst{15-12} = Rt; 3608 let Inst{11-8} = 0b1111; 3609 let Inst{7-0} = 0b11101111; 3610} 3611let hasExtraDefRegAllocReq = 1 in 3612def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2), 3613 (ins addr_offset_none:$addr), 3614 AddrModeNone, 4, NoItinerary, 3615 "ldaexd", "\t$Rt, $Rt2, $addr", "", 3616 [], {?, ?, ?, ?}>, Requires<[IsThumb, 3617 HasAcquireRelease, HasV7Clrex, IsNotMClass]>, Sched<[WriteLd]> { 3618 bits<4> Rt2; 3619 let Inst{11-8} = Rt2; 3620 3621 let Inst{7} = 1; 3622} 3623} 3624 3625let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 3626def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd), 3627 (ins rGPR:$Rt, addr_offset_none:$addr), 3628 AddrModeNone, 4, NoItinerary, 3629 "strexb", "\t$Rd, $Rt, $addr", "", 3630 [(set rGPR:$Rd, 3631 (strex_1 rGPR:$Rt, addr_offset_none:$addr))]>, 3632 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteST]>; 3633def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd), 3634 (ins rGPR:$Rt, addr_offset_none:$addr), 3635 AddrModeNone, 4, NoItinerary, 3636 "strexh", "\t$Rd, $Rt, $addr", "", 3637 [(set rGPR:$Rd, 3638 (strex_2 rGPR:$Rt, addr_offset_none:$addr))]>, 3639 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteST]>; 3640 3641def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, 3642 t2addrmode_imm0_1020s4:$addr), 3643 AddrModeT2_ldrex, 4, NoItinerary, 3644 "strex", "\t$Rd, $Rt, $addr", "", 3645 [(set rGPR:$Rd, 3646 (strex_4 rGPR:$Rt, t2addrmode_imm0_1020s4:$addr))]>, 3647 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteST]> { 3648 bits<4> Rd; 3649 bits<4> Rt; 3650 bits<12> addr; 3651 let Inst{31-27} = 0b11101; 3652 let Inst{26-20} = 0b0000100; 3653 let Inst{19-16} = addr{11-8}; 3654 let Inst{15-12} = Rt; 3655 let Inst{11-8} = Rd; 3656 let Inst{7-0} = addr{7-0}; 3657} 3658let hasExtraSrcRegAllocReq = 1 in 3659def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd), 3660 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr), 3661 AddrModeNone, 4, NoItinerary, 3662 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [], 3663 {?, ?, ?, ?}>, 3664 Requires<[IsThumb2, IsNotMClass]>, Sched<[WriteST]> { 3665 bits<4> Rt2; 3666 let Inst{11-8} = Rt2; 3667} 3668def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd), 3669 (ins rGPR:$Rt, addr_offset_none:$addr), 3670 AddrModeNone, 4, NoItinerary, 3671 "stlexb", "\t$Rd, $Rt, $addr", "", 3672 [(set rGPR:$Rd, 3673 (stlex_1 rGPR:$Rt, addr_offset_none:$addr))]>, 3674 Requires<[IsThumb, HasAcquireRelease, 3675 HasV7Clrex]>, Sched<[WriteST]>; 3676 3677def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd), 3678 (ins rGPR:$Rt, addr_offset_none:$addr), 3679 AddrModeNone, 4, NoItinerary, 3680 "stlexh", "\t$Rd, $Rt, $addr", "", 3681 [(set rGPR:$Rd, 3682 (stlex_2 rGPR:$Rt, addr_offset_none:$addr))]>, 3683 Requires<[IsThumb, HasAcquireRelease, 3684 HasV7Clrex]>, Sched<[WriteST]>; 3685 3686def t2STLEX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, 3687 addr_offset_none:$addr), 3688 AddrModeNone, 4, NoItinerary, 3689 "stlex", "\t$Rd, $Rt, $addr", "", 3690 [(set rGPR:$Rd, 3691 (stlex_4 rGPR:$Rt, addr_offset_none:$addr))]>, 3692 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>, 3693 Sched<[WriteST]> { 3694 bits<4> Rd; 3695 bits<4> Rt; 3696 bits<4> addr; 3697 let Inst{31-27} = 0b11101; 3698 let Inst{26-20} = 0b0001100; 3699 let Inst{19-16} = addr; 3700 let Inst{15-12} = Rt; 3701 let Inst{11-4} = 0b11111110; 3702 let Inst{3-0} = Rd; 3703} 3704let hasExtraSrcRegAllocReq = 1 in 3705def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd), 3706 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr), 3707 AddrModeNone, 4, NoItinerary, 3708 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [], 3709 {?, ?, ?, ?}>, Requires<[IsThumb, HasAcquireRelease, 3710 HasV7Clrex, IsNotMClass]>, Sched<[WriteST]> { 3711 bits<4> Rt2; 3712 let Inst{11-8} = Rt2; 3713} 3714} 3715 3716def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>, 3717 Requires<[IsThumb, HasV7Clrex]> { 3718 let Inst{31-16} = 0xf3bf; 3719 let Inst{15-14} = 0b10; 3720 let Inst{13} = 0; 3721 let Inst{12} = 0; 3722 let Inst{11-8} = 0b1111; 3723 let Inst{7-4} = 0b0010; 3724 let Inst{3-0} = 0b1111; 3725} 3726 3727def : T2Pat<(and (ldrex_1 addr_offset_none:$addr), 0xff), 3728 (t2LDREXB addr_offset_none:$addr)>, 3729 Requires<[IsThumb, HasV8MBaseline]>; 3730def : T2Pat<(and (ldrex_2 addr_offset_none:$addr), 0xffff), 3731 (t2LDREXH addr_offset_none:$addr)>, 3732 Requires<[IsThumb, HasV8MBaseline]>; 3733def : T2Pat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 3734 (t2STREXB GPR:$Rt, addr_offset_none:$addr)>, 3735 Requires<[IsThumb, HasV8MBaseline]>; 3736def : T2Pat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 3737 (t2STREXH GPR:$Rt, addr_offset_none:$addr)>, 3738 Requires<[IsThumb, HasV8MBaseline]>; 3739 3740def : T2Pat<(and (ldaex_1 addr_offset_none:$addr), 0xff), 3741 (t2LDAEXB addr_offset_none:$addr)>, 3742 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>; 3743def : T2Pat<(and (ldaex_2 addr_offset_none:$addr), 0xffff), 3744 (t2LDAEXH addr_offset_none:$addr)>, 3745 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>; 3746def : T2Pat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 3747 (t2STLEXB GPR:$Rt, addr_offset_none:$addr)>, 3748 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>; 3749def : T2Pat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 3750 (t2STLEXH GPR:$Rt, addr_offset_none:$addr)>, 3751 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>; 3752 3753//===----------------------------------------------------------------------===// 3754// SJLJ Exception handling intrinsics 3755// eh_sjlj_setjmp() is an instruction sequence to store the return 3756// address and save #0 in R0 for the non-longjmp case. 3757// Since by its nature we may be coming from some other function to get 3758// here, and we're using the stack frame for the containing function to 3759// save/restore registers, we can't keep anything live in regs across 3760// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 3761// when we get here from a longjmp(). We force everything out of registers 3762// except for our own input by listing the relevant registers in Defs. By 3763// doing so, we also cause the prologue/epilogue code to actively preserve 3764// all of the callee-saved registers, which is exactly what we want. 3765// $val is a scratch register for our use. 3766let Defs = 3767 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 3768 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15], 3769 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 3770 usesCustomInserter = 1 in { 3771 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), 3772 AddrModeNone, 0, NoItinerary, "", "", 3773 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, 3774 Requires<[IsThumb2, HasVFP2]>; 3775} 3776 3777let Defs = 3778 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 3779 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 3780 usesCustomInserter = 1 in { 3781 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), 3782 AddrModeNone, 0, NoItinerary, "", "", 3783 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, 3784 Requires<[IsThumb2, NoVFP]>; 3785} 3786 3787 3788//===----------------------------------------------------------------------===// 3789// Control-Flow Instructions 3790// 3791 3792// FIXME: remove when we have a way to marking a MI with these properties. 3793// FIXME: Should pc be an implicit operand like PICADD, etc? 3794let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3795 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3796def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3797 reglist:$regs, variable_ops), 3798 4, IIC_iLoad_mBr, [], 3799 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3800 RegConstraint<"$Rn = $wb">; 3801 3802let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 3803let isPredicable = 1 in 3804def t2B : T2I<(outs), (ins thumb_br_target:$target), IIC_Br, 3805 "b", ".w\t$target", 3806 [(br bb:$target)]>, Sched<[WriteBr]>, 3807 Requires<[IsThumb, HasV8MBaseline]> { 3808 let Inst{31-27} = 0b11110; 3809 let Inst{15-14} = 0b10; 3810 let Inst{12} = 1; 3811 3812 bits<24> target; 3813 let Inst{26} = target{23}; 3814 let Inst{13} = target{22}; 3815 let Inst{11} = target{21}; 3816 let Inst{25-16} = target{20-11}; 3817 let Inst{10-0} = target{10-0}; 3818 let DecoderMethod = "DecodeT2BInstruction"; 3819 let AsmMatchConverter = "cvtThumbBranches"; 3820} 3821 3822let Size = 4, isNotDuplicable = 1, isBranch = 1, isTerminator = 1, 3823 isBarrier = 1, isIndirectBranch = 1 in { 3824 3825// available in both v8-M.Baseline and Thumb2 targets 3826def t2BR_JT : t2basePseudoInst<(outs), 3827 (ins GPR:$target, GPR:$index, i32imm:$jt), 3828 0, IIC_Br, 3829 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt)]>, 3830 Sched<[WriteBr]>; 3831 3832// FIXME: Add a case that can be predicated. 3833def t2TBB_JT : t2PseudoInst<(outs), 3834 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>, 3835 Sched<[WriteBr]>; 3836 3837def t2TBH_JT : t2PseudoInst<(outs), 3838 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>, 3839 Sched<[WriteBr]>; 3840 3841def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br, 3842 "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> { 3843 bits<4> Rn; 3844 bits<4> Rm; 3845 let Inst{31-20} = 0b111010001101; 3846 let Inst{19-16} = Rn; 3847 let Inst{15-5} = 0b11110000000; 3848 let Inst{4} = 0; // B form 3849 let Inst{3-0} = Rm; 3850 3851 let DecoderMethod = "DecodeThumbTableBranch"; 3852} 3853 3854def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br, 3855 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> { 3856 bits<4> Rn; 3857 bits<4> Rm; 3858 let Inst{31-20} = 0b111010001101; 3859 let Inst{19-16} = Rn; 3860 let Inst{15-5} = 0b11110000000; 3861 let Inst{4} = 1; // H form 3862 let Inst{3-0} = Rm; 3863 3864 let DecoderMethod = "DecodeThumbTableBranch"; 3865} 3866} // isNotDuplicable, isIndirectBranch 3867 3868} // isBranch, isTerminator, isBarrier 3869 3870// FIXME: should be able to write a pattern for ARMBrcond, but can't use 3871// a two-value operand where a dag node expects ", "two operands. :( 3872let isBranch = 1, isTerminator = 1 in 3873def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br, 3874 "b", ".w\t$target", 3875 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> { 3876 let Inst{31-27} = 0b11110; 3877 let Inst{15-14} = 0b10; 3878 let Inst{12} = 0; 3879 3880 bits<4> p; 3881 let Inst{25-22} = p; 3882 3883 bits<21> target; 3884 let Inst{26} = target{20}; 3885 let Inst{11} = target{19}; 3886 let Inst{13} = target{18}; 3887 let Inst{21-16} = target{17-12}; 3888 let Inst{10-0} = target{11-1}; 3889 3890 let DecoderMethod = "DecodeThumb2BCCInstruction"; 3891 let AsmMatchConverter = "cvtThumbBranches"; 3892} 3893 3894// Tail calls. The MachO version of thumb tail calls uses a t2 branch, so 3895// it goes here. 3896let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 3897 // IOS version. 3898 let Uses = [SP] in 3899 def tTAILJMPd: tPseudoExpand<(outs), 3900 (ins thumb_br_target:$dst, pred:$p), 3901 4, IIC_Br, [], 3902 (t2B thumb_br_target:$dst, pred:$p)>, 3903 Requires<[IsThumb2, IsMachO]>, Sched<[WriteBr]>; 3904} 3905 3906// IT block 3907let Defs = [ITSTATE] in 3908def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), 3909 AddrModeNone, 2, IIC_iALUx, 3910 "it$mask\t$cc", "", []>, 3911 ComplexDeprecationPredicate<"IT"> { 3912 // 16-bit instruction. 3913 let Inst{31-16} = 0x0000; 3914 let Inst{15-8} = 0b10111111; 3915 3916 bits<4> cc; 3917 bits<4> mask; 3918 let Inst{7-4} = cc; 3919 let Inst{3-0} = mask; 3920 3921 let DecoderMethod = "DecodeIT"; 3922} 3923 3924// Branch and Exchange Jazelle -- for disassembly only 3925// Rm = Inst{19-16} 3926let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 3927def t2BXJ : T2I<(outs), (ins GPRnopc:$func), NoItinerary, "bxj", "\t$func", []>, 3928 Sched<[WriteBr]>, Requires<[IsThumb2, IsNotMClass]> { 3929 bits<4> func; 3930 let Inst{31-27} = 0b11110; 3931 let Inst{26} = 0; 3932 let Inst{25-20} = 0b111100; 3933 let Inst{19-16} = func; 3934 let Inst{15-0} = 0b1000111100000000; 3935} 3936 3937// Compare and branch on zero / non-zero 3938let isBranch = 1, isTerminator = 1 in { 3939 def tCBZ : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br, 3940 "cbz\t$Rn, $target", []>, 3941 T1Misc<{0,0,?,1,?,?,?}>, 3942 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> { 3943 // A8.6.27 3944 bits<6> target; 3945 bits<3> Rn; 3946 let Inst{9} = target{5}; 3947 let Inst{7-3} = target{4-0}; 3948 let Inst{2-0} = Rn; 3949 } 3950 3951 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br, 3952 "cbnz\t$Rn, $target", []>, 3953 T1Misc<{1,0,?,1,?,?,?}>, 3954 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> { 3955 // A8.6.27 3956 bits<6> target; 3957 bits<3> Rn; 3958 let Inst{9} = target{5}; 3959 let Inst{7-3} = target{4-0}; 3960 let Inst{2-0} = Rn; 3961 } 3962} 3963 3964 3965// Change Processor State is a system instruction. 3966// FIXME: Since the asm parser has currently no clean way to handle optional 3967// operands, create 3 versions of the same instruction. Once there's a clean 3968// framework to represent optional operands, change this behavior. 3969class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary, 3970 !strconcat("cps", asm_op), []>, 3971 Requires<[IsThumb2, IsNotMClass]> { 3972 bits<2> imod; 3973 bits<3> iflags; 3974 bits<5> mode; 3975 bit M; 3976 3977 let Inst{31-11} = 0b111100111010111110000; 3978 let Inst{10-9} = imod; 3979 let Inst{8} = M; 3980 let Inst{7-5} = iflags; 3981 let Inst{4-0} = mode; 3982 let DecoderMethod = "DecodeT2CPSInstruction"; 3983} 3984 3985let M = 1 in 3986 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 3987 "$imod\t$iflags, $mode">; 3988let mode = 0, M = 0 in 3989 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags), 3990 "$imod.w\t$iflags">; 3991let imod = 0, iflags = 0, M = 1 in 3992 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">; 3993 3994def : t2InstAlias<"cps$imod.w $iflags, $mode", 3995 (t2CPS3p imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 0>; 3996def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>; 3997 3998// A6.3.4 Branches and miscellaneous control 3999// Table A6-14 Change Processor State, and hint instructions 4000def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm", 4001 [(int_arm_hint imm0_239:$imm)]> { 4002 bits<8> imm; 4003 let Inst{31-3} = 0b11110011101011111000000000000; 4004 let Inst{7-0} = imm; 4005} 4006 4007def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p), 0>; 4008def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p), 1>; 4009def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p), 1>; 4010def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p), 1>; 4011def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p), 1>; 4012def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p), 1>; 4013def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p), 1> { 4014 let Predicates = [IsThumb2, HasV8]; 4015} 4016def : t2InstAlias<"esb$p.w", (t2HINT 16, pred:$p), 1> { 4017 let Predicates = [IsThumb2, HasRAS]; 4018} 4019def : t2InstAlias<"esb$p", (t2HINT 16, pred:$p), 0> { 4020 let Predicates = [IsThumb2, HasRAS]; 4021} 4022def : t2InstAlias<"csdb$p.w", (t2HINT 20, pred:$p), 0>; 4023def : t2InstAlias<"csdb$p", (t2HINT 20, pred:$p), 1>; 4024 4025def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", 4026 [(int_arm_dbg imm0_15:$opt)]> { 4027 bits<4> opt; 4028 let Inst{31-20} = 0b111100111010; 4029 let Inst{19-16} = 0b1111; 4030 let Inst{15-8} = 0b10000000; 4031 let Inst{7-4} = 0b1111; 4032 let Inst{3-0} = opt; 4033} 4034 4035// Secure Monitor Call is a system instruction. 4036// Option = Inst{19-16} 4037let isCall = 1, Uses = [SP] in 4038def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 4039 []>, Requires<[IsThumb2, HasTrustZone]> { 4040 let Inst{31-27} = 0b11110; 4041 let Inst{26-20} = 0b1111111; 4042 let Inst{15-12} = 0b1000; 4043 4044 bits<4> opt; 4045 let Inst{19-16} = opt; 4046} 4047 4048class T2DCPS<bits<2> opt, string opc> 4049 : T2I<(outs), (ins), NoItinerary, opc, "", []>, Requires<[IsThumb2, HasV8]> { 4050 let Inst{31-27} = 0b11110; 4051 let Inst{26-20} = 0b1111000; 4052 let Inst{19-16} = 0b1111; 4053 let Inst{15-12} = 0b1000; 4054 let Inst{11-2} = 0b0000000000; 4055 let Inst{1-0} = opt; 4056} 4057 4058def t2DCPS1 : T2DCPS<0b01, "dcps1">; 4059def t2DCPS2 : T2DCPS<0b10, "dcps2">; 4060def t2DCPS3 : T2DCPS<0b11, "dcps3">; 4061 4062class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin, 4063 string opc, string asm, list<dag> pattern> 4064 : T2I<oops, iops, itin, opc, asm, pattern>, 4065 Requires<[IsThumb2,IsNotMClass]> { 4066 bits<5> mode; 4067 let Inst{31-25} = 0b1110100; 4068 let Inst{24-23} = Op; 4069 let Inst{22} = 0; 4070 let Inst{21} = W; 4071 let Inst{20-16} = 0b01101; 4072 let Inst{15-5} = 0b11000000000; 4073 let Inst{4-0} = mode{4-0}; 4074} 4075 4076// Store Return State is a system instruction. 4077def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary, 4078 "srsdb", "\tsp!, $mode", []>; 4079def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary, 4080 "srsdb","\tsp, $mode", []>; 4081def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary, 4082 "srsia","\tsp!, $mode", []>; 4083def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary, 4084 "srsia","\tsp, $mode", []>; 4085 4086 4087def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>; 4088def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>; 4089 4090def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>; 4091def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>; 4092 4093// Return From Exception is a system instruction. 4094let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 4095class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin, 4096 string opc, string asm, list<dag> pattern> 4097 : T2I<oops, iops, itin, opc, asm, pattern>, 4098 Requires<[IsThumb2,IsNotMClass]> { 4099 let Inst{31-20} = op31_20{11-0}; 4100 4101 bits<4> Rn; 4102 let Inst{19-16} = Rn; 4103 let Inst{15-0} = 0xc000; 4104} 4105 4106def t2RFEDBW : T2RFE<0b111010000011, 4107 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!", 4108 [/* For disassembly only; pattern left blank */]>; 4109def t2RFEDB : T2RFE<0b111010000001, 4110 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn", 4111 [/* For disassembly only; pattern left blank */]>; 4112def t2RFEIAW : T2RFE<0b111010011011, 4113 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!", 4114 [/* For disassembly only; pattern left blank */]>; 4115def t2RFEIA : T2RFE<0b111010011001, 4116 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn", 4117 [/* For disassembly only; pattern left blank */]>; 4118 4119// B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction. 4120// Exception return instruction is "subs pc, lr, #imm". 4121let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 4122def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary, 4123 "subs", "\tpc, lr, $imm", 4124 [(ARMintretflag imm0_255:$imm)]>, 4125 Requires<[IsThumb2,IsNotMClass]> { 4126 let Inst{31-8} = 0b111100111101111010001111; 4127 4128 bits<8> imm; 4129 let Inst{7-0} = imm; 4130} 4131 4132// Hypervisor Call is a system instruction. 4133let isCall = 1 in { 4134def t2HVC : T2XI <(outs), (ins imm0_65535:$imm16), IIC_Br, "hvc.w\t$imm16", []>, 4135 Requires<[IsThumb2, HasVirtualization]>, Sched<[WriteBr]> { 4136 bits<16> imm16; 4137 let Inst{31-20} = 0b111101111110; 4138 let Inst{19-16} = imm16{15-12}; 4139 let Inst{15-12} = 0b1000; 4140 let Inst{11-0} = imm16{11-0}; 4141} 4142} 4143 4144// Alias for HVC without the ".w" optional width specifier 4145def : t2InstAlias<"hvc\t$imm16", (t2HVC imm0_65535:$imm16)>; 4146 4147// ERET - Return from exception in Hypervisor mode. 4148// B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that 4149// includes virtualization extensions. 4150def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p), 1>, 4151 Requires<[IsThumb2, HasVirtualization]>; 4152 4153//===----------------------------------------------------------------------===// 4154// Non-Instruction Patterns 4155// 4156 4157// 32-bit immediate using movw + movt. 4158// This is a single pseudo instruction to make it re-materializable. 4159// FIXME: Remove this when we can do generalized remat. 4160let isReMaterializable = 1, isMoveImm = 1 in 4161def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 4162 [(set rGPR:$dst, (i32 imm:$src))]>, 4163 Requires<[IsThumb, UseMovt]>; 4164 4165// Pseudo instruction that combines movw + movt + add pc (if pic). 4166// It also makes it possible to rematerialize the instructions. 4167// FIXME: Remove this when we can do generalized remat and when machine licm 4168// can properly the instructions. 4169let isReMaterializable = 1 in { 4170def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr), 4171 IIC_iMOVix2addpc, 4172 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 4173 Requires<[IsThumb, HasV8MBaseline, UseMovtInPic]>; 4174 4175} 4176 4177def : T2Pat<(ARMWrapperPIC tglobaltlsaddr :$dst), 4178 (t2MOV_ga_pcrel tglobaltlsaddr:$dst)>, 4179 Requires<[IsThumb2, UseMovtInPic]>; 4180def : T2Pat<(ARMWrapper tglobaltlsaddr:$dst), 4181 (t2MOVi32imm tglobaltlsaddr:$dst)>, 4182 Requires<[IsThumb2, UseMovt]>; 4183 4184// ConstantPool, GlobalAddress, and JumpTable 4185def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; 4186def : T2Pat<(ARMWrapper texternalsym :$dst), (t2MOVi32imm texternalsym :$dst)>, 4187 Requires<[IsThumb, HasV8MBaseline, UseMovt]>; 4188def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>, 4189 Requires<[IsThumb, HasV8MBaseline, UseMovt]>; 4190 4191def : T2Pat<(ARMWrapperJT tjumptable:$dst), (t2LEApcrelJT tjumptable:$dst)>; 4192 4193// Pseudo instruction that combines ldr from constpool and add pc. This should 4194// be expanded into two instructions late to allow if-conversion and 4195// scheduling. 4196let canFoldAsLoad = 1, isReMaterializable = 1 in 4197def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp), 4198 IIC_iLoadiALU, 4199 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 4200 imm:$cp))]>, 4201 Requires<[IsThumb2]>; 4202 4203// Pseudo instruction that combines movs + predicated rsbmi 4204// to implement integer ABS 4205let usesCustomInserter = 1, Defs = [CPSR], hasNoSchedulingInfo = 1 in { 4206def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src), 4207 NoItinerary, []>, Requires<[IsThumb2]>; 4208} 4209 4210//===----------------------------------------------------------------------===// 4211// Coprocessor load/store -- for disassembly only 4212// 4213class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm, list<dag> pattern> 4214 : T2I<oops, iops, NoItinerary, opc, asm, pattern> { 4215 let Inst{31-28} = op31_28; 4216 let Inst{27-25} = 0b110; 4217} 4218 4219multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm, list<dag> pattern> { 4220 def _OFFSET : T2CI<op31_28, 4221 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4222 asm, "\t$cop, $CRd, $addr", pattern> { 4223 bits<13> addr; 4224 bits<4> cop; 4225 bits<4> CRd; 4226 let Inst{24} = 1; // P = 1 4227 let Inst{23} = addr{8}; 4228 let Inst{22} = Dbit; 4229 let Inst{21} = 0; // W = 0 4230 let Inst{20} = load; 4231 let Inst{19-16} = addr{12-9}; 4232 let Inst{15-12} = CRd; 4233 let Inst{11-8} = cop; 4234 let Inst{7-0} = addr{7-0}; 4235 let DecoderMethod = "DecodeCopMemInstruction"; 4236 } 4237 def _PRE : T2CI<op31_28, 4238 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 4239 asm, "\t$cop, $CRd, $addr!", []> { 4240 bits<13> addr; 4241 bits<4> cop; 4242 bits<4> CRd; 4243 let Inst{24} = 1; // P = 1 4244 let Inst{23} = addr{8}; 4245 let Inst{22} = Dbit; 4246 let Inst{21} = 1; // W = 1 4247 let Inst{20} = load; 4248 let Inst{19-16} = addr{12-9}; 4249 let Inst{15-12} = CRd; 4250 let Inst{11-8} = cop; 4251 let Inst{7-0} = addr{7-0}; 4252 let DecoderMethod = "DecodeCopMemInstruction"; 4253 } 4254 def _POST: T2CI<op31_28, 4255 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4256 postidx_imm8s4:$offset), 4257 asm, "\t$cop, $CRd, $addr, $offset", []> { 4258 bits<9> offset; 4259 bits<4> addr; 4260 bits<4> cop; 4261 bits<4> CRd; 4262 let Inst{24} = 0; // P = 0 4263 let Inst{23} = offset{8}; 4264 let Inst{22} = Dbit; 4265 let Inst{21} = 1; // W = 1 4266 let Inst{20} = load; 4267 let Inst{19-16} = addr; 4268 let Inst{15-12} = CRd; 4269 let Inst{11-8} = cop; 4270 let Inst{7-0} = offset{7-0}; 4271 let DecoderMethod = "DecodeCopMemInstruction"; 4272 } 4273 def _OPTION : T2CI<op31_28, (outs), 4274 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4275 coproc_option_imm:$option), 4276 asm, "\t$cop, $CRd, $addr, $option", []> { 4277 bits<8> option; 4278 bits<4> addr; 4279 bits<4> cop; 4280 bits<4> CRd; 4281 let Inst{24} = 0; // P = 0 4282 let Inst{23} = 1; // U = 1 4283 let Inst{22} = Dbit; 4284 let Inst{21} = 0; // W = 0 4285 let Inst{20} = load; 4286 let Inst{19-16} = addr; 4287 let Inst{15-12} = CRd; 4288 let Inst{11-8} = cop; 4289 let Inst{7-0} = option; 4290 let DecoderMethod = "DecodeCopMemInstruction"; 4291 } 4292} 4293 4294let DecoderNamespace = "Thumb2CoProc" in { 4295defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc", [(int_arm_ldc timm:$cop, timm:$CRd, addrmode5:$addr)]>; 4296defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl", [(int_arm_ldcl timm:$cop, timm:$CRd, addrmode5:$addr)]>; 4297defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2", [(int_arm_ldc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>; 4298defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l", [(int_arm_ldc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>; 4299 4300defm t2STC : t2LdStCop<0b1110, 0, 0, "stc", [(int_arm_stc timm:$cop, timm:$CRd, addrmode5:$addr)]>; 4301defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl", [(int_arm_stcl timm:$cop, timm:$CRd, addrmode5:$addr)]>; 4302defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2", [(int_arm_stc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>; 4303defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l", [(int_arm_stc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>; 4304} 4305 4306 4307//===----------------------------------------------------------------------===// 4308// Move between special register and ARM core register -- for disassembly only 4309// 4310// Move to ARM core register from Special Register 4311 4312// A/R class MRS. 4313// 4314// A/R class can only move from CPSR or SPSR. 4315def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", 4316 []>, Requires<[IsThumb2,IsNotMClass]> { 4317 bits<4> Rd; 4318 let Inst{31-12} = 0b11110011111011111000; 4319 let Inst{11-8} = Rd; 4320 let Inst{7-0} = 0b00000000; 4321} 4322 4323def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>; 4324 4325def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", 4326 []>, Requires<[IsThumb2,IsNotMClass]> { 4327 bits<4> Rd; 4328 let Inst{31-12} = 0b11110011111111111000; 4329 let Inst{11-8} = Rd; 4330 let Inst{7-0} = 0b00000000; 4331} 4332 4333def t2MRSbanked : T2I<(outs rGPR:$Rd), (ins banked_reg:$banked), 4334 NoItinerary, "mrs", "\t$Rd, $banked", []>, 4335 Requires<[IsThumb, HasVirtualization]> { 4336 bits<6> banked; 4337 bits<4> Rd; 4338 4339 let Inst{31-21} = 0b11110011111; 4340 let Inst{20} = banked{5}; // R bit 4341 let Inst{19-16} = banked{3-0}; 4342 let Inst{15-12} = 0b1000; 4343 let Inst{11-8} = Rd; 4344 let Inst{7-5} = 0b001; 4345 let Inst{4} = banked{4}; 4346 let Inst{3-0} = 0b0000; 4347} 4348 4349 4350// M class MRS. 4351// 4352// This MRS has a mask field in bits 7-0 and can take more values than 4353// the A/R class (a full msr_mask). 4354def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$SYSm), NoItinerary, 4355 "mrs", "\t$Rd, $SYSm", []>, 4356 Requires<[IsThumb,IsMClass]> { 4357 bits<4> Rd; 4358 bits<8> SYSm; 4359 let Inst{31-12} = 0b11110011111011111000; 4360 let Inst{11-8} = Rd; 4361 let Inst{7-0} = SYSm; 4362 4363 let Unpredictable{20-16} = 0b11111; 4364 let Unpredictable{13} = 0b1; 4365} 4366 4367 4368// Move from ARM core register to Special Register 4369// 4370// A/R class MSR. 4371// 4372// No need to have both system and application versions, the encodings are the 4373// same and the assembly parser has no way to distinguish between them. The mask 4374// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains 4375// the mask with the fields to be accessed in the special register. 4376let Defs = [CPSR] in 4377def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn), 4378 NoItinerary, "msr", "\t$mask, $Rn", []>, 4379 Requires<[IsThumb2,IsNotMClass]> { 4380 bits<5> mask; 4381 bits<4> Rn; 4382 let Inst{31-21} = 0b11110011100; 4383 let Inst{20} = mask{4}; // R Bit 4384 let Inst{19-16} = Rn; 4385 let Inst{15-12} = 0b1000; 4386 let Inst{11-8} = mask{3-0}; 4387 let Inst{7-0} = 0; 4388} 4389 4390// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a 4391// separate encoding (distinguished by bit 5. 4392def t2MSRbanked : T2I<(outs), (ins banked_reg:$banked, rGPR:$Rn), 4393 NoItinerary, "msr", "\t$banked, $Rn", []>, 4394 Requires<[IsThumb, HasVirtualization]> { 4395 bits<6> banked; 4396 bits<4> Rn; 4397 4398 let Inst{31-21} = 0b11110011100; 4399 let Inst{20} = banked{5}; // R bit 4400 let Inst{19-16} = Rn; 4401 let Inst{15-12} = 0b1000; 4402 let Inst{11-8} = banked{3-0}; 4403 let Inst{7-5} = 0b001; 4404 let Inst{4} = banked{4}; 4405 let Inst{3-0} = 0b0000; 4406} 4407 4408 4409// M class MSR. 4410// 4411// Move from ARM core register to Special Register 4412let Defs = [CPSR] in 4413def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn), 4414 NoItinerary, "msr", "\t$SYSm, $Rn", []>, 4415 Requires<[IsThumb,IsMClass]> { 4416 bits<12> SYSm; 4417 bits<4> Rn; 4418 let Inst{31-21} = 0b11110011100; 4419 let Inst{20} = 0b0; 4420 let Inst{19-16} = Rn; 4421 let Inst{15-12} = 0b1000; 4422 let Inst{11-10} = SYSm{11-10}; 4423 let Inst{9-8} = 0b00; 4424 let Inst{7-0} = SYSm{7-0}; 4425 4426 let Unpredictable{20} = 0b1; 4427 let Unpredictable{13} = 0b1; 4428 let Unpredictable{9-8} = 0b11; 4429} 4430 4431 4432//===----------------------------------------------------------------------===// 4433// Move between coprocessor and ARM core register 4434// 4435 4436class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops, 4437 list<dag> pattern> 4438 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", 4439 pattern> { 4440 let Inst{27-24} = 0b1110; 4441 let Inst{20} = direction; 4442 let Inst{4} = 1; 4443 4444 bits<4> Rt; 4445 bits<4> cop; 4446 bits<3> opc1; 4447 bits<3> opc2; 4448 bits<4> CRm; 4449 bits<4> CRn; 4450 4451 let Inst{15-12} = Rt; 4452 let Inst{11-8} = cop; 4453 let Inst{23-21} = opc1; 4454 let Inst{7-5} = opc2; 4455 let Inst{3-0} = CRm; 4456 let Inst{19-16} = CRn; 4457 4458 let DecoderNamespace = "Thumb2CoProc"; 4459} 4460 4461class t2MovRRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops, 4462 list<dag> pattern = []> 4463 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> { 4464 let Inst{27-24} = 0b1100; 4465 let Inst{23-21} = 0b010; 4466 let Inst{20} = direction; 4467 4468 bits<4> Rt; 4469 bits<4> Rt2; 4470 bits<4> cop; 4471 bits<4> opc1; 4472 bits<4> CRm; 4473 4474 let Inst{15-12} = Rt; 4475 let Inst{19-16} = Rt2; 4476 let Inst{11-8} = cop; 4477 let Inst{7-4} = opc1; 4478 let Inst{3-0} = CRm; 4479 4480 let DecoderNamespace = "Thumb2CoProc"; 4481} 4482 4483/* from ARM core register to coprocessor */ 4484def t2MCR : t2MovRCopro<0b1110, "mcr", 0, 4485 (outs), 4486 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4487 c_imm:$CRm, imm0_7:$opc2), 4488 [(int_arm_mcr timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn, 4489 timm:$CRm, timm:$opc2)]>, 4490 ComplexDeprecationPredicate<"MCR">; 4491def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 4492 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4493 c_imm:$CRm, 0, pred:$p)>; 4494def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0, 4495 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4496 c_imm:$CRm, imm0_7:$opc2), 4497 [(int_arm_mcr2 timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn, 4498 timm:$CRm, timm:$opc2)]> { 4499 let Predicates = [IsThumb2, PreV8]; 4500} 4501def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm", 4502 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4503 c_imm:$CRm, 0, pred:$p)>; 4504 4505/* from coprocessor to ARM core register */ 4506def t2MRC : t2MovRCopro<0b1110, "mrc", 1, 4507 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4508 c_imm:$CRm, imm0_7:$opc2), []>; 4509def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 4510 (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4511 c_imm:$CRm, 0, pred:$p)>; 4512 4513def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1, 4514 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4515 c_imm:$CRm, imm0_7:$opc2), []> { 4516 let Predicates = [IsThumb2, PreV8]; 4517} 4518def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm", 4519 (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4520 c_imm:$CRm, 0, pred:$p)>; 4521 4522def : T2v6Pat<(int_arm_mrc timm:$cop, timm:$opc1, timm:$CRn, timm:$CRm, timm:$opc2), 4523 (t2MRC p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2)>; 4524 4525def : T2v6Pat<(int_arm_mrc2 timm:$cop, timm:$opc1, timm:$CRn, timm:$CRm, timm:$opc2), 4526 (t2MRC2 p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2)>; 4527 4528 4529/* from ARM core register to coprocessor */ 4530def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0, (outs), 4531 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, 4532 c_imm:$CRm), 4533 [(int_arm_mcrr timm:$cop, timm:$opc1, GPR:$Rt, GPR:$Rt2, 4534 timm:$CRm)]>; 4535def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0, (outs), 4536 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, 4537 c_imm:$CRm), 4538 [(int_arm_mcrr2 timm:$cop, timm:$opc1, GPR:$Rt, 4539 GPR:$Rt2, timm:$CRm)]> { 4540 let Predicates = [IsThumb2, PreV8]; 4541} 4542 4543/* from coprocessor to ARM core register */ 4544def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1, (outs GPR:$Rt, GPR:$Rt2), 4545 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)>; 4546 4547def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1, (outs GPR:$Rt, GPR:$Rt2), 4548 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)> { 4549 let Predicates = [IsThumb2, PreV8]; 4550} 4551 4552//===----------------------------------------------------------------------===// 4553// Other Coprocessor Instructions. 4554// 4555 4556def t2CDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4557 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4558 "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4559 [(int_arm_cdp timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn, 4560 timm:$CRm, timm:$opc2)]> { 4561 let Inst{27-24} = 0b1110; 4562 4563 bits<4> opc1; 4564 bits<4> CRn; 4565 bits<4> CRd; 4566 bits<4> cop; 4567 bits<3> opc2; 4568 bits<4> CRm; 4569 4570 let Inst{3-0} = CRm; 4571 let Inst{4} = 0; 4572 let Inst{7-5} = opc2; 4573 let Inst{11-8} = cop; 4574 let Inst{15-12} = CRd; 4575 let Inst{19-16} = CRn; 4576 let Inst{23-20} = opc1; 4577 4578 let Predicates = [IsThumb2, PreV8]; 4579 let DecoderNamespace = "Thumb2CoProc"; 4580} 4581 4582def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4583 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4584 "cdp2", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4585 [(int_arm_cdp2 timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn, 4586 timm:$CRm, timm:$opc2)]> { 4587 let Inst{27-24} = 0b1110; 4588 4589 bits<4> opc1; 4590 bits<4> CRn; 4591 bits<4> CRd; 4592 bits<4> cop; 4593 bits<3> opc2; 4594 bits<4> CRm; 4595 4596 let Inst{3-0} = CRm; 4597 let Inst{4} = 0; 4598 let Inst{7-5} = opc2; 4599 let Inst{11-8} = cop; 4600 let Inst{15-12} = CRd; 4601 let Inst{19-16} = CRn; 4602 let Inst{23-20} = opc1; 4603 4604 let Predicates = [IsThumb2, PreV8]; 4605 let DecoderNamespace = "Thumb2CoProc"; 4606} 4607 4608 4609 4610//===----------------------------------------------------------------------===// 4611// ARMv8.1 Privilege Access Never extension 4612// 4613// SETPAN #imm1 4614 4615def t2SETPAN : T1I<(outs), (ins imm0_1:$imm), NoItinerary, "setpan\t$imm", []>, 4616 T1Misc<0b0110000>, Requires<[IsThumb2, HasV8, HasV8_1a]> { 4617 bits<1> imm; 4618 4619 let Inst{4} = 0b1; 4620 let Inst{3} = imm; 4621 let Inst{2-0} = 0b000; 4622 4623 let Unpredictable{4} = 0b1; 4624 let Unpredictable{2-0} = 0b111; 4625} 4626 4627//===----------------------------------------------------------------------===// 4628// ARMv8-M Security Extensions instructions 4629// 4630 4631let hasSideEffects = 1 in 4632def t2SG : T2I<(outs), (ins), NoItinerary, "sg", "", []>, 4633 Requires<[Has8MSecExt]> { 4634 let Inst = 0xe97fe97f; 4635} 4636 4637class T2TT<bits<2> at, string asm, list<dag> pattern> 4638 : T2I<(outs rGPR:$Rt), (ins GPRnopc:$Rn), NoItinerary, asm, "\t$Rt, $Rn", 4639 pattern> { 4640 bits<4> Rn; 4641 bits<4> Rt; 4642 4643 let Inst{31-20} = 0b111010000100; 4644 let Inst{19-16} = Rn; 4645 let Inst{15-12} = 0b1111; 4646 let Inst{11-8} = Rt; 4647 let Inst{7-6} = at; 4648 let Inst{5-0} = 0b000000; 4649 4650 let Unpredictable{5-0} = 0b111111; 4651} 4652 4653def t2TT : T2TT<0b00, "tt", 4654 [(set rGPR:$Rt, (int_arm_cmse_tt GPRnopc:$Rn))]>, 4655 Requires<[IsThumb, Has8MSecExt]>; 4656def t2TTT : T2TT<0b01, "ttt", 4657 [(set rGPR:$Rt, (int_arm_cmse_ttt GPRnopc:$Rn))]>, 4658 Requires<[IsThumb, Has8MSecExt]>; 4659def t2TTA : T2TT<0b10, "tta", 4660 [(set rGPR:$Rt, (int_arm_cmse_tta GPRnopc:$Rn))]>, 4661 Requires<[IsThumb, Has8MSecExt]>; 4662def t2TTAT : T2TT<0b11, "ttat", 4663 [(set rGPR:$Rt, (int_arm_cmse_ttat GPRnopc:$Rn))]>, 4664 Requires<[IsThumb, Has8MSecExt]>; 4665 4666//===----------------------------------------------------------------------===// 4667// Non-Instruction Patterns 4668// 4669 4670// SXT/UXT with no rotate 4671let AddedComplexity = 16 in { 4672def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>, 4673 Requires<[IsThumb2]>; 4674def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>, 4675 Requires<[IsThumb2]>; 4676def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>, 4677 Requires<[HasDSP, IsThumb2]>; 4678def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)), 4679 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>, 4680 Requires<[HasDSP, IsThumb2]>; 4681def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)), 4682 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>, 4683 Requires<[HasDSP, IsThumb2]>; 4684} 4685 4686def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>, 4687 Requires<[IsThumb2]>; 4688def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>, 4689 Requires<[IsThumb2]>; 4690def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)), 4691 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>, 4692 Requires<[HasDSP, IsThumb2]>; 4693def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)), 4694 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>, 4695 Requires<[HasDSP, IsThumb2]>; 4696 4697// Atomic load/store patterns 4698def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr), 4699 (t2LDRBi12 t2addrmode_imm12:$addr)>; 4700def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr), 4701 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 4702def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr), 4703 (t2LDRBs t2addrmode_so_reg:$addr)>; 4704def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr), 4705 (t2LDRHi12 t2addrmode_imm12:$addr)>; 4706def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr), 4707 (t2LDRHi8 t2addrmode_negimm8:$addr)>; 4708def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr), 4709 (t2LDRHs t2addrmode_so_reg:$addr)>; 4710def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr), 4711 (t2LDRi12 t2addrmode_imm12:$addr)>; 4712def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr), 4713 (t2LDRi8 t2addrmode_negimm8:$addr)>; 4714def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr), 4715 (t2LDRs t2addrmode_so_reg:$addr)>; 4716def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val), 4717 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>; 4718def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val), 4719 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>; 4720def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val), 4721 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>; 4722def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val), 4723 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>; 4724def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val), 4725 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>; 4726def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val), 4727 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>; 4728def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val), 4729 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>; 4730def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val), 4731 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>; 4732def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val), 4733 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>; 4734 4735let AddedComplexity = 8, Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex] in { 4736 def : Pat<(atomic_load_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>; 4737 def : Pat<(atomic_load_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>; 4738 def : Pat<(atomic_load_acquire_32 addr_offset_none:$addr), (t2LDA addr_offset_none:$addr)>; 4739 def : Pat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (t2STLB GPR:$val, addr_offset_none:$addr)>; 4740 def : Pat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (t2STLH GPR:$val, addr_offset_none:$addr)>; 4741 def : Pat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (t2STL GPR:$val, addr_offset_none:$addr)>; 4742} 4743 4744 4745//===----------------------------------------------------------------------===// 4746// Assembler aliases 4747// 4748 4749// Aliases for ADC without the ".w" optional width specifier. 4750def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm", 4751 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4752def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm", 4753 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, 4754 pred:$p, cc_out:$s)>; 4755 4756// Aliases for SBC without the ".w" optional width specifier. 4757def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm", 4758 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4759def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm", 4760 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, 4761 pred:$p, cc_out:$s)>; 4762 4763// Aliases for ADD without the ".w" optional width specifier. 4764def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm", 4765 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, 4766 cc_out:$s)>; 4767def : t2InstAlias<"add${p} $Rd, $Rn, $imm", 4768 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>; 4769def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm", 4770 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4771def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm", 4772 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, 4773 pred:$p, cc_out:$s)>; 4774// ... and with the destination and source register combined. 4775def : t2InstAlias<"add${s}${p} $Rdn, $imm", 4776 (t2ADDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4777def : t2InstAlias<"add${p} $Rdn, $imm", 4778 (t2ADDri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095:$imm, pred:$p)>; 4779def : t2InstAlias<"addw${p} $Rdn, $imm", 4780 (t2ADDri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095:$imm, pred:$p)>; 4781def : t2InstAlias<"add${s}${p} $Rdn, $Rm", 4782 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4783def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm", 4784 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm, 4785 pred:$p, cc_out:$s)>; 4786 4787// add w/ negative immediates is just a sub. 4788def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm", 4789 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p, 4790 cc_out:$s)>; 4791def : t2InstSubst<"add${p} $Rd, $Rn, $imm", 4792 (t2SUBri12 rGPR:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>; 4793def : t2InstSubst<"add${s}${p} $Rdn, $imm", 4794 (t2SUBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_neg:$imm, pred:$p, 4795 cc_out:$s)>; 4796def : t2InstSubst<"add${p} $Rdn, $imm", 4797 (t2SUBri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095_neg:$imm, pred:$p)>; 4798 4799def : t2InstSubst<"add${s}${p}.w $Rd, $Rn, $imm", 4800 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p, 4801 cc_out:$s)>; 4802def : t2InstSubst<"addw${p} $Rd, $Rn, $imm", 4803 (t2SUBri12 rGPR:$Rd, rGPR:$Rn, imm0_4095_neg:$imm, pred:$p)>; 4804def : t2InstSubst<"add${s}${p}.w $Rdn, $imm", 4805 (t2SUBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_neg:$imm, pred:$p, 4806 cc_out:$s)>; 4807def : t2InstSubst<"addw${p} $Rdn, $imm", 4808 (t2SUBri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095_neg:$imm, pred:$p)>; 4809 4810 4811// Aliases for SUB without the ".w" optional width specifier. 4812def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm", 4813 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4814def : t2InstAlias<"sub${p} $Rd, $Rn, $imm", 4815 (t2SUBri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>; 4816def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm", 4817 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4818def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm", 4819 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, 4820 pred:$p, cc_out:$s)>; 4821// ... and with the destination and source register combined. 4822def : t2InstAlias<"sub${s}${p} $Rdn, $imm", 4823 (t2SUBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4824def : t2InstAlias<"sub${p} $Rdn, $imm", 4825 (t2SUBri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095:$imm, pred:$p)>; 4826def : t2InstAlias<"subw${p} $Rdn, $imm", 4827 (t2SUBri12 rGPR:$Rdn, rGPR:$Rdn, imm0_4095:$imm, pred:$p)>; 4828def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm", 4829 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4830def : t2InstAlias<"sub${s}${p} $Rdn, $Rm", 4831 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4832def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm", 4833 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm, 4834 pred:$p, cc_out:$s)>; 4835 4836// SP to SP alike aliases 4837// Aliases for ADD without the ".w" optional width specifier. 4838def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm", 4839 (t2ADDspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm:$imm, pred:$p, 4840 cc_out:$s)>; 4841def : t2InstAlias<"add${p} $Rd, $Rn, $imm", 4842 (t2ADDspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095:$imm, pred:$p)>; 4843// ... and with the destination and source register combined. 4844def : t2InstAlias<"add${s}${p} $Rdn, $imm", 4845 (t2ADDspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4846 4847def : t2InstAlias<"add${s}${p}.w $Rdn, $imm", 4848 (t2ADDspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4849 4850def : t2InstAlias<"add${p} $Rdn, $imm", 4851 (t2ADDspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095:$imm, pred:$p)>; 4852 4853def : t2InstAlias<"addw${p} $Rdn, $imm", 4854 (t2ADDspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095:$imm, pred:$p)>; 4855 4856// add w/ negative immediates is just a sub. 4857def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm", 4858 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm_neg:$imm, pred:$p, 4859 cc_out:$s)>; 4860def : t2InstSubst<"add${p} $Rd, $Rn, $imm", 4861 (t2SUBspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095_neg:$imm, pred:$p)>; 4862def : t2InstSubst<"add${s}${p} $Rdn, $imm", 4863 (t2SUBspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm_neg:$imm, pred:$p, 4864 cc_out:$s)>; 4865def : t2InstSubst<"add${p} $Rdn, $imm", 4866 (t2SUBspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095_neg:$imm, pred:$p)>; 4867 4868def : t2InstSubst<"add${s}${p}.w $Rd, $Rn, $imm", 4869 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm_neg:$imm, pred:$p, 4870 cc_out:$s)>; 4871def : t2InstSubst<"addw${p} $Rd, $Rn, $imm", 4872 (t2SUBspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095_neg:$imm, pred:$p)>; 4873def : t2InstSubst<"add${s}${p}.w $Rdn, $imm", 4874 (t2SUBspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm_neg:$imm, pred:$p, 4875 cc_out:$s)>; 4876def : t2InstSubst<"addw${p} $Rdn, $imm", 4877 (t2SUBspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095_neg:$imm, pred:$p)>; 4878 4879 4880// Aliases for SUB without the ".w" optional width specifier. 4881def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm", 4882 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4883def : t2InstAlias<"sub${p} $Rd, $Rn, $imm", 4884 (t2SUBspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095:$imm, pred:$p)>; 4885// ... and with the destination and source register combined. 4886def : t2InstAlias<"sub${s}${p} $Rdn, $imm", 4887 (t2SUBspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4888def : t2InstAlias<"sub${s}${p}.w $Rdn, $imm", 4889 (t2SUBspImm GPRsp:$Rdn, GPRsp:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4890def : t2InstAlias<"sub${p} $Rdn, $imm", 4891 (t2SUBspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095:$imm, pred:$p)>; 4892def : t2InstAlias<"subw${p} $Rdn, $imm", 4893 (t2SUBspImm12 GPRsp:$Rdn, GPRsp:$Rdn, imm0_4095:$imm, pred:$p)>; 4894 4895// Alias for compares without the ".w" optional width specifier. 4896def : t2InstAlias<"cmn${p} $Rn, $Rm", 4897 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; 4898def : t2InstAlias<"teq${p} $Rn, $Rm", 4899 (t2TEQrr rGPR:$Rn, rGPR:$Rm, pred:$p)>; 4900def : t2InstAlias<"tst${p} $Rn, $Rm", 4901 (t2TSTrr rGPR:$Rn, rGPR:$Rm, pred:$p)>; 4902 4903// Memory barriers 4904def : InstAlias<"dmb${p}.w\t$opt", (t2DMB memb_opt:$opt, pred:$p), 0>, Requires<[HasDB]>; 4905def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>; 4906def : InstAlias<"dmb${p}.w", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>; 4907def : InstAlias<"dsb${p}.w\t$opt", (t2DSB memb_opt:$opt, pred:$p), 0>, Requires<[HasDB]>; 4908def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>; 4909def : InstAlias<"dsb${p}.w", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>; 4910def : InstAlias<"isb${p}.w\t$opt", (t2ISB memb_opt:$opt, pred:$p), 0>, Requires<[HasDB]>; 4911def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>; 4912def : InstAlias<"isb${p}.w", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>; 4913 4914// Non-predicable aliases of a predicable DSB: the predicate is (14, 0) where 4915// 14 = AL (always execute) and 0 = "instruction doesn't read the CPSR". 4916def : InstAlias<"ssbb", (t2DSB 0x0, 14, 0), 1>, Requires<[HasDB, IsThumb2]>; 4917def : InstAlias<"pssbb", (t2DSB 0x4, 14, 0), 1>, Requires<[HasDB, IsThumb2]>; 4918 4919// Armv8-R 'Data Full Barrier' 4920def : InstAlias<"dfb${p}", (t2DSB 0xc, pred:$p), 1>, Requires<[HasDFB]>; 4921 4922// Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional 4923// width specifier. 4924def : t2InstAlias<"ldr${p} $Rt, $addr", 4925 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4926def : t2InstAlias<"ldrb${p} $Rt, $addr", 4927 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4928def : t2InstAlias<"ldrh${p} $Rt, $addr", 4929 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4930def : t2InstAlias<"ldrsb${p} $Rt, $addr", 4931 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4932def : t2InstAlias<"ldrsh${p} $Rt, $addr", 4933 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4934 4935def : t2InstAlias<"ldr${p} $Rt, $addr", 4936 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4937def : t2InstAlias<"ldrb${p} $Rt, $addr", 4938 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4939def : t2InstAlias<"ldrh${p} $Rt, $addr", 4940 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4941def : t2InstAlias<"ldrsb${p} $Rt, $addr", 4942 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4943def : t2InstAlias<"ldrsh${p} $Rt, $addr", 4944 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4945 4946def : t2InstAlias<"ldr${p} $Rt, $addr", 4947 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4948def : t2InstAlias<"ldrb${p} $Rt, $addr", 4949 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4950def : t2InstAlias<"ldrh${p} $Rt, $addr", 4951 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4952def : t2InstAlias<"ldrsb${p} $Rt, $addr", 4953 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4954def : t2InstAlias<"ldrsh${p} $Rt, $addr", 4955 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4956 4957// Alias for MVN with(out) the ".w" optional width specifier. 4958def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm", 4959 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4960def : t2InstAlias<"mvn${s}${p} $Rd, $Rm", 4961 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>; 4962def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm", 4963 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>; 4964 4965// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the 4966// input operands swapped when the shift amount is zero (i.e., unspecified). 4967def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 4968 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, 4969 Requires<[HasDSP, IsThumb2]>; 4970def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 4971 (t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p), 0>, 4972 Requires<[HasDSP, IsThumb2]>; 4973 4974// PUSH/POP aliases for STM/LDM 4975def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>; 4976def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>; 4977def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>; 4978def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>; 4979 4980// STMIA/STMIA_UPD aliases w/o the optional .w suffix 4981def : t2InstAlias<"stm${p} $Rn, $regs", 4982 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>; 4983def : t2InstAlias<"stm${p} $Rn!, $regs", 4984 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>; 4985 4986// LDMIA/LDMIA_UPD aliases w/o the optional .w suffix 4987def : t2InstAlias<"ldm${p} $Rn, $regs", 4988 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>; 4989def : t2InstAlias<"ldm${p} $Rn!, $regs", 4990 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>; 4991 4992// STMDB/STMDB_UPD aliases w/ the optional .w suffix 4993def : t2InstAlias<"stmdb${p}.w $Rn, $regs", 4994 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>; 4995def : t2InstAlias<"stmdb${p}.w $Rn!, $regs", 4996 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>; 4997 4998// LDMDB/LDMDB_UPD aliases w/ the optional .w suffix 4999def : t2InstAlias<"ldmdb${p}.w $Rn, $regs", 5000 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>; 5001def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs", 5002 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>; 5003 5004// Alias for REV/REV16/REVSH without the ".w" optional width specifier. 5005def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>; 5006def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>; 5007def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>; 5008 5009 5010// Alias for RSB without the ".w" optional width specifier, and with optional 5011// implied destination register. 5012def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm", 5013 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 5014def : t2InstAlias<"rsb${s}${p} $Rdn, $imm", 5015 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 5016def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm", 5017 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 5018def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm", 5019 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p, 5020 cc_out:$s)>; 5021 5022// SSAT/USAT optional shift operand. 5023def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 5024 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>; 5025def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn", 5026 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>; 5027 5028// STM w/o the .w suffix. 5029def : t2InstAlias<"stm${p} $Rn, $regs", 5030 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>; 5031 5032// Alias for STR, STRB, and STRH without the ".w" optional 5033// width specifier. 5034def : t2InstAlias<"str${p} $Rt, $addr", 5035 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 5036def : t2InstAlias<"strb${p} $Rt, $addr", 5037 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 5038def : t2InstAlias<"strh${p} $Rt, $addr", 5039 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 5040 5041def : t2InstAlias<"str${p} $Rt, $addr", 5042 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 5043def : t2InstAlias<"strb${p} $Rt, $addr", 5044 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 5045def : t2InstAlias<"strh${p} $Rt, $addr", 5046 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 5047 5048// Extend instruction optional rotate operand. 5049def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm", 5050 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, 5051 Requires<[HasDSP, IsThumb2]>; 5052def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm", 5053 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, 5054 Requires<[HasDSP, IsThumb2]>; 5055def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 5056 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, 5057 Requires<[HasDSP, IsThumb2]>; 5058def : InstAlias<"sxtb16${p} $Rd, $Rm", 5059 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>, 5060 Requires<[HasDSP, IsThumb2]>; 5061 5062def : t2InstAlias<"sxtb${p} $Rd, $Rm", 5063 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 5064def : t2InstAlias<"sxth${p} $Rd, $Rm", 5065 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 5066def : t2InstAlias<"sxtb${p}.w $Rd, $Rm", 5067 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 5068def : t2InstAlias<"sxth${p}.w $Rd, $Rm", 5069 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 5070 5071def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm", 5072 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, 5073 Requires<[HasDSP, IsThumb2]>; 5074def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm", 5075 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, 5076 Requires<[HasDSP, IsThumb2]>; 5077def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 5078 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, 5079 Requires<[HasDSP, IsThumb2]>; 5080def : InstAlias<"uxtb16${p} $Rd, $Rm", 5081 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>, 5082 Requires<[HasDSP, IsThumb2]>; 5083 5084def : t2InstAlias<"uxtb${p} $Rd, $Rm", 5085 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 5086def : t2InstAlias<"uxth${p} $Rd, $Rm", 5087 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 5088def : t2InstAlias<"uxtb${p}.w $Rd, $Rm", 5089 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 5090def : t2InstAlias<"uxth${p}.w $Rd, $Rm", 5091 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 5092 5093// Extend instruction w/o the ".w" optional width specifier. 5094def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot", 5095 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 5096def : InstAlias<"uxtb16${p} $Rd, $Rm$rot", 5097 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>, 5098 Requires<[HasDSP, IsThumb2]>; 5099def : t2InstAlias<"uxth${p} $Rd, $Rm$rot", 5100 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 5101 5102def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot", 5103 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 5104def : InstAlias<"sxtb16${p} $Rd, $Rm$rot", 5105 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>, 5106 Requires<[HasDSP, IsThumb2]>; 5107def : t2InstAlias<"sxth${p} $Rd, $Rm$rot", 5108 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 5109 5110 5111// "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like 5112// for isel. 5113def : t2InstSubst<"mov${p} $Rd, $imm", 5114 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>; 5115def : t2InstSubst<"mvn${s}${p} $Rd, $imm", 5116 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>; 5117// Same for AND <--> BIC 5118def : t2InstSubst<"bic${s}${p} $Rd, $Rn, $imm", 5119 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, 5120 pred:$p, cc_out:$s)>; 5121def : t2InstSubst<"bic${s}${p} $Rdn, $imm", 5122 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, 5123 pred:$p, cc_out:$s)>; 5124def : t2InstSubst<"bic${s}${p}.w $Rd, $Rn, $imm", 5125 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, 5126 pred:$p, cc_out:$s)>; 5127def : t2InstSubst<"bic${s}${p}.w $Rdn, $imm", 5128 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, 5129 pred:$p, cc_out:$s)>; 5130def : t2InstSubst<"and${s}${p} $Rd, $Rn, $imm", 5131 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, 5132 pred:$p, cc_out:$s)>; 5133def : t2InstSubst<"and${s}${p} $Rdn, $imm", 5134 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, 5135 pred:$p, cc_out:$s)>; 5136def : t2InstSubst<"and${s}${p}.w $Rd, $Rn, $imm", 5137 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, 5138 pred:$p, cc_out:$s)>; 5139def : t2InstSubst<"and${s}${p}.w $Rdn, $imm", 5140 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, 5141 pred:$p, cc_out:$s)>; 5142// And ORR <--> ORN 5143def : t2InstSubst<"orn${s}${p} $Rd, $Rn, $imm", 5144 (t2ORRri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, 5145 pred:$p, cc_out:$s)>; 5146def : t2InstSubst<"orn${s}${p} $Rdn, $imm", 5147 (t2ORRri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, 5148 pred:$p, cc_out:$s)>; 5149def : t2InstSubst<"orr${s}${p} $Rd, $Rn, $imm", 5150 (t2ORNri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, 5151 pred:$p, cc_out:$s)>; 5152def : t2InstSubst<"orr${s}${p} $Rdn, $imm", 5153 (t2ORNri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, 5154 pred:$p, cc_out:$s)>; 5155// Likewise, "add Rd, t2_so_imm_neg" -> sub 5156def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm", 5157 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, 5158 pred:$p, cc_out:$s)>; 5159def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm", 5160 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm_neg:$imm, 5161 pred:$p, cc_out:$s)>; 5162def : t2InstSubst<"add${s}${p} $Rd, $imm", 5163 (t2SUBri rGPR:$Rd, rGPR:$Rd, t2_so_imm_neg:$imm, 5164 pred:$p, cc_out:$s)>; 5165def : t2InstSubst<"add${s}${p} $Rd, $imm", 5166 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rd, t2_so_imm_neg:$imm, 5167 pred:$p, cc_out:$s)>; 5168// Same for CMP <--> CMN via t2_so_imm_neg 5169def : t2InstSubst<"cmp${p} $Rd, $imm", 5170 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>; 5171def : t2InstSubst<"cmn${p} $Rd, $imm", 5172 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>; 5173 5174 5175// Wide 'mul' encoding can be specified with only two operands. 5176def : t2InstAlias<"mul${p} $Rn, $Rm", 5177 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>; 5178 5179// "neg" is and alias for "rsb rd, rn, #0" 5180def : t2InstAlias<"neg${s}${p} $Rd, $Rm", 5181 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>; 5182 5183// MOV so_reg assembler pseudos. InstAlias isn't expressive enough for 5184// these, unfortunately. 5185// FIXME: LSL #0 in the shift should allow SP to be used as either the 5186// source or destination (but not both). 5187def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift", 5188 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>; 5189def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift", 5190 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>; 5191 5192def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift", 5193 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; 5194def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift", 5195 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; 5196 5197// Aliases for the above with the .w qualifier 5198def : t2InstAlias<"mov${p}.w $Rd, $shift", 5199 (t2MOVsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>; 5200def : t2InstAlias<"movs${p}.w $Rd, $shift", 5201 (t2MOVSsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>; 5202def : t2InstAlias<"mov${p}.w $Rd, $shift", 5203 (t2MOVsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; 5204def : t2InstAlias<"movs${p}.w $Rd, $shift", 5205 (t2MOVSsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; 5206 5207// ADR w/o the .w suffix 5208def : t2InstAlias<"adr${p} $Rd, $addr", 5209 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>; 5210 5211// LDR(literal) w/ alternate [pc, #imm] syntax. 5212def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr", 5213 (ins GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 5214def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr", 5215 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 5216def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr", 5217 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 5218def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr", 5219 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 5220def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr", 5221 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 5222 // Version w/ the .w suffix. 5223def : t2InstAlias<"ldr${p}.w $Rt, $addr", 5224 (t2LDRpcrel GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p), 0>; 5225def : t2InstAlias<"ldrb${p}.w $Rt, $addr", 5226 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 5227def : t2InstAlias<"ldrh${p}.w $Rt, $addr", 5228 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 5229def : t2InstAlias<"ldrsb${p}.w $Rt, $addr", 5230 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 5231def : t2InstAlias<"ldrsh${p}.w $Rt, $addr", 5232 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 5233 5234def : t2InstAlias<"add${p} $Rd, pc, $imm", 5235 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>; 5236 5237// Pseudo instruction ldr Rt, =immediate 5238def t2LDRConstPool 5239 : t2AsmPseudo<"ldr${p} $Rt, $immediate", 5240 (ins GPR:$Rt, const_pool_asm_imm:$immediate, pred:$p)>; 5241// Version w/ the .w suffix. 5242def : t2InstAlias<"ldr${p}.w $Rt, $immediate", 5243 (t2LDRConstPool GPRnopc:$Rt, 5244 const_pool_asm_imm:$immediate, pred:$p)>; 5245 5246//===----------------------------------------------------------------------===// 5247// ARMv8.1m instructions 5248// 5249 5250class V8_1MI<dag oops, dag iops, AddrMode am, InstrItinClass itin, string asm, 5251 string ops, string cstr, list<dag> pattern> 5252 : Thumb2XI<oops, iops, am, 4, itin, !strconcat(asm, "\t", ops), cstr, 5253 pattern>, 5254 Requires<[HasV8_1MMainline]>; 5255 5256def t2CLRM : V8_1MI<(outs), 5257 (ins pred:$p, reglist_with_apsr:$regs, variable_ops), 5258 AddrModeNone, NoItinerary, "clrm${p}", "$regs", "", []> { 5259 bits<16> regs; 5260 5261 let Inst{31-16} = 0b1110100010011111; 5262 let Inst{15-14} = regs{15-14}; 5263 let Inst{13} = 0b0; 5264 let Inst{12-0} = regs{12-0}; 5265} 5266 5267class t2BF<dag iops, string asm, string ops> 5268 : V8_1MI<(outs ), iops, AddrModeNone, NoItinerary, asm, ops, "", []> { 5269 5270 let Inst{31-27} = 0b11110; 5271 let Inst{15-14} = 0b11; 5272 let Inst{12} = 0b0; 5273 let Inst{0} = 0b1; 5274 5275 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB]; 5276} 5277 5278def t2BF_LabelPseudo 5279 : t2PseudoInst<(outs ), (ins pclabel:$cp), 0, NoItinerary, []> { 5280 let isTerminator = 1; 5281 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB]; 5282 let hasNoSchedulingInfo = 1; 5283} 5284 5285def t2BFi : t2BF<(ins bflabel_u4:$b_label, bflabel_s16:$label, pred:$p), 5286 !strconcat("bf", "${p}"), "$b_label, $label"> { 5287 bits<4> b_label; 5288 bits<16> label; 5289 5290 let Inst{26-23} = b_label{3-0}; 5291 let Inst{22-21} = 0b10; 5292 let Inst{20-16} = label{15-11}; 5293 let Inst{13} = 0b1; 5294 let Inst{11} = label{0}; 5295 let Inst{10-1} = label{10-1}; 5296} 5297 5298def t2BFic : t2BF<(ins bflabel_u4:$b_label, bflabel_s12:$label, 5299 bfafter_target:$ba_label, pred_noal:$bcond), "bfcsel", 5300 "$b_label, $label, $ba_label, $bcond"> { 5301 bits<4> bcond; 5302 bits<12> label; 5303 bits<1> ba_label; 5304 bits<4> b_label; 5305 5306 let Inst{26-23} = b_label{3-0}; 5307 let Inst{22} = 0b0; 5308 let Inst{21-18} = bcond{3-0}; 5309 let Inst{17} = ba_label{0}; 5310 let Inst{16} = label{11}; 5311 let Inst{13} = 0b1; 5312 let Inst{11} = label{0}; 5313 let Inst{10-1} = label{10-1}; 5314} 5315 5316def t2BFr : t2BF<(ins bflabel_u4:$b_label, rGPR:$Rn, pred:$p), 5317 !strconcat("bfx", "${p}"), "$b_label, $Rn"> { 5318 bits<4> b_label; 5319 bits<4> Rn; 5320 5321 let Inst{26-23} = b_label{3-0}; 5322 let Inst{22-20} = 0b110; 5323 let Inst{19-16} = Rn{3-0}; 5324 let Inst{13-1} = 0b1000000000000; 5325} 5326 5327def t2BFLi : t2BF<(ins bflabel_u4:$b_label, bflabel_s18:$label, pred:$p), 5328 !strconcat("bfl", "${p}"), "$b_label, $label"> { 5329 bits<4> b_label; 5330 bits<18> label; 5331 5332 let Inst{26-23} = b_label{3-0}; 5333 let Inst{22-16} = label{17-11}; 5334 let Inst{13} = 0b0; 5335 let Inst{11} = label{0}; 5336 let Inst{10-1} = label{10-1}; 5337} 5338 5339def t2BFLr : t2BF<(ins bflabel_u4:$b_label, rGPR:$Rn, pred:$p), 5340 !strconcat("bflx", "${p}"), "$b_label, $Rn"> { 5341 bits<4> b_label; 5342 bits<4> Rn; 5343 5344 let Inst{26-23} = b_label{3-0}; 5345 let Inst{22-20} = 0b111; 5346 let Inst{19-16} = Rn{3-0}; 5347 let Inst{13-1} = 0b1000000000000; 5348} 5349 5350class t2LOL<dag oops, dag iops, string asm, string ops> 5351 : V8_1MI<oops, iops, AddrModeNone, NoItinerary, asm, ops, "", [] > { 5352 let Inst{31-23} = 0b111100000; 5353 let Inst{15-14} = 0b11; 5354 let Inst{0} = 0b1; 5355 let DecoderMethod = "DecodeLOLoop"; 5356 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB]; 5357} 5358 5359let isNotDuplicable = 1 in { 5360def t2WLS : t2LOL<(outs GPRlr:$LR), 5361 (ins rGPR:$Rn, wlslabel_u11:$label), 5362 "wls", "$LR, $Rn, $label"> { 5363 bits<4> Rn; 5364 bits<11> label; 5365 let Inst{22-20} = 0b100; 5366 let Inst{19-16} = Rn{3-0}; 5367 let Inst{13-12} = 0b00; 5368 let Inst{11} = label{0}; 5369 let Inst{10-1} = label{10-1}; 5370 let usesCustomInserter = 1; 5371 let isBranch = 1; 5372 let isTerminator = 1; 5373} 5374 5375def t2DLS : t2LOL<(outs GPRlr:$LR), (ins rGPR:$Rn), 5376 "dls", "$LR, $Rn"> { 5377 bits<4> Rn; 5378 let Inst{22-20} = 0b100; 5379 let Inst{19-16} = Rn{3-0}; 5380 let Inst{13-1} = 0b1000000000000; 5381 let usesCustomInserter = 1; 5382} 5383 5384def t2LEUpdate : t2LOL<(outs GPRlr:$LRout), 5385 (ins GPRlr:$LRin, lelabel_u11:$label), 5386 "le", "$LRin, $label"> { 5387 bits<11> label; 5388 let Inst{22-16} = 0b0001111; 5389 let Inst{13-12} = 0b00; 5390 let Inst{11} = label{0}; 5391 let Inst{10-1} = label{10-1}; 5392 let usesCustomInserter = 1; 5393 let isBranch = 1; 5394 let isTerminator = 1; 5395} 5396 5397def t2LE : t2LOL<(outs ), (ins lelabel_u11:$label), "le", "$label"> { 5398 bits<11> label; 5399 let Inst{22-16} = 0b0101111; 5400 let Inst{13-12} = 0b00; 5401 let Inst{11} = label{0}; 5402 let Inst{10-1} = label{10-1}; 5403 let isBranch = 1; 5404 let isTerminator = 1; 5405} 5406 5407def t2DoLoopStart : 5408 t2PseudoInst<(outs), (ins rGPR:$elts), 4, IIC_Br, 5409 [(int_set_loop_iterations rGPR:$elts)]>, Sched<[WriteBr]>; 5410 5411let hasSideEffects = 0 in 5412def t2LoopDec : 5413 t2PseudoInst<(outs GPRlr:$Rm), (ins GPRlr:$Rn, imm0_7:$size), 5414 4, IIC_Br, []>, Sched<[WriteBr]>; 5415 5416let isBranch = 1, isTerminator = 1, hasSideEffects = 1, Defs = [CPSR] in { 5417// Set WhileLoopStart and LoopEnd to occupy 8 bytes because they may 5418// get converted into t2CMP and t2Bcc. 5419def t2WhileLoopStart : 5420 t2PseudoInst<(outs), 5421 (ins rGPR:$elts, brtarget:$target), 5422 8, IIC_Br, []>, 5423 Sched<[WriteBr]>; 5424 5425def t2LoopEnd : 5426 t2PseudoInst<(outs), (ins GPRlr:$elts, brtarget:$target), 5427 8, IIC_Br, []>, Sched<[WriteBr]>; 5428 5429} // end isBranch, isTerminator, hasSideEffects 5430 5431} // end isNotDuplicable 5432 5433class CS<string iname, bits<4> opcode, list<dag> pattern=[]> 5434 : V8_1MI<(outs rGPR:$Rd), (ins GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rm, pred_noal:$fcond), 5435 AddrModeNone, NoItinerary, iname, "$Rd, $Rn, $Rm, $fcond", "", pattern> { 5436 bits<4> Rd; 5437 bits<4> Rm; 5438 bits<4> Rn; 5439 bits<4> fcond; 5440 5441 let Inst{31-20} = 0b111010100101; 5442 let Inst{19-16} = Rn{3-0}; 5443 let Inst{15-12} = opcode; 5444 let Inst{11-8} = Rd{3-0}; 5445 let Inst{7-4} = fcond{3-0}; 5446 let Inst{3-0} = Rm{3-0}; 5447 5448 let Uses = [CPSR]; 5449} 5450 5451def t2CSEL : CS<"csel", 0b1000>; 5452def t2CSINC : CS<"csinc", 0b1001>; 5453def t2CSINV : CS<"csinv", 0b1010>; 5454def t2CSNEG : CS<"csneg", 0b1011>; 5455 5456let Predicates = [HasV8_1MMainline] in { 5457 def : T2Pat<(ARMcsinc GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm), 5458 (t2CSINC GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>; 5459 def : T2Pat<(ARMcsinv GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm), 5460 (t2CSINV GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>; 5461 def : T2Pat<(ARMcsneg GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm), 5462 (t2CSNEG GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>; 5463 5464 multiclass ModifiedV8_1CSEL<Instruction Insn, dag modvalue> { 5465 def : T2Pat<(ARMcmov modvalue, GPRwithZR:$tval, cmovpred:$imm), 5466 (Insn GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>; 5467 def : T2Pat<(ARMcmov GPRwithZR:$tval, modvalue, cmovpred:$imm), 5468 (Insn GPRwithZR:$tval, GPRwithZR:$fval, 5469 (i32 (inv_cond_XFORM imm:$imm)))>; 5470 } 5471 defm : ModifiedV8_1CSEL<t2CSINC, (add rGPR:$fval, 1)>; 5472 defm : ModifiedV8_1CSEL<t2CSINV, (xor rGPR:$fval, -1)>; 5473 defm : ModifiedV8_1CSEL<t2CSNEG, (sub 0, rGPR:$fval)>; 5474} 5475 5476// CS aliases. 5477let Predicates = [HasV8_1MMainline] in { 5478 def : InstAlias<"csetm\t$Rd, $fcond", 5479 (t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>; 5480 5481 def : InstAlias<"cset\t$Rd, $fcond", 5482 (t2CSINC rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>; 5483 5484 def : InstAlias<"cinc\t$Rd, $Rn, $fcond", 5485 (t2CSINC rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>; 5486 5487 def : InstAlias<"cinv\t$Rd, $Rn, $fcond", 5488 (t2CSINV rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>; 5489 5490 def : InstAlias<"cneg\t$Rd, $Rn, $fcond", 5491 (t2CSNEG rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>; 5492} 5493