1//===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the Thumb instruction set. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Thumb specific DAG Nodes. 15// 16 17def ARMtsecall : SDNode<"ARMISD::tSECALL", SDT_ARMcall, 18 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 19 SDNPVariadic]>; 20 21def imm_sr_XFORM: SDNodeXForm<imm, [{ 22 unsigned Imm = N->getZExtValue(); 23 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32); 24}]>; 25def ThumbSRImmAsmOperand: ImmAsmOperand<1,32> { let Name = "ImmThumbSR"; } 26def imm_sr : Operand<i32>, PatLeaf<(imm), [{ 27 uint64_t Imm = N->getZExtValue(); 28 return Imm > 0 && Imm <= 32; 29}], imm_sr_XFORM> { 30 let PrintMethod = "printThumbSRImm"; 31 let ParserMatchClass = ThumbSRImmAsmOperand; 32} 33 34def imm0_7_neg : PatLeaf<(i32 imm), [{ 35 return (uint32_t)-N->getZExtValue() < 8; 36}], imm_neg_XFORM>; 37 38def ThumbModImmNeg1_7AsmOperand : AsmOperandClass { let Name = "ThumbModImmNeg1_7"; } 39def mod_imm1_7_neg : Operand<i32>, PatLeaf<(imm), [{ 40 unsigned Value = -(unsigned)N->getZExtValue(); 41 return 0 < Value && Value < 8; 42 }], imm_neg_XFORM> { 43 let ParserMatchClass = ThumbModImmNeg1_7AsmOperand; 44} 45 46def ThumbModImmNeg8_255AsmOperand : AsmOperandClass { let Name = "ThumbModImmNeg8_255"; } 47def mod_imm8_255_neg : Operand<i32>, PatLeaf<(imm), [{ 48 unsigned Value = -(unsigned)N->getZExtValue(); 49 return 7 < Value && Value < 256; 50 }], imm_neg_XFORM> { 51 let ParserMatchClass = ThumbModImmNeg8_255AsmOperand; 52} 53 54 55def imm0_255_comp : PatLeaf<(i32 imm), [{ 56 return ~((uint32_t)N->getZExtValue()) < 256; 57}]>; 58 59def imm8_255_neg : PatLeaf<(i32 imm), [{ 60 unsigned Val = -N->getZExtValue(); 61 return Val >= 8 && Val < 256; 62}], imm_neg_XFORM>; 63 64// Break imm's up into two pieces: an immediate + a left shift. This uses 65// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt 66// to get the val/shift pieces. 67def thumb_immshifted : PatLeaf<(imm), [{ 68 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 69}]>; 70 71def thumb_immshifted_val : SDNodeXForm<imm, [{ 72 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 73 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32); 74}]>; 75 76def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 77 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 78 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32); 79}]>; 80 81def imm256_510 : ImmLeaf<i32, [{ 82 return Imm >= 256 && Imm < 511; 83}]>; 84 85def thumb_imm256_510_addend : SDNodeXForm<imm, [{ 86 return CurDAG->getTargetConstant(N->getZExtValue() - 255, SDLoc(N), MVT::i32); 87}]>; 88 89// Scaled 4 immediate. 90def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; } 91def t_imm0_1020s4 : Operand<i32> { 92 let PrintMethod = "printThumbS4ImmOperand"; 93 let ParserMatchClass = t_imm0_1020s4_asmoperand; 94 let OperandType = "OPERAND_IMMEDIATE"; 95} 96 97def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; } 98def t_imm0_508s4 : Operand<i32> { 99 let PrintMethod = "printThumbS4ImmOperand"; 100 let ParserMatchClass = t_imm0_508s4_asmoperand; 101 let OperandType = "OPERAND_IMMEDIATE"; 102} 103// Alias use only, so no printer is necessary. 104def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; } 105def t_imm0_508s4_neg : Operand<i32> { 106 let ParserMatchClass = t_imm0_508s4_neg_asmoperand; 107 let OperandType = "OPERAND_IMMEDIATE"; 108} 109 110// Define Thumb specific addressing modes. 111 112// unsigned 8-bit, 2-scaled memory offset 113class OperandUnsignedOffset_b8s2 : AsmOperandClass { 114 let Name = "UnsignedOffset_b8s2"; 115 let PredicateMethod = "isUnsignedOffset<8, 2>"; 116} 117 118def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2; 119 120// thumb style PC relative operand. signed, 8 bits magnitude, 121// two bits shift. can be represented as either [pc, #imm], #imm, 122// or relocatable expression... 123def ThumbMemPC : AsmOperandClass { 124 let Name = "ThumbMemPC"; 125} 126 127let OperandType = "OPERAND_PCREL" in { 128def t_brtarget : Operand<OtherVT> { 129 let EncoderMethod = "getThumbBRTargetOpValue"; 130 let DecoderMethod = "DecodeThumbBROperand"; 131} 132 133// ADR instruction labels. 134def t_adrlabel : Operand<i32> { 135 let EncoderMethod = "getThumbAdrLabelOpValue"; 136 let PrintMethod = "printAdrLabelOperand<2>"; 137 let ParserMatchClass = UnsignedOffset_b8s2; 138} 139 140 141def thumb_br_target : Operand<OtherVT> { 142 let ParserMatchClass = ThumbBranchTarget; 143 let EncoderMethod = "getThumbBranchTargetOpValue"; 144 let OperandType = "OPERAND_PCREL"; 145} 146 147def thumb_bl_target : Operand<i32> { 148 let ParserMatchClass = ThumbBranchTarget; 149 let EncoderMethod = "getThumbBLTargetOpValue"; 150 let DecoderMethod = "DecodeThumbBLTargetOperand"; 151} 152 153// Target for BLX *from* thumb mode. 154def thumb_blx_target : Operand<i32> { 155 let ParserMatchClass = ARMBranchTarget; 156 let EncoderMethod = "getThumbBLXTargetOpValue"; 157 let DecoderMethod = "DecodeThumbBLXOffset"; 158} 159 160def thumb_bcc_target : Operand<OtherVT> { 161 let ParserMatchClass = ThumbBranchTarget; 162 let EncoderMethod = "getThumbBCCTargetOpValue"; 163 let DecoderMethod = "DecodeThumbBCCTargetOperand"; 164} 165 166def thumb_cb_target : Operand<OtherVT> { 167 let ParserMatchClass = ThumbBranchTarget; 168 let EncoderMethod = "getThumbCBTargetOpValue"; 169 let DecoderMethod = "DecodeThumbCmpBROperand"; 170} 171 172// t_addrmode_pc := <label> => pc + imm8 * 4 173// 174def t_addrmode_pc : MemOperand { 175 let EncoderMethod = "getAddrModePCOpValue"; 176 let DecoderMethod = "DecodeThumbAddrModePC"; 177 let PrintMethod = "printThumbLdrLabelOperand"; 178 let ParserMatchClass = ThumbMemPC; 179} 180} 181 182// t_addrmode_rr := reg + reg 183// 184def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; } 185def t_addrmode_rr : MemOperand, 186 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 187 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 188 let PrintMethod = "printThumbAddrModeRROperand"; 189 let DecoderMethod = "DecodeThumbAddrModeRR"; 190 let ParserMatchClass = t_addrmode_rr_asm_operand; 191 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 192} 193 194// t_addrmode_rr_sext := reg + reg 195// 196// This is similar to t_addrmode_rr, but uses different heuristics for 197// ldrsb/ldrsh. 198def t_addrmode_rr_sext : MemOperand, 199 ComplexPattern<i32, 2, "SelectThumbAddrModeRRSext", []> { 200 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 201 let PrintMethod = "printThumbAddrModeRROperand"; 202 let DecoderMethod = "DecodeThumbAddrModeRR"; 203 let ParserMatchClass = t_addrmode_rr_asm_operand; 204 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 205} 206 207// t_addrmode_rrs := reg + reg 208// 209// We use separate scaled versions because the Select* functions need 210// to explicitly check for a matching constant and return false here so that 211// the reg+imm forms will match instead. This is a horrible way to do that, 212// as it forces tight coupling between the methods, but it's how selectiondag 213// currently works. 214def t_addrmode_rrs1 : MemOperand, 215 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { 216 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 217 let PrintMethod = "printThumbAddrModeRROperand"; 218 let DecoderMethod = "DecodeThumbAddrModeRR"; 219 let ParserMatchClass = t_addrmode_rr_asm_operand; 220 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 221} 222def t_addrmode_rrs2 : MemOperand, 223 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> { 224 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 225 let DecoderMethod = "DecodeThumbAddrModeRR"; 226 let PrintMethod = "printThumbAddrModeRROperand"; 227 let ParserMatchClass = t_addrmode_rr_asm_operand; 228 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 229} 230def t_addrmode_rrs4 : MemOperand, 231 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> { 232 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 233 let DecoderMethod = "DecodeThumbAddrModeRR"; 234 let PrintMethod = "printThumbAddrModeRROperand"; 235 let ParserMatchClass = t_addrmode_rr_asm_operand; 236 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 237} 238 239// t_addrmode_is4 := reg + imm5 * 4 240// 241def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; } 242def t_addrmode_is4 : MemOperand, 243 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> { 244 let EncoderMethod = "getAddrModeISOpValue"; 245 let DecoderMethod = "DecodeThumbAddrModeIS"; 246 let PrintMethod = "printThumbAddrModeImm5S4Operand"; 247 let ParserMatchClass = t_addrmode_is4_asm_operand; 248 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 249} 250 251// t_addrmode_is2 := reg + imm5 * 2 252// 253def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; } 254def t_addrmode_is2 : MemOperand, 255 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> { 256 let EncoderMethod = "getAddrModeISOpValue"; 257 let DecoderMethod = "DecodeThumbAddrModeIS"; 258 let PrintMethod = "printThumbAddrModeImm5S2Operand"; 259 let ParserMatchClass = t_addrmode_is2_asm_operand; 260 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 261} 262 263// t_addrmode_is1 := reg + imm5 264// 265def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; } 266def t_addrmode_is1 : MemOperand, 267 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { 268 let EncoderMethod = "getAddrModeISOpValue"; 269 let DecoderMethod = "DecodeThumbAddrModeIS"; 270 let PrintMethod = "printThumbAddrModeImm5S1Operand"; 271 let ParserMatchClass = t_addrmode_is1_asm_operand; 272 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 273} 274 275// t_addrmode_sp := sp + imm8 * 4 276// 277// FIXME: This really shouldn't have an explicit SP operand at all. It should 278// be implicit, just like in the instruction encoding itself. 279def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; } 280def t_addrmode_sp : MemOperand, 281 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 282 let EncoderMethod = "getAddrModeThumbSPOpValue"; 283 let DecoderMethod = "DecodeThumbAddrModeSP"; 284 let PrintMethod = "printThumbAddrModeSPOperand"; 285 let ParserMatchClass = t_addrmode_sp_asm_operand; 286 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 287} 288 289// Inspects parent to determine whether an or instruction can be implemented as 290// an add (i.e. whether we know overflow won't occur in the add). 291def AddLikeOrOp : ComplexPattern<i32, 1, "SelectAddLikeOr", [], 292 [SDNPWantParent]>; 293 294// Pattern to exclude immediates from matching 295def non_imm32 : PatLeaf<(i32 GPR), [{ return !isa<ConstantSDNode>(N); }]>; 296 297//===----------------------------------------------------------------------===// 298// Miscellaneous Instructions. 299// 300 301// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 302// from removing one half of the matched pairs. That breaks PEI, which assumes 303// these will always be in pairs, and asserts if it finds otherwise. Better way? 304let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 305def tADJCALLSTACKUP : 306 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 307 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, 308 Requires<[IsThumb, IsThumb1Only]>; 309 310def tADJCALLSTACKDOWN : 311 PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2), NoItinerary, 312 [(ARMcallseq_start imm:$amt, imm:$amt2)]>, 313 Requires<[IsThumb, IsThumb1Only]>; 314} 315 316class T1SystemEncoding<bits<8> opc> 317 : T1Encoding<0b101111> { 318 let Inst{9-8} = 0b11; 319 let Inst{7-0} = opc; 320} 321 322def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm", 323 [(int_arm_hint imm0_15:$imm)]>, 324 T1SystemEncoding<0x00>, 325 Requires<[IsThumb, HasV6M]> { 326 bits<4> imm; 327 let Inst{7-4} = imm; 328} 329 330// Note: When EmitPriority == 1, the alias will be used for printing 331class tHintAlias<string Asm, dag Result, bit EmitPriority = 0> : tInstAlias<Asm, Result, EmitPriority> { 332 let Predicates = [IsThumb, HasV6M]; 333} 334 335def : tHintAlias<"nop$p", (tHINT 0, pred:$p), 1>; // A8.6.110 336def : tHintAlias<"yield$p", (tHINT 1, pred:$p), 1>; // A8.6.410 337def : tHintAlias<"wfe$p", (tHINT 2, pred:$p), 1>; // A8.6.408 338def : tHintAlias<"wfi$p", (tHINT 3, pred:$p), 1>; // A8.6.409 339def : tHintAlias<"sev$p", (tHINT 4, pred:$p), 1>; // A8.6.157 340def : tInstAlias<"sevl$p", (tHINT 5, pred:$p), 1> { 341 let Predicates = [IsThumb2, HasV8]; 342} 343 344// The imm operand $val can be used by a debugger to store more information 345// about the breakpoint. 346def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val", 347 []>, 348 T1Encoding<0b101111> { 349 let Inst{9-8} = 0b10; 350 // A8.6.22 351 bits<8> val; 352 let Inst{7-0} = val; 353} 354// default immediate for breakpoint mnemonic 355def : InstAlias<"bkpt", (tBKPT 0), 0>, Requires<[IsThumb]>; 356 357def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val", 358 []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> { 359 let Inst{9-6} = 0b1010; 360 bits<6> val; 361 let Inst{5-0} = val; 362} 363 364def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", 365 []>, T1Encoding<0b101101>, Requires<[IsThumb, IsNotMClass]>, Deprecated<HasV8Ops> { 366 bits<1> end; 367 // A8.6.156 368 let Inst{9-5} = 0b10010; 369 let Inst{4} = 1; 370 let Inst{3} = end; 371 let Inst{2-0} = 0b000; 372} 373 374// Change Processor State is a system instruction -- for disassembly only. 375def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), 376 NoItinerary, "cps$imod $iflags", []>, 377 T1Misc<0b0110011> { 378 // A8.6.38 & B6.1.1 379 bit imod; 380 bits<3> iflags; 381 382 let Inst{4} = imod; 383 let Inst{3} = 0; 384 let Inst{2-0} = iflags; 385 let DecoderMethod = "DecodeThumbCPS"; 386} 387 388// For both thumb1 and thumb2. 389let isNotDuplicable = 1, isCodeGenOnly = 1 in 390def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "", 391 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 392 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 393 // A8.6.6 394 bits<3> dst; 395 let Inst{6-3} = 0b1111; // Rm = pc 396 let Inst{2-0} = dst; 397} 398 399// ADD <Rd>, sp, #<imm8> 400// FIXME: This should not be marked as having side effects, and it should be 401// rematerializable. Clearing the side effect bit causes miscompilations, 402// probably because the instruction can be moved around. 403def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm), 404 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>, 405 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> { 406 // A6.2 & A8.6.8 407 bits<3> dst; 408 bits<8> imm; 409 let Inst{10-8} = dst; 410 let Inst{7-0} = imm; 411 let DecoderMethod = "DecodeThumbAddSpecialReg"; 412} 413 414// Thumb1 frame lowering is rather fragile, we hope to be able to use 415// tADDrSPi, but we may need to insert a sequence that clobbers CPSR. 416def tADDframe : PseudoInst<(outs tGPR:$dst), (ins i32imm:$base, i32imm:$offset), 417 NoItinerary, []>, 418 Requires<[IsThumb, IsThumb1Only]> { 419 let Defs = [CPSR]; 420} 421 422// ADD sp, sp, #<imm7> 423def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 424 IIC_iALUi, "add", "\t$Rdn, $imm", []>, 425 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> { 426 // A6.2.5 & A8.6.8 427 bits<7> imm; 428 let Inst{6-0} = imm; 429 let DecoderMethod = "DecodeThumbAddSPImm"; 430} 431 432// SUB sp, sp, #<imm7> 433// FIXME: The encoding and the ASM string don't match up. 434def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 435 IIC_iALUi, "sub", "\t$Rdn, $imm", []>, 436 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> { 437 // A6.2.5 & A8.6.214 438 bits<7> imm; 439 let Inst{6-0} = imm; 440 let DecoderMethod = "DecodeThumbAddSPImm"; 441} 442 443def : tInstSubst<"add${p} sp, $imm", 444 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 445def : tInstSubst<"add${p} sp, sp, $imm", 446 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 447 448// Can optionally specify SP as a three operand instruction. 449def : tInstAlias<"add${p} sp, sp, $imm", 450 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; 451def : tInstAlias<"sub${p} sp, sp, $imm", 452 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>; 453 454// ADD <Rm>, sp 455def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr, 456 "add", "\t$Rdn, $sp, $Rn", []>, 457 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 458 // A8.6.9 Encoding T1 459 bits<4> Rdn; 460 let Inst{7} = Rdn{3}; 461 let Inst{6-3} = 0b1101; 462 let Inst{2-0} = Rdn{2-0}; 463 let DecoderMethod = "DecodeThumbAddSPReg"; 464} 465 466// ADD sp, <Rm> 467def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr, 468 "add", "\t$Rdn, $Rm", []>, 469 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 470 // A8.6.9 Encoding T2 471 bits<4> Rm; 472 let Inst{7} = 1; 473 let Inst{6-3} = Rm; 474 let Inst{2-0} = 0b101; 475 let DecoderMethod = "DecodeThumbAddSPReg"; 476} 477 478//===----------------------------------------------------------------------===// 479// Control Flow Instructions. 480// 481 482// Indirect branches 483let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 484 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, 485 T1Special<{1,1,0,?}>, Sched<[WriteBr]> { 486 // A6.2.3 & A8.6.25 487 bits<4> Rm; 488 let Inst{6-3} = Rm; 489 let Inst{2-0} = 0b000; 490 let Unpredictable{2-0} = 0b111; 491 } 492 def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>, 493 Requires<[IsThumb, Has8MSecExt]>, 494 T1Special<{1,1,0,?}>, Sched<[WriteBr]> { 495 bits<4> Rm; 496 let Inst{6-3} = Rm; 497 let Inst{2-0} = 0b100; 498 let Unpredictable{1-0} = 0b11; 499 } 500} 501 502let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 503 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br, 504 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>; 505 506 // alternative return for CMSE entry functions 507 def tBXNS_RET : tPseudoInst<(outs), (ins), 2, IIC_Br, 508 [(ARMseretflag)]>, Sched<[WriteBr]>; 509 510 // Alternative return instruction used by vararg functions. 511 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), 512 2, IIC_Br, [], 513 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 514} 515 516// All calls clobber the non-callee saved registers. SP is marked as a use to 517// prevent stack-pointer assignments that appear immediately before calls from 518// potentially appearing dead. 519let isCall = 1, 520 Defs = [LR], Uses = [SP] in { 521 // Also used for Thumb2 522 def tBL : TIx2<0b11110, 0b11, 1, 523 (outs), (ins pred:$p, thumb_bl_target:$func), IIC_Br, 524 "bl${p}\t$func", 525 [(ARMcall tglobaladdr:$func)]>, 526 Requires<[IsThumb]>, Sched<[WriteBrL]> { 527 bits<24> func; 528 let Inst{26} = func{23}; 529 let Inst{25-16} = func{20-11}; 530 let Inst{13} = func{22}; 531 let Inst{11} = func{21}; 532 let Inst{10-0} = func{10-0}; 533 } 534 535 // ARMv5T and above, also used for Thumb2 536 def tBLXi : TIx2<0b11110, 0b11, 0, 537 (outs), (ins pred:$p, thumb_blx_target:$func), IIC_Br, 538 "blx${p}\t$func", []>, 539 Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> { 540 bits<24> func; 541 let Inst{26} = func{23}; 542 let Inst{25-16} = func{20-11}; 543 let Inst{13} = func{22}; 544 let Inst{11} = func{21}; 545 let Inst{10-1} = func{10-1}; 546 let Inst{0} = 0; // func{0} is assumed zero 547 } 548 549 // Also used for Thumb2 550 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br, 551 "blx${p}\t$func", 552 [(ARMcall GPR:$func)]>, 553 Requires<[IsThumb, HasV5T]>, 554 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24; 555 bits<4> func; 556 let Inst{6-3} = func; 557 let Inst{2-0} = 0b000; 558 } 559 560 // ARMv8-M Security Extensions 561 def tBLXNSr : TI<(outs), (ins pred:$p, GPRnopc:$func), IIC_Br, 562 "blxns${p}\t$func", []>, 563 Requires<[IsThumb, Has8MSecExt]>, 564 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { 565 bits<4> func; 566 let Inst{6-3} = func; 567 let Inst{2-0} = 0b100; 568 let Unpredictable{1-0} = 0b11; 569 } 570 571 def tBLXNS_CALL : PseudoInst<(outs), (ins GPRnopc:$func), IIC_Br, 572 [(ARMtsecall GPRnopc:$func)]>, 573 Requires<[IsThumb, Has8MSecExt]>, Sched<[WriteBr]>; 574 575 // ARMv4T 576 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func), 577 4, IIC_Br, 578 [(ARMcall_nolink tGPR:$func)]>, 579 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>; 580 581 // Also used for Thumb2 582 // push lr before the call 583 def tBL_PUSHLR : tPseudoInst<(outs), (ins GPRlr:$ra, pred:$p, thumb_bl_target:$func), 584 4, IIC_Br, 585 []>, 586 Requires<[IsThumb]>, Sched<[WriteBr]>; 587} 588 589let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 590 let isPredicable = 1 in 591 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br, 592 "b", "\t$target", [(br bb:$target)]>, 593 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> { 594 bits<11> target; 595 let Inst{10-0} = target; 596 let AsmMatchConverter = "cvtThumbBranches"; 597 } 598 599 // Far jump 600 // Just a pseudo for a tBL instruction. Needed to let regalloc know about 601 // the clobber of LR. 602 let Defs = [LR] in 603 def tBfar : tPseudoExpand<(outs), (ins thumb_bl_target:$target, pred:$p), 604 4, IIC_Br, [], 605 (tBL pred:$p, thumb_bl_target:$target)>, 606 Sched<[WriteBrTbl]>; 607 608 def tBR_JTr : tPseudoInst<(outs), 609 (ins tGPR:$target, i32imm:$jt), 610 0, IIC_Br, 611 [(ARMbrjt tGPR:$target, tjumptable:$jt)]>, 612 Sched<[WriteBrTbl]> { 613 let Size = 2; 614 let isNotDuplicable = 1; 615 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 616 } 617} 618 619// FIXME: should be able to write a pattern for ARMBrcond, but can't use 620// a two-value operand where a dag node expects two operands. :( 621let isBranch = 1, isTerminator = 1 in 622 def tBcc : T1I<(outs), (ins thumb_bcc_target:$target, pred:$p), IIC_Br, 623 "b${p}\t$target", 624 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 625 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> { 626 bits<4> p; 627 bits<8> target; 628 let Inst{11-8} = p; 629 let Inst{7-0} = target; 630 let AsmMatchConverter = "cvtThumbBranches"; 631} 632 633 634// Tail calls 635let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 636 // IOS versions. 637 let Uses = [SP] in { 638 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst), 639 4, IIC_Br, [], 640 (tBX GPR:$dst, (ops 14, zero_reg))>, 641 Requires<[IsThumb]>, Sched<[WriteBr]>; 642 } 643 // tTAILJMPd: MachO version uses a Thumb2 branch (no Thumb1 tail calls 644 // on MachO), so it's in ARMInstrThumb2.td. 645 // Non-MachO version: 646 let Uses = [SP] in { 647 def tTAILJMPdND : tPseudoExpand<(outs), 648 (ins t_brtarget:$dst, pred:$p), 649 4, IIC_Br, [], 650 (tB t_brtarget:$dst, pred:$p)>, 651 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>; 652 } 653} 654 655 656// A8.6.218 Supervisor Call (Software Interrupt) 657// A8.6.16 B: Encoding T1 658// If Inst{11-8} == 0b1111 then SEE SVC 659let isCall = 1, Uses = [SP] in 660def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br, 661 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> { 662 bits<8> imm; 663 let Inst{15-12} = 0b1101; 664 let Inst{11-8} = 0b1111; 665 let Inst{7-0} = imm; 666} 667 668// The assembler uses 0xDEFE for a trap instruction. 669let isBarrier = 1, isTerminator = 1 in 670def tTRAP : TI<(outs), (ins), IIC_Br, 671 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> { 672 let Inst = 0xdefe; 673} 674 675//===----------------------------------------------------------------------===// 676// Load Store Instructions. 677// 678 679// PC-relative loads need to be matched first as constant pool accesses need to 680// always be PC-relative. We do this using AddedComplexity, as the pattern is 681// simpler than the patterns of the other load instructions. 682let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 10 in 683def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 684 "ldr", "\t$Rt, $addr", 685 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>, 686 T1Encoding<{0,1,0,0,1,?}>, Sched<[WriteLd]> { 687 // A6.2 & A8.6.59 688 bits<3> Rt; 689 bits<8> addr; 690 let Inst{10-8} = Rt; 691 let Inst{7-0} = addr; 692} 693 694// SP-relative loads should be matched before standard immediate-offset loads as 695// it means we avoid having to move SP to another register. 696let canFoldAsLoad = 1 in 697def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 698 "ldr", "\t$Rt, $addr", 699 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>, 700 T1LdStSP<{1,?,?}>, Sched<[WriteLd]> { 701 bits<3> Rt; 702 bits<8> addr; 703 let Inst{10-8} = Rt; 704 let Inst{7-0} = addr; 705} 706 707// Loads: reg/reg and reg/imm5 708let canFoldAsLoad = 1, isReMaterializable = 1 in 709multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 710 Operand AddrMode_r, Operand AddrMode_i, 711 AddrMode am, InstrItinClass itin_r, 712 InstrItinClass itin_i, string asm, 713 PatFrag opnode> { 714 // Immediate-offset loads should be matched before register-offset loads as 715 // when the offset is a constant it's simpler to first check if it fits in the 716 // immediate offset field then fall back to register-offset if it doesn't. 717 def i : // reg/imm5 718 T1pILdStEncodeImm<imm_opc, 1 /* Load */, 719 (outs tGPR:$Rt), (ins AddrMode_i:$addr), 720 am, itin_i, asm, "\t$Rt, $addr", 721 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>; 722 // Register-offset loads are matched last. 723 def r : // reg/reg 724 T1pILdStEncode<reg_opc, 725 (outs tGPR:$Rt), (ins AddrMode_r:$addr), 726 am, itin_r, asm, "\t$Rt, $addr", 727 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>; 728} 729// Stores: reg/reg and reg/imm5 730multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 731 Operand AddrMode_r, Operand AddrMode_i, 732 AddrMode am, InstrItinClass itin_r, 733 InstrItinClass itin_i, string asm, 734 PatFrag opnode> { 735 def i : // reg/imm5 736 T1pILdStEncodeImm<imm_opc, 0 /* Store */, 737 (outs), (ins tGPR:$Rt, AddrMode_i:$addr), 738 am, itin_i, asm, "\t$Rt, $addr", 739 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>; 740 def r : // reg/reg 741 T1pILdStEncode<reg_opc, 742 (outs), (ins tGPR:$Rt, AddrMode_r:$addr), 743 am, itin_r, asm, "\t$Rt, $addr", 744 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>; 745} 746 747// A8.6.57 & A8.6.60 748defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rr, 749 t_addrmode_is4, AddrModeT1_4, 750 IIC_iLoad_r, IIC_iLoad_i, "ldr", 751 load>, Sched<[WriteLd]>; 752 753// A8.6.64 & A8.6.61 754defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rr, 755 t_addrmode_is1, AddrModeT1_1, 756 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb", 757 zextloadi8>, Sched<[WriteLd]>; 758 759// A8.6.76 & A8.6.73 760defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rr, 761 t_addrmode_is2, AddrModeT1_2, 762 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh", 763 zextloadi16>, Sched<[WriteLd]>; 764 765let AddedComplexity = 10 in 766def tLDRSB : // A8.6.80 767 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr_sext:$addr), 768 AddrModeT1_1, IIC_iLoad_bh_r, 769 "ldrsb", "\t$Rt, $addr", 770 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr_sext:$addr))]>, Sched<[WriteLd]>; 771 772let AddedComplexity = 10 in 773def tLDRSH : // A8.6.84 774 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr_sext:$addr), 775 AddrModeT1_2, IIC_iLoad_bh_r, 776 "ldrsh", "\t$Rt, $addr", 777 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr_sext:$addr))]>, Sched<[WriteLd]>; 778 779 780def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, 781 "str", "\t$Rt, $addr", 782 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>, 783 T1LdStSP<{0,?,?}>, Sched<[WriteST]> { 784 bits<3> Rt; 785 bits<8> addr; 786 let Inst{10-8} = Rt; 787 let Inst{7-0} = addr; 788} 789 790// A8.6.194 & A8.6.192 791defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rr, 792 t_addrmode_is4, AddrModeT1_4, 793 IIC_iStore_r, IIC_iStore_i, "str", 794 store>, Sched<[WriteST]>; 795 796// A8.6.197 & A8.6.195 797defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rr, 798 t_addrmode_is1, AddrModeT1_1, 799 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb", 800 truncstorei8>, Sched<[WriteST]>; 801 802// A8.6.207 & A8.6.205 803defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rr, 804 t_addrmode_is2, AddrModeT1_2, 805 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", 806 truncstorei16>, Sched<[WriteST]>; 807 808 809//===----------------------------------------------------------------------===// 810// Load / store multiple Instructions. 811// 812 813// These require base address to be written back or one of the loaded regs. 814let hasSideEffects = 0 in { 815 816let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in 817def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 818 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> { 819 bits<3> Rn; 820 bits<8> regs; 821 let Inst{10-8} = Rn; 822 let Inst{7-0} = regs; 823} 824 825// Writeback version is just a pseudo, as there's no encoding difference. 826// Writeback happens iff the base register is not in the destination register 827// list. 828let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 829def tLDMIA_UPD : 830 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 831 "$Rn = $wb", IIC_iLoad_mu>, 832 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> { 833 let Size = 2; 834 let OutOperandList = (outs tGPR:$wb); 835 let InOperandList = (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops); 836 let Pattern = []; 837 let isCodeGenOnly = 1; 838 let isPseudo = 1; 839 list<Predicate> Predicates = [IsThumb]; 840} 841 842// There is no non-writeback version of STM for Thumb. 843let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 844def tSTMIA_UPD : Thumb1I<(outs tGPR:$wb), 845 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 846 AddrModeNone, 2, IIC_iStore_mu, 847 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>, 848 T1Encoding<{1,1,0,0,0,?}> { 849 bits<3> Rn; 850 bits<8> regs; 851 let Inst{10-8} = Rn; 852 let Inst{7-0} = regs; 853} 854 855} // hasSideEffects 856 857def : InstAlias<"ldm${p} $Rn!, $regs", 858 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>, 859 Requires<[IsThumb, IsThumb1Only]>; 860 861let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1, 862 variadicOpsAreDefs = 1 in 863def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 864 IIC_iPop, 865 "pop${p}\t$regs", []>, 866 T1Misc<{1,1,0,?,?,?,?}>, Sched<[WriteLd]> { 867 bits<16> regs; 868 let Inst{8} = regs{15}; 869 let Inst{7-0} = regs{7-0}; 870} 871 872let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 873def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 874 IIC_iStore_m, 875 "push${p}\t$regs", []>, 876 T1Misc<{0,1,0,?,?,?,?}>, Sched<[WriteST]> { 877 bits<16> regs; 878 let Inst{8} = regs{14}; 879 let Inst{7-0} = regs{7-0}; 880} 881 882//===----------------------------------------------------------------------===// 883// Arithmetic Instructions. 884// 885 886// Helper classes for encoding T1pI patterns: 887class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 888 string opc, string asm, list<dag> pattern> 889 : T1pI<oops, iops, itin, opc, asm, pattern>, 890 T1DataProcessing<opA> { 891 bits<3> Rm; 892 bits<3> Rn; 893 let Inst{5-3} = Rm; 894 let Inst{2-0} = Rn; 895} 896class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin, 897 string opc, string asm, list<dag> pattern> 898 : T1pI<oops, iops, itin, opc, asm, pattern>, 899 T1Misc<opA> { 900 bits<3> Rm; 901 bits<3> Rd; 902 let Inst{5-3} = Rm; 903 let Inst{2-0} = Rd; 904} 905 906// Helper classes for encoding T1sI patterns: 907class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 908 string opc, string asm, list<dag> pattern> 909 : T1sI<oops, iops, itin, opc, asm, pattern>, 910 T1DataProcessing<opA> { 911 bits<3> Rd; 912 bits<3> Rn; 913 let Inst{5-3} = Rn; 914 let Inst{2-0} = Rd; 915} 916class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 917 string opc, string asm, list<dag> pattern> 918 : T1sI<oops, iops, itin, opc, asm, pattern>, 919 T1General<opA> { 920 bits<3> Rm; 921 bits<3> Rn; 922 bits<3> Rd; 923 let Inst{8-6} = Rm; 924 let Inst{5-3} = Rn; 925 let Inst{2-0} = Rd; 926} 927class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 928 string opc, string asm, list<dag> pattern> 929 : T1sI<oops, iops, itin, opc, asm, pattern>, 930 T1General<opA> { 931 bits<3> Rd; 932 bits<3> Rm; 933 let Inst{5-3} = Rm; 934 let Inst{2-0} = Rd; 935} 936 937// Helper classes for encoding T1sIt patterns: 938class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 939 string opc, string asm, list<dag> pattern> 940 : T1sIt<oops, iops, itin, opc, asm, pattern>, 941 T1DataProcessing<opA> { 942 bits<3> Rdn; 943 bits<3> Rm; 944 let Inst{5-3} = Rm; 945 let Inst{2-0} = Rdn; 946} 947class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 948 string opc, string asm, list<dag> pattern> 949 : T1sIt<oops, iops, itin, opc, asm, pattern>, 950 T1General<opA> { 951 bits<3> Rdn; 952 bits<8> imm8; 953 let Inst{10-8} = Rdn; 954 let Inst{7-0} = imm8; 955} 956 957let isAdd = 1 in { 958 // Add with carry register 959 let isCommutable = 1, Uses = [CPSR] in 960 def tADC : // A8.6.2 961 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr, 962 "adc", "\t$Rdn, $Rm", 963 []>, Sched<[WriteALU]>; 964 965 // Add immediate 966 def tADDi3 : // A8.6.4 T1 967 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 968 IIC_iALUi, 969 "add", "\t$Rd, $Rm, $imm3", 970 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>, 971 Sched<[WriteALU]> { 972 bits<3> imm3; 973 let Inst{8-6} = imm3; 974 } 975 976 def tADDi8 : // A8.6.4 T2 977 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), 978 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 979 "add", "\t$Rdn, $imm8", 980 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>, 981 Sched<[WriteALU]>; 982 983 // Add register 984 let isCommutable = 1 in 985 def tADDrr : // A8.6.6 T1 986 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 987 IIC_iALUr, 988 "add", "\t$Rd, $Rn, $Rm", 989 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 990 991 /// Similar to the above except these set the 's' bit so the 992 /// instruction modifies the CPSR register. 993 /// 994 /// These opcodes will be converted to the real non-S opcodes by 995 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand. 996 let hasPostISelHook = 1, Defs = [CPSR] in { 997 let isCommutable = 1, Uses = [CPSR] in 998 def tADCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 999 2, IIC_iALUr, 1000 [(set tGPR:$Rdn, CPSR, (ARMadde tGPR:$Rn, tGPR:$Rm, 1001 CPSR))]>, 1002 Requires<[IsThumb1Only]>, 1003 Sched<[WriteALU]>; 1004 1005 def tADDSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 1006 2, IIC_iALUi, 1007 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rm, 1008 imm0_7:$imm3))]>, 1009 Requires<[IsThumb1Only]>, 1010 Sched<[WriteALU]>; 1011 1012 def tADDSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8), 1013 2, IIC_iALUi, 1014 [(set tGPR:$Rdn, CPSR, (ARMaddc tGPR:$Rn, 1015 imm8_255:$imm8))]>, 1016 Requires<[IsThumb1Only]>, 1017 Sched<[WriteALU]>; 1018 1019 let isCommutable = 1 in 1020 def tADDSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1021 2, IIC_iALUr, 1022 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rn, 1023 tGPR:$Rm))]>, 1024 Requires<[IsThumb1Only]>, 1025 Sched<[WriteALU]>; 1026 } 1027 1028 let hasSideEffects = 0 in 1029 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, 1030 "add", "\t$Rdn, $Rm", []>, 1031 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 1032 // A8.6.6 T2 1033 bits<4> Rdn; 1034 bits<4> Rm; 1035 let Inst{7} = Rdn{3}; 1036 let Inst{6-3} = Rm; 1037 let Inst{2-0} = Rdn{2-0}; 1038 } 1039} 1040 1041// Thumb has more flexible short encodings for ADD than ORR, so use those where 1042// possible. 1043def : T1Pat<(or AddLikeOrOp:$Rn, imm0_7:$imm), (tADDi3 $Rn, imm0_7:$imm)>; 1044 1045def : T1Pat<(or AddLikeOrOp:$Rn, imm8_255:$imm), (tADDi8 $Rn, imm8_255:$imm)>; 1046 1047def : T1Pat<(or AddLikeOrOp:$Rn, tGPR:$Rm), (tADDrr $Rn, $Rm)>; 1048 1049 1050def : tInstAlias <"add${s}${p} $Rdn, $Rm", 1051 (tADDrr tGPR:$Rdn,s_cc_out:$s, tGPR:$Rdn, tGPR:$Rm, pred:$p)>; 1052 1053def : tInstSubst<"sub${s}${p} $rd, $rn, $imm", 1054 (tADDi3 tGPR:$rd, s_cc_out:$s, tGPR:$rn, mod_imm1_7_neg:$imm, pred:$p)>; 1055def : tInstSubst<"sub${s}${p} $rdn, $imm", 1056 (tADDi8 tGPR:$rdn, s_cc_out:$s, mod_imm8_255_neg:$imm, pred:$p)>; 1057 1058 1059// AND register 1060let isCommutable = 1 in 1061def tAND : // A8.6.12 1062 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1063 IIC_iBITr, 1064 "and", "\t$Rdn, $Rm", 1065 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1066 1067// ASR immediate 1068def tASRri : // A8.6.14 1069 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 1070 IIC_iMOVsi, 1071 "asr", "\t$Rd, $Rm, $imm5", 1072 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 1073 Sched<[WriteALU]> { 1074 bits<5> imm5; 1075 let Inst{10-6} = imm5; 1076} 1077 1078// ASR register 1079def tASRrr : // A8.6.15 1080 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1081 IIC_iMOVsr, 1082 "asr", "\t$Rdn, $Rm", 1083 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1084 1085// BIC register 1086def tBIC : // A8.6.20 1087 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1088 IIC_iBITr, 1089 "bic", "\t$Rdn, $Rm", 1090 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>, 1091 Sched<[WriteALU]>; 1092 1093// CMN register 1094let isCompare = 1, Defs = [CPSR] in { 1095//FIXME: Disable CMN, as CCodes are backwards from compare expectations 1096// Compare-to-zero still works out, just not the relationals 1097//def tCMN : // A8.6.33 1098// T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs), 1099// IIC_iCMPr, 1100// "cmn", "\t$lhs, $rhs", 1101// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 1102 1103def tCMNz : // A8.6.33 1104 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm), 1105 IIC_iCMPr, 1106 "cmn", "\t$Rn, $Rm", 1107 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>; 1108 1109} // isCompare = 1, Defs = [CPSR] 1110 1111// CMP immediate 1112let isCompare = 1, Defs = [CPSR] in { 1113def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi, 1114 "cmp", "\t$Rn, $imm8", 1115 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>, 1116 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> { 1117 // A8.6.35 1118 bits<3> Rn; 1119 bits<8> imm8; 1120 let Inst{10-8} = Rn; 1121 let Inst{7-0} = imm8; 1122} 1123 1124// CMP register 1125def tCMPr : // A8.6.36 T1 1126 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), 1127 IIC_iCMPr, 1128 "cmp", "\t$Rn, $Rm", 1129 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>; 1130 1131def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr, 1132 "cmp", "\t$Rn, $Rm", []>, 1133 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> { 1134 // A8.6.36 T2 1135 bits<4> Rm; 1136 bits<4> Rn; 1137 let Inst{7} = Rn{3}; 1138 let Inst{6-3} = Rm; 1139 let Inst{2-0} = Rn{2-0}; 1140} 1141} // isCompare = 1, Defs = [CPSR] 1142 1143 1144// XOR register 1145let isCommutable = 1 in 1146def tEOR : // A8.6.45 1147 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1148 IIC_iBITr, 1149 "eor", "\t$Rdn, $Rm", 1150 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1151 1152// LSL immediate 1153def tLSLri : // A8.6.88 1154 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5), 1155 IIC_iMOVsi, 1156 "lsl", "\t$Rd, $Rm, $imm5", 1157 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>, 1158 Sched<[WriteALU]> { 1159 bits<5> imm5; 1160 let Inst{10-6} = imm5; 1161} 1162 1163// LSL register 1164def tLSLrr : // A8.6.89 1165 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1166 IIC_iMOVsr, 1167 "lsl", "\t$Rdn, $Rm", 1168 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1169 1170// LSR immediate 1171def tLSRri : // A8.6.90 1172 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 1173 IIC_iMOVsi, 1174 "lsr", "\t$Rd, $Rm, $imm5", 1175 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 1176 Sched<[WriteALU]> { 1177 bits<5> imm5; 1178 let Inst{10-6} = imm5; 1179} 1180 1181// LSR register 1182def tLSRrr : // A8.6.91 1183 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1184 IIC_iMOVsr, 1185 "lsr", "\t$Rdn, $Rm", 1186 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1187 1188// Move register 1189let isMoveImm = 1 in 1190def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, 1191 "mov", "\t$Rd, $imm8", 1192 [(set tGPR:$Rd, imm0_255:$imm8)]>, 1193 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> { 1194 // A8.6.96 1195 bits<3> Rd; 1196 bits<8> imm8; 1197 let Inst{10-8} = Rd; 1198 let Inst{7-0} = imm8; 1199} 1200// Because we have an explicit tMOVSr below, we need an alias to handle 1201// the immediate "movs" form here. Blech. 1202def : tInstAlias <"movs $Rdn, $imm", 1203 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>; 1204 1205// A7-73: MOV(2) - mov setting flag. 1206 1207let hasSideEffects = 0, isMoveReg = 1 in { 1208def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, 1209 2, IIC_iMOVr, 1210 "mov", "\t$Rd, $Rm", "", []>, 1211 T1Special<{1,0,?,?}>, Sched<[WriteALU]> { 1212 // A8.6.97 1213 bits<4> Rd; 1214 bits<4> Rm; 1215 let Inst{7} = Rd{3}; 1216 let Inst{6-3} = Rm; 1217 let Inst{2-0} = Rd{2-0}; 1218} 1219let Defs = [CPSR] in 1220def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1221 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> { 1222 // A8.6.97 1223 bits<3> Rd; 1224 bits<3> Rm; 1225 let Inst{15-6} = 0b0000000000; 1226 let Inst{5-3} = Rm; 1227 let Inst{2-0} = Rd; 1228} 1229} // hasSideEffects 1230 1231// Multiply register 1232let isCommutable = 1 in 1233def tMUL : // A8.6.105 T1 1234 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2, 1235 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd", 1236 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>, 1237 T1DataProcessing<0b1101>, Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 1238 bits<3> Rd; 1239 bits<3> Rn; 1240 let Inst{5-3} = Rn; 1241 let Inst{2-0} = Rd; 1242 let AsmMatchConverter = "cvtThumbMultiply"; 1243} 1244 1245def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, 1246 pred:$p)>; 1247 1248// Move inverse register 1249def tMVN : // A8.6.107 1250 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr, 1251 "mvn", "\t$Rd, $Rn", 1252 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>; 1253 1254// Bitwise or register 1255let isCommutable = 1 in 1256def tORR : // A8.6.114 1257 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1258 IIC_iBITr, 1259 "orr", "\t$Rdn, $Rm", 1260 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1261 1262// Swaps 1263def tREV : // A8.6.134 1264 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1265 IIC_iUNAr, 1266 "rev", "\t$Rd, $Rm", 1267 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>, 1268 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1269 1270def tREV16 : // A8.6.135 1271 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1272 IIC_iUNAr, 1273 "rev16", "\t$Rd, $Rm", 1274 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>, 1275 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1276 1277def tREVSH : // A8.6.136 1278 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1279 IIC_iUNAr, 1280 "revsh", "\t$Rd, $Rm", 1281 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>, 1282 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1283 1284// Rotate right register 1285def tROR : // A8.6.139 1286 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1287 IIC_iMOVsr, 1288 "ror", "\t$Rdn, $Rm", 1289 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>, 1290 Sched<[WriteALU]>; 1291 1292// Negate register 1293def tRSB : // A8.6.141 1294 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn), 1295 IIC_iALUi, 1296 "rsb", "\t$Rd, $Rn, #0", 1297 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>; 1298 1299// Subtract with carry register 1300let Uses = [CPSR] in 1301def tSBC : // A8.6.151 1302 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1303 IIC_iALUr, 1304 "sbc", "\t$Rdn, $Rm", 1305 []>, 1306 Sched<[WriteALU]>; 1307 1308// Subtract immediate 1309def tSUBi3 : // A8.6.210 T1 1310 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 1311 IIC_iALUi, 1312 "sub", "\t$Rd, $Rm, $imm3", 1313 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>, 1314 Sched<[WriteALU]> { 1315 bits<3> imm3; 1316 let Inst{8-6} = imm3; 1317} 1318 1319def tSUBi8 : // A8.6.210 T2 1320 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), 1321 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 1322 "sub", "\t$Rdn, $imm8", 1323 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>, 1324 Sched<[WriteALU]>; 1325 1326def : tInstSubst<"add${s}${p} $rd, $rn, $imm", 1327 (tSUBi3 tGPR:$rd, s_cc_out:$s, tGPR:$rn, mod_imm1_7_neg:$imm, pred:$p)>; 1328 1329 1330def : tInstSubst<"add${s}${p} $rdn, $imm", 1331 (tSUBi8 tGPR:$rdn, s_cc_out:$s, mod_imm8_255_neg:$imm, pred:$p)>; 1332 1333 1334// Subtract register 1335def tSUBrr : // A8.6.212 1336 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1337 IIC_iALUr, 1338 "sub", "\t$Rd, $Rn, $Rm", 1339 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>, 1340 Sched<[WriteALU]>; 1341 1342def : tInstAlias <"sub${s}${p} $Rdn, $Rm", 1343 (tSUBrr tGPR:$Rdn,s_cc_out:$s, tGPR:$Rdn, tGPR:$Rm, pred:$p)>; 1344 1345/// Similar to the above except these set the 's' bit so the 1346/// instruction modifies the CPSR register. 1347/// 1348/// These opcodes will be converted to the real non-S opcodes by 1349/// AdjustInstrPostInstrSelection after giving then an optional CPSR operand. 1350let hasPostISelHook = 1, Defs = [CPSR] in { 1351 let Uses = [CPSR] in 1352 def tSBCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1353 2, IIC_iALUr, 1354 [(set tGPR:$Rdn, CPSR, (ARMsube tGPR:$Rn, tGPR:$Rm, 1355 CPSR))]>, 1356 Requires<[IsThumb1Only]>, 1357 Sched<[WriteALU]>; 1358 1359 def tSUBSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 1360 2, IIC_iALUi, 1361 [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rm, 1362 imm0_7:$imm3))]>, 1363 Requires<[IsThumb1Only]>, 1364 Sched<[WriteALU]>; 1365 1366 def tSUBSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8), 1367 2, IIC_iALUi, 1368 [(set tGPR:$Rdn, CPSR, (ARMsubc tGPR:$Rn, 1369 imm8_255:$imm8))]>, 1370 Requires<[IsThumb1Only]>, 1371 Sched<[WriteALU]>; 1372 1373 def tSUBSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1374 2, IIC_iALUr, 1375 [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rn, 1376 tGPR:$Rm))]>, 1377 Requires<[IsThumb1Only]>, 1378 Sched<[WriteALU]>; 1379 1380 def tRSBS : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn), 1381 2, IIC_iALUr, 1382 [(set tGPR:$Rd, CPSR, (ARMsubc 0, tGPR:$Rn))]>, 1383 Requires<[IsThumb1Only]>, 1384 Sched<[WriteALU]>; 1385 1386 def tLSLSri : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, imm0_31:$imm5), 1387 2, IIC_iALUr, 1388 [(set tGPR:$Rd, CPSR, (ARMlsls tGPR:$Rn, imm0_31:$imm5))]>, 1389 Requires<[IsThumb1Only]>, 1390 Sched<[WriteALU]>; 1391} 1392 1393 1394def : T1Pat<(ARMsubs tGPR:$Rn, tGPR:$Rm), (tSUBSrr $Rn, $Rm)>; 1395def : T1Pat<(ARMsubs tGPR:$Rn, imm0_7:$imm3), (tSUBSi3 $Rn, imm0_7:$imm3)>; 1396def : T1Pat<(ARMsubs tGPR:$Rn, imm0_255:$imm8), (tSUBSi8 $Rn, imm0_255:$imm8)>; 1397 1398 1399// Sign-extend byte 1400def tSXTB : // A8.6.222 1401 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1402 IIC_iUNAr, 1403 "sxtb", "\t$Rd, $Rm", 1404 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, 1405 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1406 Sched<[WriteALU]>; 1407 1408// Sign-extend short 1409def tSXTH : // A8.6.224 1410 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1411 IIC_iUNAr, 1412 "sxth", "\t$Rd, $Rm", 1413 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>, 1414 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1415 Sched<[WriteALU]>; 1416 1417// Test 1418let isCompare = 1, isCommutable = 1, Defs = [CPSR] in 1419def tTST : // A8.6.230 1420 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr, 1421 "tst", "\t$Rn, $Rm", 1422 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>, 1423 Sched<[WriteALU]>; 1424 1425// A8.8.247 UDF - Undefined (Encoding T1) 1426def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8", 1427 [(int_arm_undefined imm0_255:$imm8)]>, Encoding16 { 1428 bits<8> imm8; 1429 let Inst{15-12} = 0b1101; 1430 let Inst{11-8} = 0b1110; 1431 let Inst{7-0} = imm8; 1432} 1433 1434def : Pat<(debugtrap), (tBKPT 0)>, Requires<[IsThumb, HasV5T]>; 1435def : Pat<(debugtrap), (tUDF 254)>, Requires<[IsThumb, NoV5T]>; 1436 1437def t__brkdiv0 : TI<(outs), (ins), IIC_Br, "__brkdiv0", 1438 [(int_arm_undefined 249)]>, Encoding16, 1439 Requires<[IsThumb, IsWindows]> { 1440 let Inst = 0xdef9; 1441 let isTerminator = 1; 1442} 1443 1444// Zero-extend byte 1445def tUXTB : // A8.6.262 1446 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1447 IIC_iUNAr, 1448 "uxtb", "\t$Rd, $Rm", 1449 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>, 1450 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1451 Sched<[WriteALU]>; 1452 1453// Zero-extend short 1454def tUXTH : // A8.6.264 1455 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1456 IIC_iUNAr, 1457 "uxth", "\t$Rd, $Rm", 1458 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>, 1459 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1460 1461// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 1462// Expanded after instruction selection into a branch sequence. 1463let usesCustomInserter = 1 in // Expanded after instruction selection. 1464 def tMOVCCr_pseudo : 1465 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, cmovpred:$p), 1466 NoItinerary, 1467 [(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))]>; 1468 1469// tLEApcrel - Load a pc-relative address into a register without offending the 1470// assembler. 1471 1472def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), 1473 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>, 1474 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> { 1475 bits<3> Rd; 1476 bits<8> addr; 1477 let Inst{10-8} = Rd; 1478 let Inst{7-0} = addr; 1479 let DecoderMethod = "DecodeThumbAddSpecialReg"; 1480} 1481 1482let hasSideEffects = 0, isReMaterializable = 1 in 1483def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 1484 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1485 1486let hasSideEffects = 1 in 1487def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 1488 (ins i32imm:$label, pred:$p), 1489 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1490 1491// Thumb-1 doesn't have the TBB or TBH instructions, but we can synthesize them 1492// and make use of the same compressed jump table format as Thumb-2. 1493let Size = 2, isBranch = 1, isTerminator = 1, isBarrier = 1, 1494 isIndirectBranch = 1, isNotDuplicable = 1 in { 1495def tTBB_JT : tPseudoInst<(outs), 1496 (ins tGPRwithpc:$base, tGPR:$index, i32imm:$jt, i32imm:$pclbl), 0, 1497 IIC_Br, []>, Sched<[WriteBr]>; 1498 1499def tTBH_JT : tPseudoInst<(outs), 1500 (ins tGPRwithpc:$base, tGPR:$index, i32imm:$jt, i32imm:$pclbl), 0, 1501 IIC_Br, []>, Sched<[WriteBr]>; 1502} 1503 1504//===----------------------------------------------------------------------===// 1505// TLS Instructions 1506// 1507 1508// __aeabi_read_tp preserves the registers r1-r3. 1509// This is a pseudo inst so that we can get the encoding right, 1510// complete with fixup for the aeabi_read_tp function. 1511let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in 1512def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br, 1513 [(set R0, ARMthread_pointer)]>, 1514 Sched<[WriteBr]>; 1515 1516//===----------------------------------------------------------------------===// 1517// SJLJ Exception handling intrinsics 1518// 1519 1520// eh_sjlj_setjmp() is an instruction sequence to store the return address and 1521// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming 1522// from some other function to get here, and we're using the stack frame for the 1523// containing function to save/restore registers, we can't keep anything live in 1524// regs across the eh_sjlj_setjmp(), else it will almost certainly have been 1525// tromped upon when we get here from a longjmp(). We force everything out of 1526// registers except for our own input by listing the relevant registers in 1527// Defs. By doing so, we also cause the prologue/epilogue code to actively 1528// preserve all of the callee-saved registers, which is exactly what we want. 1529// $val is a scratch register for our use. 1530let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1531 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 1532 usesCustomInserter = 1 in 1533def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 1534 AddrModeNone, 0, NoItinerary, "","", 1535 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 1536 1537// FIXME: Non-IOS version(s) 1538let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1539 Defs = [ R7, LR, SP ] in 1540def tInt_eh_sjlj_longjmp : XI<(outs), (ins tGPR:$src, tGPR:$scratch), 1541 AddrModeNone, 0, IndexModeNone, 1542 Pseudo, NoItinerary, "", "", 1543 [(ARMeh_sjlj_longjmp tGPR:$src, tGPR:$scratch)]>, 1544 Requires<[IsThumb,IsNotWindows]>; 1545 1546// (Windows is Thumb2-only) 1547let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1548 Defs = [ R11, LR, SP ] in 1549def tInt_WIN_eh_sjlj_longjmp 1550 : XI<(outs), (ins GPR:$src, GPR:$scratch), AddrModeNone, 0, IndexModeNone, 1551 Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1552 Requires<[IsThumb,IsWindows]>; 1553 1554//===----------------------------------------------------------------------===// 1555// Non-Instruction Patterns 1556// 1557 1558// Comparisons 1559def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8), 1560 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>; 1561def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm), 1562 (tCMPr tGPR:$Rn, tGPR:$Rm)>; 1563 1564// Bswap 16 with load/store 1565def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)), 1566 (tREV16 (tLDRHi t_addrmode_is2:$addr))>; 1567def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rr:$addr)), (i32 16)), 1568 (tREV16 (tLDRHr t_addrmode_rr:$addr))>; 1569def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), 1570 t_addrmode_is2:$addr), 1571 (tSTRHi(tREV16 tGPR:$Rn), t_addrmode_is2:$addr)>; 1572def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), 1573 t_addrmode_rr:$addr), 1574 (tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rr:$addr)>; 1575 1576// ConstantPool 1577def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 1578 1579// GlobalAddress 1580def tLDRLIT_ga_pcrel : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr), 1581 IIC_iLoadiALU, 1582 [(set tGPR:$dst, 1583 (ARMWrapperPIC tglobaladdr:$addr))]>, 1584 Requires<[IsThumb, DontUseMovtInPic]>; 1585 1586def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src), 1587 IIC_iLoad_i, 1588 [(set tGPR:$dst, 1589 (ARMWrapper tglobaladdr:$src))]>, 1590 Requires<[IsThumb, DontUseMovt]>; 1591 1592// TLS globals 1593def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 1594 (tLDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 1595 Requires<[IsThumb, DontUseMovtInPic]>; 1596def : Pat<(ARMWrapper tglobaltlsaddr:$addr), 1597 (tLDRLIT_ga_abs tglobaltlsaddr:$addr)>, 1598 Requires<[IsThumb, DontUseMovt]>; 1599 1600 1601// JumpTable 1602def : T1Pat<(ARMWrapperJT tjumptable:$dst), 1603 (tLEApcrelJT tjumptable:$dst)>; 1604 1605// Direct calls 1606def : T1Pat<(ARMcall texternalsym:$func), (tBL texternalsym:$func)>, 1607 Requires<[IsThumb]>; 1608 1609// zextload i1 -> zextload i8 1610def : T1Pat<(zextloadi1 t_addrmode_is1:$addr), 1611 (tLDRBi t_addrmode_is1:$addr)>; 1612def : T1Pat<(zextloadi1 t_addrmode_rr:$addr), 1613 (tLDRBr t_addrmode_rr:$addr)>; 1614 1615// extload from the stack -> word load from the stack, as it avoids having to 1616// materialize the base in a separate register. This only works when a word 1617// load puts the byte/halfword value in the same place in the register that the 1618// byte/halfword load would, i.e. when little-endian. 1619def : T1Pat<(extloadi1 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1620 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1621def : T1Pat<(extloadi8 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1622 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1623def : T1Pat<(extloadi16 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1624 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1625 1626// extload -> zextload 1627def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1628def : T1Pat<(extloadi1 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>; 1629def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1630def : T1Pat<(extloadi8 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>; 1631def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; 1632def : T1Pat<(extloadi16 t_addrmode_rr:$addr), (tLDRHr t_addrmode_rr:$addr)>; 1633 1634// post-inc loads and stores 1635 1636// post-inc LDR -> LDM r0!, {r1}. The way operands are layed out in LDMs is 1637// different to how ISel expects them for a post-inc load, so use a pseudo 1638// and expand it just after ISel. 1639let usesCustomInserter = 1, mayLoad =1, 1640 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in 1641 def tLDR_postidx: tPseudoInst<(outs tGPR:$Rt, tGPR:$Rn_wb), 1642 (ins tGPR:$Rn, pred:$p), 1643 4, IIC_iStore_ru, 1644 []>; 1645 1646// post-inc STR -> STM r0!, {r1}. The layout of this (because it doesn't def 1647// multiple registers) is the same in ISel as MachineInstr, so there's no need 1648// for a pseudo. 1649def : T1Pat<(post_store tGPR:$Rt, tGPR:$Rn, 4), 1650 (tSTMIA_UPD tGPR:$Rn, tGPR:$Rt)>; 1651 1652// If it's impossible to use [r,r] address mode for sextload, select to 1653// ldr{b|h} + sxt{b|h} instead. 1654def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1655 (tSXTB (tLDRBi t_addrmode_is1:$addr))>, 1656 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1657def : T1Pat<(sextloadi8 t_addrmode_rr:$addr), 1658 (tSXTB (tLDRBr t_addrmode_rr:$addr))>, 1659 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1660def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1661 (tSXTH (tLDRHi t_addrmode_is2:$addr))>, 1662 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1663def : T1Pat<(sextloadi16 t_addrmode_rr:$addr), 1664 (tSXTH (tLDRHr t_addrmode_rr:$addr))>, 1665 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1666 1667def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1668 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; 1669def : T1Pat<(sextloadi8 t_addrmode_rr:$addr), 1670 (tASRri (tLSLri (tLDRBr t_addrmode_rr:$addr), 24), 24)>; 1671def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1672 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; 1673def : T1Pat<(sextloadi16 t_addrmode_rr:$addr), 1674 (tASRri (tLSLri (tLDRHr t_addrmode_rr:$addr), 16), 16)>; 1675 1676def : T1Pat<(atomic_load_8 t_addrmode_is1:$src), 1677 (tLDRBi t_addrmode_is1:$src)>; 1678def : T1Pat<(atomic_load_8 t_addrmode_rr:$src), 1679 (tLDRBr t_addrmode_rr:$src)>; 1680def : T1Pat<(atomic_load_16 t_addrmode_is2:$src), 1681 (tLDRHi t_addrmode_is2:$src)>; 1682def : T1Pat<(atomic_load_16 t_addrmode_rr:$src), 1683 (tLDRHr t_addrmode_rr:$src)>; 1684def : T1Pat<(atomic_load_32 t_addrmode_is4:$src), 1685 (tLDRi t_addrmode_is4:$src)>; 1686def : T1Pat<(atomic_load_32 t_addrmode_rr:$src), 1687 (tLDRr t_addrmode_rr:$src)>; 1688def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val), 1689 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>; 1690def : T1Pat<(atomic_store_8 t_addrmode_rr:$ptr, tGPR:$val), 1691 (tSTRBr tGPR:$val, t_addrmode_rr:$ptr)>; 1692def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val), 1693 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>; 1694def : T1Pat<(atomic_store_16 t_addrmode_rr:$ptr, tGPR:$val), 1695 (tSTRHr tGPR:$val, t_addrmode_rr:$ptr)>; 1696def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val), 1697 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>; 1698def : T1Pat<(atomic_store_32 t_addrmode_rr:$ptr, tGPR:$val), 1699 (tSTRr tGPR:$val, t_addrmode_rr:$ptr)>; 1700 1701// Large immediate handling. 1702 1703// Two piece imms. 1704def : T1Pat<(i32 thumb_immshifted:$src), 1705 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1706 (thumb_immshifted_shamt imm:$src))>; 1707 1708def : T1Pat<(i32 imm0_255_comp:$src), 1709 (tMVN (tMOVi8 (imm_not_XFORM imm:$src)))>; 1710 1711def : T1Pat<(i32 imm256_510:$src), 1712 (tADDi8 (tMOVi8 255), 1713 (thumb_imm256_510_addend imm:$src))>; 1714 1715// Pseudo instruction that combines ldr from constpool and add pc. This should 1716// be expanded into two instructions late to allow if-conversion and 1717// scheduling. 1718let isReMaterializable = 1 in 1719def tLDRpci_pic : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1720 NoItinerary, 1721 [(set tGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1722 imm:$cp))]>, 1723 Requires<[IsThumb, IsThumb1Only]>; 1724 1725// Pseudo-instruction for merged POP and return. 1726// FIXME: remove when we have a way to marking a MI with these properties. 1727let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1728 hasExtraDefRegAllocReq = 1 in 1729def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), 1730 2, IIC_iPop_Br, [], 1731 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>; 1732 1733// Indirect branch using "mov pc, $Rm" 1734let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1735 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), 1736 2, IIC_Br, [(brind GPR:$Rm)], 1737 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 1738} 1739 1740 1741// In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00 1742// encoding is available on ARMv6K, but we don't differentiate that finely. 1743def : InstAlias<"nop", (tMOVr R8, R8, 14, 0), 0>, Requires<[IsThumb, IsThumb1Only]>; 1744 1745 1746// "neg" is and alias for "rsb rd, rn, #0" 1747def : tInstAlias<"neg${s}${p} $Rd, $Rm", 1748 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>; 1749 1750 1751// Implied destination operand forms for shifts. 1752def : tInstAlias<"lsl${s}${p} $Rdm, $imm", 1753 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>; 1754def : tInstAlias<"lsr${s}${p} $Rdm, $imm", 1755 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1756def : tInstAlias<"asr${s}${p} $Rdm, $imm", 1757 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1758 1759// Pseudo instruction ldr Rt, =immediate 1760def tLDRConstPool 1761 : tAsmPseudo<"ldr${p} $Rt, $immediate", 1762 (ins tGPR:$Rt, const_pool_asm_imm:$immediate, pred:$p)>; 1763