xref: /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ARMInstrMVE.td (revision 0d8fe2373503aeac48492f28073049a8bfa4feb5)
1//===-- ARMInstrMVE.td - MVE support for ARM ---------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the ARM MVE instruction set.
10//
11//===----------------------------------------------------------------------===//
12
13// VPT condition mask
14def vpt_mask : Operand<i32> {
15  let PrintMethod = "printVPTMask";
16  let ParserMatchClass = it_mask_asmoperand;
17  let EncoderMethod = "getVPTMaskOpValue";
18  let DecoderMethod = "DecodeVPTMaskOperand";
19}
20
21// VPT/VCMP restricted predicate for sign invariant types
22def pred_restricted_i_asmoperand : AsmOperandClass {
23  let Name = "CondCodeRestrictedI";
24  let RenderMethod = "addITCondCodeOperands";
25  let PredicateMethod = "isITCondCodeRestrictedI";
26  let ParserMethod = "parseITCondCode";
27  let DiagnosticString = "condition code for sign-independent integer "#
28                         "comparison must be EQ or NE";
29}
30
31// VPT/VCMP restricted predicate for signed types
32def pred_restricted_s_asmoperand : AsmOperandClass {
33  let Name = "CondCodeRestrictedS";
34  let RenderMethod = "addITCondCodeOperands";
35  let PredicateMethod = "isITCondCodeRestrictedS";
36  let ParserMethod = "parseITCondCode";
37  let DiagnosticString = "condition code for signed integer "#
38                         "comparison must be EQ, NE, LT, GT, LE or GE";
39}
40
41// VPT/VCMP restricted predicate for unsigned types
42def pred_restricted_u_asmoperand : AsmOperandClass {
43  let Name = "CondCodeRestrictedU";
44  let RenderMethod = "addITCondCodeOperands";
45  let PredicateMethod = "isITCondCodeRestrictedU";
46  let ParserMethod = "parseITCondCode";
47  let DiagnosticString = "condition code for unsigned integer "#
48                         "comparison must be EQ, NE, HS or HI";
49}
50
51// VPT/VCMP restricted predicate for floating point
52def pred_restricted_fp_asmoperand : AsmOperandClass {
53  let Name = "CondCodeRestrictedFP";
54  let RenderMethod = "addITCondCodeOperands";
55  let PredicateMethod = "isITCondCodeRestrictedFP";
56  let ParserMethod = "parseITCondCode";
57  let DiagnosticString = "condition code for floating-point "#
58                         "comparison must be EQ, NE, LT, GT, LE or GE";
59}
60
61class VCMPPredicateOperand : Operand<i32>;
62
63def pred_basic_i : VCMPPredicateOperand {
64  let PrintMethod = "printMandatoryRestrictedPredicateOperand";
65  let ParserMatchClass = pred_restricted_i_asmoperand;
66  let DecoderMethod = "DecodeRestrictedIPredicateOperand";
67  let EncoderMethod = "getRestrictedCondCodeOpValue";
68}
69
70def pred_basic_u : VCMPPredicateOperand {
71  let PrintMethod = "printMandatoryRestrictedPredicateOperand";
72  let ParserMatchClass = pred_restricted_u_asmoperand;
73  let DecoderMethod = "DecodeRestrictedUPredicateOperand";
74  let EncoderMethod = "getRestrictedCondCodeOpValue";
75}
76
77def pred_basic_s : VCMPPredicateOperand {
78  let PrintMethod = "printMandatoryRestrictedPredicateOperand";
79  let ParserMatchClass = pred_restricted_s_asmoperand;
80  let DecoderMethod = "DecodeRestrictedSPredicateOperand";
81  let EncoderMethod = "getRestrictedCondCodeOpValue";
82}
83
84def pred_basic_fp : VCMPPredicateOperand {
85  let PrintMethod = "printMandatoryRestrictedPredicateOperand";
86  let ParserMatchClass = pred_restricted_fp_asmoperand;
87  let DecoderMethod = "DecodeRestrictedFPPredicateOperand";
88  let EncoderMethod = "getRestrictedCondCodeOpValue";
89}
90
91// Register list operands for interleaving load/stores
92def VecList2QAsmOperand : AsmOperandClass {
93  let Name = "VecListTwoMQ";
94  let ParserMethod = "parseVectorList";
95  let RenderMethod = "addMVEVecListOperands";
96  let DiagnosticString = "operand must be a list of two consecutive "#
97                         "q-registers in range [q0,q7]";
98}
99
100def VecList2Q : RegisterOperand<QQPR, "printMVEVectorListTwoQ"> {
101  let ParserMatchClass = VecList2QAsmOperand;
102  let PrintMethod = "printMVEVectorList<2>";
103}
104
105def VecList4QAsmOperand : AsmOperandClass {
106  let Name = "VecListFourMQ";
107  let ParserMethod = "parseVectorList";
108  let RenderMethod = "addMVEVecListOperands";
109  let DiagnosticString = "operand must be a list of four consecutive "#
110                         "q-registers in range [q0,q7]";
111}
112
113def VecList4Q : RegisterOperand<QQQQPR, "printMVEVectorListFourQ"> {
114  let ParserMatchClass = VecList4QAsmOperand;
115  let PrintMethod = "printMVEVectorList<4>";
116}
117
118// taddrmode_imm7  := reg[r0-r7] +/- (imm7 << shift)
119class TMemImm7ShiftOffsetAsmOperand<int shift> : AsmOperandClass {
120  let Name = "TMemImm7Shift"#shift#"Offset";
121  let PredicateMethod = "isMemImm7ShiftedOffset<"#shift#",ARM::tGPRRegClassID>";
122  let RenderMethod = "addMemImmOffsetOperands";
123}
124
125class taddrmode_imm7<int shift> : MemOperand,
126    ComplexPattern<i32, 2, "SelectTAddrModeImm7<"#shift#">", []>  {
127  let ParserMatchClass = TMemImm7ShiftOffsetAsmOperand<shift>;
128  // They are printed the same way as the T2 imm8 version
129  let PrintMethod = "printT2AddrModeImm8Operand<false>";
130  // This can also be the same as the T2 version.
131  let EncoderMethod = "getT2AddrModeImmOpValue<7,"#shift#">";
132  let DecoderMethod = "DecodeTAddrModeImm7<"#shift#">";
133  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
134}
135
136// t2addrmode_imm7  := reg +/- (imm7)
137class MemImm7ShiftOffsetAsmOperand<int shift> : AsmOperandClass {
138  let Name = "MemImm7Shift"#shift#"Offset";
139  let PredicateMethod = "isMemImm7ShiftedOffset<" # shift #
140                        ",ARM::GPRnopcRegClassID>";
141  let RenderMethod = "addMemImmOffsetOperands";
142}
143
144def MemImm7Shift0OffsetAsmOperand : MemImm7ShiftOffsetAsmOperand<0>;
145def MemImm7Shift1OffsetAsmOperand : MemImm7ShiftOffsetAsmOperand<1>;
146def MemImm7Shift2OffsetAsmOperand : MemImm7ShiftOffsetAsmOperand<2>;
147class T2AddrMode_Imm7<int shift> : MemOperand,
148      ComplexPattern<i32, 2, "SelectT2AddrModeImm7<"#shift#">", []> {
149  let EncoderMethod = "getT2AddrModeImmOpValue<7,"#shift#">";
150  let DecoderMethod = "DecodeT2AddrModeImm7<"#shift#", 0>";
151  let ParserMatchClass =
152    !cast<AsmOperandClass>("MemImm7Shift"#shift#"OffsetAsmOperand");
153  let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
154}
155
156class t2addrmode_imm7<int shift> : T2AddrMode_Imm7<shift> {
157  // They are printed the same way as the imm8 version
158  let PrintMethod = "printT2AddrModeImm8Operand<false>";
159}
160
161class MemImm7ShiftOffsetWBAsmOperand<int shift> : AsmOperandClass {
162  let Name = "MemImm7Shift"#shift#"OffsetWB";
163  let PredicateMethod = "isMemImm7ShiftedOffset<" # shift #
164                        ",ARM::rGPRRegClassID>";
165  let RenderMethod = "addMemImmOffsetOperands";
166}
167
168def MemImm7Shift0OffsetWBAsmOperand : MemImm7ShiftOffsetWBAsmOperand<0>;
169def MemImm7Shift1OffsetWBAsmOperand : MemImm7ShiftOffsetWBAsmOperand<1>;
170def MemImm7Shift2OffsetWBAsmOperand : MemImm7ShiftOffsetWBAsmOperand<2>;
171
172class t2addrmode_imm7_pre<int shift> : T2AddrMode_Imm7<shift> {
173  // They are printed the same way as the imm8 version
174  let PrintMethod = "printT2AddrModeImm8Operand<true>";
175  let ParserMatchClass =
176    !cast<AsmOperandClass>("MemImm7Shift"#shift#"OffsetWBAsmOperand");
177  let DecoderMethod = "DecodeT2AddrModeImm7<"#shift#", 1>";
178  let MIOperandInfo = (ops rGPR:$base, i32imm:$offsim);
179}
180
181class t2am_imm7shiftOffsetAsmOperand<int shift>
182  : AsmOperandClass { let Name = "Imm7Shift"#shift; }
183def t2am_imm7shift0OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<0>;
184def t2am_imm7shift1OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<1>;
185def t2am_imm7shift2OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<2>;
186
187class t2am_imm7_offset<int shift> : MemOperand,
188      ComplexPattern<i32, 1, "SelectT2AddrModeImm7Offset<"#shift#">",
189                     [], [SDNPWantRoot]> {
190  // They are printed the same way as the imm8 version
191  let PrintMethod = "printT2AddrModeImm8OffsetOperand";
192  let ParserMatchClass =
193    !cast<AsmOperandClass>("t2am_imm7shift"#shift#"OffsetAsmOperand");
194  let EncoderMethod = "getT2ScaledImmOpValue<7,"#shift#">";
195  let DecoderMethod = "DecodeT2Imm7<"#shift#">";
196}
197
198// Operands for gather/scatter loads of the form [Rbase, Qoffsets]
199class MemRegRQOffsetAsmOperand<int shift> : AsmOperandClass {
200  let Name = "MemRegRQS"#shift#"Offset";
201  let PredicateMethod = "isMemRegRQOffset<"#shift#">";
202  let RenderMethod = "addMemRegRQOffsetOperands";
203}
204
205def MemRegRQS0OffsetAsmOperand : MemRegRQOffsetAsmOperand<0>;
206def MemRegRQS1OffsetAsmOperand : MemRegRQOffsetAsmOperand<1>;
207def MemRegRQS2OffsetAsmOperand : MemRegRQOffsetAsmOperand<2>;
208def MemRegRQS3OffsetAsmOperand : MemRegRQOffsetAsmOperand<3>;
209
210// mve_addr_rq_shift  := reg + vreg{ << UXTW #shift}
211class mve_addr_rq_shift<int shift> : MemOperand {
212  let EncoderMethod = "getMveAddrModeRQOpValue";
213  let PrintMethod = "printMveAddrModeRQOperand<"#shift#">";
214  let ParserMatchClass =
215    !cast<AsmOperandClass>("MemRegRQS"#shift#"OffsetAsmOperand");
216  let DecoderMethod = "DecodeMveAddrModeRQ";
217  let MIOperandInfo = (ops GPRnopc:$base, MQPR:$offsreg);
218}
219
220class MemRegQOffsetAsmOperand<int shift> : AsmOperandClass {
221  let Name = "MemRegQS"#shift#"Offset";
222  let PredicateMethod = "isMemRegQOffset<"#shift#">";
223  let RenderMethod = "addMemImmOffsetOperands";
224}
225
226def MemRegQS2OffsetAsmOperand : MemRegQOffsetAsmOperand<2>;
227def MemRegQS3OffsetAsmOperand : MemRegQOffsetAsmOperand<3>;
228
229// mve_addr_q_shift  := vreg {+ #imm7s2/4}
230class mve_addr_q_shift<int shift> : MemOperand {
231  let EncoderMethod = "getMveAddrModeQOpValue<"#shift#">";
232  // Can be printed same way as other reg + imm operands
233  let PrintMethod = "printT2AddrModeImm8Operand<false>";
234  let ParserMatchClass =
235    !cast<AsmOperandClass>("MemRegQS"#shift#"OffsetAsmOperand");
236  let DecoderMethod = "DecodeMveAddrModeQ<"#shift#">";
237  let MIOperandInfo = (ops MQPR:$base, i32imm:$imm);
238}
239
240// A family of classes wrapping up information about the vector types
241// used by MVE.
242class MVEVectorVTInfo<ValueType vec, ValueType dblvec,
243                      ValueType pred, ValueType dblpred,
244                      bits<2> size, string suffixletter, bit unsigned> {
245  // The LLVM ValueType representing the vector, so we can use it in
246  // ISel patterns.
247  ValueType Vec = vec;
248
249  // The LLVM ValueType representing a vector with elements double the size
250  // of those in Vec, so we can use it in ISel patterns. It is up to the
251  // invoker of this class to ensure that this is a correct choice.
252  ValueType DblVec = dblvec;
253
254  // An LLVM ValueType representing a corresponding vector of
255  // predicate bits, for use in ISel patterns that handle an IR
256  // intrinsic describing the predicated form of the instruction.
257  //
258  // Usually, for a vector of N things, this will be vNi1. But for
259  // vectors of 2 values, we make an exception, and use v4i1 instead
260  // of v2i1. Rationale: MVE codegen doesn't support doing all the
261  // auxiliary operations on v2i1 (vector shuffles etc), and also,
262  // there's no MVE compare instruction that will _generate_ v2i1
263  // directly.
264  ValueType Pred = pred;
265
266  // Same as Pred but for DblVec rather than Vec.
267  ValueType DblPred = dblpred;
268
269  // The most common representation of the vector element size in MVE
270  // instruction encodings: a 2-bit value V representing an (8<<V)-bit
271  // vector element.
272  bits<2> Size = size;
273
274  // For vectors explicitly mentioning a signedness of integers: 0 for
275  // signed and 1 for unsigned. For anything else, undefined.
276  bit Unsigned = unsigned;
277
278  // The number of bits in a vector element, in integer form.
279  int LaneBits = !shl(8, Size);
280
281  // The suffix used in assembly language on an instruction operating
282  // on this lane if it only cares about number of bits.
283  string BitsSuffix = !if(!eq(suffixletter, "p"),
284                          !if(!eq(unsigned, 0b0), "8", "16"),
285                          !cast<string>(LaneBits));
286
287  // The suffix used on an instruction that mentions the whole type.
288  string Suffix = suffixletter # BitsSuffix;
289
290  // The letter part of the suffix only.
291  string SuffixLetter = suffixletter;
292}
293
294// Integer vector types that don't treat signed and unsigned differently.
295def MVE_v16i8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "i", ?>;
296def MVE_v8i16 : MVEVectorVTInfo<v8i16, v4i32, v8i1,  v4i1, 0b01, "i", ?>;
297def MVE_v4i32 : MVEVectorVTInfo<v4i32, v2i64, v4i1,  v4i1, 0b10, "i", ?>;
298def MVE_v2i64 : MVEVectorVTInfo<v2i64, ?,     v4i1,  ?,    0b11, "i", ?>;
299
300// Explicitly signed and unsigned integer vectors. They map to the
301// same set of LLVM ValueTypes as above, but are represented
302// differently in assembly and instruction encodings.
303def MVE_v16s8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "s", 0b0>;
304def MVE_v8s16 : MVEVectorVTInfo<v8i16, v4i32, v8i1,  v4i1, 0b01, "s", 0b0>;
305def MVE_v4s32 : MVEVectorVTInfo<v4i32, v2i64, v4i1,  v4i1, 0b10, "s", 0b0>;
306def MVE_v2s64 : MVEVectorVTInfo<v2i64, ?,     v4i1,  ?,    0b11, "s", 0b0>;
307def MVE_v16u8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "u", 0b1>;
308def MVE_v8u16 : MVEVectorVTInfo<v8i16, v4i32, v8i1,  v4i1, 0b01, "u", 0b1>;
309def MVE_v4u32 : MVEVectorVTInfo<v4i32, v2i64, v4i1,  v4i1, 0b10, "u", 0b1>;
310def MVE_v2u64 : MVEVectorVTInfo<v2i64, ?,     v4i1,  ?,    0b11, "u", 0b1>;
311
312// FP vector types.
313def MVE_v8f16 : MVEVectorVTInfo<v8f16, v4f32, v8i1,  v4i1, 0b01, "f", ?>;
314def MVE_v4f32 : MVEVectorVTInfo<v4f32, v2f64, v4i1,  v4i1, 0b10, "f", ?>;
315def MVE_v2f64 : MVEVectorVTInfo<v2f64, ?,     v4i1,  ?,    0b11, "f", ?>;
316
317// Polynomial vector types.
318def MVE_v16p8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b11, "p", 0b0>;
319def MVE_v8p16 : MVEVectorVTInfo<v8i16, v4i32, v8i1,  v4i1, 0b11, "p", 0b1>;
320
321multiclass MVE_TwoOpPattern<MVEVectorVTInfo VTI, PatFrag Op, Intrinsic PredInt,
322                            dag PredOperands, Instruction Inst,
323                            SDPatternOperator IdentityVec = null_frag> {
324  // Unpredicated
325  def : Pat<(VTI.Vec (Op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn))),
326            (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
327
328  // Predicated with select
329  if !ne(VTI.Size, 0b11) then {
330    def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$mask),
331                                (VTI.Vec (Op (VTI.Vec MQPR:$Qm),
332                                             (VTI.Vec MQPR:$Qn))),
333                                (VTI.Vec MQPR:$inactive))),
334              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
335                              ARMVCCThen, (VTI.Pred VCCR:$mask),
336                              (VTI.Vec MQPR:$inactive)))>;
337
338    // Optionally with the select folded through the op
339    def : Pat<(VTI.Vec (Op (VTI.Vec MQPR:$Qm),
340                           (VTI.Vec (vselect (VTI.Pred VCCR:$mask),
341                                             (VTI.Vec MQPR:$Qn),
342                                             (VTI.Vec IdentityVec))))),
343              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
344                              ARMVCCThen, (VTI.Pred VCCR:$mask),
345                              (VTI.Vec MQPR:$Qm)))>;
346  }
347
348  // Predicated with intrinsic
349  def : Pat<(VTI.Vec !con((PredInt (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)),
350                          PredOperands,
351                          (? (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive)))),
352            (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
353                            ARMVCCThen, (VTI.Pred VCCR:$mask),
354                            (VTI.Vec MQPR:$inactive)))>;
355}
356
357multiclass MVE_TwoOpPatternDup<MVEVectorVTInfo VTI, PatFrag Op, Intrinsic PredInt,
358                               dag PredOperands, Instruction Inst,
359                               SDPatternOperator IdentityVec = null_frag> {
360  // Unpredicated
361  def : Pat<(VTI.Vec (Op (VTI.Vec MQPR:$Qm), (VTI.Vec (ARMvdup rGPR:$Rn)))),
362            (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn))>;
363
364  // Predicated with select
365  if !ne(VTI.Size, 0b11) then {
366    def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$mask),
367                                (VTI.Vec (Op (VTI.Vec MQPR:$Qm),
368                                             (VTI.Vec (ARMvdup rGPR:$Rn)))),
369                                (VTI.Vec MQPR:$inactive))),
370              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn,
371                              ARMVCCThen, (VTI.Pred VCCR:$mask),
372                              (VTI.Vec MQPR:$inactive)))>;
373
374    // Optionally with the select folded through the op
375    def : Pat<(VTI.Vec (Op (VTI.Vec MQPR:$Qm),
376                           (VTI.Vec (vselect (VTI.Pred VCCR:$mask),
377                                             (ARMvdup rGPR:$Rn),
378                                             (VTI.Vec IdentityVec))))),
379              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn,
380                              ARMVCCThen, (VTI.Pred VCCR:$mask),
381                              (VTI.Vec MQPR:$Qm)))>;
382  }
383
384  // Predicated with intrinsic
385  def : Pat<(VTI.Vec !con((PredInt (VTI.Vec MQPR:$Qm), (VTI.Vec (ARMvdup rGPR:$Rn))),
386                          PredOperands,
387                          (? (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive)))),
388            (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn,
389                            ARMVCCThen, (VTI.Pred VCCR:$mask),
390                            (VTI.Vec MQPR:$inactive)))>;
391}
392
393// --------- Start of base classes for the instructions themselves
394
395class MVE_MI<dag oops, dag iops, InstrItinClass itin, string asm,
396             string ops, string cstr, list<dag> pattern>
397  : Thumb2XI<oops, iops, AddrModeNone, 4, itin, !strconcat(asm, "\t", ops), cstr,
398             pattern>,
399    Requires<[HasMVEInt]> {
400  let D = MVEDomain;
401  let DecoderNamespace = "MVE";
402}
403
404// MVE_p is used for most predicated instructions, to add the cluster
405// of input operands that provides the VPT suffix (none, T or E) and
406// the input predicate register.
407class MVE_p<dag oops, dag iops, InstrItinClass itin, string iname,
408            string suffix, string ops, vpred_ops vpred, string cstr,
409            list<dag> pattern=[]>
410  : MVE_MI<oops, !con(iops, (ins vpred:$vp)), itin,
411           // If the instruction has a suffix, like vadd.f32, then the
412           // VPT predication suffix goes before the dot, so the full
413           // name has to be "vadd${vp}.f32".
414           !strconcat(iname, "${vp}",
415                      !if(!eq(suffix, ""), "", !strconcat(".", suffix))),
416           ops, !strconcat(cstr, vpred.vpred_constraint), pattern> {
417  let Inst{31-29} = 0b111;
418  let Inst{27-26} = 0b11;
419}
420
421class MVE_f<dag oops, dag iops, InstrItinClass itin, string iname,
422            string suffix, string ops, vpred_ops vpred, string cstr,
423            list<dag> pattern=[]>
424  : MVE_p<oops, iops, itin, iname, suffix, ops, vpred, cstr, pattern> {
425  let Predicates = [HasMVEFloat];
426}
427
428class MVE_MI_with_pred<dag oops, dag iops, InstrItinClass itin, string asm,
429                       string ops, string cstr, list<dag> pattern>
430  : Thumb2I<oops, iops, AddrModeNone, 4, itin, asm, !strconcat("\t", ops), cstr,
431             pattern>,
432    Requires<[HasV8_1MMainline, HasMVEInt]> {
433  let D = MVEDomain;
434  let DecoderNamespace = "MVE";
435}
436
437class MVE_VMOV_lane_base<dag oops, dag iops, InstrItinClass itin, string asm,
438                         string suffix, string ops, string cstr,
439                         list<dag> pattern>
440  : Thumb2I<oops, iops, AddrModeNone, 4, itin, asm,
441            !if(!eq(suffix, ""), "", "." # suffix) # "\t" # ops,
442            cstr, pattern>,
443    Requires<[HasV8_1MMainline, HasMVEInt]> {
444  let D = MVEDomain;
445  let DecoderNamespace = "MVE";
446}
447
448class MVE_ScalarShift<string iname, dag oops, dag iops, string asm, string cstr,
449            list<dag> pattern=[]>
450  : MVE_MI_with_pred<oops, iops, NoItinerary, iname, asm, cstr, pattern> {
451  let Inst{31-20} = 0b111010100101;
452  let Inst{8} = 0b1;
453  let validForTailPredication=1;
454}
455
456class MVE_ScalarShiftSingleReg<string iname, dag iops, string asm, string cstr,
457                    list<dag> pattern=[]>
458  : MVE_ScalarShift<iname, (outs rGPR:$RdaDest), iops, asm, cstr, pattern> {
459  bits<4> RdaDest;
460
461  let Inst{19-16} = RdaDest{3-0};
462}
463
464class MVE_ScalarShiftSRegImm<string iname, bits<2> op5_4>
465  : MVE_ScalarShiftSingleReg<iname, (ins rGPR:$RdaSrc, long_shift:$imm),
466                     "$RdaSrc, $imm", "$RdaDest = $RdaSrc",
467                     [(set rGPR:$RdaDest,
468                          (i32 (!cast<Intrinsic>("int_arm_mve_" # iname)
469                                    (i32 rGPR:$RdaSrc), (i32 imm:$imm))))]> {
470  bits<5> imm;
471
472  let Inst{15} = 0b0;
473  let Inst{14-12} = imm{4-2};
474  let Inst{11-8} = 0b1111;
475  let Inst{7-6} = imm{1-0};
476  let Inst{5-4} = op5_4{1-0};
477  let Inst{3-0} = 0b1111;
478}
479
480def MVE_SQSHL : MVE_ScalarShiftSRegImm<"sqshl", 0b11>;
481def MVE_SRSHR : MVE_ScalarShiftSRegImm<"srshr", 0b10>;
482def MVE_UQSHL : MVE_ScalarShiftSRegImm<"uqshl", 0b00>;
483def MVE_URSHR : MVE_ScalarShiftSRegImm<"urshr", 0b01>;
484
485class MVE_ScalarShiftSRegReg<string iname, bits<2> op5_4>
486  : MVE_ScalarShiftSingleReg<iname, (ins rGPR:$RdaSrc, rGPR:$Rm),
487                     "$RdaSrc, $Rm", "$RdaDest = $RdaSrc",
488                     [(set rGPR:$RdaDest,
489                         (i32 (!cast<Intrinsic>("int_arm_mve_" # iname)
490                                   (i32 rGPR:$RdaSrc), (i32 rGPR:$Rm))))]> {
491  bits<4> Rm;
492
493  let Inst{15-12} = Rm{3-0};
494  let Inst{11-8} = 0b1111;
495  let Inst{7-6} = 0b00;
496  let Inst{5-4} = op5_4{1-0};
497  let Inst{3-0} = 0b1101;
498
499  let Unpredictable{8-6} = 0b111;
500}
501
502def MVE_SQRSHR : MVE_ScalarShiftSRegReg<"sqrshr", 0b10>;
503def MVE_UQRSHL : MVE_ScalarShiftSRegReg<"uqrshl", 0b00>;
504
505class MVE_ScalarShiftDoubleReg<string iname, dag iops, string asm,
506                               string cstr, list<dag> pattern=[]>
507  : MVE_ScalarShift<iname, (outs tGPREven:$RdaLo, tGPROdd:$RdaHi),
508                    iops, asm, cstr, pattern> {
509  bits<4> RdaLo;
510  bits<4> RdaHi;
511
512  let Inst{19-17} = RdaLo{3-1};
513  let Inst{11-9} = RdaHi{3-1};
514
515  let hasSideEffects = 0;
516}
517
518class MVE_ScalarShiftDRegImm<string iname, bits<2> op5_4, bit op16,
519                             list<dag> pattern=[]>
520  : MVE_ScalarShiftDoubleReg<
521      iname, (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, long_shift:$imm),
522      "$RdaLo, $RdaHi, $imm", "$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
523      pattern> {
524  bits<5> imm;
525
526  let Inst{16} = op16;
527  let Inst{15} = 0b0;
528  let Inst{14-12} = imm{4-2};
529  let Inst{7-6} = imm{1-0};
530  let Inst{5-4} = op5_4{1-0};
531  let Inst{3-0} = 0b1111;
532}
533
534class MVE_ScalarShiftDRegRegBase<string iname, dag iops, string asm,
535                                 bit op5, bit op16, list<dag> pattern=[]>
536  : MVE_ScalarShiftDoubleReg<
537     iname, iops, asm, "@earlyclobber $RdaHi,@earlyclobber $RdaLo,"
538                       "$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
539     pattern> {
540  bits<4> Rm;
541
542  let Inst{16} = op16;
543  let Inst{15-12} = Rm{3-0};
544  let Inst{6} = 0b0;
545  let Inst{5} = op5;
546  let Inst{4} = 0b0;
547  let Inst{3-0} = 0b1101;
548
549  // Custom decoder method because of the following overlapping encodings:
550  // ASRL and SQRSHR
551  // LSLL and UQRSHL
552  // SQRSHRL and SQRSHR
553  // UQRSHLL and UQRSHL
554  let DecoderMethod = "DecodeMVEOverlappingLongShift";
555}
556
557class MVE_ScalarShiftDRegReg<string iname, bit op5, list<dag> pattern=[]>
558  : MVE_ScalarShiftDRegRegBase<
559     iname, (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, rGPR:$Rm),
560     "$RdaLo, $RdaHi, $Rm", op5, 0b0, pattern> {
561
562  let Inst{7} = 0b0;
563}
564
565class MVE_ScalarShiftDRegRegWithSat<string iname, bit op5, list<dag> pattern=[]>
566  : MVE_ScalarShiftDRegRegBase<
567     iname, (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, rGPR:$Rm, saturateop:$sat),
568     "$RdaLo, $RdaHi, $sat, $Rm", op5, 0b1, pattern> {
569  bit sat;
570
571  let Inst{7} = sat;
572}
573
574def MVE_ASRLr   : MVE_ScalarShiftDRegReg<"asrl",    0b1,  [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
575                                        (ARMasrl tGPREven:$RdaLo_src,
576                                        tGPROdd:$RdaHi_src, rGPR:$Rm))]>;
577def MVE_ASRLi   : MVE_ScalarShiftDRegImm<"asrl",    0b10, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
578                                        (ARMasrl tGPREven:$RdaLo_src,
579                                        tGPROdd:$RdaHi_src, (i32 long_shift:$imm)))]>;
580def MVE_LSLLr   : MVE_ScalarShiftDRegReg<"lsll",    0b0,  [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
581                                        (ARMlsll tGPREven:$RdaLo_src,
582                                        tGPROdd:$RdaHi_src, rGPR:$Rm))]>;
583def MVE_LSLLi   : MVE_ScalarShiftDRegImm<"lsll",    0b00, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
584                                        (ARMlsll tGPREven:$RdaLo_src,
585                                        tGPROdd:$RdaHi_src, (i32 long_shift:$imm)))]>;
586def MVE_LSRL    : MVE_ScalarShiftDRegImm<"lsrl",    0b01, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
587                                        (ARMlsrl tGPREven:$RdaLo_src,
588                                        tGPROdd:$RdaHi_src, (i32 long_shift:$imm)))]>;
589
590def MVE_SQRSHRL : MVE_ScalarShiftDRegRegWithSat<"sqrshrl", 0b1>;
591def MVE_SQSHLL  : MVE_ScalarShiftDRegImm<"sqshll",  0b11, 0b1>;
592def MVE_SRSHRL  : MVE_ScalarShiftDRegImm<"srshrl",  0b10, 0b1>;
593
594def MVE_UQRSHLL : MVE_ScalarShiftDRegRegWithSat<"uqrshll", 0b0>;
595def MVE_UQSHLL  : MVE_ScalarShiftDRegImm<"uqshll",  0b00, 0b1>;
596def MVE_URSHRL  : MVE_ScalarShiftDRegImm<"urshrl",  0b01, 0b1>;
597
598// start of mve_rDest instructions
599
600class MVE_rDest<dag oops, dag iops, InstrItinClass itin,
601                string iname, string suffix,
602                string ops, string cstr, list<dag> pattern=[]>
603// Always use vpred_n and not vpred_r: with the output register being
604// a GPR and not a vector register, there can't be any question of
605// what to put in its inactive lanes.
606  : MVE_p<oops, iops, itin, iname, suffix, ops, vpred_n, cstr, pattern> {
607
608  let Inst{25-23} = 0b101;
609  let Inst{11-9} = 0b111;
610  let Inst{4} = 0b0;
611}
612
613class MVE_VABAV<string suffix, bit U, bits<2> size>
614  : MVE_rDest<(outs rGPR:$Rda), (ins rGPR:$Rda_src, MQPR:$Qn, MQPR:$Qm),
615              NoItinerary, "vabav", suffix, "$Rda, $Qn, $Qm", "$Rda = $Rda_src",
616              []> {
617  bits<4> Qm;
618  bits<4> Qn;
619  bits<4> Rda;
620
621  let Inst{28} = U;
622  let Inst{22} = 0b0;
623  let Inst{21-20} = size{1-0};
624  let Inst{19-17} = Qn{2-0};
625  let Inst{16} = 0b0;
626  let Inst{15-12} = Rda{3-0};
627  let Inst{8} = 0b1;
628  let Inst{7} = Qn{3};
629  let Inst{6} = 0b0;
630  let Inst{5} = Qm{3};
631  let Inst{3-1} = Qm{2-0};
632  let Inst{0} = 0b1;
633  let horizontalReduction = 1;
634}
635
636multiclass MVE_VABAV_m<MVEVectorVTInfo VTI> {
637  def "" : MVE_VABAV<VTI.Suffix, VTI.Unsigned, VTI.Size>;
638  defvar Inst = !cast<Instruction>(NAME);
639
640  let Predicates = [HasMVEInt] in {
641    def : Pat<(i32 (int_arm_mve_vabav
642                         (i32 VTI.Unsigned),
643                         (i32 rGPR:$Rda_src),
644                         (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
645              (i32 (Inst (i32 rGPR:$Rda_src),
646                         (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm)))>;
647
648    def : Pat<(i32 (int_arm_mve_vabav_predicated
649                         (i32 VTI.Unsigned),
650                         (i32 rGPR:$Rda_src),
651                         (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
652                         (VTI.Pred VCCR:$mask))),
653              (i32 (Inst (i32 rGPR:$Rda_src),
654                         (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
655                         ARMVCCThen, (VTI.Pred VCCR:$mask)))>;
656  }
657}
658
659defm MVE_VABAVs8  : MVE_VABAV_m<MVE_v16s8>;
660defm MVE_VABAVs16 : MVE_VABAV_m<MVE_v8s16>;
661defm MVE_VABAVs32 : MVE_VABAV_m<MVE_v4s32>;
662defm MVE_VABAVu8  : MVE_VABAV_m<MVE_v16u8>;
663defm MVE_VABAVu16 : MVE_VABAV_m<MVE_v8u16>;
664defm MVE_VABAVu32 : MVE_VABAV_m<MVE_v4u32>;
665
666class MVE_VADDV<string iname, string suffix, dag iops, string cstr,
667              bit A, bit U, bits<2> size, list<dag> pattern=[]>
668  : MVE_rDest<(outs tGPREven:$Rda), iops, NoItinerary,
669              iname, suffix, "$Rda, $Qm", cstr, pattern> {
670  bits<3> Qm;
671  bits<4> Rda;
672
673  let Inst{28} = U;
674  let Inst{22-20} = 0b111;
675  let Inst{19-18} = size{1-0};
676  let Inst{17-16} = 0b01;
677  let Inst{15-13} = Rda{3-1};
678  let Inst{12} = 0b0;
679  let Inst{8-6} = 0b100;
680  let Inst{5} = A;
681  let Inst{3-1} = Qm{2-0};
682  let Inst{0} = 0b0;
683  let horizontalReduction = 1;
684  let validForTailPredication = 1;
685}
686
687def SDTVecReduceP : SDTypeProfile<1, 2, [    // VADDLVp
688  SDTCisInt<0>, SDTCisVec<1>, SDTCisVec<2>
689]>;
690def ARMVADDVs       : SDNode<"ARMISD::VADDVs", SDTVecReduce>;
691def ARMVADDVu       : SDNode<"ARMISD::VADDVu", SDTVecReduce>;
692def ARMVADDVps      : SDNode<"ARMISD::VADDVps", SDTVecReduceP>;
693def ARMVADDVpu      : SDNode<"ARMISD::VADDVpu", SDTVecReduceP>;
694
695multiclass MVE_VADDV_A<MVEVectorVTInfo VTI> {
696  def acc    : MVE_VADDV<"vaddva", VTI.Suffix,
697                         (ins tGPREven:$Rda_src, MQPR:$Qm), "$Rda = $Rda_src",
698                         0b1, VTI.Unsigned, VTI.Size>;
699  def no_acc : MVE_VADDV<"vaddv", VTI.Suffix,
700                         (ins MQPR:$Qm), "",
701                         0b0, VTI.Unsigned, VTI.Size>;
702
703  defvar InstA = !cast<Instruction>(NAME # "acc");
704  defvar InstN = !cast<Instruction>(NAME # "no_acc");
705
706  let Predicates = [HasMVEInt] in {
707    if VTI.Unsigned then {
708      def : Pat<(i32 (vecreduce_add (VTI.Vec MQPR:$vec))),
709                (i32 (InstN $vec))>;
710      def : Pat<(i32 (vecreduce_add (VTI.Vec (vselect (VTI.Pred VCCR:$pred),
711                                                      (VTI.Vec MQPR:$vec),
712                                                      (VTI.Vec ARMimmAllZerosV))))),
713                (i32 (InstN $vec, ARMVCCThen, $pred))>;
714      def : Pat<(i32 (ARMVADDVu (VTI.Vec MQPR:$vec))),
715                (i32 (InstN $vec))>;
716      def : Pat<(i32 (ARMVADDVpu (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
717                (i32 (InstN $vec, ARMVCCThen, $pred))>;
718      def : Pat<(i32 (add (i32 (vecreduce_add (VTI.Vec MQPR:$vec))),
719                          (i32 tGPREven:$acc))),
720                (i32 (InstA $acc, $vec))>;
721      def : Pat<(i32 (add (i32 (vecreduce_add (VTI.Vec (vselect (VTI.Pred VCCR:$pred),
722                                                                (VTI.Vec MQPR:$vec),
723                                                                (VTI.Vec ARMimmAllZerosV))))),
724                          (i32 tGPREven:$acc))),
725                (i32 (InstA $acc, $vec, ARMVCCThen, $pred))>;
726      def : Pat<(i32 (add (i32 (ARMVADDVu (VTI.Vec MQPR:$vec))),
727                          (i32 tGPREven:$acc))),
728                (i32 (InstA $acc, $vec))>;
729      def : Pat<(i32 (add (i32 (ARMVADDVpu (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
730                          (i32 tGPREven:$acc))),
731                (i32 (InstA $acc, $vec, ARMVCCThen, $pred))>;
732    } else {
733      def : Pat<(i32 (ARMVADDVs (VTI.Vec MQPR:$vec))),
734                (i32 (InstN $vec))>;
735      def : Pat<(i32 (add (i32 (ARMVADDVs (VTI.Vec MQPR:$vec))),
736                          (i32 tGPREven:$acc))),
737                (i32 (InstA $acc, $vec))>;
738      def : Pat<(i32 (ARMVADDVps (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
739                (i32 (InstN $vec, ARMVCCThen, $pred))>;
740      def : Pat<(i32 (add (i32 (ARMVADDVps (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
741                          (i32 tGPREven:$acc))),
742                (i32 (InstA $acc, $vec, ARMVCCThen, $pred))>;
743    }
744
745    def : Pat<(i32 (int_arm_mve_addv_predicated (VTI.Vec MQPR:$vec),
746                                                (i32 VTI.Unsigned),
747                                                (VTI.Pred VCCR:$pred))),
748              (i32 (InstN $vec, ARMVCCThen, $pred))>;
749    def : Pat<(i32 (add (int_arm_mve_addv_predicated (VTI.Vec MQPR:$vec),
750                                                     (i32 VTI.Unsigned),
751                                                     (VTI.Pred VCCR:$pred)),
752                        (i32 tGPREven:$acc))),
753              (i32 (InstA $acc, $vec, ARMVCCThen, $pred))>;
754  }
755}
756
757defm MVE_VADDVs8  : MVE_VADDV_A<MVE_v16s8>;
758defm MVE_VADDVs16 : MVE_VADDV_A<MVE_v8s16>;
759defm MVE_VADDVs32 : MVE_VADDV_A<MVE_v4s32>;
760defm MVE_VADDVu8  : MVE_VADDV_A<MVE_v16u8>;
761defm MVE_VADDVu16 : MVE_VADDV_A<MVE_v8u16>;
762defm MVE_VADDVu32 : MVE_VADDV_A<MVE_v4u32>;
763
764class MVE_VADDLV<string iname, string suffix, dag iops, string cstr,
765               bit A, bit U, list<dag> pattern=[]>
766  : MVE_rDest<(outs tGPREven:$RdaLo, tGPROdd:$RdaHi), iops, NoItinerary, iname,
767              suffix, "$RdaLo, $RdaHi, $Qm", cstr, pattern> {
768  bits<3> Qm;
769  bits<4> RdaLo;
770  bits<4> RdaHi;
771
772  let Inst{28} = U;
773  let Inst{22-20} = RdaHi{3-1};
774  let Inst{19-18} = 0b10;
775  let Inst{17-16} = 0b01;
776  let Inst{15-13} = RdaLo{3-1};
777  let Inst{12} = 0b0;
778  let Inst{8-6} = 0b100;
779  let Inst{5} = A;
780  let Inst{3-1} = Qm{2-0};
781  let Inst{0} = 0b0;
782  let horizontalReduction = 1;
783}
784
785def SDTVecReduceL : SDTypeProfile<2, 1, [    // VADDLV
786  SDTCisInt<0>, SDTCisInt<1>, SDTCisVec<2>
787]>;
788def SDTVecReduceLA : SDTypeProfile<2, 3, [    // VADDLVA
789  SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>, SDTCisInt<3>,
790  SDTCisVec<4>
791]>;
792def SDTVecReduceLP : SDTypeProfile<2, 2, [    // VADDLVp
793  SDTCisInt<0>, SDTCisInt<1>, SDTCisVec<2>, SDTCisVec<2>
794]>;
795def SDTVecReduceLPA : SDTypeProfile<2, 4, [    // VADDLVAp
796  SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>, SDTCisInt<3>,
797  SDTCisVec<4>, SDTCisVec<5>
798]>;
799
800multiclass MVE_VADDLV_A<MVEVectorVTInfo VTI> {
801  def acc    : MVE_VADDLV<"vaddlva", VTI.Suffix,
802                        (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, MQPR:$Qm),
803                        "$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
804                        0b1, VTI.Unsigned>;
805  def no_acc : MVE_VADDLV<"vaddlv", VTI.Suffix,
806                        (ins MQPR:$Qm), "",
807                        0b0, VTI.Unsigned>;
808
809  defvar InstA = !cast<Instruction>(NAME # "acc");
810  defvar InstN = !cast<Instruction>(NAME # "no_acc");
811
812  defvar letter = VTI.SuffixLetter;
813  defvar ARMVADDLV = SDNode<"ARMISD::VADDLV" # letter, SDTVecReduceL>;
814  defvar ARMVADDLVA = SDNode<"ARMISD::VADDLVA" # letter, SDTVecReduceLA>;
815  defvar ARMVADDLVp = SDNode<"ARMISD::VADDLVp" # letter, SDTVecReduceLP>;
816  defvar ARMVADDLVAp = SDNode<"ARMISD::VADDLVAp" # letter, SDTVecReduceLPA>;
817
818  let Predicates = [HasMVEInt] in {
819    def : Pat<(ARMVADDLV (v4i32 MQPR:$vec)),
820              (InstN (v4i32 MQPR:$vec))>;
821    def : Pat<(ARMVADDLVA tGPREven:$acclo, tGPROdd:$acchi, (v4i32 MQPR:$vec)),
822              (InstA tGPREven:$acclo, tGPROdd:$acchi, (v4i32 MQPR:$vec))>;
823    def : Pat<(ARMVADDLVp (v4i32 MQPR:$vec), (VTI.Pred VCCR:$pred)),
824              (InstN (v4i32 MQPR:$vec), ARMVCCThen, (VTI.Pred VCCR:$pred))>;
825    def : Pat<(ARMVADDLVAp tGPREven:$acclo, tGPROdd:$acchi, (v4i32 MQPR:$vec),
826                           (VTI.Pred VCCR:$pred)),
827              (InstA tGPREven:$acclo, tGPROdd:$acchi, (v4i32 MQPR:$vec),
828                     ARMVCCThen, (VTI.Pred VCCR:$pred))>;
829  }
830}
831
832defm MVE_VADDLVs32 : MVE_VADDLV_A<MVE_v4s32>;
833defm MVE_VADDLVu32 : MVE_VADDLV_A<MVE_v4u32>;
834
835class MVE_VMINMAXNMV<string iname, string suffix, bit sz,
836                     bit bit_17, bit bit_7, list<dag> pattern=[]>
837  : MVE_rDest<(outs rGPR:$RdaDest), (ins rGPR:$RdaSrc, MQPR:$Qm),
838              NoItinerary, iname, suffix, "$RdaSrc, $Qm",
839              "$RdaDest = $RdaSrc", pattern> {
840  bits<3> Qm;
841  bits<4> RdaDest;
842
843  let Inst{28} = sz;
844  let Inst{22-20} = 0b110;
845  let Inst{19-18} = 0b11;
846  let Inst{17} = bit_17;
847  let Inst{16} = 0b0;
848  let Inst{15-12} = RdaDest{3-0};
849  let Inst{8} = 0b1;
850  let Inst{7} = bit_7;
851  let Inst{6-5} = 0b00;
852  let Inst{3-1} = Qm{2-0};
853  let Inst{0} = 0b0;
854  let horizontalReduction = 1;
855
856  let Predicates = [HasMVEFloat];
857  let hasSideEffects = 0;
858}
859
860multiclass MVE_VMINMAXNMV_p<string iname, bit notAbs, bit isMin,
861                            MVEVectorVTInfo VTI, string intrBaseName,
862                            ValueType Scalar, RegisterClass ScalarReg> {
863  def "": MVE_VMINMAXNMV<iname, VTI.Suffix, VTI.Size{0}, notAbs, isMin>;
864  defvar Inst        = !cast<Instruction>(NAME);
865  defvar unpred_intr = !cast<Intrinsic>(intrBaseName);
866  defvar pred_intr   = !cast<Intrinsic>(intrBaseName#"_predicated");
867
868  let Predicates = [HasMVEFloat] in {
869    def : Pat<(Scalar (unpred_intr (Scalar ScalarReg:$prev),
870                                   (VTI.Vec MQPR:$vec))),
871           (COPY_TO_REGCLASS (Inst (COPY_TO_REGCLASS ScalarReg:$prev, rGPR),
872                                   (VTI.Vec MQPR:$vec)),
873                              ScalarReg)>;
874    def : Pat<(Scalar (pred_intr   (Scalar ScalarReg:$prev),
875                                   (VTI.Vec MQPR:$vec),
876                                   (VTI.Pred VCCR:$pred))),
877           (COPY_TO_REGCLASS (Inst (COPY_TO_REGCLASS ScalarReg:$prev, rGPR),
878                                   (VTI.Vec MQPR:$vec),
879                                   ARMVCCThen, (VTI.Pred VCCR:$pred)),
880                              ScalarReg)>;
881  }
882}
883
884multiclass MVE_VMINMAXNMV_fty<string iname, bit notAbs, bit isMin,
885                              string intrBase> {
886  defm f32 : MVE_VMINMAXNMV_p<iname, notAbs, isMin, MVE_v4f32, intrBase,
887                              f32, SPR>;
888  defm f16 : MVE_VMINMAXNMV_p<iname, notAbs, isMin, MVE_v8f16, intrBase,
889                              f16, HPR>;
890}
891
892defm MVE_VMINNMV : MVE_VMINMAXNMV_fty<"vminnmv",  1, 1, "int_arm_mve_minnmv">;
893defm MVE_VMAXNMV : MVE_VMINMAXNMV_fty<"vmaxnmv",  1, 0, "int_arm_mve_maxnmv">;
894defm MVE_VMINNMAV: MVE_VMINMAXNMV_fty<"vminnmav", 0, 1, "int_arm_mve_minnmav">;
895defm MVE_VMAXNMAV: MVE_VMINMAXNMV_fty<"vmaxnmav", 0, 0, "int_arm_mve_maxnmav">;
896
897class MVE_VMINMAXV<string iname, string suffix, bit U, bits<2> size,
898                 bit bit_17, bit bit_7, list<dag> pattern=[]>
899  : MVE_rDest<(outs rGPR:$RdaDest), (ins rGPR:$RdaSrc, MQPR:$Qm), NoItinerary,
900              iname, suffix, "$RdaSrc, $Qm", "$RdaDest = $RdaSrc", pattern> {
901  bits<3> Qm;
902  bits<4> RdaDest;
903
904  let Inst{28} = U;
905  let Inst{22-20} = 0b110;
906  let Inst{19-18} = size{1-0};
907  let Inst{17} = bit_17;
908  let Inst{16} = 0b0;
909  let Inst{15-12} = RdaDest{3-0};
910  let Inst{8} = 0b1;
911  let Inst{7} = bit_7;
912  let Inst{6-5} = 0b00;
913  let Inst{3-1} = Qm{2-0};
914  let Inst{0} = 0b0;
915  let horizontalReduction = 1;
916}
917
918multiclass MVE_VMINMAXV_p<string iname, bit notAbs, bit isMin,
919                          MVEVectorVTInfo VTI, string intrBaseName> {
920  def "": MVE_VMINMAXV<iname, VTI.Suffix, VTI.Unsigned, VTI.Size,
921                       notAbs, isMin>;
922  defvar Inst        = !cast<Instruction>(NAME);
923  defvar unpred_intr = !cast<Intrinsic>(intrBaseName);
924  defvar pred_intr   = !cast<Intrinsic>(intrBaseName#"_predicated");
925  defvar base_args   = (? (i32 rGPR:$prev), (VTI.Vec MQPR:$vec));
926  defvar args        = !if(notAbs, !con(base_args, (? (i32 VTI.Unsigned))),
927                           base_args);
928
929  let Predicates = [HasMVEInt] in {
930    def : Pat<(i32 !con(args, (unpred_intr))),
931              (i32 (Inst (i32 rGPR:$prev), (VTI.Vec MQPR:$vec)))>;
932    def : Pat<(i32 !con(args, (pred_intr (VTI.Pred VCCR:$pred)))),
933              (i32 (Inst (i32 rGPR:$prev), (VTI.Vec MQPR:$vec),
934                         ARMVCCThen, (VTI.Pred VCCR:$pred)))>;
935  }
936}
937
938multiclass MVE_VMINMAXV_ty<string iname, bit isMin, string intrBaseName> {
939  defm s8 : MVE_VMINMAXV_p<iname, 1, isMin, MVE_v16s8, intrBaseName>;
940  defm s16: MVE_VMINMAXV_p<iname, 1, isMin, MVE_v8s16, intrBaseName>;
941  defm s32: MVE_VMINMAXV_p<iname, 1, isMin, MVE_v4s32, intrBaseName>;
942  defm u8 : MVE_VMINMAXV_p<iname, 1, isMin, MVE_v16u8, intrBaseName>;
943  defm u16: MVE_VMINMAXV_p<iname, 1, isMin, MVE_v8u16, intrBaseName>;
944  defm u32: MVE_VMINMAXV_p<iname, 1, isMin, MVE_v4u32, intrBaseName>;
945}
946
947def SDTVecReduceR : SDTypeProfile<1, 2, [   // Reduction of an integer and vector into an integer
948  SDTCisInt<0>, SDTCisInt<1>, SDTCisVec<2>
949]>;
950def ARMVMINVu       : SDNode<"ARMISD::VMINVu", SDTVecReduceR>;
951def ARMVMINVs       : SDNode<"ARMISD::VMINVs", SDTVecReduceR>;
952def ARMVMAXVu       : SDNode<"ARMISD::VMAXVu", SDTVecReduceR>;
953def ARMVMAXVs       : SDNode<"ARMISD::VMAXVs", SDTVecReduceR>;
954
955defm MVE_VMINV : MVE_VMINMAXV_ty<"vminv", 1, "int_arm_mve_minv">;
956defm MVE_VMAXV : MVE_VMINMAXV_ty<"vmaxv", 0, "int_arm_mve_maxv">;
957
958let Predicates = [HasMVEInt] in {
959  def : Pat<(i32 (vecreduce_smax (v16i8 MQPR:$src))),
960            (i32 (MVE_VMAXVs8 (t2MVNi (i32 127)), $src))>;
961  def : Pat<(i32 (vecreduce_smax (v8i16 MQPR:$src))),
962            (i32 (MVE_VMAXVs16 (t2MOVi32imm (i32 -32768)), $src))>;
963  def : Pat<(i32 (vecreduce_smax (v4i32 MQPR:$src))),
964            (i32 (MVE_VMAXVs32 (t2MOVi (i32 -2147483648)), $src))>;
965  def : Pat<(i32 (vecreduce_umax (v16i8 MQPR:$src))),
966            (i32 (MVE_VMAXVu8 (t2MOVi (i32 0)), $src))>;
967  def : Pat<(i32 (vecreduce_umax (v8i16 MQPR:$src))),
968            (i32 (MVE_VMAXVu16 (t2MOVi (i32 0)), $src))>;
969  def : Pat<(i32 (vecreduce_umax (v4i32 MQPR:$src))),
970            (i32 (MVE_VMAXVu32 (t2MOVi (i32 0)), $src))>;
971
972  def : Pat<(i32 (vecreduce_smin (v16i8 MQPR:$src))),
973            (i32 (MVE_VMINVs8 (t2MOVi (i32 127)), $src))>;
974  def : Pat<(i32 (vecreduce_smin (v8i16 MQPR:$src))),
975            (i32 (MVE_VMINVs16 (t2MOVi16 (i32 32767)), $src))>;
976  def : Pat<(i32 (vecreduce_smin (v4i32 MQPR:$src))),
977            (i32 (MVE_VMINVs32 (t2MVNi (i32 -2147483648)), $src))>;
978  def : Pat<(i32 (vecreduce_umin (v16i8 MQPR:$src))),
979            (i32 (MVE_VMINVu8 (t2MOVi (i32 255)), $src))>;
980  def : Pat<(i32 (vecreduce_umin (v8i16 MQPR:$src))),
981            (i32 (MVE_VMINVu16 (t2MOVi16 (i32 65535)), $src))>;
982  def : Pat<(i32 (vecreduce_umin (v4i32 MQPR:$src))),
983            (i32 (MVE_VMINVu32 (t2MOVi (i32 4294967295)), $src))>;
984
985  def : Pat<(i32 (ARMVMINVu (i32 rGPR:$x), (v16i8 MQPR:$src))),
986            (i32 (MVE_VMINVu8 $x, $src))>;
987  def : Pat<(i32 (ARMVMINVu (i32 rGPR:$x), (v8i16 MQPR:$src))),
988            (i32 (MVE_VMINVu16 $x, $src))>;
989  def : Pat<(i32 (ARMVMINVu (i32 rGPR:$x), (v4i32 MQPR:$src))),
990            (i32 (MVE_VMINVu32 $x, $src))>;
991  def : Pat<(i32 (ARMVMINVs (i32 rGPR:$x), (v16i8 MQPR:$src))),
992            (i32 (MVE_VMINVs8 $x, $src))>;
993  def : Pat<(i32 (ARMVMINVs (i32 rGPR:$x), (v8i16 MQPR:$src))),
994            (i32 (MVE_VMINVs16 $x, $src))>;
995  def : Pat<(i32 (ARMVMINVs (i32 rGPR:$x), (v4i32 MQPR:$src))),
996            (i32 (MVE_VMINVs32 $x, $src))>;
997
998  def : Pat<(i32 (ARMVMAXVu (i32 rGPR:$x), (v16i8 MQPR:$src))),
999            (i32 (MVE_VMAXVu8 $x, $src))>;
1000  def : Pat<(i32 (ARMVMAXVu (i32 rGPR:$x), (v8i16 MQPR:$src))),
1001            (i32 (MVE_VMAXVu16 $x, $src))>;
1002  def : Pat<(i32 (ARMVMAXVu (i32 rGPR:$x), (v4i32 MQPR:$src))),
1003            (i32 (MVE_VMAXVu32 $x, $src))>;
1004  def : Pat<(i32 (ARMVMAXVs (i32 rGPR:$x), (v16i8 MQPR:$src))),
1005            (i32 (MVE_VMAXVs8 $x, $src))>;
1006  def : Pat<(i32 (ARMVMAXVs (i32 rGPR:$x), (v8i16 MQPR:$src))),
1007            (i32 (MVE_VMAXVs16 $x, $src))>;
1008  def : Pat<(i32 (ARMVMAXVs (i32 rGPR:$x), (v4i32 MQPR:$src))),
1009            (i32 (MVE_VMAXVs32 $x, $src))>;
1010
1011}
1012
1013multiclass MVE_VMINMAXAV_ty<string iname, bit isMin, string intrBaseName> {
1014  defm s8 : MVE_VMINMAXV_p<iname, 0, isMin, MVE_v16s8, intrBaseName>;
1015  defm s16: MVE_VMINMAXV_p<iname, 0, isMin, MVE_v8s16, intrBaseName>;
1016  defm s32: MVE_VMINMAXV_p<iname, 0, isMin, MVE_v4s32, intrBaseName>;
1017}
1018
1019defm MVE_VMINAV : MVE_VMINMAXAV_ty<"vminav", 1, "int_arm_mve_minav">;
1020defm MVE_VMAXAV : MVE_VMINMAXAV_ty<"vmaxav", 0, "int_arm_mve_maxav">;
1021
1022class MVE_VMLAMLSDAV<string iname, string suffix, dag iops, string cstr,
1023                   bit sz, bit bit_28, bit A, bit X, bit bit_8, bit bit_0>
1024  : MVE_rDest<(outs tGPREven:$RdaDest), iops, NoItinerary, iname, suffix,
1025              "$RdaDest, $Qn, $Qm", cstr, []> {
1026  bits<4> RdaDest;
1027  bits<3> Qm;
1028  bits<3> Qn;
1029
1030  let Inst{28} = bit_28;
1031  let Inst{22-20} = 0b111;
1032  let Inst{19-17} = Qn{2-0};
1033  let Inst{16} = sz;
1034  let Inst{15-13} = RdaDest{3-1};
1035  let Inst{12} = X;
1036  let Inst{8} = bit_8;
1037  let Inst{7-6} = 0b00;
1038  let Inst{5} = A;
1039  let Inst{3-1} = Qm{2-0};
1040  let Inst{0} = bit_0;
1041  let horizontalReduction = 1;
1042  // Allow tail predication for non-exchanging versions. As this is also a
1043  // horizontalReduction, ARMLowOverheadLoops will also have to check that
1044  // the vector operands contain zeros in their false lanes for the instruction
1045  // to be properly valid.
1046  let validForTailPredication = !eq(X, 0);
1047}
1048
1049multiclass MVE_VMLAMLSDAV_A<string iname, string x, MVEVectorVTInfo VTI,
1050                            bit sz, bit bit_28, bit X, bit bit_8, bit bit_0> {
1051  def ""#x#VTI.Suffix : MVE_VMLAMLSDAV<iname # x, VTI.Suffix,
1052                                   (ins MQPR:$Qn, MQPR:$Qm), "",
1053                                   sz, bit_28, 0b0, X, bit_8, bit_0>;
1054  def "a"#x#VTI.Suffix : MVE_VMLAMLSDAV<iname # "a" # x, VTI.Suffix,
1055                                    (ins tGPREven:$RdaSrc, MQPR:$Qn, MQPR:$Qm),
1056                                    "$RdaDest = $RdaSrc",
1057                                    sz, bit_28, 0b1, X, bit_8, bit_0>;
1058  let Predicates = [HasMVEInt] in {
1059    def : Pat<(i32 (int_arm_mve_vmldava
1060                            (i32 VTI.Unsigned),
1061                            (i32 bit_0) /* subtract */,
1062                            (i32 X) /* exchange */,
1063                            (i32 0) /* accumulator */,
1064                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
1065              (i32 (!cast<Instruction>(NAME # x # VTI.Suffix)
1066                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm)))>;
1067
1068    def : Pat<(i32 (int_arm_mve_vmldava_predicated
1069                            (i32 VTI.Unsigned),
1070                            (i32 bit_0) /* subtract */,
1071                            (i32 X) /* exchange */,
1072                            (i32 0) /* accumulator */,
1073                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
1074                            (VTI.Pred VCCR:$mask))),
1075              (i32 (!cast<Instruction>(NAME # x # VTI.Suffix)
1076                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
1077                             ARMVCCThen, (VTI.Pred VCCR:$mask)))>;
1078
1079    def : Pat<(i32 (int_arm_mve_vmldava
1080                            (i32 VTI.Unsigned),
1081                            (i32 bit_0) /* subtract */,
1082                            (i32 X) /* exchange */,
1083                            (i32 tGPREven:$RdaSrc),
1084                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
1085              (i32 (!cast<Instruction>(NAME # "a" # x # VTI.Suffix)
1086                            (i32 tGPREven:$RdaSrc),
1087                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm)))>;
1088
1089    def : Pat<(i32 (int_arm_mve_vmldava_predicated
1090                            (i32 VTI.Unsigned),
1091                            (i32 bit_0) /* subtract */,
1092                            (i32 X) /* exchange */,
1093                            (i32 tGPREven:$RdaSrc),
1094                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
1095                            (VTI.Pred VCCR:$mask))),
1096              (i32 (!cast<Instruction>(NAME # "a" # x # VTI.Suffix)
1097                            (i32 tGPREven:$RdaSrc),
1098                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
1099                             ARMVCCThen, (VTI.Pred VCCR:$mask)))>;
1100  }
1101}
1102
1103multiclass MVE_VMLAMLSDAV_AX<string iname, MVEVectorVTInfo VTI, bit sz,
1104                             bit bit_28, bit bit_8, bit bit_0> {
1105  defm "" : MVE_VMLAMLSDAV_A<iname, "", VTI, sz, bit_28,
1106                             0b0, bit_8, bit_0>;
1107  defm "" : MVE_VMLAMLSDAV_A<iname, "x", VTI, sz, bit_28,
1108                             0b1, bit_8, bit_0>;
1109}
1110
1111multiclass MVE_VMLADAV_multi<MVEVectorVTInfo SVTI, MVEVectorVTInfo UVTI,
1112                             bit sz, bit bit_8> {
1113  defm "" : MVE_VMLAMLSDAV_AX<"vmladav", SVTI,
1114                              sz, 0b0, bit_8, 0b0>;
1115  defm "" : MVE_VMLAMLSDAV_A<"vmladav", "", UVTI,
1116                             sz, 0b1, 0b0, bit_8, 0b0>;
1117}
1118
1119multiclass MVE_VMLSDAV_multi<MVEVectorVTInfo VTI, bit sz, bit bit_28> {
1120  defm "" : MVE_VMLAMLSDAV_AX<"vmlsdav", VTI,
1121                              sz, bit_28, 0b0, 0b1>;
1122}
1123
1124defm MVE_VMLADAV : MVE_VMLADAV_multi<MVE_v16s8, MVE_v16u8, 0b0, 0b1>;
1125defm MVE_VMLADAV : MVE_VMLADAV_multi<MVE_v8s16, MVE_v8u16, 0b0, 0b0>;
1126defm MVE_VMLADAV : MVE_VMLADAV_multi<MVE_v4s32, MVE_v4u32, 0b1, 0b0>;
1127
1128defm MVE_VMLSDAV : MVE_VMLSDAV_multi<MVE_v16s8, 0b0, 0b1>;
1129defm MVE_VMLSDAV : MVE_VMLSDAV_multi<MVE_v8s16, 0b0, 0b0>;
1130defm MVE_VMLSDAV : MVE_VMLSDAV_multi<MVE_v4s32, 0b1, 0b0>;
1131
1132def SDTVecReduce2 : SDTypeProfile<1, 2, [    // VMLAV
1133  SDTCisInt<0>, SDTCisVec<1>, SDTCisVec<2>
1134]>;
1135def SDTVecReduce2L : SDTypeProfile<2, 2, [    // VMLALV
1136  SDTCisInt<0>, SDTCisInt<1>, SDTCisVec<2>, SDTCisVec<3>
1137]>;
1138def SDTVecReduce2LA : SDTypeProfile<2, 4, [    // VMLALVA
1139  SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>, SDTCisInt<3>,
1140  SDTCisVec<4>, SDTCisVec<5>
1141]>;
1142def SDTVecReduce2P : SDTypeProfile<1, 3, [    // VMLAV
1143  SDTCisInt<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisVec<3>
1144]>;
1145def SDTVecReduce2LP : SDTypeProfile<2, 3, [    // VMLALV
1146  SDTCisInt<0>, SDTCisInt<1>, SDTCisVec<2>, SDTCisVec<3>, SDTCisVec<4>
1147]>;
1148def SDTVecReduce2LAP : SDTypeProfile<2, 5, [    // VMLALVA
1149  SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>, SDTCisInt<3>,
1150  SDTCisVec<4>, SDTCisVec<5>, SDTCisVec<6>
1151]>;
1152def ARMVMLAVs       : SDNode<"ARMISD::VMLAVs", SDTVecReduce2>;
1153def ARMVMLAVu       : SDNode<"ARMISD::VMLAVu", SDTVecReduce2>;
1154def ARMVMLALVs      : SDNode<"ARMISD::VMLALVs", SDTVecReduce2L>;
1155def ARMVMLALVu      : SDNode<"ARMISD::VMLALVu", SDTVecReduce2L>;
1156def ARMVMLALVAs     : SDNode<"ARMISD::VMLALVAs", SDTVecReduce2LA>;
1157def ARMVMLALVAu     : SDNode<"ARMISD::VMLALVAu", SDTVecReduce2LA>;
1158def ARMVMLAVps      : SDNode<"ARMISD::VMLAVps", SDTVecReduce2P>;
1159def ARMVMLAVpu      : SDNode<"ARMISD::VMLAVpu", SDTVecReduce2P>;
1160def ARMVMLALVps     : SDNode<"ARMISD::VMLALVps", SDTVecReduce2LP>;
1161def ARMVMLALVpu     : SDNode<"ARMISD::VMLALVpu", SDTVecReduce2LP>;
1162def ARMVMLALVAps    : SDNode<"ARMISD::VMLALVAps", SDTVecReduce2LAP>;
1163def ARMVMLALVApu    : SDNode<"ARMISD::VMLALVApu", SDTVecReduce2LAP>;
1164
1165let Predicates = [HasMVEInt] in {
1166  def : Pat<(i32 (vecreduce_add (mul (v4i32 MQPR:$src1), (v4i32 MQPR:$src2)))),
1167            (i32 (MVE_VMLADAVu32 $src1, $src2))>;
1168  def : Pat<(i32 (vecreduce_add (mul (v8i16 MQPR:$src1), (v8i16 MQPR:$src2)))),
1169            (i32 (MVE_VMLADAVu16 $src1, $src2))>;
1170  def : Pat<(i32 (ARMVMLAVs (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))),
1171            (i32 (MVE_VMLADAVs16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
1172  def : Pat<(i32 (ARMVMLAVu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))),
1173            (i32 (MVE_VMLADAVu16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
1174  def : Pat<(i32 (vecreduce_add (mul (v16i8 MQPR:$src1), (v16i8 MQPR:$src2)))),
1175            (i32 (MVE_VMLADAVu8 $src1, $src2))>;
1176  def : Pat<(i32 (ARMVMLAVs (v16i8 MQPR:$val1), (v16i8 MQPR:$val2))),
1177            (i32 (MVE_VMLADAVs8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
1178  def : Pat<(i32 (ARMVMLAVu (v16i8 MQPR:$val1), (v16i8 MQPR:$val2))),
1179            (i32 (MVE_VMLADAVu8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
1180
1181  def : Pat<(i32 (add (i32 (vecreduce_add (mul (v4i32 MQPR:$src1), (v4i32 MQPR:$src2)))),
1182                      (i32 tGPREven:$src3))),
1183            (i32 (MVE_VMLADAVau32 $src3, $src1, $src2))>;
1184  def : Pat<(i32 (add (i32 (vecreduce_add (mul (v8i16 MQPR:$src1), (v8i16 MQPR:$src2)))),
1185                      (i32 tGPREven:$src3))),
1186            (i32 (MVE_VMLADAVau16 $src3, $src1, $src2))>;
1187  def : Pat<(i32 (add (ARMVMLAVs (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)), tGPREven:$Rd)),
1188            (i32 (MVE_VMLADAVas16 tGPREven:$Rd, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
1189  def : Pat<(i32 (add (ARMVMLAVu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)), tGPREven:$Rd)),
1190            (i32 (MVE_VMLADAVau16 tGPREven:$Rd, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
1191  def : Pat<(i32 (add (i32 (vecreduce_add (mul (v16i8 MQPR:$src1), (v16i8 MQPR:$src2)))),
1192                      (i32 tGPREven:$src3))),
1193            (i32 (MVE_VMLADAVau8 $src3, $src1, $src2))>;
1194  def : Pat<(i32 (add (ARMVMLAVs (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)), tGPREven:$Rd)),
1195            (i32 (MVE_VMLADAVas8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
1196  def : Pat<(i32 (add (ARMVMLAVu (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)), tGPREven:$Rd)),
1197            (i32 (MVE_VMLADAVau8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
1198
1199  // Predicated
1200  def : Pat<(i32 (vecreduce_add (vselect (v4i1 VCCR:$pred),
1201                                         (mul (v4i32 MQPR:$src1), (v4i32 MQPR:$src2)),
1202                                         (v4i32 ARMimmAllZerosV)))),
1203            (i32 (MVE_VMLADAVu32 $src1, $src2, ARMVCCThen, $pred))>;
1204  def : Pat<(i32 (vecreduce_add (vselect (v8i1 VCCR:$pred),
1205                                         (mul (v8i16 MQPR:$src1), (v8i16 MQPR:$src2)),
1206                                         (v8i16 ARMimmAllZerosV)))),
1207            (i32 (MVE_VMLADAVu16 $src1, $src2, ARMVCCThen, $pred))>;
1208  def : Pat<(i32 (ARMVMLAVps (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred))),
1209            (i32 (MVE_VMLADAVs16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred))>;
1210  def : Pat<(i32 (ARMVMLAVpu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred))),
1211            (i32 (MVE_VMLADAVu16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred))>;
1212  def : Pat<(i32 (vecreduce_add (vselect (v16i1 VCCR:$pred),
1213                                         (mul (v16i8 MQPR:$src1), (v16i8 MQPR:$src2)),
1214                                         (v16i8 ARMimmAllZerosV)))),
1215            (i32 (MVE_VMLADAVu8 $src1, $src2, ARMVCCThen, $pred))>;
1216  def : Pat<(i32 (ARMVMLAVps (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred))),
1217            (i32 (MVE_VMLADAVs8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred))>;
1218  def : Pat<(i32 (ARMVMLAVpu (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred))),
1219            (i32 (MVE_VMLADAVu8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred))>;
1220
1221  def : Pat<(i32 (add (i32 (vecreduce_add (vselect (v4i1 VCCR:$pred),
1222                                                   (mul (v4i32 MQPR:$src1), (v4i32 MQPR:$src2)),
1223                                                   (v4i32 ARMimmAllZerosV)))),
1224                      (i32 tGPREven:$src3))),
1225            (i32 (MVE_VMLADAVau32 $src3, $src1, $src2, ARMVCCThen, $pred))>;
1226  def : Pat<(i32 (add (i32 (vecreduce_add (vselect (v8i1 VCCR:$pred),
1227                                                   (mul (v8i16 MQPR:$src1), (v8i16 MQPR:$src2)),
1228                                                   (v8i16 ARMimmAllZerosV)))),
1229                      (i32 tGPREven:$src3))),
1230            (i32 (MVE_VMLADAVau16 $src3, $src1, $src2, ARMVCCThen, $pred))>;
1231  def : Pat<(i32 (add (ARMVMLAVps (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), tGPREven:$Rd)),
1232            (i32 (MVE_VMLADAVas16 tGPREven:$Rd, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred))>;
1233  def : Pat<(i32 (add (ARMVMLAVpu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), tGPREven:$Rd)),
1234            (i32 (MVE_VMLADAVau16 tGPREven:$Rd, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred))>;
1235  def : Pat<(i32 (add (i32 (vecreduce_add (vselect (v16i1 VCCR:$pred),
1236                                                   (mul (v16i8 MQPR:$src1), (v16i8 MQPR:$src2)),
1237                                                   (v16i8 ARMimmAllZerosV)))),
1238                      (i32 tGPREven:$src3))),
1239            (i32 (MVE_VMLADAVau8 $src3, $src1, $src2, ARMVCCThen, $pred))>;
1240  def : Pat<(i32 (add (ARMVMLAVps (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred)), tGPREven:$Rd)),
1241            (i32 (MVE_VMLADAVas8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred))>;
1242  def : Pat<(i32 (add (ARMVMLAVpu (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred)), tGPREven:$Rd)),
1243            (i32 (MVE_VMLADAVau8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred))>;
1244}
1245
1246// vmlav aliases vmladav
1247foreach acc = ["", "a"] in {
1248  foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32"] in {
1249    def : MVEInstAlias<"vmlav"#acc#"${vp}."#suffix#"\t$RdaDest, $Qn, $Qm",
1250                       (!cast<Instruction>("MVE_VMLADAV"#acc#suffix)
1251                        tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
1252  }
1253}
1254
1255// Base class for VMLALDAV and VMLSLDAV, VRMLALDAVH, VRMLSLDAVH
1256class MVE_VMLALDAVBase<string iname, string suffix, dag iops, string cstr,
1257                       bit sz, bit bit_28, bit A, bit X, bit bit_8, bit bit_0,
1258                       list<dag> pattern=[]>
1259  : MVE_rDest<(outs tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest), iops, NoItinerary,
1260              iname, suffix, "$RdaLoDest, $RdaHiDest, $Qn, $Qm", cstr, pattern> {
1261  bits<4> RdaLoDest;
1262  bits<4> RdaHiDest;
1263  bits<3> Qm;
1264  bits<3> Qn;
1265
1266  let Inst{28} = bit_28;
1267  let Inst{22-20} = RdaHiDest{3-1};
1268  let Inst{19-17} = Qn{2-0};
1269  let Inst{16} = sz;
1270  let Inst{15-13} = RdaLoDest{3-1};
1271  let Inst{12} = X;
1272  let Inst{8} = bit_8;
1273  let Inst{7-6} = 0b00;
1274  let Inst{5} = A;
1275  let Inst{3-1} = Qm{2-0};
1276  let Inst{0} = bit_0;
1277  let horizontalReduction = 1;
1278  // Allow tail predication for non-exchanging versions. As this is also a
1279  // horizontalReduction, ARMLowOverheadLoops will also have to check that
1280  // the vector operands contain zeros in their false lanes for the instruction
1281  // to be properly valid.
1282  let validForTailPredication = !eq(X, 0);
1283
1284  let hasSideEffects = 0;
1285}
1286
1287multiclass MVE_VMLALDAVBase_A<string iname, string x, string suffix,
1288                               bit sz, bit bit_28, bit X, bit bit_8, bit bit_0,
1289                               list<dag> pattern=[]> {
1290  def ""#x#suffix : MVE_VMLALDAVBase<
1291     iname # x, suffix, (ins MQPR:$Qn, MQPR:$Qm), "",
1292     sz, bit_28, 0b0, X, bit_8, bit_0, pattern>;
1293  def "a"#x#suffix : MVE_VMLALDAVBase<
1294     iname # "a" # x, suffix,
1295     (ins tGPREven:$RdaLoSrc, tGPROdd:$RdaHiSrc, MQPR:$Qn, MQPR:$Qm),
1296     "$RdaLoDest = $RdaLoSrc,$RdaHiDest = $RdaHiSrc",
1297     sz, bit_28, 0b1, X, bit_8, bit_0, pattern>;
1298}
1299
1300
1301multiclass MVE_VMLALDAVBase_AX<string iname, string suffix, bit sz, bit bit_28,
1302                               bit bit_8, bit bit_0, list<dag> pattern=[]> {
1303  defm "" : MVE_VMLALDAVBase_A<iname, "", suffix, sz,
1304                               bit_28, 0b0, bit_8, bit_0, pattern>;
1305  defm "" : MVE_VMLALDAVBase_A<iname, "x", suffix, sz,
1306                               bit_28, 0b1, bit_8, bit_0, pattern>;
1307}
1308
1309multiclass MVE_VRMLALDAVH_multi<string suffix, list<dag> pattern=[]> {
1310  defm "" : MVE_VMLALDAVBase_AX<"vrmlaldavh", "s"#suffix,
1311                                0b0, 0b0, 0b1, 0b0, pattern>;
1312  defm "" : MVE_VMLALDAVBase_A<"vrmlaldavh", "", "u"#suffix,
1313                               0b0, 0b1, 0b0, 0b1, 0b0, pattern>;
1314}
1315
1316defm MVE_VRMLALDAVH : MVE_VRMLALDAVH_multi<"32">;
1317
1318// vrmlalvh aliases for vrmlaldavh
1319def : MVEInstAlias<"vrmlalvh${vp}.s32\t$RdaLo, $RdaHi, $Qn, $Qm",
1320                  (MVE_VRMLALDAVHs32
1321                   tGPREven:$RdaLo, tGPROdd:$RdaHi,
1322                   MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
1323def : MVEInstAlias<"vrmlalvha${vp}.s32\t$RdaLo, $RdaHi, $Qn, $Qm",
1324                  (MVE_VRMLALDAVHas32
1325                   tGPREven:$RdaLo, tGPROdd:$RdaHi,
1326                   MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
1327def : MVEInstAlias<"vrmlalvh${vp}.u32\t$RdaLo, $RdaHi, $Qn, $Qm",
1328                  (MVE_VRMLALDAVHu32
1329                   tGPREven:$RdaLo, tGPROdd:$RdaHi,
1330                   MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
1331def : MVEInstAlias<"vrmlalvha${vp}.u32\t$RdaLo, $RdaHi, $Qn, $Qm",
1332                  (MVE_VRMLALDAVHau32
1333                   tGPREven:$RdaLo, tGPROdd:$RdaHi,
1334                   MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
1335
1336multiclass MVE_VMLALDAV_multi<string suffix, bit sz, list<dag> pattern=[]> {
1337  defm "" : MVE_VMLALDAVBase_AX<"vmlaldav", "s"#suffix, sz, 0b0, 0b0, 0b0, pattern>;
1338  defm "" : MVE_VMLALDAVBase_A<"vmlaldav", "", "u"#suffix,
1339                               sz, 0b1, 0b0, 0b0, 0b0, pattern>;
1340}
1341
1342defm MVE_VMLALDAV : MVE_VMLALDAV_multi<"16", 0b0>;
1343defm MVE_VMLALDAV : MVE_VMLALDAV_multi<"32", 0b1>;
1344
1345let Predicates = [HasMVEInt] in {
1346  def : Pat<(ARMVMLALVs (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)),
1347            (MVE_VMLALDAVs32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))>;
1348  def : Pat<(ARMVMLALVu (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)),
1349            (MVE_VMLALDAVu32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))>;
1350  def : Pat<(ARMVMLALVs (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)),
1351            (MVE_VMLALDAVs16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))>;
1352  def : Pat<(ARMVMLALVu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)),
1353            (MVE_VMLALDAVu16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))>;
1354
1355  def : Pat<(ARMVMLALVAs tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)),
1356            (MVE_VMLALDAVas32 tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))>;
1357  def : Pat<(ARMVMLALVAu tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)),
1358            (MVE_VMLALDAVau32 tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))>;
1359  def : Pat<(ARMVMLALVAs tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)),
1360            (MVE_VMLALDAVas16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))>;
1361  def : Pat<(ARMVMLALVAu tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)),
1362            (MVE_VMLALDAVau16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))>;
1363
1364  // Predicated
1365  def : Pat<(ARMVMLALVps (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)),
1366            (MVE_VMLALDAVs32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred)>;
1367  def : Pat<(ARMVMLALVpu (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)),
1368            (MVE_VMLALDAVu32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred)>;
1369  def : Pat<(ARMVMLALVps (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)),
1370            (MVE_VMLALDAVs16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred)>;
1371  def : Pat<(ARMVMLALVpu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)),
1372            (MVE_VMLALDAVu16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred)>;
1373
1374  def : Pat<(ARMVMLALVAps tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)),
1375            (MVE_VMLALDAVas32 tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred)>;
1376  def : Pat<(ARMVMLALVApu tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)),
1377            (MVE_VMLALDAVau32 tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred)>;
1378  def : Pat<(ARMVMLALVAps tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)),
1379            (MVE_VMLALDAVas16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred)>;
1380  def : Pat<(ARMVMLALVApu tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)),
1381            (MVE_VMLALDAVau16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred)>;
1382}
1383
1384// vmlalv aliases vmlaldav
1385foreach acc = ["", "a"] in {
1386  foreach suffix = ["s16", "s32", "u16", "u32"] in {
1387    def : MVEInstAlias<"vmlalv" # acc # "${vp}." # suffix #
1388                          "\t$RdaLoDest, $RdaHiDest, $Qn, $Qm",
1389                       (!cast<Instruction>("MVE_VMLALDAV"#acc#suffix)
1390                       tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest,
1391                       MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
1392  }
1393}
1394
1395multiclass MVE_VMLSLDAV_multi<string iname, string suffix, bit sz,
1396                              bit bit_28, list<dag> pattern=[]> {
1397  defm "" : MVE_VMLALDAVBase_AX<iname, suffix, sz, bit_28, 0b0, 0b1, pattern>;
1398}
1399
1400defm MVE_VMLSLDAV   : MVE_VMLSLDAV_multi<"vmlsldav", "s16", 0b0, 0b0>;
1401defm MVE_VMLSLDAV   : MVE_VMLSLDAV_multi<"vmlsldav", "s32", 0b1, 0b0>;
1402defm MVE_VRMLSLDAVH : MVE_VMLSLDAV_multi<"vrmlsldavh", "s32", 0b0, 0b1>;
1403
1404// end of mve_rDest instructions
1405
1406// start of mve_comp instructions
1407
1408class MVE_comp<InstrItinClass itin, string iname, string suffix,
1409               string cstr, list<dag> pattern=[]>
1410  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), itin, iname, suffix,
1411           "$Qd, $Qn, $Qm", vpred_r, cstr, pattern> {
1412  bits<4> Qd;
1413  bits<4> Qn;
1414  bits<4> Qm;
1415
1416  let Inst{22} = Qd{3};
1417  let Inst{19-17} = Qn{2-0};
1418  let Inst{16} = 0b0;
1419  let Inst{15-13} = Qd{2-0};
1420  let Inst{12} = 0b0;
1421  let Inst{10-9} = 0b11;
1422  let Inst{7} = Qn{3};
1423  let Inst{5} = Qm{3};
1424  let Inst{3-1} = Qm{2-0};
1425  let Inst{0} = 0b0;
1426}
1427
1428class MVE_VMINMAXNM<string iname, string suffix, bit sz, bit bit_21,
1429                    list<dag> pattern=[]>
1430  : MVE_comp<NoItinerary, iname, suffix, "", pattern> {
1431
1432  let Inst{28} = 0b1;
1433  let Inst{25-24} = 0b11;
1434  let Inst{23} = 0b0;
1435  let Inst{21} = bit_21;
1436  let Inst{20} = sz;
1437  let Inst{11} = 0b1;
1438  let Inst{8} = 0b1;
1439  let Inst{6} = 0b1;
1440  let Inst{4} = 0b1;
1441
1442  let Predicates = [HasMVEFloat];
1443}
1444
1445multiclass MVE_VMINMAXNM_m<string iname, bit bit_4, MVEVectorVTInfo VTI, SDNode Op, Intrinsic PredInt> {
1446  def "" : MVE_VMINMAXNM<iname, VTI.Suffix, VTI.Size{0}, bit_4>;
1447
1448  let Predicates = [HasMVEFloat] in {
1449    defm : MVE_TwoOpPattern<VTI, Op, PredInt, (? (i32 0)), !cast<Instruction>(NAME)>;
1450  }
1451}
1452
1453defm MVE_VMAXNMf32 : MVE_VMINMAXNM_m<"vmaxnm", 0b0, MVE_v4f32, fmaxnum, int_arm_mve_max_predicated>;
1454defm MVE_VMAXNMf16 : MVE_VMINMAXNM_m<"vmaxnm", 0b0, MVE_v8f16, fmaxnum, int_arm_mve_max_predicated>;
1455defm MVE_VMINNMf32 : MVE_VMINMAXNM_m<"vminnm", 0b1, MVE_v4f32, fminnum, int_arm_mve_min_predicated>;
1456defm MVE_VMINNMf16 : MVE_VMINMAXNM_m<"vminnm", 0b1, MVE_v8f16, fminnum, int_arm_mve_min_predicated>;
1457
1458
1459class MVE_VMINMAX<string iname, string suffix, bit U, bits<2> size,
1460              bit bit_4, list<dag> pattern=[]>
1461  : MVE_comp<NoItinerary, iname, suffix, "", pattern> {
1462
1463  let Inst{28} = U;
1464  let Inst{25-24} = 0b11;
1465  let Inst{23} = 0b0;
1466  let Inst{21-20} = size{1-0};
1467  let Inst{11} = 0b0;
1468  let Inst{8} = 0b0;
1469  let Inst{6} = 0b1;
1470  let Inst{4} = bit_4;
1471  let validForTailPredication = 1;
1472}
1473
1474multiclass MVE_VMINMAX_m<string iname, bit bit_4, MVEVectorVTInfo VTI,
1475                      SDNode Op, Intrinsic PredInt> {
1476  def "" : MVE_VMINMAX<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, bit_4>;
1477
1478  let Predicates = [HasMVEInt] in {
1479    defm : MVE_TwoOpPattern<VTI, Op, PredInt, (? (i32 VTI.Unsigned)), !cast<Instruction>(NAME)>;
1480  }
1481}
1482
1483multiclass MVE_VMAX<MVEVectorVTInfo VTI>
1484  : MVE_VMINMAX_m<"vmax", 0b0, VTI, !if(VTI.Unsigned, umax, smax), int_arm_mve_max_predicated>;
1485multiclass MVE_VMIN<MVEVectorVTInfo VTI>
1486  : MVE_VMINMAX_m<"vmin", 0b1, VTI, !if(VTI.Unsigned, umin, smin), int_arm_mve_min_predicated>;
1487
1488defm MVE_VMINs8   : MVE_VMIN<MVE_v16s8>;
1489defm MVE_VMINs16  : MVE_VMIN<MVE_v8s16>;
1490defm MVE_VMINs32  : MVE_VMIN<MVE_v4s32>;
1491defm MVE_VMINu8   : MVE_VMIN<MVE_v16u8>;
1492defm MVE_VMINu16  : MVE_VMIN<MVE_v8u16>;
1493defm MVE_VMINu32  : MVE_VMIN<MVE_v4u32>;
1494
1495defm MVE_VMAXs8   : MVE_VMAX<MVE_v16s8>;
1496defm MVE_VMAXs16  : MVE_VMAX<MVE_v8s16>;
1497defm MVE_VMAXs32  : MVE_VMAX<MVE_v4s32>;
1498defm MVE_VMAXu8   : MVE_VMAX<MVE_v16u8>;
1499defm MVE_VMAXu16  : MVE_VMAX<MVE_v8u16>;
1500defm MVE_VMAXu32  : MVE_VMAX<MVE_v4u32>;
1501
1502// end of mve_comp instructions
1503
1504// start of mve_bit instructions
1505
1506class MVE_bit_arith<dag oops, dag iops, string iname, string suffix,
1507                    string ops, string cstr, list<dag> pattern=[]>
1508  : MVE_p<oops, iops, NoItinerary, iname, suffix, ops, vpred_r, cstr, pattern> {
1509  bits<4> Qd;
1510  bits<4> Qm;
1511
1512  let Inst{22} = Qd{3};
1513  let Inst{15-13} = Qd{2-0};
1514  let Inst{5} = Qm{3};
1515  let Inst{3-1} = Qm{2-0};
1516}
1517
1518def MVE_VBIC : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm),
1519                             "vbic", "", "$Qd, $Qn, $Qm", ""> {
1520  bits<4> Qn;
1521
1522  let Inst{28} = 0b0;
1523  let Inst{25-23} = 0b110;
1524  let Inst{21-20} = 0b01;
1525  let Inst{19-17} = Qn{2-0};
1526  let Inst{16} = 0b0;
1527  let Inst{12-8} = 0b00001;
1528  let Inst{7} = Qn{3};
1529  let Inst{6} = 0b1;
1530  let Inst{4} = 0b1;
1531  let Inst{0} = 0b0;
1532  let validForTailPredication = 1;
1533}
1534
1535class MVE_VREV<string iname, string suffix, bits<2> size, bits<2> bit_8_7, string cstr="">
1536  : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qm), iname,
1537                  suffix, "$Qd, $Qm", cstr> {
1538
1539  let Inst{28} = 0b1;
1540  let Inst{25-23} = 0b111;
1541  let Inst{21-20} = 0b11;
1542  let Inst{19-18} = size;
1543  let Inst{17-16} = 0b00;
1544  let Inst{12-9} = 0b0000;
1545  let Inst{8-7} = bit_8_7;
1546  let Inst{6} = 0b1;
1547  let Inst{4} = 0b0;
1548  let Inst{0} = 0b0;
1549}
1550
1551def MVE_VREV64_8  : MVE_VREV<"vrev64", "8", 0b00, 0b00, "@earlyclobber $Qd">;
1552def MVE_VREV64_16 : MVE_VREV<"vrev64", "16", 0b01, 0b00, "@earlyclobber $Qd">;
1553def MVE_VREV64_32 : MVE_VREV<"vrev64", "32", 0b10, 0b00, "@earlyclobber $Qd">;
1554
1555def MVE_VREV32_8  : MVE_VREV<"vrev32", "8", 0b00, 0b01>;
1556def MVE_VREV32_16 : MVE_VREV<"vrev32", "16", 0b01, 0b01>;
1557
1558def MVE_VREV16_8  : MVE_VREV<"vrev16", "8", 0b00, 0b10>;
1559
1560let Predicates = [HasMVEInt] in {
1561  def : Pat<(v8i16 (bswap (v8i16 MQPR:$src))),
1562            (v8i16 (MVE_VREV16_8 (v8i16 MQPR:$src)))>;
1563  def : Pat<(v4i32 (bswap (v4i32 MQPR:$src))),
1564            (v4i32 (MVE_VREV32_8 (v4i32 MQPR:$src)))>;
1565}
1566
1567multiclass MVE_VREV_basic_patterns<int revbits, list<MVEVectorVTInfo> VTIs,
1568                                   Instruction Inst> {
1569  defvar unpred_op = !cast<SDNode>("ARMvrev" # revbits);
1570
1571  foreach VTI = VTIs in {
1572    def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$src))),
1573              (VTI.Vec (Inst (VTI.Vec MQPR:$src)))>;
1574    def : Pat<(VTI.Vec (int_arm_mve_vrev_predicated (VTI.Vec MQPR:$src),
1575                  revbits, (VTI.Pred VCCR:$pred), (VTI.Vec MQPR:$inactive))),
1576              (VTI.Vec (Inst (VTI.Vec MQPR:$src), ARMVCCThen,
1577                  (VTI.Pred VCCR:$pred), (VTI.Vec MQPR:$inactive)))>;
1578  }
1579}
1580
1581let Predicates = [HasMVEInt] in {
1582  defm: MVE_VREV_basic_patterns<64, [MVE_v4i32, MVE_v4f32], MVE_VREV64_32>;
1583  defm: MVE_VREV_basic_patterns<64, [MVE_v8i16, MVE_v8f16], MVE_VREV64_16>;
1584  defm: MVE_VREV_basic_patterns<64, [MVE_v16i8           ], MVE_VREV64_8>;
1585
1586  defm: MVE_VREV_basic_patterns<32, [MVE_v8i16, MVE_v8f16], MVE_VREV32_16>;
1587  defm: MVE_VREV_basic_patterns<32, [MVE_v16i8           ], MVE_VREV32_8>;
1588
1589  defm: MVE_VREV_basic_patterns<16, [MVE_v16i8           ], MVE_VREV16_8>;
1590}
1591
1592def MVE_VMVN : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qm),
1593                             "vmvn", "", "$Qd, $Qm", ""> {
1594  let Inst{28} = 0b1;
1595  let Inst{25-23} = 0b111;
1596  let Inst{21-16} = 0b110000;
1597  let Inst{12-6} = 0b0010111;
1598  let Inst{4} = 0b0;
1599  let Inst{0} = 0b0;
1600  let validForTailPredication = 1;
1601}
1602
1603let Predicates = [HasMVEInt] in {
1604  foreach VTI = [ MVE_v16i8, MVE_v8i16, MVE_v4i32, MVE_v2i64 ] in {
1605    def : Pat<(VTI.Vec (vnotq    (VTI.Vec MQPR:$val1))),
1606              (VTI.Vec (MVE_VMVN (VTI.Vec MQPR:$val1)))>;
1607    def : Pat<(VTI.Vec (int_arm_mve_mvn_predicated (VTI.Vec MQPR:$val1),
1608                       (VTI.Pred VCCR:$pred), (VTI.Vec MQPR:$inactive))),
1609              (VTI.Vec (MVE_VMVN (VTI.Vec MQPR:$val1), ARMVCCThen,
1610                       (VTI.Pred VCCR:$pred), (VTI.Vec MQPR:$inactive)))>;
1611  }
1612}
1613
1614class MVE_bit_ops<string iname, bits<2> bit_21_20, bit bit_28>
1615  : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm),
1616                  iname, "", "$Qd, $Qn, $Qm", ""> {
1617  bits<4> Qn;
1618
1619  let Inst{28} = bit_28;
1620  let Inst{25-23} = 0b110;
1621  let Inst{21-20} = bit_21_20;
1622  let Inst{19-17} = Qn{2-0};
1623  let Inst{16} = 0b0;
1624  let Inst{12-8} = 0b00001;
1625  let Inst{7} = Qn{3};
1626  let Inst{6} = 0b1;
1627  let Inst{4} = 0b1;
1628  let Inst{0} = 0b0;
1629  let validForTailPredication = 1;
1630}
1631
1632def MVE_VEOR : MVE_bit_ops<"veor", 0b00, 0b1>;
1633def MVE_VORN : MVE_bit_ops<"vorn", 0b11, 0b0>;
1634def MVE_VORR : MVE_bit_ops<"vorr", 0b10, 0b0>;
1635def MVE_VAND : MVE_bit_ops<"vand", 0b00, 0b0>;
1636
1637// add ignored suffixes as aliases
1638
1639foreach s=["s8", "s16", "s32", "u8", "u16", "u32", "i8", "i16", "i32", "f16", "f32"] in {
1640  def : MVEInstAlias<"vbic${vp}." # s # "\t$QdSrc, $QnSrc, $QmSrc",
1641        (MVE_VBIC MQPR:$QdSrc, MQPR:$QnSrc, MQPR:$QmSrc, vpred_r:$vp)>;
1642  def : MVEInstAlias<"veor${vp}." # s # "\t$QdSrc, $QnSrc, $QmSrc",
1643        (MVE_VEOR MQPR:$QdSrc, MQPR:$QnSrc, MQPR:$QmSrc, vpred_r:$vp)>;
1644  def : MVEInstAlias<"vorn${vp}." # s # "\t$QdSrc, $QnSrc, $QmSrc",
1645        (MVE_VORN MQPR:$QdSrc, MQPR:$QnSrc, MQPR:$QmSrc, vpred_r:$vp)>;
1646  def : MVEInstAlias<"vorr${vp}." # s # "\t$QdSrc, $QnSrc, $QmSrc",
1647        (MVE_VORR MQPR:$QdSrc, MQPR:$QnSrc, MQPR:$QmSrc, vpred_r:$vp)>;
1648  def : MVEInstAlias<"vand${vp}." # s # "\t$QdSrc, $QnSrc, $QmSrc",
1649        (MVE_VAND MQPR:$QdSrc, MQPR:$QnSrc, MQPR:$QmSrc, vpred_r:$vp)>;
1650}
1651
1652let Predicates = [HasMVEInt] in {
1653  defm : MVE_TwoOpPattern<MVE_v16i8, and, int_arm_mve_and_predicated, (? ), MVE_VAND, ARMimmAllOnesV>;
1654  defm : MVE_TwoOpPattern<MVE_v8i16, and, int_arm_mve_and_predicated, (? ), MVE_VAND, ARMimmAllOnesV>;
1655  defm : MVE_TwoOpPattern<MVE_v4i32, and, int_arm_mve_and_predicated, (? ), MVE_VAND, ARMimmAllOnesV>;
1656  defm : MVE_TwoOpPattern<MVE_v2i64, and, int_arm_mve_and_predicated, (? ), MVE_VAND, ARMimmAllOnesV>;
1657
1658  defm : MVE_TwoOpPattern<MVE_v16i8, or, int_arm_mve_orr_predicated, (? ), MVE_VORR, ARMimmAllZerosV>;
1659  defm : MVE_TwoOpPattern<MVE_v8i16, or, int_arm_mve_orr_predicated, (? ), MVE_VORR, ARMimmAllZerosV>;
1660  defm : MVE_TwoOpPattern<MVE_v4i32, or, int_arm_mve_orr_predicated, (? ), MVE_VORR, ARMimmAllZerosV>;
1661  defm : MVE_TwoOpPattern<MVE_v2i64, or, int_arm_mve_orr_predicated, (? ), MVE_VORR, ARMimmAllZerosV>;
1662
1663  defm : MVE_TwoOpPattern<MVE_v16i8, xor, int_arm_mve_eor_predicated, (? ), MVE_VEOR, ARMimmAllZerosV>;
1664  defm : MVE_TwoOpPattern<MVE_v8i16, xor, int_arm_mve_eor_predicated, (? ), MVE_VEOR, ARMimmAllZerosV>;
1665  defm : MVE_TwoOpPattern<MVE_v4i32, xor, int_arm_mve_eor_predicated, (? ), MVE_VEOR, ARMimmAllZerosV>;
1666  defm : MVE_TwoOpPattern<MVE_v2i64, xor, int_arm_mve_eor_predicated, (? ), MVE_VEOR, ARMimmAllZerosV>;
1667
1668  defm : MVE_TwoOpPattern<MVE_v16i8, BinOpFrag<(and node:$LHS, (vnotq node:$RHS))>,
1669                          int_arm_mve_bic_predicated, (? ), MVE_VBIC>;
1670  defm : MVE_TwoOpPattern<MVE_v8i16, BinOpFrag<(and node:$LHS, (vnotq node:$RHS))>,
1671                          int_arm_mve_bic_predicated, (? ), MVE_VBIC>;
1672  defm : MVE_TwoOpPattern<MVE_v4i32, BinOpFrag<(and node:$LHS, (vnotq node:$RHS))>,
1673                          int_arm_mve_bic_predicated, (? ), MVE_VBIC>;
1674  defm : MVE_TwoOpPattern<MVE_v2i64, BinOpFrag<(and node:$LHS, (vnotq node:$RHS))>,
1675                          int_arm_mve_bic_predicated, (? ), MVE_VBIC>;
1676
1677  defm : MVE_TwoOpPattern<MVE_v16i8, BinOpFrag<(or node:$LHS, (vnotq node:$RHS))>,
1678                          int_arm_mve_orn_predicated, (? ), MVE_VORN>;
1679  defm : MVE_TwoOpPattern<MVE_v8i16, BinOpFrag<(or node:$LHS, (vnotq node:$RHS))>,
1680                          int_arm_mve_orn_predicated, (? ), MVE_VORN>;
1681  defm : MVE_TwoOpPattern<MVE_v4i32, BinOpFrag<(or node:$LHS, (vnotq node:$RHS))>,
1682                          int_arm_mve_orn_predicated, (? ), MVE_VORN>;
1683  defm : MVE_TwoOpPattern<MVE_v2i64, BinOpFrag<(or node:$LHS, (vnotq node:$RHS))>,
1684                          int_arm_mve_orn_predicated, (? ), MVE_VORN>;
1685}
1686
1687class MVE_bit_cmode<string iname, string suffix, bit halfword, dag inOps>
1688  : MVE_p<(outs MQPR:$Qd), inOps, NoItinerary,
1689          iname, suffix, "$Qd, $imm", vpred_n, "$Qd = $Qd_src"> {
1690  bits<12> imm;
1691  bits<4> Qd;
1692
1693  let Inst{28} = imm{7};
1694  let Inst{27-23} = 0b11111;
1695  let Inst{22} = Qd{3};
1696  let Inst{21-19} = 0b000;
1697  let Inst{18-16} = imm{6-4};
1698  let Inst{15-13} = Qd{2-0};
1699  let Inst{12} = 0b0;
1700  let Inst{11} = halfword;
1701  let Inst{10} = !if(halfword, 0, imm{10});
1702  let Inst{9} = imm{9};
1703  let Inst{8} = 0b1;
1704  let Inst{7-6} = 0b01;
1705  let Inst{4} = 0b1;
1706  let Inst{3-0} = imm{3-0};
1707}
1708
1709multiclass MVE_bit_cmode_p<string iname, bit opcode,
1710                           MVEVectorVTInfo VTI, Operand imm_type, SDNode op> {
1711  def "" : MVE_bit_cmode<iname, VTI.Suffix, VTI.Size{0},
1712                         (ins MQPR:$Qd_src, imm_type:$imm)> {
1713    let Inst{5} = opcode;
1714    let validForTailPredication = 1;
1715  }
1716
1717  defvar Inst = !cast<Instruction>(NAME);
1718  defvar UnpredPat = (VTI.Vec (op (VTI.Vec MQPR:$src), timm:$simm));
1719
1720  let Predicates = [HasMVEInt] in {
1721    def : Pat<UnpredPat,
1722              (VTI.Vec (Inst (VTI.Vec MQPR:$src), imm_type:$simm))>;
1723    def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
1724                          UnpredPat, (VTI.Vec MQPR:$src))),
1725              (VTI.Vec (Inst (VTI.Vec MQPR:$src), imm_type:$simm,
1726                             ARMVCCThen, (VTI.Pred VCCR:$pred)))>;
1727  }
1728}
1729
1730multiclass MVE_VORRimm<MVEVectorVTInfo VTI, Operand imm_type> {
1731  defm "": MVE_bit_cmode_p<"vorr", 0, VTI, imm_type, ARMvorrImm>;
1732}
1733multiclass MVE_VBICimm<MVEVectorVTInfo VTI, Operand imm_type> {
1734  defm "": MVE_bit_cmode_p<"vbic", 1, VTI, imm_type, ARMvbicImm>;
1735}
1736
1737defm MVE_VORRimmi16 : MVE_VORRimm<MVE_v8i16, nImmSplatI16>;
1738defm MVE_VORRimmi32 : MVE_VORRimm<MVE_v4i32, nImmSplatI32>;
1739defm MVE_VBICimmi16 : MVE_VBICimm<MVE_v8i16, nImmSplatI16>;
1740defm MVE_VBICimmi32 : MVE_VBICimm<MVE_v4i32, nImmSplatI32>;
1741
1742def MVE_VORNimmi16 : MVEInstAlias<"vorn${vp}.i16\t$Qd, $imm",
1743    (MVE_VORRimmi16 MQPR:$Qd, nImmSplatNotI16:$imm, vpred_n:$vp), 0>;
1744def MVE_VORNimmi32 : MVEInstAlias<"vorn${vp}.i32\t$Qd, $imm",
1745    (MVE_VORRimmi32 MQPR:$Qd, nImmSplatNotI32:$imm, vpred_n:$vp), 0>;
1746
1747def MVE_VANDimmi16 : MVEInstAlias<"vand${vp}.i16\t$Qd, $imm",
1748    (MVE_VBICimmi16 MQPR:$Qd, nImmSplatNotI16:$imm, vpred_n:$vp), 0>;
1749def MVE_VANDimmi32 : MVEInstAlias<"vand${vp}.i32\t$Qd, $imm",
1750    (MVE_VBICimmi32 MQPR:$Qd, nImmSplatNotI32:$imm, vpred_n:$vp), 0>;
1751
1752def MVE_VMOV : MVEInstAlias<"vmov${vp}\t$Qd, $Qm",
1753    (MVE_VORR MQPR:$Qd, MQPR:$Qm, MQPR:$Qm, vpred_r:$vp)>;
1754
1755class MVE_VMOV_lane_direction {
1756  bit bit_20;
1757  dag oops;
1758  dag iops;
1759  string ops;
1760  string cstr;
1761}
1762def MVE_VMOV_from_lane : MVE_VMOV_lane_direction {
1763  let bit_20 = 0b1;
1764  let oops = (outs rGPR:$Rt);
1765  let iops = (ins MQPR:$Qd);
1766  let ops = "$Rt, $Qd$Idx";
1767  let cstr = "";
1768}
1769def MVE_VMOV_to_lane : MVE_VMOV_lane_direction {
1770  let bit_20 = 0b0;
1771  let oops = (outs MQPR:$Qd);
1772  let iops = (ins MQPR:$Qd_src, rGPR:$Rt);
1773  let ops = "$Qd$Idx, $Rt";
1774  let cstr = "$Qd = $Qd_src";
1775}
1776
1777class MVE_VMOV_lane<string suffix, bit U, dag indexop,
1778                    MVE_VMOV_lane_direction dir>
1779  : MVE_VMOV_lane_base<dir.oops, !con(dir.iops, indexop), NoItinerary,
1780                       "vmov", suffix, dir.ops, dir.cstr, []> {
1781  bits<4> Qd;
1782  bits<4> Rt;
1783
1784  let Inst{31-24} = 0b11101110;
1785  let Inst{23} = U;
1786  let Inst{20} = dir.bit_20;
1787  let Inst{19-17} = Qd{2-0};
1788  let Inst{15-12} = Rt{3-0};
1789  let Inst{11-8} = 0b1011;
1790  let Inst{7} = Qd{3};
1791  let Inst{4-0} = 0b10000;
1792
1793  let hasSideEffects = 0;
1794}
1795
1796class MVE_VMOV_lane_32<MVE_VMOV_lane_direction dir>
1797    : MVE_VMOV_lane<"32", 0b0, (ins MVEVectorIndex<4>:$Idx), dir> {
1798  bits<2> Idx;
1799  let Inst{22} = 0b0;
1800  let Inst{6-5} = 0b00;
1801  let Inst{16} = Idx{1};
1802  let Inst{21} = Idx{0};
1803
1804  let Predicates = [HasFPRegsV8_1M];
1805}
1806
1807class MVE_VMOV_lane_16<string suffix, bit U, MVE_VMOV_lane_direction dir>
1808  : MVE_VMOV_lane<suffix, U, (ins MVEVectorIndex<8>:$Idx), dir> {
1809  bits<3> Idx;
1810  let Inst{22} = 0b0;
1811  let Inst{5} = 0b1;
1812  let Inst{16} = Idx{2};
1813  let Inst{21} = Idx{1};
1814  let Inst{6} = Idx{0};
1815}
1816
1817class MVE_VMOV_lane_8<string suffix, bit U, MVE_VMOV_lane_direction dir>
1818  : MVE_VMOV_lane<suffix, U, (ins MVEVectorIndex<16>:$Idx), dir> {
1819  bits<4> Idx;
1820  let Inst{22} = 0b1;
1821  let Inst{16} = Idx{3};
1822  let Inst{21} = Idx{2};
1823  let Inst{6} = Idx{1};
1824  let Inst{5} = Idx{0};
1825}
1826
1827def MVE_VMOV_from_lane_32  : MVE_VMOV_lane_32<            MVE_VMOV_from_lane>;
1828def MVE_VMOV_to_lane_32    : MVE_VMOV_lane_32<            MVE_VMOV_to_lane>;
1829def MVE_VMOV_from_lane_s16 : MVE_VMOV_lane_16<"s16", 0b0, MVE_VMOV_from_lane>;
1830def MVE_VMOV_from_lane_u16 : MVE_VMOV_lane_16<"u16", 0b1, MVE_VMOV_from_lane>;
1831def MVE_VMOV_to_lane_16    : MVE_VMOV_lane_16< "16", 0b0, MVE_VMOV_to_lane>;
1832def MVE_VMOV_from_lane_s8  : MVE_VMOV_lane_8 < "s8", 0b0, MVE_VMOV_from_lane>;
1833def MVE_VMOV_from_lane_u8  : MVE_VMOV_lane_8 < "u8", 0b1, MVE_VMOV_from_lane>;
1834def MVE_VMOV_to_lane_8     : MVE_VMOV_lane_8 <  "8", 0b0, MVE_VMOV_to_lane>;
1835
1836let Predicates = [HasMVEInt] in {
1837  def : Pat<(extractelt (v2f64 MQPR:$src), imm:$lane),
1838            (f64 (EXTRACT_SUBREG MQPR:$src, (DSubReg_f64_reg imm:$lane)))>;
1839  def : Pat<(insertelt (v2f64 MQPR:$src1), DPR:$src2, imm:$lane),
1840            (INSERT_SUBREG (v2f64 (COPY_TO_REGCLASS MQPR:$src1, MQPR)), DPR:$src2, (DSubReg_f64_reg imm:$lane))>;
1841
1842  def : Pat<(extractelt (v4i32 MQPR:$src), imm:$lane),
1843            (COPY_TO_REGCLASS
1844              (i32 (EXTRACT_SUBREG MQPR:$src, (SSubReg_f32_reg imm:$lane))), rGPR)>;
1845  def : Pat<(insertelt (v4i32 MQPR:$src1), rGPR:$src2, imm:$lane),
1846            (MVE_VMOV_to_lane_32 MQPR:$src1, rGPR:$src2, imm:$lane)>;
1847
1848  def : Pat<(vector_insert (v16i8 MQPR:$src1), rGPR:$src2, imm:$lane),
1849            (MVE_VMOV_to_lane_8  MQPR:$src1, rGPR:$src2, imm:$lane)>;
1850  def : Pat<(vector_insert (v8i16 MQPR:$src1), rGPR:$src2, imm:$lane),
1851            (MVE_VMOV_to_lane_16 MQPR:$src1, rGPR:$src2, imm:$lane)>;
1852
1853  def : Pat<(ARMvgetlanes (v16i8 MQPR:$src), imm:$lane),
1854            (MVE_VMOV_from_lane_s8 MQPR:$src, imm:$lane)>;
1855  def : Pat<(ARMvgetlanes (v8i16 MQPR:$src), imm:$lane),
1856            (MVE_VMOV_from_lane_s16 MQPR:$src, imm:$lane)>;
1857  def : Pat<(ARMvgetlanes (v8f16 MQPR:$src), imm:$lane),
1858            (MVE_VMOV_from_lane_s16 MQPR:$src, imm:$lane)>;
1859  def : Pat<(ARMvgetlaneu (v16i8 MQPR:$src), imm:$lane),
1860            (MVE_VMOV_from_lane_u8 MQPR:$src, imm:$lane)>;
1861  def : Pat<(ARMvgetlaneu (v8i16 MQPR:$src), imm:$lane),
1862            (MVE_VMOV_from_lane_u16 MQPR:$src, imm:$lane)>;
1863  def : Pat<(ARMvgetlaneu (v8f16 MQPR:$src), imm:$lane),
1864            (MVE_VMOV_from_lane_u16 MQPR:$src, imm:$lane)>;
1865
1866  def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
1867            (MVE_VMOV_to_lane_8  (v16i8 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>;
1868  def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
1869            (MVE_VMOV_to_lane_16 (v8i16 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>;
1870  def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
1871            (MVE_VMOV_to_lane_32 (v4i32 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>;
1872
1873  // Floating point patterns, still enabled under HasMVEInt
1874  def : Pat<(extractelt (v4f32 MQPR:$src), imm:$lane),
1875            (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG MQPR:$src, (SSubReg_f32_reg imm:$lane))), SPR)>;
1876  def : Pat<(insertelt (v4f32 MQPR:$src1), (f32 SPR:$src2), imm:$lane),
1877            (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS MQPR:$src1, MQPR)), SPR:$src2, (SSubReg_f32_reg imm:$lane))>;
1878
1879  def : Pat<(insertelt (v8f16 MQPR:$src1), (f16 HPR:$src2), imm:$lane),
1880            (MVE_VMOV_to_lane_16 MQPR:$src1, (COPY_TO_REGCLASS (f16 HPR:$src2), rGPR), imm:$lane)>;
1881  def : Pat<(extractelt (v8f16 MQPR:$src), imm_even:$lane),
1882            (EXTRACT_SUBREG MQPR:$src, (SSubReg_f16_reg imm_even:$lane))>;
1883  def : Pat<(extractelt (v8f16 MQPR:$src), imm_odd:$lane),
1884            (COPY_TO_REGCLASS
1885              (VMOVH (EXTRACT_SUBREG MQPR:$src, (SSubReg_f16_reg imm_odd:$lane))),
1886              HPR)>;
1887
1888  def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
1889            (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
1890  def : Pat<(v4f32 (scalar_to_vector GPR:$src)),
1891            (MVE_VMOV_to_lane_32 (v4f32 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>;
1892  def : Pat<(v8f16 (scalar_to_vector (f16 HPR:$src))),
1893            (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), (f16 HPR:$src), ssub_0)>;
1894  def : Pat<(v8f16 (scalar_to_vector GPR:$src)),
1895            (MVE_VMOV_to_lane_16 (v8f16 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>;
1896}
1897
1898// end of mve_bit instructions
1899
1900// start of MVE Integer instructions
1901
1902class MVE_int<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
1903  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), NoItinerary,
1904          iname, suffix, "$Qd, $Qn, $Qm", vpred_r, "", pattern> {
1905  bits<4> Qd;
1906  bits<4> Qn;
1907  bits<4> Qm;
1908
1909  let Inst{22} = Qd{3};
1910  let Inst{21-20} = size;
1911  let Inst{19-17} = Qn{2-0};
1912  let Inst{15-13} = Qd{2-0};
1913  let Inst{7} = Qn{3};
1914  let Inst{6} = 0b1;
1915  let Inst{5} = Qm{3};
1916  let Inst{3-1} = Qm{2-0};
1917}
1918
1919class MVE_VMULt1<string iname, string suffix, bits<2> size,
1920                   list<dag> pattern=[]>
1921  : MVE_int<iname, suffix, size, pattern> {
1922
1923  let Inst{28} = 0b0;
1924  let Inst{25-23} = 0b110;
1925  let Inst{16} = 0b0;
1926  let Inst{12-8} = 0b01001;
1927  let Inst{4} = 0b1;
1928  let Inst{0} = 0b0;
1929  let validForTailPredication = 1;
1930}
1931
1932multiclass MVE_VMUL_m<MVEVectorVTInfo VTI> {
1933  def "" : MVE_VMULt1<"vmul", VTI.Suffix, VTI.Size>;
1934
1935  let Predicates = [HasMVEInt] in {
1936    defm : MVE_TwoOpPattern<VTI, mul, int_arm_mve_mul_predicated, (? ),
1937                            !cast<Instruction>(NAME), ARMimmOneV>;
1938  }
1939}
1940
1941defm MVE_VMULi8  : MVE_VMUL_m<MVE_v16i8>;
1942defm MVE_VMULi16 : MVE_VMUL_m<MVE_v8i16>;
1943defm MVE_VMULi32 : MVE_VMUL_m<MVE_v4i32>;
1944
1945class MVE_VQxDMULH_Base<string iname, string suffix, bits<2> size, bit rounding,
1946                  list<dag> pattern=[]>
1947  : MVE_int<iname, suffix, size, pattern> {
1948
1949  let Inst{28} = rounding;
1950  let Inst{25-23} = 0b110;
1951  let Inst{16} = 0b0;
1952  let Inst{12-8} = 0b01011;
1953  let Inst{4} = 0b0;
1954  let Inst{0} = 0b0;
1955  let validForTailPredication = 1;
1956}
1957
1958def MVEvqdmulh : SDNode<"ARMISD::VQDMULH", SDTIntBinOp>;
1959
1960multiclass MVE_VQxDMULH_m<string iname, MVEVectorVTInfo VTI,
1961                      SDNode Op, Intrinsic unpred_int, Intrinsic pred_int,
1962                      bit rounding> {
1963  def "" : MVE_VQxDMULH_Base<iname, VTI.Suffix, VTI.Size, rounding>;
1964  defvar Inst = !cast<Instruction>(NAME);
1965
1966  let Predicates = [HasMVEInt] in {
1967    defm : MVE_TwoOpPattern<VTI, Op, pred_int, (? ), Inst>;
1968
1969    // Extra unpredicated multiply intrinsic patterns
1970    def : Pat<(VTI.Vec (unpred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn))),
1971              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
1972  }
1973}
1974
1975multiclass MVE_VQxDMULH<string iname, MVEVectorVTInfo VTI, bit rounding>
1976  : MVE_VQxDMULH_m<iname, VTI, !if(rounding, null_frag,
1977                                             MVEvqdmulh),
1978                               !if(rounding, int_arm_mve_vqrdmulh,
1979                                             int_arm_mve_vqdmulh),
1980                               !if(rounding, int_arm_mve_qrdmulh_predicated,
1981                                             int_arm_mve_qdmulh_predicated),
1982                   rounding>;
1983
1984defm MVE_VQDMULHi8  : MVE_VQxDMULH<"vqdmulh", MVE_v16s8, 0b0>;
1985defm MVE_VQDMULHi16 : MVE_VQxDMULH<"vqdmulh", MVE_v8s16, 0b0>;
1986defm MVE_VQDMULHi32 : MVE_VQxDMULH<"vqdmulh", MVE_v4s32, 0b0>;
1987
1988defm MVE_VQRDMULHi8  : MVE_VQxDMULH<"vqrdmulh", MVE_v16s8, 0b1>;
1989defm MVE_VQRDMULHi16 : MVE_VQxDMULH<"vqrdmulh", MVE_v8s16, 0b1>;
1990defm MVE_VQRDMULHi32 : MVE_VQxDMULH<"vqrdmulh", MVE_v4s32, 0b1>;
1991
1992class MVE_VADDSUB<string iname, string suffix, bits<2> size, bit subtract,
1993                    list<dag> pattern=[]>
1994  : MVE_int<iname, suffix, size, pattern> {
1995
1996  let Inst{28} = subtract;
1997  let Inst{25-23} = 0b110;
1998  let Inst{16} = 0b0;
1999  let Inst{12-8} = 0b01000;
2000  let Inst{4} = 0b0;
2001  let Inst{0} = 0b0;
2002  let validForTailPredication = 1;
2003}
2004
2005multiclass MVE_VADDSUB_m<string iname, MVEVectorVTInfo VTI, bit subtract,
2006                         SDNode Op, Intrinsic PredInt> {
2007  def "" : MVE_VADDSUB<iname, VTI.Suffix, VTI.Size, subtract>;
2008  defvar Inst = !cast<Instruction>(NAME);
2009
2010  let Predicates = [HasMVEInt] in {
2011    defm : MVE_TwoOpPattern<VTI, Op, PredInt, (? ), !cast<Instruction>(NAME), ARMimmAllZerosV>;
2012  }
2013}
2014
2015multiclass MVE_VADD<MVEVectorVTInfo VTI>
2016  : MVE_VADDSUB_m<"vadd", VTI, 0b0, add, int_arm_mve_add_predicated>;
2017multiclass MVE_VSUB<MVEVectorVTInfo VTI>
2018  : MVE_VADDSUB_m<"vsub", VTI, 0b1, sub, int_arm_mve_sub_predicated>;
2019
2020defm MVE_VADDi8  : MVE_VADD<MVE_v16i8>;
2021defm MVE_VADDi16 : MVE_VADD<MVE_v8i16>;
2022defm MVE_VADDi32 : MVE_VADD<MVE_v4i32>;
2023
2024defm MVE_VSUBi8  : MVE_VSUB<MVE_v16i8>;
2025defm MVE_VSUBi16 : MVE_VSUB<MVE_v8i16>;
2026defm MVE_VSUBi32 : MVE_VSUB<MVE_v4i32>;
2027
2028class MVE_VQADDSUB<string iname, string suffix, bit U, bit subtract,
2029                   bits<2> size>
2030  : MVE_int<iname, suffix, size, []> {
2031
2032  let Inst{28} = U;
2033  let Inst{25-23} = 0b110;
2034  let Inst{16} = 0b0;
2035  let Inst{12-10} = 0b000;
2036  let Inst{9} = subtract;
2037  let Inst{8} = 0b0;
2038  let Inst{4} = 0b1;
2039  let Inst{0} = 0b0;
2040  let validForTailPredication = 1;
2041}
2042
2043class MVE_VQADD_<string suffix, bit U, bits<2> size>
2044  : MVE_VQADDSUB<"vqadd", suffix, U, 0b0, size>;
2045class MVE_VQSUB_<string suffix, bit U, bits<2> size>
2046  : MVE_VQADDSUB<"vqsub", suffix, U, 0b1, size>;
2047
2048multiclass MVE_VQADD_m<MVEVectorVTInfo VTI,
2049                      SDNode Op, Intrinsic PredInt> {
2050  def "" : MVE_VQADD_<VTI.Suffix, VTI.Unsigned, VTI.Size>;
2051  defvar Inst = !cast<Instruction>(NAME);
2052
2053  let Predicates = [HasMVEInt] in {
2054    defm : MVE_TwoOpPattern<VTI, Op, PredInt, (? (i32 VTI.Unsigned)),
2055                            !cast<Instruction>(NAME)>;
2056  }
2057}
2058
2059multiclass MVE_VQADD<MVEVectorVTInfo VTI, SDNode unpred_op>
2060  : MVE_VQADD_m<VTI, unpred_op, int_arm_mve_qadd_predicated>;
2061
2062defm MVE_VQADDs8  : MVE_VQADD<MVE_v16s8, saddsat>;
2063defm MVE_VQADDs16 : MVE_VQADD<MVE_v8s16, saddsat>;
2064defm MVE_VQADDs32 : MVE_VQADD<MVE_v4s32, saddsat>;
2065defm MVE_VQADDu8  : MVE_VQADD<MVE_v16u8, uaddsat>;
2066defm MVE_VQADDu16 : MVE_VQADD<MVE_v8u16, uaddsat>;
2067defm MVE_VQADDu32 : MVE_VQADD<MVE_v4u32, uaddsat>;
2068
2069multiclass MVE_VQSUB_m<MVEVectorVTInfo VTI,
2070                      SDNode Op, Intrinsic PredInt> {
2071  def "" : MVE_VQSUB_<VTI.Suffix, VTI.Unsigned, VTI.Size>;
2072  defvar Inst = !cast<Instruction>(NAME);
2073
2074  let Predicates = [HasMVEInt] in {
2075    defm : MVE_TwoOpPattern<VTI, Op, PredInt, (? (i32 VTI.Unsigned)),
2076                            !cast<Instruction>(NAME)>;
2077  }
2078}
2079
2080multiclass MVE_VQSUB<MVEVectorVTInfo VTI, SDNode unpred_op>
2081  : MVE_VQSUB_m<VTI, unpred_op, int_arm_mve_qsub_predicated>;
2082
2083defm MVE_VQSUBs8  : MVE_VQSUB<MVE_v16s8, ssubsat>;
2084defm MVE_VQSUBs16 : MVE_VQSUB<MVE_v8s16, ssubsat>;
2085defm MVE_VQSUBs32 : MVE_VQSUB<MVE_v4s32, ssubsat>;
2086defm MVE_VQSUBu8  : MVE_VQSUB<MVE_v16u8, usubsat>;
2087defm MVE_VQSUBu16 : MVE_VQSUB<MVE_v8u16, usubsat>;
2088defm MVE_VQSUBu32 : MVE_VQSUB<MVE_v4u32, usubsat>;
2089
2090class MVE_VABD_int<string suffix, bit U, bits<2> size,
2091                     list<dag> pattern=[]>
2092  : MVE_int<"vabd", suffix, size, pattern> {
2093
2094  let Inst{28} = U;
2095  let Inst{25-23} = 0b110;
2096  let Inst{16} = 0b0;
2097  let Inst{12-8} = 0b00111;
2098  let Inst{4} = 0b0;
2099  let Inst{0} = 0b0;
2100  let validForTailPredication = 1;
2101}
2102
2103multiclass MVE_VABD_m<MVEVectorVTInfo VTI,
2104                      Intrinsic unpred_int, Intrinsic pred_int> {
2105  def "" : MVE_VABD_int<VTI.Suffix, VTI.Unsigned, VTI.Size>;
2106  defvar Inst = !cast<Instruction>(NAME);
2107
2108  let Predicates = [HasMVEInt] in {
2109    // Unpredicated absolute difference
2110    def : Pat<(VTI.Vec (unpred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
2111                            (i32 VTI.Unsigned))),
2112              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
2113
2114    // Predicated absolute difference
2115    def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
2116                            (i32 VTI.Unsigned), (VTI.Pred VCCR:$mask),
2117                            (VTI.Vec MQPR:$inactive))),
2118              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
2119                             ARMVCCThen, (VTI.Pred VCCR:$mask),
2120                             (VTI.Vec MQPR:$inactive)))>;
2121  }
2122}
2123
2124multiclass MVE_VABD<MVEVectorVTInfo VTI>
2125  : MVE_VABD_m<VTI, int_arm_mve_vabd, int_arm_mve_abd_predicated>;
2126
2127defm MVE_VABDs8  : MVE_VABD<MVE_v16s8>;
2128defm MVE_VABDs16 : MVE_VABD<MVE_v8s16>;
2129defm MVE_VABDs32 : MVE_VABD<MVE_v4s32>;
2130defm MVE_VABDu8  : MVE_VABD<MVE_v16u8>;
2131defm MVE_VABDu16 : MVE_VABD<MVE_v8u16>;
2132defm MVE_VABDu32 : MVE_VABD<MVE_v4u32>;
2133
2134class MVE_VRHADD_Base<string suffix, bit U, bits<2> size, list<dag> pattern=[]>
2135  : MVE_int<"vrhadd", suffix, size, pattern> {
2136
2137  let Inst{28} = U;
2138  let Inst{25-23} = 0b110;
2139  let Inst{16} = 0b0;
2140  let Inst{12-8} = 0b00001;
2141  let Inst{4} = 0b0;
2142  let Inst{0} = 0b0;
2143  let validForTailPredication = 1;
2144}
2145
2146def addnuw : PatFrag<(ops node:$lhs, node:$rhs),
2147                     (add node:$lhs, node:$rhs), [{
2148  return N->getFlags().hasNoUnsignedWrap();
2149}]>;
2150
2151def addnsw : PatFrag<(ops node:$lhs, node:$rhs),
2152                     (add node:$lhs, node:$rhs), [{
2153  return N->getFlags().hasNoSignedWrap();
2154}]>;
2155
2156def subnuw : PatFrag<(ops node:$lhs, node:$rhs),
2157                     (sub node:$lhs, node:$rhs), [{
2158  return N->getFlags().hasNoUnsignedWrap();
2159}]>;
2160
2161def subnsw : PatFrag<(ops node:$lhs, node:$rhs),
2162                     (sub node:$lhs, node:$rhs), [{
2163  return N->getFlags().hasNoSignedWrap();
2164}]>;
2165
2166multiclass MVE_VRHADD_m<MVEVectorVTInfo VTI,
2167                      SDNode unpred_op, Intrinsic pred_int> {
2168  def "" : MVE_VRHADD_Base<VTI.Suffix, VTI.Unsigned, VTI.Size>;
2169  defvar Inst = !cast<Instruction>(NAME);
2170
2171  let Predicates = [HasMVEInt] in {
2172    // Unpredicated rounding add-with-divide-by-two
2173    def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
2174                            (i32 VTI.Unsigned))),
2175              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
2176
2177    // Predicated add-with-divide-by-two
2178    def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
2179                            (i32 VTI.Unsigned), (VTI.Pred VCCR:$mask),
2180                            (VTI.Vec MQPR:$inactive))),
2181              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
2182                             ARMVCCThen, (VTI.Pred VCCR:$mask),
2183                             (VTI.Vec MQPR:$inactive)))>;
2184  }
2185}
2186
2187multiclass MVE_VRHADD<MVEVectorVTInfo VTI>
2188  : MVE_VRHADD_m<VTI, int_arm_mve_vrhadd, int_arm_mve_rhadd_predicated>;
2189
2190defm MVE_VRHADDs8  : MVE_VRHADD<MVE_v16s8>;
2191defm MVE_VRHADDs16 : MVE_VRHADD<MVE_v8s16>;
2192defm MVE_VRHADDs32 : MVE_VRHADD<MVE_v4s32>;
2193defm MVE_VRHADDu8  : MVE_VRHADD<MVE_v16u8>;
2194defm MVE_VRHADDu16 : MVE_VRHADD<MVE_v8u16>;
2195defm MVE_VRHADDu32 : MVE_VRHADD<MVE_v4u32>;
2196
2197// Rounding Halving Add perform the arithemtic operation with an extra bit of
2198// precision, before performing the shift, to void clipping errors. We're not
2199// modelling that here with these patterns, but we're using no wrap forms of
2200// add to ensure that the extra bit of information is not needed for the
2201// arithmetic or the rounding.
2202let Predicates = [HasMVEInt] in {
2203  def : Pat<(v16i8 (ARMvshrsImm (addnsw (addnsw (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn)),
2204                                        (v16i8 (ARMvmovImm (i32 3585)))),
2205                                (i32 1))),
2206            (MVE_VRHADDs8 MQPR:$Qm, MQPR:$Qn)>;
2207  def : Pat<(v8i16 (ARMvshrsImm (addnsw (addnsw (v8i16 MQPR:$Qm), (v8i16 MQPR:$Qn)),
2208                                        (v8i16 (ARMvmovImm (i32 2049)))),
2209                                (i32 1))),
2210            (MVE_VRHADDs16 MQPR:$Qm, MQPR:$Qn)>;
2211  def : Pat<(v4i32 (ARMvshrsImm (addnsw (addnsw (v4i32 MQPR:$Qm), (v4i32 MQPR:$Qn)),
2212                                        (v4i32 (ARMvmovImm (i32 1)))),
2213                                (i32 1))),
2214            (MVE_VRHADDs32 MQPR:$Qm, MQPR:$Qn)>;
2215  def : Pat<(v16i8 (ARMvshruImm (addnuw (addnuw (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn)),
2216                                        (v16i8 (ARMvmovImm (i32 3585)))),
2217                                (i32 1))),
2218            (MVE_VRHADDu8 MQPR:$Qm, MQPR:$Qn)>;
2219  def : Pat<(v8i16 (ARMvshruImm (addnuw (addnuw (v8i16 MQPR:$Qm), (v8i16 MQPR:$Qn)),
2220                                        (v8i16 (ARMvmovImm (i32 2049)))),
2221                                (i32 1))),
2222            (MVE_VRHADDu16 MQPR:$Qm, MQPR:$Qn)>;
2223  def : Pat<(v4i32 (ARMvshruImm (addnuw (addnuw (v4i32 MQPR:$Qm), (v4i32 MQPR:$Qn)),
2224                                        (v4i32 (ARMvmovImm (i32 1)))),
2225                                (i32 1))),
2226            (MVE_VRHADDu32 MQPR:$Qm, MQPR:$Qn)>;
2227}
2228
2229
2230class MVE_VHADDSUB<string iname, string suffix, bit U, bit subtract,
2231                   bits<2> size, list<dag> pattern=[]>
2232  : MVE_int<iname, suffix, size, pattern> {
2233
2234  let Inst{28} = U;
2235  let Inst{25-23} = 0b110;
2236  let Inst{16} = 0b0;
2237  let Inst{12-10} = 0b000;
2238  let Inst{9} = subtract;
2239  let Inst{8} = 0b0;
2240  let Inst{4} = 0b0;
2241  let Inst{0} = 0b0;
2242  let validForTailPredication = 1;
2243}
2244
2245class MVE_VHADD_<string suffix, bit U, bits<2> size,
2246              list<dag> pattern=[]>
2247  : MVE_VHADDSUB<"vhadd", suffix, U, 0b0, size, pattern>;
2248class MVE_VHSUB_<string suffix, bit U, bits<2> size,
2249              list<dag> pattern=[]>
2250  : MVE_VHADDSUB<"vhsub", suffix, U, 0b1, size, pattern>;
2251
2252multiclass MVE_VHADD_m<MVEVectorVTInfo VTI,
2253                      SDNode unpred_op, Intrinsic pred_int, PatFrag add_op,
2254                      SDNode shift_op> {
2255  def "" : MVE_VHADD_<VTI.Suffix, VTI.Unsigned, VTI.Size>;
2256  defvar Inst = !cast<Instruction>(NAME);
2257
2258  let Predicates = [HasMVEInt] in {
2259    // Unpredicated add-and-divide-by-two
2260    def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (i32 VTI.Unsigned))),
2261              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
2262
2263    def : Pat<(VTI.Vec (shift_op (add_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)), (i32 1))),
2264              (Inst MQPR:$Qm, MQPR:$Qn)>;
2265
2266    // Predicated add-and-divide-by-two
2267    def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (i32 VTI.Unsigned),
2268                            (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))),
2269              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
2270                             ARMVCCThen, (VTI.Pred VCCR:$mask),
2271                             (VTI.Vec MQPR:$inactive)))>;
2272  }
2273}
2274
2275multiclass MVE_VHADD<MVEVectorVTInfo VTI, PatFrag add_op, SDNode shift_op>
2276  : MVE_VHADD_m<VTI, int_arm_mve_vhadd, int_arm_mve_hadd_predicated, add_op,
2277                shift_op>;
2278
2279// Halving add/sub perform the arithemtic operation with an extra bit of
2280// precision, before performing the shift, to void clipping errors. We're not
2281// modelling that here with these patterns, but we're using no wrap forms of
2282// add/sub to ensure that the extra bit of information is not needed.
2283defm MVE_VHADDs8  : MVE_VHADD<MVE_v16s8, addnsw, ARMvshrsImm>;
2284defm MVE_VHADDs16 : MVE_VHADD<MVE_v8s16, addnsw, ARMvshrsImm>;
2285defm MVE_VHADDs32 : MVE_VHADD<MVE_v4s32, addnsw, ARMvshrsImm>;
2286defm MVE_VHADDu8  : MVE_VHADD<MVE_v16u8, addnuw, ARMvshruImm>;
2287defm MVE_VHADDu16 : MVE_VHADD<MVE_v8u16, addnuw, ARMvshruImm>;
2288defm MVE_VHADDu32 : MVE_VHADD<MVE_v4u32, addnuw, ARMvshruImm>;
2289
2290multiclass MVE_VHSUB_m<MVEVectorVTInfo VTI,
2291                      SDNode unpred_op, Intrinsic pred_int, PatFrag sub_op,
2292                      SDNode shift_op> {
2293  def "" : MVE_VHSUB_<VTI.Suffix, VTI.Unsigned, VTI.Size>;
2294  defvar Inst = !cast<Instruction>(NAME);
2295
2296  let Predicates = [HasMVEInt] in {
2297    // Unpredicated subtract-and-divide-by-two
2298    def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
2299                            (i32 VTI.Unsigned))),
2300              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
2301
2302    def : Pat<(VTI.Vec (shift_op (sub_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)), (i32 1))),
2303              (Inst MQPR:$Qm, MQPR:$Qn)>;
2304
2305
2306    // Predicated subtract-and-divide-by-two
2307    def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
2308                            (i32 VTI.Unsigned), (VTI.Pred VCCR:$mask),
2309                            (VTI.Vec MQPR:$inactive))),
2310              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
2311                             ARMVCCThen, (VTI.Pred VCCR:$mask),
2312                             (VTI.Vec MQPR:$inactive)))>;
2313  }
2314}
2315
2316multiclass MVE_VHSUB<MVEVectorVTInfo VTI, PatFrag sub_op, SDNode shift_op>
2317  : MVE_VHSUB_m<VTI, int_arm_mve_vhsub, int_arm_mve_hsub_predicated, sub_op,
2318                shift_op>;
2319
2320defm MVE_VHSUBs8  : MVE_VHSUB<MVE_v16s8, subnsw, ARMvshrsImm>;
2321defm MVE_VHSUBs16 : MVE_VHSUB<MVE_v8s16, subnsw, ARMvshrsImm>;
2322defm MVE_VHSUBs32 : MVE_VHSUB<MVE_v4s32, subnsw, ARMvshrsImm>;
2323defm MVE_VHSUBu8  : MVE_VHSUB<MVE_v16u8, subnuw, ARMvshruImm>;
2324defm MVE_VHSUBu16 : MVE_VHSUB<MVE_v8u16, subnuw, ARMvshruImm>;
2325defm MVE_VHSUBu32 : MVE_VHSUB<MVE_v4u32, subnuw, ARMvshruImm>;
2326
2327class MVE_VDUP<string suffix, bit B, bit E, list<dag> pattern=[]>
2328  : MVE_p<(outs MQPR:$Qd), (ins rGPR:$Rt), NoItinerary,
2329          "vdup", suffix, "$Qd, $Rt", vpred_r, "", pattern> {
2330  bits<4> Qd;
2331  bits<4> Rt;
2332
2333  let Inst{28} = 0b0;
2334  let Inst{25-23} = 0b101;
2335  let Inst{22} = B;
2336  let Inst{21-20} = 0b10;
2337  let Inst{19-17} = Qd{2-0};
2338  let Inst{16} = 0b0;
2339  let Inst{15-12} = Rt;
2340  let Inst{11-8} = 0b1011;
2341  let Inst{7} = Qd{3};
2342  let Inst{6} = 0b0;
2343  let Inst{5} = E;
2344  let Inst{4-0} = 0b10000;
2345  let validForTailPredication = 1;
2346}
2347
2348def MVE_VDUP32 : MVE_VDUP<"32", 0b0, 0b0>;
2349def MVE_VDUP16 : MVE_VDUP<"16", 0b0, 0b1>;
2350def MVE_VDUP8  : MVE_VDUP<"8",  0b1, 0b0>;
2351
2352let Predicates = [HasMVEInt] in {
2353  def : Pat<(v16i8 (ARMvdup (i32 rGPR:$elem))),
2354            (MVE_VDUP8  rGPR:$elem)>;
2355  def : Pat<(v8i16 (ARMvdup (i32 rGPR:$elem))),
2356            (MVE_VDUP16 rGPR:$elem)>;
2357  def : Pat<(v4i32 (ARMvdup (i32 rGPR:$elem))),
2358            (MVE_VDUP32 rGPR:$elem)>;
2359
2360  def : Pat<(v8f16 (ARMvdup (i32 rGPR:$elem))),
2361            (MVE_VDUP16 rGPR:$elem)>;
2362  def : Pat<(v4f32 (ARMvdup (i32 rGPR:$elem))),
2363            (MVE_VDUP32 rGPR:$elem)>;
2364
2365  // Match a vselect with an ARMvdup as a predicated MVE_VDUP
2366  def : Pat<(v16i8 (vselect (v16i1 VCCR:$pred),
2367                            (v16i8 (ARMvdup (i32 rGPR:$elem))),
2368                            (v16i8 MQPR:$inactive))),
2369            (MVE_VDUP8  rGPR:$elem, ARMVCCThen, (v16i1 VCCR:$pred),
2370                        (v16i8 MQPR:$inactive))>;
2371  def : Pat<(v8i16 (vselect (v8i1 VCCR:$pred),
2372                            (v8i16 (ARMvdup (i32 rGPR:$elem))),
2373                            (v8i16 MQPR:$inactive))),
2374            (MVE_VDUP16 rGPR:$elem, ARMVCCThen, (v8i1 VCCR:$pred),
2375                            (v8i16 MQPR:$inactive))>;
2376  def : Pat<(v4i32 (vselect (v4i1 VCCR:$pred),
2377                            (v4i32 (ARMvdup (i32 rGPR:$elem))),
2378                            (v4i32 MQPR:$inactive))),
2379            (MVE_VDUP32 rGPR:$elem, ARMVCCThen, (v4i1 VCCR:$pred),
2380                            (v4i32 MQPR:$inactive))>;
2381  def : Pat<(v4f32 (vselect (v4i1 VCCR:$pred),
2382                            (v4f32 (ARMvdup (i32 rGPR:$elem))),
2383                            (v4f32 MQPR:$inactive))),
2384            (MVE_VDUP32 rGPR:$elem, ARMVCCThen, (v4i1 VCCR:$pred),
2385                            (v4f32 MQPR:$inactive))>;
2386  def : Pat<(v8f16 (vselect (v8i1 VCCR:$pred),
2387                            (v8f16 (ARMvdup (i32 rGPR:$elem))),
2388                            (v8f16 MQPR:$inactive))),
2389            (MVE_VDUP16 rGPR:$elem, ARMVCCThen, (v8i1 VCCR:$pred),
2390                            (v8f16 MQPR:$inactive))>;
2391}
2392
2393
2394class MVEIntSingleSrc<string iname, string suffix, bits<2> size,
2395                         list<dag> pattern=[]>
2396  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qm), NoItinerary,
2397          iname, suffix, "$Qd, $Qm", vpred_r, "", pattern> {
2398  bits<4> Qd;
2399  bits<4> Qm;
2400
2401  let Inst{22} = Qd{3};
2402  let Inst{19-18} = size{1-0};
2403  let Inst{15-13} = Qd{2-0};
2404  let Inst{5} = Qm{3};
2405  let Inst{3-1} = Qm{2-0};
2406}
2407
2408class MVE_VCLSCLZ<string iname, string suffix, bits<2> size,
2409                   bit count_zeroes, list<dag> pattern=[]>
2410  : MVEIntSingleSrc<iname, suffix, size, pattern> {
2411
2412  let Inst{28} = 0b1;
2413  let Inst{25-23} = 0b111;
2414  let Inst{21-20} = 0b11;
2415  let Inst{17-16} = 0b00;
2416  let Inst{12-8} = 0b00100;
2417  let Inst{7} = count_zeroes;
2418  let Inst{6} = 0b1;
2419  let Inst{4} = 0b0;
2420  let Inst{0} = 0b0;
2421  let validForTailPredication = 1;
2422}
2423
2424multiclass MVE_VCLSCLZ_p<string opname, bit opcode, MVEVectorVTInfo VTI,
2425                         SDNode unpred_op> {
2426  def "": MVE_VCLSCLZ<"v"#opname, VTI.Suffix, VTI.Size, opcode>;
2427
2428  defvar Inst     = !cast<Instruction>(NAME);
2429  defvar pred_int = !cast<Intrinsic>("int_arm_mve_"#opname#"_predicated");
2430
2431  let Predicates = [HasMVEInt] in {
2432    def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$val))),
2433              (VTI.Vec (Inst (VTI.Vec MQPR:$val)))>;
2434    def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$val), (VTI.Pred VCCR:$pred),
2435                                 (VTI.Vec MQPR:$inactive))),
2436              (VTI.Vec (Inst (VTI.Vec MQPR:$val), ARMVCCThen,
2437                             (VTI.Pred VCCR:$pred), (VTI.Vec MQPR:$inactive)))>;
2438  }
2439}
2440
2441defm MVE_VCLSs8  : MVE_VCLSCLZ_p<"cls", 0, MVE_v16s8, int_arm_mve_vcls>;
2442defm MVE_VCLSs16 : MVE_VCLSCLZ_p<"cls", 0, MVE_v8s16, int_arm_mve_vcls>;
2443defm MVE_VCLSs32 : MVE_VCLSCLZ_p<"cls", 0, MVE_v4s32, int_arm_mve_vcls>;
2444
2445defm MVE_VCLZs8  : MVE_VCLSCLZ_p<"clz", 1, MVE_v16i8, ctlz>;
2446defm MVE_VCLZs16 : MVE_VCLSCLZ_p<"clz", 1, MVE_v8i16, ctlz>;
2447defm MVE_VCLZs32 : MVE_VCLSCLZ_p<"clz", 1, MVE_v4i32, ctlz>;
2448
2449class MVE_VABSNEG_int<string iname, string suffix, bits<2> size, bit negate,
2450                      bit saturate, list<dag> pattern=[]>
2451  : MVEIntSingleSrc<iname, suffix, size, pattern> {
2452
2453  let Inst{28} = 0b1;
2454  let Inst{25-23} = 0b111;
2455  let Inst{21-20} = 0b11;
2456  let Inst{17} = 0b0;
2457  let Inst{16} = !eq(saturate, 0);
2458  let Inst{12-11} = 0b00;
2459  let Inst{10} = saturate;
2460  let Inst{9-8} = 0b11;
2461  let Inst{7} = negate;
2462  let Inst{6} = 0b1;
2463  let Inst{4} = 0b0;
2464  let Inst{0} = 0b0;
2465  let validForTailPredication = 1;
2466}
2467
2468multiclass MVE_VABSNEG_int_m<string iname, bit negate, bit saturate,
2469                             SDNode unpred_op, Intrinsic pred_int,
2470                             MVEVectorVTInfo VTI> {
2471  def "" : MVE_VABSNEG_int<iname, VTI.Suffix, VTI.Size, negate, saturate>;
2472  defvar Inst = !cast<Instruction>(NAME);
2473
2474  let Predicates = [HasMVEInt] in {
2475    // VQABS and VQNEG have more difficult isel patterns defined elsewhere
2476    if !not(saturate) then {
2477      def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$v))),
2478                (VTI.Vec (Inst $v))>;
2479    }
2480
2481    def : Pat<(VTI.Vec (pred_int  (VTI.Vec MQPR:$v), (VTI.Pred VCCR:$mask),
2482                                  (VTI.Vec MQPR:$inactive))),
2483              (VTI.Vec (Inst $v, ARMVCCThen, $mask, $inactive))>;
2484  }
2485}
2486
2487foreach VTI = [ MVE_v16s8, MVE_v8s16, MVE_v4s32 ] in {
2488  defm "MVE_VABS" # VTI.Suffix : MVE_VABSNEG_int_m<
2489     "vabs",  0, 0, abs,   int_arm_mve_abs_predicated,  VTI>;
2490  defm "MVE_VQABS" # VTI.Suffix : MVE_VABSNEG_int_m<
2491     "vqabs", 0, 1, ?,     int_arm_mve_qabs_predicated, VTI>;
2492  defm "MVE_VNEG" # VTI.Suffix : MVE_VABSNEG_int_m<
2493     "vneg",  1, 0, vnegq, int_arm_mve_neg_predicated,  VTI>;
2494  defm "MVE_VQNEG" # VTI.Suffix : MVE_VABSNEG_int_m<
2495     "vqneg", 1, 1, ?,     int_arm_mve_qneg_predicated, VTI>;
2496}
2497
2498// int_min/int_max: vector containing INT_MIN/INT_MAX VTI.Size times
2499// zero_vec: v4i32-initialized zero vector, potentially wrapped in a bitconvert
2500multiclass vqabsneg_pattern<MVEVectorVTInfo VTI, dag int_min, dag int_max,
2501                         dag zero_vec,  MVE_VABSNEG_int vqabs_instruction,
2502                         MVE_VABSNEG_int vqneg_instruction> {
2503  let Predicates = [HasMVEInt] in {
2504    // The below tree can be replaced by a vqabs instruction, as it represents
2505    // the following vectorized expression (r being the value in $reg):
2506    // r > 0 ? r : (r == INT_MIN ? INT_MAX : -r)
2507    def : Pat<(VTI.Vec (vselect
2508                      (VTI.Pred (ARMvcmpz (VTI.Vec MQPR:$reg), ARMCCgt)),
2509                      (VTI.Vec MQPR:$reg),
2510                      (VTI.Vec (vselect
2511                                (VTI.Pred (ARMvcmp (VTI.Vec MQPR:$reg), int_min, ARMCCeq)),
2512                                int_max,
2513                                (sub (VTI.Vec zero_vec), (VTI.Vec MQPR:$reg)))))),
2514            (VTI.Vec (vqabs_instruction (VTI.Vec MQPR:$reg)))>;
2515    // Similarly, this tree represents vqneg, i.e. the following vectorized expression:
2516    // r == INT_MIN ? INT_MAX : -r
2517    def : Pat<(VTI.Vec (vselect
2518                        (VTI.Pred (ARMvcmp (VTI.Vec MQPR:$reg), int_min, ARMCCeq)),
2519                        int_max,
2520                        (sub (VTI.Vec zero_vec), (VTI.Vec MQPR:$reg)))),
2521               (VTI.Vec (vqneg_instruction (VTI.Vec MQPR:$reg)))>;
2522  }
2523}
2524
2525defm MVE_VQABSNEG_Ps8  : vqabsneg_pattern<MVE_v16i8,
2526                                    (v16i8 (ARMvmovImm (i32 3712))),
2527                                    (v16i8 (ARMvmovImm (i32 3711))),
2528                                    (bitconvert (v4i32 (ARMvmovImm (i32 0)))),
2529                                    MVE_VQABSs8, MVE_VQNEGs8>;
2530defm MVE_VQABSNEG_Ps16 : vqabsneg_pattern<MVE_v8i16,
2531                                    (v8i16 (ARMvmovImm (i32 2688))),
2532                                    (v8i16 (ARMvmvnImm (i32 2688))),
2533                                    (bitconvert (v4i32 (ARMvmovImm (i32 0)))),
2534                                    MVE_VQABSs16, MVE_VQNEGs16>;
2535defm MVE_VQABSNEG_Ps32 : vqabsneg_pattern<MVE_v4i32,
2536                                    (v4i32 (ARMvmovImm (i32 1664))),
2537                                    (v4i32 (ARMvmvnImm (i32 1664))),
2538                                    (ARMvmovImm (i32 0)),
2539                                    MVE_VQABSs32, MVE_VQNEGs32>;
2540
2541class MVE_mod_imm<string iname, string suffix, bits<4> cmode, bit op,
2542                  dag iops, list<dag> pattern=[]>
2543  : MVE_p<(outs MQPR:$Qd), iops, NoItinerary, iname, suffix, "$Qd, $imm",
2544          vpred_r, "", pattern> {
2545  bits<13> imm;
2546  bits<4> Qd;
2547
2548  let Inst{28} = imm{7};
2549  let Inst{25-23} = 0b111;
2550  let Inst{22} = Qd{3};
2551  let Inst{21-19} = 0b000;
2552  let Inst{18-16} = imm{6-4};
2553  let Inst{15-13} = Qd{2-0};
2554  let Inst{12} = 0b0;
2555  let Inst{11-8} = cmode{3-0};
2556  let Inst{7-6} = 0b01;
2557  let Inst{5} = op;
2558  let Inst{4} = 0b1;
2559  let Inst{3-0} = imm{3-0};
2560
2561  let DecoderMethod = "DecodeMVEModImmInstruction";
2562  let validForTailPredication = 1;
2563}
2564
2565let isReMaterializable = 1 in {
2566let isAsCheapAsAMove = 1 in {
2567def MVE_VMOVimmi8  : MVE_mod_imm<"vmov", "i8",  {1,1,1,0}, 0b0, (ins nImmSplatI8:$imm)>;
2568def MVE_VMOVimmi16 : MVE_mod_imm<"vmov", "i16", {1,0,?,0}, 0b0, (ins nImmSplatI16:$imm)> {
2569  let Inst{9} = imm{9};
2570}
2571def MVE_VMOVimmi32 : MVE_mod_imm<"vmov", "i32", {?,?,?,?}, 0b0, (ins nImmVMOVI32:$imm)> {
2572  let Inst{11-8} = imm{11-8};
2573}
2574def MVE_VMOVimmi64 : MVE_mod_imm<"vmov", "i64", {1,1,1,0}, 0b1, (ins nImmSplatI64:$imm)>;
2575def MVE_VMOVimmf32 : MVE_mod_imm<"vmov", "f32", {1,1,1,1}, 0b0, (ins nImmVMOVF32:$imm)>;
2576} // let isAsCheapAsAMove = 1
2577
2578def MVE_VMVNimmi16 : MVE_mod_imm<"vmvn", "i16", {1,0,?,0}, 0b1, (ins nImmSplatI16:$imm)> {
2579  let Inst{9} = imm{9};
2580}
2581def MVE_VMVNimmi32 : MVE_mod_imm<"vmvn", "i32", {?,?,?,?}, 0b1, (ins nImmVMOVI32:$imm)> {
2582  let Inst{11-8} = imm{11-8};
2583}
2584} // let isReMaterializable = 1
2585
2586let Predicates = [HasMVEInt] in {
2587  def : Pat<(v16i8 (ARMvmovImm timm:$simm)),
2588            (v16i8 (MVE_VMOVimmi8  nImmSplatI8:$simm))>;
2589  def : Pat<(v8i16 (ARMvmovImm timm:$simm)),
2590            (v8i16 (MVE_VMOVimmi16 nImmSplatI16:$simm))>;
2591  def : Pat<(v4i32 (ARMvmovImm timm:$simm)),
2592            (v4i32 (MVE_VMOVimmi32 nImmVMOVI32:$simm))>;
2593  def : Pat<(v2i64 (ARMvmovImm timm:$simm)),
2594            (v2i64 (MVE_VMOVimmi64 nImmSplatI64:$simm))>;
2595
2596  def : Pat<(v8i16 (ARMvmvnImm timm:$simm)),
2597            (v8i16 (MVE_VMVNimmi16 nImmSplatI16:$simm))>;
2598  def : Pat<(v4i32 (ARMvmvnImm timm:$simm)),
2599            (v4i32 (MVE_VMVNimmi32 nImmVMOVI32:$simm))>;
2600
2601  def : Pat<(v4f32 (ARMvmovFPImm timm:$simm)),
2602            (v4f32 (MVE_VMOVimmf32 nImmVMOVF32:$simm))>;
2603
2604  def : Pat<(v8i16 (vselect (v8i1 VCCR:$pred), (ARMvmvnImm timm:$simm),
2605                            MQPR:$inactive)),
2606            (v8i16 (MVE_VMVNimmi16 nImmSplatI16:$simm,
2607                            ARMVCCThen, VCCR:$pred, MQPR:$inactive))>;
2608  def : Pat<(v4i32 (vselect (v4i1 VCCR:$pred), (ARMvmvnImm timm:$simm),
2609                            MQPR:$inactive)),
2610            (v4i32 (MVE_VMVNimmi32 nImmSplatI32:$simm,
2611                            ARMVCCThen, VCCR:$pred, MQPR:$inactive))>;
2612}
2613
2614class MVE_VMINMAXA<string iname, string suffix, bits<2> size,
2615                   bit bit_12, list<dag> pattern=[]>
2616  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
2617          NoItinerary, iname, suffix, "$Qd, $Qm", vpred_n, "$Qd = $Qd_src",
2618          pattern> {
2619  bits<4> Qd;
2620  bits<4> Qm;
2621
2622  let Inst{28} = 0b0;
2623  let Inst{25-23} = 0b100;
2624  let Inst{22} = Qd{3};
2625  let Inst{21-20} = 0b11;
2626  let Inst{19-18} = size;
2627  let Inst{17-16} = 0b11;
2628  let Inst{15-13} = Qd{2-0};
2629  let Inst{12} = bit_12;
2630  let Inst{11-6} = 0b111010;
2631  let Inst{5} = Qm{3};
2632  let Inst{4} = 0b0;
2633  let Inst{3-1} = Qm{2-0};
2634  let Inst{0} = 0b1;
2635  let validForTailPredication = 1;
2636}
2637
2638multiclass MVE_VMINMAXA_m<string iname, MVEVectorVTInfo VTI,
2639                      SDNode unpred_op, Intrinsic pred_int, bit bit_12> {
2640  def "" : MVE_VMINMAXA<iname, VTI.Suffix, VTI.Size, bit_12>;
2641  defvar Inst = !cast<Instruction>(NAME);
2642
2643  let Predicates = [HasMVEInt] in {
2644    // Unpredicated v(min|max)a
2645    def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qd), (abs (VTI.Vec MQPR:$Qm)))),
2646              (VTI.Vec (Inst (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm)))>;
2647
2648    // Predicated v(min|max)a
2649    def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm),
2650                            (VTI.Pred VCCR:$mask))),
2651              (VTI.Vec (Inst (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm),
2652                            ARMVCCThen, (VTI.Pred VCCR:$mask)))>;
2653  }
2654}
2655
2656multiclass MVE_VMINA<MVEVectorVTInfo VTI>
2657  : MVE_VMINMAXA_m<"vmina", VTI, umin, int_arm_mve_vmina_predicated, 0b1>;
2658
2659defm MVE_VMINAs8  : MVE_VMINA<MVE_v16s8>;
2660defm MVE_VMINAs16 : MVE_VMINA<MVE_v8s16>;
2661defm MVE_VMINAs32 : MVE_VMINA<MVE_v4s32>;
2662
2663multiclass MVE_VMAXA<MVEVectorVTInfo VTI>
2664  : MVE_VMINMAXA_m<"vmaxa", VTI, umax, int_arm_mve_vmaxa_predicated, 0b0>;
2665
2666defm MVE_VMAXAs8  : MVE_VMAXA<MVE_v16s8>;
2667defm MVE_VMAXAs16 : MVE_VMAXA<MVE_v8s16>;
2668defm MVE_VMAXAs32 : MVE_VMAXA<MVE_v4s32>;
2669
2670// end of MVE Integer instructions
2671
2672// start of mve_imm_shift instructions
2673
2674def MVE_VSHLC : MVE_p<(outs rGPR:$RdmDest, MQPR:$Qd),
2675                      (ins MQPR:$QdSrc, rGPR:$RdmSrc, long_shift:$imm),
2676                      NoItinerary, "vshlc", "", "$QdSrc, $RdmSrc, $imm",
2677                      vpred_n, "$RdmDest = $RdmSrc,$Qd = $QdSrc"> {
2678  bits<5> imm;
2679  bits<4> Qd;
2680  bits<4> RdmDest;
2681
2682  let Inst{28} = 0b0;
2683  let Inst{25-23} = 0b101;
2684  let Inst{22} = Qd{3};
2685  let Inst{21} = 0b1;
2686  let Inst{20-16} = imm{4-0};
2687  let Inst{15-13} = Qd{2-0};
2688  let Inst{12-4} = 0b011111100;
2689  let Inst{3-0} = RdmDest{3-0};
2690}
2691
2692class MVE_shift_imm<dag oops, dag iops, string iname, string suffix,
2693                    string ops, vpred_ops vpred, string cstr,
2694                    list<dag> pattern=[]>
2695  : MVE_p<oops, iops, NoItinerary, iname, suffix, ops, vpred, cstr, pattern> {
2696  bits<4> Qd;
2697  bits<4> Qm;
2698
2699  let Inst{22} = Qd{3};
2700  let Inst{15-13} = Qd{2-0};
2701  let Inst{5} = Qm{3};
2702  let Inst{3-1} = Qm{2-0};
2703}
2704
2705class MVE_VMOVL<string iname, string suffix, bits<2> sz, bit U, bit top,
2706              list<dag> pattern=[]>
2707  : MVE_shift_imm<(outs MQPR:$Qd), (ins MQPR:$Qm),
2708                  iname, suffix, "$Qd, $Qm", vpred_r, "",
2709                  pattern> {
2710  let Inst{28} = U;
2711  let Inst{25-23} = 0b101;
2712  let Inst{21} = 0b1;
2713  let Inst{20-19} = sz{1-0};
2714  let Inst{18-16} = 0b000;
2715  let Inst{12} = top;
2716  let Inst{11-6} = 0b111101;
2717  let Inst{4} = 0b0;
2718  let Inst{0} = 0b0;
2719  let doubleWidthResult = 1;
2720}
2721
2722multiclass MVE_VMOVL_m<bit top, string chr, MVEVectorVTInfo OutVTI,
2723                       MVEVectorVTInfo InVTI> {
2724  def "": MVE_VMOVL<"vmovl" # chr, InVTI.Suffix, OutVTI.Size,
2725                    InVTI.Unsigned, top>;
2726  defvar Inst = !cast<Instruction>(NAME);
2727
2728  def : Pat<(OutVTI.Vec (int_arm_mve_vmovl_predicated (InVTI.Vec MQPR:$src),
2729                            (i32 InVTI.Unsigned), (i32 top),
2730                            (OutVTI.Pred VCCR:$pred),
2731                            (OutVTI.Vec MQPR:$inactive))),
2732            (OutVTI.Vec (Inst (InVTI.Vec MQPR:$src), ARMVCCThen,
2733                            (OutVTI.Pred VCCR:$pred),
2734                            (OutVTI.Vec MQPR:$inactive)))>;
2735}
2736
2737defm MVE_VMOVLs8bh  : MVE_VMOVL_m<0, "b", MVE_v8s16, MVE_v16s8>;
2738defm MVE_VMOVLs8th  : MVE_VMOVL_m<1, "t", MVE_v8s16, MVE_v16s8>;
2739defm MVE_VMOVLu8bh  : MVE_VMOVL_m<0, "b", MVE_v8u16, MVE_v16u8>;
2740defm MVE_VMOVLu8th  : MVE_VMOVL_m<1, "t", MVE_v8u16, MVE_v16u8>;
2741defm MVE_VMOVLs16bh : MVE_VMOVL_m<0, "b", MVE_v4s32, MVE_v8s16>;
2742defm MVE_VMOVLs16th : MVE_VMOVL_m<1, "t", MVE_v4s32, MVE_v8s16>;
2743defm MVE_VMOVLu16bh : MVE_VMOVL_m<0, "b", MVE_v4s32, MVE_v8u16>;
2744defm MVE_VMOVLu16th : MVE_VMOVL_m<1, "t", MVE_v4s32, MVE_v8u16>;
2745
2746let Predicates = [HasMVEInt] in {
2747  def : Pat<(sext_inreg (v4i32 MQPR:$src), v4i16),
2748            (MVE_VMOVLs16bh MQPR:$src)>;
2749  def : Pat<(sext_inreg (v8i16 MQPR:$src), v8i8),
2750            (MVE_VMOVLs8bh MQPR:$src)>;
2751  def : Pat<(sext_inreg (v4i32 MQPR:$src), v4i8),
2752            (MVE_VMOVLs16bh (MVE_VMOVLs8bh MQPR:$src))>;
2753
2754  def : Pat<(sext_inreg (v8i16 (ARMVectorRegCast (ARMvrev16 (v16i8 MQPR:$src)))), v8i8),
2755            (MVE_VMOVLs8th MQPR:$src)>;
2756  def : Pat<(sext_inreg (v4i32 (ARMVectorRegCast (ARMvrev32 (v8i16 MQPR:$src)))), v4i16),
2757            (MVE_VMOVLs16th MQPR:$src)>;
2758
2759  // zext_inreg 8 -> 16
2760  def : Pat<(ARMvbicImm (v8i16 MQPR:$src), (i32 0xAFF)),
2761            (MVE_VMOVLu8bh MQPR:$src)>;
2762  // zext_inreg 16 -> 32
2763  def : Pat<(and (v4i32 MQPR:$src), (v4i32 (ARMvmovImm (i32 0xCFF)))),
2764            (MVE_VMOVLu16bh MQPR:$src)>;
2765  // Same zext_inreg with vrevs, picking the top half
2766  def : Pat<(ARMvbicImm (v8i16 (ARMVectorRegCast (ARMvrev16 (v16i8 MQPR:$src)))), (i32 0xAFF)),
2767            (MVE_VMOVLu8th MQPR:$src)>;
2768  def : Pat<(and (v4i32 (ARMVectorRegCast (ARMvrev32 (v8i16 MQPR:$src)))),
2769                 (v4i32 (ARMvmovImm (i32 0xCFF)))),
2770            (MVE_VMOVLu16th MQPR:$src)>;
2771}
2772
2773
2774class MVE_VSHLL_imm<string iname, string suffix, bit U, bit th,
2775                    Operand immtype, list<dag> pattern=[]>
2776  : MVE_shift_imm<(outs MQPR:$Qd), (ins MQPR:$Qm, immtype:$imm),
2777                  iname, suffix, "$Qd, $Qm, $imm", vpred_r, "", pattern> {
2778  let Inst{28} = U;
2779  let Inst{25-23} = 0b101;
2780  let Inst{21} = 0b1;
2781  let Inst{12} = th;
2782  let Inst{11-6} = 0b111101;
2783  let Inst{4} = 0b0;
2784  let Inst{0} = 0b0;
2785
2786  // For the MVE_VSHLL_patterns multiclass to refer to
2787  Operand immediateType = immtype;
2788
2789  let doubleWidthResult = 1;
2790}
2791
2792// The immediate VSHLL instructions accept shift counts from 1 up to
2793// the lane width (8 or 16), but the full-width shifts have an
2794// entirely separate encoding, given below with 'lw' in the name.
2795
2796class MVE_VSHLL_imm8<string iname, string suffix,
2797                     bit U, bit th, list<dag> pattern=[]>
2798  : MVE_VSHLL_imm<iname, suffix, U, th, mve_shift_imm1_7, pattern> {
2799  bits<3> imm;
2800  let Inst{20-19} = 0b01;
2801  let Inst{18-16} = imm;
2802}
2803
2804class MVE_VSHLL_imm16<string iname, string suffix,
2805                      bit U, bit th, list<dag> pattern=[]>
2806  : MVE_VSHLL_imm<iname, suffix, U, th, mve_shift_imm1_15, pattern> {
2807  bits<4> imm;
2808  let Inst{20} = 0b1;
2809  let Inst{19-16} = imm;
2810}
2811
2812def MVE_VSHLL_imms8bh  : MVE_VSHLL_imm8 <"vshllb", "s8", 0b0, 0b0>;
2813def MVE_VSHLL_imms8th  : MVE_VSHLL_imm8 <"vshllt", "s8", 0b0, 0b1>;
2814def MVE_VSHLL_immu8bh  : MVE_VSHLL_imm8 <"vshllb", "u8", 0b1, 0b0>;
2815def MVE_VSHLL_immu8th  : MVE_VSHLL_imm8 <"vshllt", "u8", 0b1, 0b1>;
2816def MVE_VSHLL_imms16bh : MVE_VSHLL_imm16<"vshllb", "s16", 0b0, 0b0>;
2817def MVE_VSHLL_imms16th : MVE_VSHLL_imm16<"vshllt", "s16", 0b0, 0b1>;
2818def MVE_VSHLL_immu16bh : MVE_VSHLL_imm16<"vshllb", "u16", 0b1, 0b0>;
2819def MVE_VSHLL_immu16th : MVE_VSHLL_imm16<"vshllt", "u16", 0b1, 0b1>;
2820
2821class MVE_VSHLL_by_lane_width<string iname, string suffix, bits<2> size,
2822                              bit U, string ops, list<dag> pattern=[]>
2823  : MVE_shift_imm<(outs MQPR:$Qd), (ins MQPR:$Qm),
2824                  iname, suffix, ops, vpred_r, "", pattern> {
2825  let Inst{28} = U;
2826  let Inst{25-23} = 0b100;
2827  let Inst{21-20} = 0b11;
2828  let Inst{19-18} = size{1-0};
2829  let Inst{17-16} = 0b01;
2830  let Inst{11-6} = 0b111000;
2831  let Inst{4} = 0b0;
2832  let Inst{0} = 0b1;
2833  let doubleWidthResult = 1;
2834}
2835
2836multiclass MVE_VSHLL_lw<string iname, string suffix, bits<2> sz, bit U,
2837                              string ops, list<dag> pattern=[]> {
2838  def bh : MVE_VSHLL_by_lane_width<iname#"b", suffix, sz, U, ops, pattern> {
2839    let Inst{12} = 0b0;
2840  }
2841  def th : MVE_VSHLL_by_lane_width<iname#"t", suffix, sz, U, ops, pattern> {
2842    let Inst{12} = 0b1;
2843  }
2844}
2845
2846defm MVE_VSHLL_lws8  : MVE_VSHLL_lw<"vshll", "s8",  0b00, 0b0, "$Qd, $Qm, #8">;
2847defm MVE_VSHLL_lws16 : MVE_VSHLL_lw<"vshll", "s16", 0b01, 0b0, "$Qd, $Qm, #16">;
2848defm MVE_VSHLL_lwu8  : MVE_VSHLL_lw<"vshll", "u8",  0b00, 0b1, "$Qd, $Qm, #8">;
2849defm MVE_VSHLL_lwu16 : MVE_VSHLL_lw<"vshll", "u16", 0b01, 0b1, "$Qd, $Qm, #16">;
2850
2851multiclass MVE_VSHLL_patterns<MVEVectorVTInfo VTI, int top> {
2852  defvar suffix     = !strconcat(VTI.Suffix, !if(top, "th", "bh"));
2853  defvar inst_imm   = !cast<MVE_VSHLL_imm>("MVE_VSHLL_imm" # suffix);
2854  defvar inst_lw    = !cast<MVE_VSHLL_by_lane_width>("MVE_VSHLL_lw" # suffix);
2855  defvar unpred_int = int_arm_mve_vshll_imm;
2856  defvar pred_int   = int_arm_mve_vshll_imm_predicated;
2857  defvar imm        = inst_imm.immediateType;
2858
2859  def : Pat<(VTI.DblVec (unpred_int (VTI.Vec MQPR:$src), imm:$imm,
2860                                    (i32 VTI.Unsigned), (i32 top))),
2861            (VTI.DblVec (inst_imm   (VTI.Vec MQPR:$src), imm:$imm))>;
2862  def : Pat<(VTI.DblVec (unpred_int (VTI.Vec MQPR:$src), (i32 VTI.LaneBits),
2863                                    (i32 VTI.Unsigned), (i32 top))),
2864            (VTI.DblVec (inst_lw    (VTI.Vec MQPR:$src)))>;
2865
2866  def : Pat<(VTI.DblVec (pred_int   (VTI.Vec MQPR:$src), imm:$imm,
2867                                    (i32 VTI.Unsigned), (i32 top),
2868                                    (VTI.DblPred VCCR:$mask),
2869                                    (VTI.DblVec MQPR:$inactive))),
2870            (VTI.DblVec (inst_imm   (VTI.Vec MQPR:$src), imm:$imm,
2871                                    ARMVCCThen, (VTI.DblPred VCCR:$mask),
2872                                    (VTI.DblVec MQPR:$inactive)))>;
2873  def : Pat<(VTI.DblVec (pred_int   (VTI.Vec MQPR:$src), (i32 VTI.LaneBits),
2874                                    (i32 VTI.Unsigned), (i32 top),
2875                                    (VTI.DblPred VCCR:$mask),
2876                                    (VTI.DblVec MQPR:$inactive))),
2877            (VTI.DblVec (inst_lw    (VTI.Vec MQPR:$src), ARMVCCThen,
2878                                    (VTI.DblPred VCCR:$mask),
2879                                    (VTI.DblVec MQPR:$inactive)))>;
2880}
2881
2882foreach VTI = [MVE_v16s8, MVE_v8s16, MVE_v16u8, MVE_v8u16] in
2883  foreach top = [0, 1] in
2884    defm : MVE_VSHLL_patterns<VTI, top>;
2885
2886class MVE_shift_imm_partial<Operand imm, string iname, string suffix>
2887  : MVE_shift_imm<(outs MQPR:$Qd), (ins MQPR:$QdSrc, MQPR:$Qm, imm:$imm),
2888                  iname, suffix, "$Qd, $Qm, $imm", vpred_n, "$Qd = $QdSrc"> {
2889  Operand immediateType = imm;
2890}
2891
2892class MVE_VxSHRN<string iname, string suffix, bit bit_12, bit bit_28,
2893                 Operand imm, list<dag> pattern=[]>
2894  : MVE_shift_imm_partial<imm, iname, suffix> {
2895  bits<5> imm;
2896
2897  let Inst{28} = bit_28;
2898  let Inst{25-23} = 0b101;
2899  let Inst{21} = 0b0;
2900  let Inst{20-16} = imm{4-0};
2901  let Inst{12} = bit_12;
2902  let Inst{11-6} = 0b111111;
2903  let Inst{4} = 0b0;
2904  let Inst{0} = 0b1;
2905  let validForTailPredication = 1;
2906  let retainsPreviousHalfElement = 1;
2907}
2908
2909def MVE_VRSHRNi16bh : MVE_VxSHRN<"vrshrnb", "i16", 0b0, 0b1, shr_imm8> {
2910  let Inst{20-19} = 0b01;
2911}
2912def MVE_VRSHRNi16th : MVE_VxSHRN<"vrshrnt", "i16", 0b1, 0b1, shr_imm8> {
2913  let Inst{20-19} = 0b01;
2914}
2915def MVE_VRSHRNi32bh : MVE_VxSHRN<"vrshrnb", "i32", 0b0, 0b1, shr_imm16> {
2916  let Inst{20} = 0b1;
2917}
2918def MVE_VRSHRNi32th : MVE_VxSHRN<"vrshrnt", "i32", 0b1, 0b1, shr_imm16> {
2919  let Inst{20} = 0b1;
2920}
2921
2922def MVE_VSHRNi16bh : MVE_VxSHRN<"vshrnb", "i16", 0b0, 0b0, shr_imm8> {
2923  let Inst{20-19} = 0b01;
2924}
2925def MVE_VSHRNi16th : MVE_VxSHRN<"vshrnt", "i16", 0b1, 0b0, shr_imm8> {
2926  let Inst{20-19} = 0b01;
2927}
2928def MVE_VSHRNi32bh : MVE_VxSHRN<"vshrnb", "i32", 0b0, 0b0, shr_imm16> {
2929  let Inst{20} = 0b1;
2930}
2931def MVE_VSHRNi32th : MVE_VxSHRN<"vshrnt", "i32", 0b1, 0b0, shr_imm16> {
2932  let Inst{20} = 0b1;
2933}
2934
2935class MVE_VxQRSHRUN<string iname, string suffix, bit bit_28, bit bit_12,
2936                    Operand imm, list<dag> pattern=[]>
2937  : MVE_shift_imm_partial<imm, iname, suffix> {
2938  bits<5> imm;
2939
2940  let Inst{28} = bit_28;
2941  let Inst{25-23} = 0b101;
2942  let Inst{21} = 0b0;
2943  let Inst{20-16} = imm{4-0};
2944  let Inst{12} = bit_12;
2945  let Inst{11-6} = 0b111111;
2946  let Inst{4} = 0b0;
2947  let Inst{0} = 0b0;
2948  let validForTailPredication = 1;
2949  let retainsPreviousHalfElement = 1;
2950}
2951
2952def MVE_VQRSHRUNs16bh : MVE_VxQRSHRUN<
2953    "vqrshrunb", "s16", 0b1, 0b0, shr_imm8> {
2954  let Inst{20-19} = 0b01;
2955}
2956def MVE_VQRSHRUNs16th : MVE_VxQRSHRUN<
2957    "vqrshrunt", "s16", 0b1, 0b1, shr_imm8> {
2958  let Inst{20-19} = 0b01;
2959}
2960def MVE_VQRSHRUNs32bh : MVE_VxQRSHRUN<
2961    "vqrshrunb", "s32", 0b1, 0b0, shr_imm16> {
2962  let Inst{20} = 0b1;
2963}
2964def MVE_VQRSHRUNs32th : MVE_VxQRSHRUN<
2965    "vqrshrunt", "s32", 0b1, 0b1, shr_imm16> {
2966  let Inst{20} = 0b1;
2967}
2968
2969def MVE_VQSHRUNs16bh : MVE_VxQRSHRUN<
2970    "vqshrunb", "s16", 0b0, 0b0, shr_imm8> {
2971  let Inst{20-19} = 0b01;
2972}
2973def MVE_VQSHRUNs16th : MVE_VxQRSHRUN<
2974    "vqshrunt", "s16", 0b0, 0b1, shr_imm8> {
2975  let Inst{20-19} = 0b01;
2976}
2977def MVE_VQSHRUNs32bh : MVE_VxQRSHRUN<
2978    "vqshrunb", "s32", 0b0, 0b0, shr_imm16> {
2979  let Inst{20} = 0b1;
2980}
2981def MVE_VQSHRUNs32th : MVE_VxQRSHRUN<
2982    "vqshrunt", "s32", 0b0, 0b1, shr_imm16> {
2983  let Inst{20} = 0b1;
2984}
2985
2986class MVE_VxQRSHRN<string iname, string suffix, bit bit_0, bit bit_12,
2987                   Operand imm, list<dag> pattern=[]>
2988  : MVE_shift_imm_partial<imm, iname, suffix> {
2989  bits<5> imm;
2990
2991  let Inst{25-23} = 0b101;
2992  let Inst{21} = 0b0;
2993  let Inst{20-16} = imm{4-0};
2994  let Inst{12} = bit_12;
2995  let Inst{11-6} = 0b111101;
2996  let Inst{4} = 0b0;
2997  let Inst{0} = bit_0;
2998  let validForTailPredication = 1;
2999  let retainsPreviousHalfElement = 1;
3000}
3001
3002multiclass MVE_VxQRSHRN_types<string iname, bit bit_0, bit bit_12> {
3003  def s16 : MVE_VxQRSHRN<iname, "s16", bit_0, bit_12, shr_imm8> {
3004    let Inst{28} = 0b0;
3005    let Inst{20-19} = 0b01;
3006  }
3007  def u16 : MVE_VxQRSHRN<iname, "u16", bit_0, bit_12, shr_imm8> {
3008    let Inst{28} = 0b1;
3009    let Inst{20-19} = 0b01;
3010  }
3011  def s32 : MVE_VxQRSHRN<iname, "s32", bit_0, bit_12, shr_imm16> {
3012    let Inst{28} = 0b0;
3013    let Inst{20} = 0b1;
3014  }
3015  def u32 : MVE_VxQRSHRN<iname, "u32", bit_0, bit_12, shr_imm16> {
3016    let Inst{28} = 0b1;
3017    let Inst{20} = 0b1;
3018  }
3019}
3020
3021defm MVE_VQRSHRNbh : MVE_VxQRSHRN_types<"vqrshrnb", 0b1, 0b0>;
3022defm MVE_VQRSHRNth : MVE_VxQRSHRN_types<"vqrshrnt", 0b1, 0b1>;
3023defm MVE_VQSHRNbh  : MVE_VxQRSHRN_types<"vqshrnb", 0b0, 0b0>;
3024defm MVE_VQSHRNth  : MVE_VxQRSHRN_types<"vqshrnt", 0b0, 0b1>;
3025
3026multiclass MVE_VSHRN_patterns<MVE_shift_imm_partial inst,
3027                              MVEVectorVTInfo OutVTI, MVEVectorVTInfo InVTI,
3028                              bit q, bit r, bit top> {
3029  defvar inparams = (? (OutVTI.Vec MQPR:$QdSrc), (InVTI.Vec MQPR:$Qm),
3030                       (inst.immediateType:$imm), (i32 q), (i32 r),
3031                       (i32 OutVTI.Unsigned), (i32 InVTI.Unsigned), (i32 top));
3032  defvar outparams = (inst (OutVTI.Vec MQPR:$QdSrc), (InVTI.Vec MQPR:$Qm),
3033                           (imm:$imm));
3034
3035  def : Pat<(OutVTI.Vec !setdagop(inparams, int_arm_mve_vshrn)),
3036            (OutVTI.Vec outparams)>;
3037  def : Pat<(OutVTI.Vec !con(inparams, (int_arm_mve_vshrn_predicated
3038                                           (InVTI.Pred VCCR:$pred)))),
3039            (OutVTI.Vec !con(outparams, (? ARMVCCThen, VCCR:$pred)))>;
3040}
3041
3042defm : MVE_VSHRN_patterns<MVE_VSHRNi16bh,    MVE_v16s8, MVE_v8s16, 0,0,0>;
3043defm : MVE_VSHRN_patterns<MVE_VSHRNi16th,    MVE_v16s8, MVE_v8s16, 0,0,1>;
3044defm : MVE_VSHRN_patterns<MVE_VSHRNi32bh,    MVE_v8s16, MVE_v4s32, 0,0,0>;
3045defm : MVE_VSHRN_patterns<MVE_VSHRNi32th,    MVE_v8s16, MVE_v4s32, 0,0,1>;
3046defm : MVE_VSHRN_patterns<MVE_VSHRNi16bh,    MVE_v16u8, MVE_v8u16, 0,0,0>;
3047defm : MVE_VSHRN_patterns<MVE_VSHRNi16th,    MVE_v16u8, MVE_v8u16, 0,0,1>;
3048defm : MVE_VSHRN_patterns<MVE_VSHRNi32bh,    MVE_v8u16, MVE_v4u32, 0,0,0>;
3049defm : MVE_VSHRN_patterns<MVE_VSHRNi32th,    MVE_v8u16, MVE_v4u32, 0,0,1>;
3050defm : MVE_VSHRN_patterns<MVE_VRSHRNi16bh,   MVE_v16s8, MVE_v8s16, 0,1,0>;
3051defm : MVE_VSHRN_patterns<MVE_VRSHRNi16th,   MVE_v16s8, MVE_v8s16, 0,1,1>;
3052defm : MVE_VSHRN_patterns<MVE_VRSHRNi32bh,   MVE_v8s16, MVE_v4s32, 0,1,0>;
3053defm : MVE_VSHRN_patterns<MVE_VRSHRNi32th,   MVE_v8s16, MVE_v4s32, 0,1,1>;
3054defm : MVE_VSHRN_patterns<MVE_VRSHRNi16bh,   MVE_v16u8, MVE_v8u16, 0,1,0>;
3055defm : MVE_VSHRN_patterns<MVE_VRSHRNi16th,   MVE_v16u8, MVE_v8u16, 0,1,1>;
3056defm : MVE_VSHRN_patterns<MVE_VRSHRNi32bh,   MVE_v8u16, MVE_v4u32, 0,1,0>;
3057defm : MVE_VSHRN_patterns<MVE_VRSHRNi32th,   MVE_v8u16, MVE_v4u32, 0,1,1>;
3058defm : MVE_VSHRN_patterns<MVE_VQSHRNbhs16,   MVE_v16s8, MVE_v8s16, 1,0,0>;
3059defm : MVE_VSHRN_patterns<MVE_VQSHRNths16,   MVE_v16s8, MVE_v8s16, 1,0,1>;
3060defm : MVE_VSHRN_patterns<MVE_VQSHRNbhs32,   MVE_v8s16, MVE_v4s32, 1,0,0>;
3061defm : MVE_VSHRN_patterns<MVE_VQSHRNths32,   MVE_v8s16, MVE_v4s32, 1,0,1>;
3062defm : MVE_VSHRN_patterns<MVE_VQSHRNbhu16,   MVE_v16u8, MVE_v8u16, 1,0,0>;
3063defm : MVE_VSHRN_patterns<MVE_VQSHRNthu16,   MVE_v16u8, MVE_v8u16, 1,0,1>;
3064defm : MVE_VSHRN_patterns<MVE_VQSHRNbhu32,   MVE_v8u16, MVE_v4u32, 1,0,0>;
3065defm : MVE_VSHRN_patterns<MVE_VQSHRNthu32,   MVE_v8u16, MVE_v4u32, 1,0,1>;
3066defm : MVE_VSHRN_patterns<MVE_VQRSHRNbhs16,  MVE_v16s8, MVE_v8s16, 1,1,0>;
3067defm : MVE_VSHRN_patterns<MVE_VQRSHRNths16,  MVE_v16s8, MVE_v8s16, 1,1,1>;
3068defm : MVE_VSHRN_patterns<MVE_VQRSHRNbhs32,  MVE_v8s16, MVE_v4s32, 1,1,0>;
3069defm : MVE_VSHRN_patterns<MVE_VQRSHRNths32,  MVE_v8s16, MVE_v4s32, 1,1,1>;
3070defm : MVE_VSHRN_patterns<MVE_VQRSHRNbhu16,  MVE_v16u8, MVE_v8u16, 1,1,0>;
3071defm : MVE_VSHRN_patterns<MVE_VQRSHRNthu16,  MVE_v16u8, MVE_v8u16, 1,1,1>;
3072defm : MVE_VSHRN_patterns<MVE_VQRSHRNbhu32,  MVE_v8u16, MVE_v4u32, 1,1,0>;
3073defm : MVE_VSHRN_patterns<MVE_VQRSHRNthu32,  MVE_v8u16, MVE_v4u32, 1,1,1>;
3074defm : MVE_VSHRN_patterns<MVE_VQSHRUNs16bh,  MVE_v16u8, MVE_v8s16, 1,0,0>;
3075defm : MVE_VSHRN_patterns<MVE_VQSHRUNs16th,  MVE_v16u8, MVE_v8s16, 1,0,1>;
3076defm : MVE_VSHRN_patterns<MVE_VQSHRUNs32bh,  MVE_v8u16, MVE_v4s32, 1,0,0>;
3077defm : MVE_VSHRN_patterns<MVE_VQSHRUNs32th,  MVE_v8u16, MVE_v4s32, 1,0,1>;
3078defm : MVE_VSHRN_patterns<MVE_VQRSHRUNs16bh, MVE_v16u8, MVE_v8s16, 1,1,0>;
3079defm : MVE_VSHRN_patterns<MVE_VQRSHRUNs16th, MVE_v16u8, MVE_v8s16, 1,1,1>;
3080defm : MVE_VSHRN_patterns<MVE_VQRSHRUNs32bh, MVE_v8u16, MVE_v4s32, 1,1,0>;
3081defm : MVE_VSHRN_patterns<MVE_VQRSHRUNs32th, MVE_v8u16, MVE_v4s32, 1,1,1>;
3082
3083// end of mve_imm_shift instructions
3084
3085// start of mve_shift instructions
3086
3087class MVE_shift_by_vec<string iname, string suffix, bit U,
3088                       bits<2> size, bit bit_4, bit bit_8>
3089  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qm, MQPR:$Qn), NoItinerary,
3090           iname, suffix, "$Qd, $Qm, $Qn", vpred_r, "", []> {
3091  // Shift instructions which take a vector of shift counts
3092  bits<4> Qd;
3093  bits<4> Qm;
3094  bits<4> Qn;
3095
3096  let Inst{28} = U;
3097  let Inst{25-24} = 0b11;
3098  let Inst{23} = 0b0;
3099  let Inst{22} = Qd{3};
3100  let Inst{21-20} = size;
3101  let Inst{19-17} = Qn{2-0};
3102  let Inst{16} = 0b0;
3103  let Inst{15-13} = Qd{2-0};
3104  let Inst{12-9} = 0b0010;
3105  let Inst{8} = bit_8;
3106  let Inst{7} = Qn{3};
3107  let Inst{6} = 0b1;
3108  let Inst{5} = Qm{3};
3109  let Inst{4} = bit_4;
3110  let Inst{3-1} = Qm{2-0};
3111  let Inst{0} = 0b0;
3112  let validForTailPredication = 1;
3113}
3114
3115multiclass MVE_shift_by_vec_p<string iname, MVEVectorVTInfo VTI, bit q, bit r> {
3116  def "" : MVE_shift_by_vec<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, q, r>;
3117  defvar Inst = !cast<Instruction>(NAME);
3118
3119  def : Pat<(VTI.Vec (int_arm_mve_vshl_vector
3120                         (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh),
3121                         (i32 q), (i32 r), (i32 VTI.Unsigned))),
3122            (VTI.Vec (Inst (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh)))>;
3123
3124  def : Pat<(VTI.Vec (int_arm_mve_vshl_vector_predicated
3125                         (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh),
3126                         (i32 q), (i32 r), (i32 VTI.Unsigned),
3127                         (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))),
3128            (VTI.Vec (Inst (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh),
3129                           ARMVCCThen, (VTI.Pred VCCR:$mask),
3130                           (VTI.Vec MQPR:$inactive)))>;
3131}
3132
3133multiclass mve_shift_by_vec_multi<string iname, bit bit_4, bit bit_8> {
3134  defm s8  : MVE_shift_by_vec_p<iname, MVE_v16s8, bit_4, bit_8>;
3135  defm s16 : MVE_shift_by_vec_p<iname, MVE_v8s16, bit_4, bit_8>;
3136  defm s32 : MVE_shift_by_vec_p<iname, MVE_v4s32, bit_4, bit_8>;
3137  defm u8  : MVE_shift_by_vec_p<iname, MVE_v16u8, bit_4, bit_8>;
3138  defm u16 : MVE_shift_by_vec_p<iname, MVE_v8u16, bit_4, bit_8>;
3139  defm u32 : MVE_shift_by_vec_p<iname, MVE_v4u32, bit_4, bit_8>;
3140}
3141
3142defm MVE_VSHL_by_vec   : mve_shift_by_vec_multi<"vshl",   0b0, 0b0>;
3143defm MVE_VQSHL_by_vec  : mve_shift_by_vec_multi<"vqshl",  0b1, 0b0>;
3144defm MVE_VQRSHL_by_vec : mve_shift_by_vec_multi<"vqrshl", 0b1, 0b1>;
3145defm MVE_VRSHL_by_vec  : mve_shift_by_vec_multi<"vrshl",  0b0, 0b1>;
3146
3147let Predicates = [HasMVEInt] in {
3148  def : Pat<(v4i32 (ARMvshlu (v4i32 MQPR:$Qm), (v4i32 MQPR:$Qn))),
3149            (v4i32 (MVE_VSHL_by_vecu32 (v4i32 MQPR:$Qm), (v4i32 MQPR:$Qn)))>;
3150  def : Pat<(v8i16 (ARMvshlu (v8i16 MQPR:$Qm), (v8i16 MQPR:$Qn))),
3151            (v8i16 (MVE_VSHL_by_vecu16 (v8i16 MQPR:$Qm), (v8i16 MQPR:$Qn)))>;
3152  def : Pat<(v16i8 (ARMvshlu (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn))),
3153            (v16i8 (MVE_VSHL_by_vecu8 (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn)))>;
3154
3155  def : Pat<(v4i32 (ARMvshls (v4i32 MQPR:$Qm), (v4i32 MQPR:$Qn))),
3156            (v4i32 (MVE_VSHL_by_vecs32 (v4i32 MQPR:$Qm), (v4i32 MQPR:$Qn)))>;
3157  def : Pat<(v8i16 (ARMvshls (v8i16 MQPR:$Qm), (v8i16 MQPR:$Qn))),
3158            (v8i16 (MVE_VSHL_by_vecs16 (v8i16 MQPR:$Qm), (v8i16 MQPR:$Qn)))>;
3159  def : Pat<(v16i8 (ARMvshls (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn))),
3160            (v16i8 (MVE_VSHL_by_vecs8 (v16i8 MQPR:$Qm), (v16i8 MQPR:$Qn)))>;
3161}
3162
3163class MVE_shift_with_imm<string iname, string suffix, dag oops, dag iops,
3164                         string ops, vpred_ops vpred, string cstr,
3165                         list<dag> pattern=[]>
3166  : MVE_p<oops, iops, NoItinerary, iname, suffix, ops, vpred, cstr, pattern> {
3167  bits<4> Qd;
3168  bits<4> Qm;
3169
3170  let Inst{23} = 0b1;
3171  let Inst{22} = Qd{3};
3172  let Inst{15-13} = Qd{2-0};
3173  let Inst{12-11} = 0b00;
3174  let Inst{7-6} = 0b01;
3175  let Inst{5} = Qm{3};
3176  let Inst{4} = 0b1;
3177  let Inst{3-1} = Qm{2-0};
3178  let Inst{0} = 0b0;
3179  let validForTailPredication = 1;
3180
3181  // For the MVE_shift_imm_patterns multiclass to refer to
3182  MVEVectorVTInfo VTI;
3183  Operand immediateType;
3184  Intrinsic unpred_int;
3185  Intrinsic pred_int;
3186  dag unsignedFlag = (?);
3187}
3188
3189class MVE_VSxI_imm<string iname, string suffix, bit bit_8, Operand immType>
3190  : MVE_shift_with_imm<iname, suffix, (outs MQPR:$Qd),
3191                       (ins MQPR:$Qd_src, MQPR:$Qm, immType:$imm),
3192                       "$Qd, $Qm, $imm", vpred_n, "$Qd = $Qd_src"> {
3193  bits<6> imm;
3194  let Inst{28} = 0b1;
3195  let Inst{25-24} = 0b11;
3196  let Inst{21-16} = imm;
3197  let Inst{10-9} = 0b10;
3198  let Inst{8} = bit_8;
3199  let validForTailPredication = 1;
3200
3201  Operand immediateType = immType;
3202}
3203
3204def MVE_VSRIimm8 : MVE_VSxI_imm<"vsri", "8", 0b0, shr_imm8> {
3205  let Inst{21-19} = 0b001;
3206}
3207
3208def MVE_VSRIimm16 : MVE_VSxI_imm<"vsri", "16", 0b0, shr_imm16> {
3209  let Inst{21-20} = 0b01;
3210}
3211
3212def MVE_VSRIimm32 : MVE_VSxI_imm<"vsri", "32", 0b0, shr_imm32> {
3213  let Inst{21} = 0b1;
3214}
3215
3216def MVE_VSLIimm8 : MVE_VSxI_imm<"vsli", "8", 0b1, imm0_7> {
3217  let Inst{21-19} = 0b001;
3218}
3219
3220def MVE_VSLIimm16 : MVE_VSxI_imm<"vsli", "16", 0b1, imm0_15> {
3221  let Inst{21-20} = 0b01;
3222}
3223
3224def MVE_VSLIimm32 : MVE_VSxI_imm<"vsli", "32", 0b1,imm0_31> {
3225  let Inst{21} = 0b1;
3226}
3227
3228multiclass MVE_VSxI_patterns<MVE_VSxI_imm inst, string name,
3229                              MVEVectorVTInfo VTI> {
3230  defvar inparams = (? (VTI.Vec MQPR:$QdSrc), (VTI.Vec MQPR:$Qm),
3231                       (inst.immediateType:$imm));
3232  defvar outparams = (inst (VTI.Vec MQPR:$QdSrc), (VTI.Vec MQPR:$Qm),
3233                           (inst.immediateType:$imm));
3234  defvar unpred_int = !cast<Intrinsic>("int_arm_mve_" # name);
3235  defvar pred_int = !cast<Intrinsic>("int_arm_mve_" # name # "_predicated");
3236
3237  def : Pat<(VTI.Vec !setdagop(inparams, unpred_int)),
3238            (VTI.Vec outparams)>;
3239  def : Pat<(VTI.Vec !con(inparams, (pred_int (VTI.Pred VCCR:$pred)))),
3240            (VTI.Vec !con(outparams, (? ARMVCCThen, VCCR:$pred)))>;
3241}
3242
3243defm : MVE_VSxI_patterns<MVE_VSLIimm8,  "vsli", MVE_v16i8>;
3244defm : MVE_VSxI_patterns<MVE_VSLIimm16, "vsli", MVE_v8i16>;
3245defm : MVE_VSxI_patterns<MVE_VSLIimm32, "vsli", MVE_v4i32>;
3246defm : MVE_VSxI_patterns<MVE_VSRIimm8,  "vsri", MVE_v16i8>;
3247defm : MVE_VSxI_patterns<MVE_VSRIimm16, "vsri", MVE_v8i16>;
3248defm : MVE_VSxI_patterns<MVE_VSRIimm32, "vsri", MVE_v4i32>;
3249
3250class MVE_VQSHL_imm<MVEVectorVTInfo VTI_, Operand immType>
3251  : MVE_shift_with_imm<"vqshl", VTI_.Suffix, (outs MQPR:$Qd),
3252                       (ins MQPR:$Qm, immType:$imm), "$Qd, $Qm, $imm",
3253                       vpred_r, ""> {
3254  bits<6> imm;
3255
3256  let Inst{28} = VTI_.Unsigned;
3257  let Inst{25-24} = 0b11;
3258  let Inst{21-16} = imm;
3259  let Inst{10-8} = 0b111;
3260
3261  let VTI = VTI_;
3262  let immediateType = immType;
3263  let unsignedFlag = (? (i32 VTI.Unsigned));
3264}
3265
3266let unpred_int = int_arm_mve_vqshl_imm,
3267    pred_int = int_arm_mve_vqshl_imm_predicated in {
3268  def MVE_VQSHLimms8 : MVE_VQSHL_imm<MVE_v16s8, imm0_7> {
3269    let Inst{21-19} = 0b001;
3270  }
3271  def MVE_VQSHLimmu8 : MVE_VQSHL_imm<MVE_v16u8, imm0_7> {
3272    let Inst{21-19} = 0b001;
3273  }
3274
3275  def MVE_VQSHLimms16 : MVE_VQSHL_imm<MVE_v8s16, imm0_15> {
3276    let Inst{21-20} = 0b01;
3277  }
3278  def MVE_VQSHLimmu16 : MVE_VQSHL_imm<MVE_v8u16, imm0_15> {
3279    let Inst{21-20} = 0b01;
3280  }
3281
3282  def MVE_VQSHLimms32 : MVE_VQSHL_imm<MVE_v4s32, imm0_31> {
3283    let Inst{21} = 0b1;
3284  }
3285  def MVE_VQSHLimmu32 : MVE_VQSHL_imm<MVE_v4u32, imm0_31> {
3286    let Inst{21} = 0b1;
3287  }
3288}
3289
3290class MVE_VQSHLU_imm<MVEVectorVTInfo VTI_, Operand immType>
3291  : MVE_shift_with_imm<"vqshlu", VTI_.Suffix, (outs MQPR:$Qd),
3292                       (ins MQPR:$Qm, immType:$imm), "$Qd, $Qm, $imm",
3293                       vpred_r, ""> {
3294  bits<6> imm;
3295
3296  let Inst{28} = 0b1;
3297  let Inst{25-24} = 0b11;
3298  let Inst{21-16} = imm;
3299  let Inst{10-8} = 0b110;
3300
3301  let VTI = VTI_;
3302  let immediateType = immType;
3303}
3304
3305let unpred_int = int_arm_mve_vqshlu_imm,
3306    pred_int = int_arm_mve_vqshlu_imm_predicated in {
3307  def MVE_VQSHLU_imms8 : MVE_VQSHLU_imm<MVE_v16s8, imm0_7> {
3308    let Inst{21-19} = 0b001;
3309  }
3310
3311  def MVE_VQSHLU_imms16 : MVE_VQSHLU_imm<MVE_v8s16, imm0_15> {
3312    let Inst{21-20} = 0b01;
3313  }
3314
3315  def MVE_VQSHLU_imms32 : MVE_VQSHLU_imm<MVE_v4s32, imm0_31> {
3316    let Inst{21} = 0b1;
3317  }
3318}
3319
3320class MVE_VRSHR_imm<MVEVectorVTInfo VTI_, Operand immType>
3321  : MVE_shift_with_imm<"vrshr", VTI_.Suffix, (outs MQPR:$Qd),
3322                       (ins MQPR:$Qm, immType:$imm), "$Qd, $Qm, $imm",
3323                       vpred_r, ""> {
3324  bits<6> imm;
3325
3326  let Inst{28} = VTI_.Unsigned;
3327  let Inst{25-24} = 0b11;
3328  let Inst{21-16} = imm;
3329  let Inst{10-8} = 0b010;
3330
3331  let VTI = VTI_;
3332  let immediateType = immType;
3333  let unsignedFlag = (? (i32 VTI.Unsigned));
3334}
3335
3336let unpred_int = int_arm_mve_vrshr_imm,
3337    pred_int = int_arm_mve_vrshr_imm_predicated in {
3338  def MVE_VRSHR_imms8 : MVE_VRSHR_imm<MVE_v16s8, shr_imm8> {
3339    let Inst{21-19} = 0b001;
3340  }
3341
3342  def MVE_VRSHR_immu8 : MVE_VRSHR_imm<MVE_v16u8, shr_imm8> {
3343    let Inst{21-19} = 0b001;
3344  }
3345
3346  def MVE_VRSHR_imms16 : MVE_VRSHR_imm<MVE_v8s16, shr_imm16> {
3347    let Inst{21-20} = 0b01;
3348  }
3349
3350  def MVE_VRSHR_immu16 : MVE_VRSHR_imm<MVE_v8u16, shr_imm16> {
3351    let Inst{21-20} = 0b01;
3352  }
3353
3354  def MVE_VRSHR_imms32 : MVE_VRSHR_imm<MVE_v4s32, shr_imm32> {
3355    let Inst{21} = 0b1;
3356  }
3357
3358  def MVE_VRSHR_immu32 : MVE_VRSHR_imm<MVE_v4u32, shr_imm32> {
3359    let Inst{21} = 0b1;
3360  }
3361}
3362
3363multiclass MVE_shift_imm_patterns<MVE_shift_with_imm inst> {
3364  def : Pat<(inst.VTI.Vec !con((inst.unpred_int (inst.VTI.Vec MQPR:$src),
3365                                                inst.immediateType:$imm),
3366                               inst.unsignedFlag)),
3367            (inst.VTI.Vec (inst (inst.VTI.Vec MQPR:$src),
3368                                inst.immediateType:$imm))>;
3369
3370  def : Pat<(inst.VTI.Vec !con((inst.pred_int (inst.VTI.Vec MQPR:$src),
3371                                              inst.immediateType:$imm),
3372                               inst.unsignedFlag,
3373                               (? (inst.VTI.Pred VCCR:$mask),
3374                                  (inst.VTI.Vec MQPR:$inactive)))),
3375            (inst.VTI.Vec (inst (inst.VTI.Vec MQPR:$src),
3376                                inst.immediateType:$imm,
3377                                ARMVCCThen, (inst.VTI.Pred VCCR:$mask),
3378                                (inst.VTI.Vec MQPR:$inactive)))>;
3379}
3380
3381defm : MVE_shift_imm_patterns<MVE_VQSHLimms8>;
3382defm : MVE_shift_imm_patterns<MVE_VQSHLimmu8>;
3383defm : MVE_shift_imm_patterns<MVE_VQSHLimms16>;
3384defm : MVE_shift_imm_patterns<MVE_VQSHLimmu16>;
3385defm : MVE_shift_imm_patterns<MVE_VQSHLimms32>;
3386defm : MVE_shift_imm_patterns<MVE_VQSHLimmu32>;
3387defm : MVE_shift_imm_patterns<MVE_VQSHLU_imms8>;
3388defm : MVE_shift_imm_patterns<MVE_VQSHLU_imms16>;
3389defm : MVE_shift_imm_patterns<MVE_VQSHLU_imms32>;
3390defm : MVE_shift_imm_patterns<MVE_VRSHR_imms8>;
3391defm : MVE_shift_imm_patterns<MVE_VRSHR_immu8>;
3392defm : MVE_shift_imm_patterns<MVE_VRSHR_imms16>;
3393defm : MVE_shift_imm_patterns<MVE_VRSHR_immu16>;
3394defm : MVE_shift_imm_patterns<MVE_VRSHR_imms32>;
3395defm : MVE_shift_imm_patterns<MVE_VRSHR_immu32>;
3396
3397class MVE_VSHR_imm<string suffix, dag imm>
3398  : MVE_shift_with_imm<"vshr", suffix, (outs MQPR:$Qd),
3399                       !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
3400                       vpred_r, ""> {
3401  bits<6> imm;
3402
3403  let Inst{25-24} = 0b11;
3404  let Inst{21-16} = imm;
3405  let Inst{10-8} = 0b000;
3406}
3407
3408def MVE_VSHR_imms8 : MVE_VSHR_imm<"s8", (ins shr_imm8:$imm)> {
3409  let Inst{28} = 0b0;
3410  let Inst{21-19} = 0b001;
3411}
3412
3413def MVE_VSHR_immu8 : MVE_VSHR_imm<"u8", (ins shr_imm8:$imm)> {
3414  let Inst{28} = 0b1;
3415  let Inst{21-19} = 0b001;
3416}
3417
3418def MVE_VSHR_imms16 : MVE_VSHR_imm<"s16", (ins shr_imm16:$imm)> {
3419  let Inst{28} = 0b0;
3420  let Inst{21-20} = 0b01;
3421}
3422
3423def MVE_VSHR_immu16 : MVE_VSHR_imm<"u16", (ins shr_imm16:$imm)> {
3424  let Inst{28} = 0b1;
3425  let Inst{21-20} = 0b01;
3426}
3427
3428def MVE_VSHR_imms32 : MVE_VSHR_imm<"s32", (ins shr_imm32:$imm)> {
3429  let Inst{28} = 0b0;
3430  let Inst{21} = 0b1;
3431}
3432
3433def MVE_VSHR_immu32 : MVE_VSHR_imm<"u32", (ins shr_imm32:$imm)> {
3434  let Inst{28} = 0b1;
3435  let Inst{21} = 0b1;
3436}
3437
3438class MVE_VSHL_imm<string suffix, dag imm>
3439  : MVE_shift_with_imm<"vshl", suffix, (outs MQPR:$Qd),
3440                       !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
3441                       vpred_r, ""> {
3442  bits<6> imm;
3443
3444  let Inst{28} = 0b0;
3445  let Inst{25-24} = 0b11;
3446  let Inst{21-16} = imm;
3447  let Inst{10-8} = 0b101;
3448}
3449
3450def MVE_VSHL_immi8 : MVE_VSHL_imm<"i8", (ins imm0_7:$imm)> {
3451  let Inst{21-19} = 0b001;
3452}
3453
3454def MVE_VSHL_immi16 : MVE_VSHL_imm<"i16", (ins imm0_15:$imm)> {
3455  let Inst{21-20} = 0b01;
3456}
3457
3458def MVE_VSHL_immi32 : MVE_VSHL_imm<"i32", (ins imm0_31:$imm)> {
3459  let Inst{21} = 0b1;
3460}
3461
3462multiclass MVE_immediate_shift_patterns_inner<
3463    MVEVectorVTInfo VTI, Operand imm_operand_type, SDNode unpred_op,
3464    Intrinsic pred_int, Instruction inst, list<int> unsignedFlag = []> {
3465
3466  def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$src), imm_operand_type:$imm)),
3467            (VTI.Vec (inst (VTI.Vec MQPR:$src), imm_operand_type:$imm))>;
3468
3469  def : Pat<(VTI.Vec !con((pred_int (VTI.Vec MQPR:$src), imm_operand_type:$imm),
3470                          !dag(pred_int, unsignedFlag, ?),
3471                          (pred_int (VTI.Pred VCCR:$mask),
3472                                   (VTI.Vec MQPR:$inactive)))),
3473            (VTI.Vec (inst (VTI.Vec MQPR:$src), imm_operand_type:$imm,
3474                           ARMVCCThen, (VTI.Pred VCCR:$mask),
3475                           (VTI.Vec MQPR:$inactive)))>;
3476}
3477
3478multiclass MVE_immediate_shift_patterns<MVEVectorVTInfo VTI,
3479                                        Operand imm_operand_type> {
3480  defm : MVE_immediate_shift_patterns_inner<VTI, imm_operand_type,
3481      ARMvshlImm, int_arm_mve_shl_imm_predicated,
3482      !cast<Instruction>("MVE_VSHL_immi" # VTI.BitsSuffix)>;
3483  defm : MVE_immediate_shift_patterns_inner<VTI, imm_operand_type,
3484      ARMvshruImm, int_arm_mve_shr_imm_predicated,
3485      !cast<Instruction>("MVE_VSHR_immu" # VTI.BitsSuffix), [1]>;
3486  defm : MVE_immediate_shift_patterns_inner<VTI, imm_operand_type,
3487      ARMvshrsImm, int_arm_mve_shr_imm_predicated,
3488      !cast<Instruction>("MVE_VSHR_imms" # VTI.BitsSuffix), [0]>;
3489}
3490
3491let Predicates = [HasMVEInt] in {
3492  defm : MVE_immediate_shift_patterns<MVE_v16i8, imm0_7>;
3493  defm : MVE_immediate_shift_patterns<MVE_v8i16, imm0_15>;
3494  defm : MVE_immediate_shift_patterns<MVE_v4i32, imm0_31>;
3495}
3496
3497// end of mve_shift instructions
3498
3499// start of MVE Floating Point instructions
3500
3501class MVE_float<string iname, string suffix, dag oops, dag iops, string ops,
3502                vpred_ops vpred, string cstr, list<dag> pattern=[]>
3503  : MVE_f<oops, iops, NoItinerary, iname, suffix, ops, vpred, cstr, pattern> {
3504  bits<4> Qm;
3505
3506  let Inst{12} = 0b0;
3507  let Inst{6} = 0b1;
3508  let Inst{5} = Qm{3};
3509  let Inst{3-1} = Qm{2-0};
3510  let Inst{0} = 0b0;
3511}
3512
3513class MVE_VRINT<string rmode, bits<3> op, string suffix, bits<2> size,
3514                list<dag> pattern=[]>
3515  : MVE_float<!strconcat("vrint", rmode), suffix, (outs MQPR:$Qd),
3516              (ins MQPR:$Qm), "$Qd, $Qm", vpred_r, "", pattern> {
3517  bits<4> Qd;
3518
3519  let Inst{28} = 0b1;
3520  let Inst{25-23} = 0b111;
3521  let Inst{22} = Qd{3};
3522  let Inst{21-20} = 0b11;
3523  let Inst{19-18} = size;
3524  let Inst{17-16} = 0b10;
3525  let Inst{15-13} = Qd{2-0};
3526  let Inst{11-10} = 0b01;
3527  let Inst{9-7} = op{2-0};
3528  let Inst{4} = 0b0;
3529  let validForTailPredication = 1;
3530
3531}
3532
3533multiclass MVE_VRINT_m<MVEVectorVTInfo VTI, string suffix, bits<3> opcode,
3534                       SDNode unpred_op> {
3535  def "": MVE_VRINT<suffix, opcode, VTI.Suffix, VTI.Size>;
3536  defvar Inst = !cast<Instruction>(NAME);
3537  defvar pred_int = !cast<Intrinsic>("int_arm_mve_vrint"#suffix#"_predicated");
3538
3539  let Predicates = [HasMVEFloat] in {
3540    def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$val))),
3541              (VTI.Vec (Inst (VTI.Vec MQPR:$val)))>;
3542    def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$val), (VTI.Pred VCCR:$pred),
3543                                 (VTI.Vec MQPR:$inactive))),
3544              (VTI.Vec (Inst (VTI.Vec MQPR:$val), ARMVCCThen,
3545                             (VTI.Pred VCCR:$pred), (VTI.Vec MQPR:$inactive)))>;
3546  }
3547}
3548
3549multiclass MVE_VRINT_ops<MVEVectorVTInfo VTI> {
3550  defm N : MVE_VRINT_m<VTI, "n", 0b000, int_arm_mve_vrintn>;
3551  defm X : MVE_VRINT_m<VTI, "x", 0b001, frint>;
3552  defm A : MVE_VRINT_m<VTI, "a", 0b010, fround>;
3553  defm Z : MVE_VRINT_m<VTI, "z", 0b011, ftrunc>;
3554  defm M : MVE_VRINT_m<VTI, "m", 0b101, ffloor>;
3555  defm P : MVE_VRINT_m<VTI, "p", 0b111, fceil>;
3556}
3557
3558defm MVE_VRINTf16 : MVE_VRINT_ops<MVE_v8f16>;
3559defm MVE_VRINTf32 : MVE_VRINT_ops<MVE_v4f32>;
3560
3561class MVEFloatArithNeon<string iname, string suffix, bit size,
3562                           dag oops, dag iops, string ops,
3563                           vpred_ops vpred, string cstr, list<dag> pattern=[]>
3564  : MVE_float<iname, suffix, oops, iops, ops, vpred, cstr, pattern> {
3565  let Inst{20} = size;
3566  let Inst{16} = 0b0;
3567}
3568
3569class MVE_VMUL_fp<string iname, string suffix, bit size, list<dag> pattern=[]>
3570  : MVEFloatArithNeon<iname, suffix, size, (outs MQPR:$Qd),
3571                      (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm", vpred_r, "",
3572                      pattern> {
3573  bits<4> Qd;
3574  bits<4> Qn;
3575
3576  let Inst{28} = 0b1;
3577  let Inst{25-23} = 0b110;
3578  let Inst{22} = Qd{3};
3579  let Inst{21} = 0b0;
3580  let Inst{19-17} = Qn{2-0};
3581  let Inst{15-13} = Qd{2-0};
3582  let Inst{12-8} = 0b01101;
3583  let Inst{7} = Qn{3};
3584  let Inst{4} = 0b1;
3585  let validForTailPredication = 1;
3586}
3587
3588multiclass MVE_VMULT_fp_m<string iname, bit bit_21, MVEVectorVTInfo VTI,
3589                            SDNode Op, Intrinsic PredInt> {
3590  def "" : MVE_VMUL_fp<iname, VTI.Suffix, VTI.Size{0}>;
3591  defvar Inst = !cast<Instruction>(NAME);
3592
3593  let Predicates = [HasMVEFloat] in {
3594    defm : MVE_TwoOpPattern<VTI, Op, PredInt, (? ), !cast<Instruction>(NAME)>;
3595  }
3596}
3597
3598multiclass MVE_VMUL_fp_m<MVEVectorVTInfo VTI>
3599  : MVE_VMULT_fp_m<"vmul", 0, VTI, fmul, int_arm_mve_mul_predicated>;
3600
3601defm MVE_VMULf32 : MVE_VMUL_fp_m<MVE_v4f32>;
3602defm MVE_VMULf16 : MVE_VMUL_fp_m<MVE_v8f16>;
3603
3604class MVE_VCMLA<string suffix, bit size>
3605  : MVEFloatArithNeon<"vcmla", suffix, size, (outs MQPR:$Qd),
3606                         (ins MQPR:$Qd_src, MQPR:$Qn, MQPR:$Qm, complexrotateop:$rot),
3607                         "$Qd, $Qn, $Qm, $rot", vpred_n, "$Qd = $Qd_src", []> {
3608  bits<4> Qd;
3609  bits<4> Qn;
3610  bits<2> rot;
3611
3612  let Inst{28} = 0b1;
3613  let Inst{25} = 0b0;
3614  let Inst{24-23} = rot;
3615  let Inst{22} = Qd{3};
3616  let Inst{21} = 0b1;
3617  let Inst{19-17} = Qn{2-0};
3618  let Inst{15-13} = Qd{2-0};
3619  let Inst{12-8} = 0b01000;
3620  let Inst{7} = Qn{3};
3621  let Inst{4} = 0b0;
3622}
3623
3624multiclass MVE_VCMLA_m<MVEVectorVTInfo VTI, bit size> {
3625  def "" : MVE_VCMLA<VTI.Suffix, size>;
3626  defvar Inst = !cast<Instruction>(NAME);
3627
3628  let Predicates = [HasMVEFloat] in {
3629    def : Pat<(VTI.Vec (int_arm_mve_vcmlaq
3630                            imm:$rot, (VTI.Vec MQPR:$Qd_src),
3631                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
3632              (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src),
3633                             (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
3634                             imm:$rot))>;
3635
3636    def : Pat<(VTI.Vec (int_arm_mve_vcmlaq_predicated
3637                            imm:$rot, (VTI.Vec MQPR:$Qd_src),
3638                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
3639                            (VTI.Pred VCCR:$mask))),
3640              (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src), (VTI.Vec MQPR:$Qn),
3641                             (VTI.Vec MQPR:$Qm), imm:$rot,
3642                             ARMVCCThen, (VTI.Pred VCCR:$mask)))>;
3643
3644  }
3645}
3646
3647defm MVE_VCMLAf16 : MVE_VCMLA_m<MVE_v8f16, 0b0>;
3648defm MVE_VCMLAf32 : MVE_VCMLA_m<MVE_v4f32, 0b1>;
3649
3650class MVE_VADDSUBFMA_fp<string iname, string suffix, bit size, bit bit_4,
3651                        bit bit_8, bit bit_21, dag iops=(ins),
3652                        vpred_ops vpred=vpred_r, string cstr="",
3653                        list<dag> pattern=[]>
3654  : MVEFloatArithNeon<iname, suffix, size, (outs MQPR:$Qd),
3655                      !con(iops, (ins MQPR:$Qn, MQPR:$Qm)), "$Qd, $Qn, $Qm",
3656                      vpred, cstr, pattern> {
3657  bits<4> Qd;
3658  bits<4> Qn;
3659
3660  let Inst{28} = 0b0;
3661  let Inst{25-23} = 0b110;
3662  let Inst{22} = Qd{3};
3663  let Inst{21} = bit_21;
3664  let Inst{19-17} = Qn{2-0};
3665  let Inst{15-13} = Qd{2-0};
3666  let Inst{11-9} = 0b110;
3667  let Inst{8} = bit_8;
3668  let Inst{7} = Qn{3};
3669  let Inst{4} = bit_4;
3670  let validForTailPredication = 1;
3671}
3672
3673multiclass MVE_VFMA_fp_multi<string iname, bit fms, MVEVectorVTInfo VTI> {
3674  def "" : MVE_VADDSUBFMA_fp<iname, VTI.Suffix, VTI.Size{0}, 0b1, 0b0, fms,
3675                             (ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">;
3676  defvar Inst = !cast<Instruction>(NAME);
3677  defvar pred_int = int_arm_mve_fma_predicated;
3678  defvar m1   = (VTI.Vec MQPR:$m1);
3679  defvar m2   = (VTI.Vec MQPR:$m2);
3680  defvar add  = (VTI.Vec MQPR:$add);
3681  defvar pred = (VTI.Pred VCCR:$pred);
3682
3683  let Predicates = [HasMVEFloat] in {
3684    if fms then {
3685      def : Pat<(VTI.Vec (fma (fneg m1), m2, add)),
3686                (Inst $add, $m1, $m2)>;
3687      def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
3688                                  (VTI.Vec (fma (fneg m1), m2, add)),
3689                                  add)),
3690                (Inst $add, $m1, $m2, ARMVCCThen, $pred)>;
3691      def : Pat<(VTI.Vec (pred_int (fneg m1), m2, add, pred)),
3692                (Inst $add, $m1, $m2, ARMVCCThen, $pred)>;
3693      def : Pat<(VTI.Vec (pred_int m1, (fneg m2), add, pred)),
3694                (Inst $add, $m1, $m2, ARMVCCThen, $pred)>;
3695    } else {
3696      def : Pat<(VTI.Vec (fma m1, m2, add)),
3697                (Inst $add, $m1, $m2)>;
3698      def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
3699                                  (VTI.Vec (fma m1, m2, add)),
3700                                  add)),
3701                (Inst $add, $m1, $m2, ARMVCCThen, $pred)>;
3702      def : Pat<(VTI.Vec (pred_int m1, m2, add, pred)),
3703                (Inst $add, $m1, $m2, ARMVCCThen, $pred)>;
3704    }
3705  }
3706}
3707
3708defm MVE_VFMAf32 : MVE_VFMA_fp_multi<"vfma", 0, MVE_v4f32>;
3709defm MVE_VFMAf16 : MVE_VFMA_fp_multi<"vfma", 0, MVE_v8f16>;
3710defm MVE_VFMSf32 : MVE_VFMA_fp_multi<"vfms", 1, MVE_v4f32>;
3711defm MVE_VFMSf16 : MVE_VFMA_fp_multi<"vfms", 1, MVE_v8f16>;
3712
3713multiclass MVE_VADDSUB_fp_m<string iname, bit bit_21, MVEVectorVTInfo VTI,
3714                            SDNode Op, Intrinsic PredInt> {
3715  def "" : MVE_VADDSUBFMA_fp<iname, VTI.Suffix, VTI.Size{0}, 0, 1, bit_21> {
3716    let validForTailPredication = 1;
3717  }
3718  defvar Inst = !cast<Instruction>(NAME);
3719
3720  let Predicates = [HasMVEFloat] in {
3721    defm : MVE_TwoOpPattern<VTI, Op, PredInt, (? ), !cast<Instruction>(NAME)>;
3722  }
3723}
3724
3725multiclass MVE_VADD_fp_m<MVEVectorVTInfo VTI>
3726  : MVE_VADDSUB_fp_m<"vadd", 0, VTI, fadd, int_arm_mve_add_predicated>;
3727multiclass MVE_VSUB_fp_m<MVEVectorVTInfo VTI>
3728  : MVE_VADDSUB_fp_m<"vsub", 1, VTI, fsub, int_arm_mve_sub_predicated>;
3729
3730defm MVE_VADDf32 : MVE_VADD_fp_m<MVE_v4f32>;
3731defm MVE_VADDf16 : MVE_VADD_fp_m<MVE_v8f16>;
3732
3733defm MVE_VSUBf32 : MVE_VSUB_fp_m<MVE_v4f32>;
3734defm MVE_VSUBf16 : MVE_VSUB_fp_m<MVE_v8f16>;
3735
3736class MVE_VCADD<string suffix, bit size, string cstr="">
3737  : MVEFloatArithNeon<"vcadd", suffix, size, (outs MQPR:$Qd),
3738                         (ins MQPR:$Qn, MQPR:$Qm, complexrotateopodd:$rot),
3739                         "$Qd, $Qn, $Qm, $rot", vpred_r, cstr, []> {
3740  bits<4> Qd;
3741  bits<4> Qn;
3742  bit rot;
3743
3744  let Inst{28} = 0b1;
3745  let Inst{25} = 0b0;
3746  let Inst{24} = rot;
3747  let Inst{23} = 0b1;
3748  let Inst{22} = Qd{3};
3749  let Inst{21} = 0b0;
3750  let Inst{19-17} = Qn{2-0};
3751  let Inst{15-13} = Qd{2-0};
3752  let Inst{12-8} = 0b01000;
3753  let Inst{7} = Qn{3};
3754  let Inst{4} = 0b0;
3755}
3756
3757multiclass MVE_VCADD_m<MVEVectorVTInfo VTI, bit size, string cstr=""> {
3758  def "" : MVE_VCADD<VTI.Suffix, size, cstr>;
3759  defvar Inst = !cast<Instruction>(NAME);
3760
3761  let Predicates = [HasMVEFloat] in {
3762    def : Pat<(VTI.Vec (int_arm_mve_vcaddq (i32 1),
3763                            imm:$rot, (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
3764              (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
3765                             imm:$rot))>;
3766
3767    def : Pat<(VTI.Vec (int_arm_mve_vcaddq_predicated (i32 1),
3768                            imm:$rot, (VTI.Vec MQPR:$inactive),
3769                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
3770                            (VTI.Pred VCCR:$mask))),
3771              (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
3772                             imm:$rot, ARMVCCThen, (VTI.Pred VCCR:$mask),
3773                             (VTI.Vec MQPR:$inactive)))>;
3774
3775  }
3776}
3777
3778defm MVE_VCADDf16 : MVE_VCADD_m<MVE_v8f16, 0b0>;
3779defm MVE_VCADDf32 : MVE_VCADD_m<MVE_v4f32, 0b1, "@earlyclobber $Qd">;
3780
3781class MVE_VABD_fp<string suffix, bit size>
3782  : MVE_float<"vabd", suffix, (outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm),
3783              "$Qd, $Qn, $Qm", vpred_r, ""> {
3784  bits<4> Qd;
3785  bits<4> Qn;
3786
3787  let Inst{28} = 0b1;
3788  let Inst{25-23} = 0b110;
3789  let Inst{22} = Qd{3};
3790  let Inst{21} = 0b1;
3791  let Inst{20} = size;
3792  let Inst{19-17} = Qn{2-0};
3793  let Inst{16} = 0b0;
3794  let Inst{15-13} = Qd{2-0};
3795  let Inst{11-8} = 0b1101;
3796  let Inst{7} = Qn{3};
3797  let Inst{4} = 0b0;
3798  let validForTailPredication = 1;
3799}
3800
3801multiclass MVE_VABDT_fp_m<MVEVectorVTInfo VTI,
3802                            Intrinsic unpred_int, Intrinsic pred_int> {
3803  def "" : MVE_VABD_fp<VTI.Suffix, VTI.Size{0}>;
3804  defvar Inst = !cast<Instruction>(NAME);
3805
3806  let Predicates = [HasMVEFloat] in {
3807    def : Pat<(VTI.Vec (unpred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
3808                            (i32 0))),
3809              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
3810    def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
3811                            (i32 0), (VTI.Pred VCCR:$mask),
3812                            (VTI.Vec MQPR:$inactive))),
3813              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
3814                             ARMVCCThen, (VTI.Pred VCCR:$mask),
3815                             (VTI.Vec MQPR:$inactive)))>;
3816  }
3817}
3818
3819multiclass MVE_VABD_fp_m<MVEVectorVTInfo VTI>
3820  : MVE_VABDT_fp_m<VTI, int_arm_mve_vabd, int_arm_mve_abd_predicated>;
3821
3822defm MVE_VABDf32 : MVE_VABD_fp_m<MVE_v4f32>;
3823defm MVE_VABDf16 : MVE_VABD_fp_m<MVE_v8f16>;
3824
3825let Predicates = [HasMVEFloat] in {
3826  def : Pat<(v8f16 (fabs (fsub (v8f16 MQPR:$Qm), (v8f16 MQPR:$Qn)))),
3827            (MVE_VABDf16 MQPR:$Qm, MQPR:$Qn)>;
3828  def : Pat<(v4f32 (fabs (fsub (v4f32 MQPR:$Qm), (v4f32 MQPR:$Qn)))),
3829            (MVE_VABDf32 MQPR:$Qm, MQPR:$Qn)>;
3830}
3831
3832class MVE_VCVT_fix<string suffix, bit fsi, bit U, bit op,
3833                   Operand imm_operand_type>
3834  : MVE_float<"vcvt", suffix,
3835              (outs MQPR:$Qd), (ins MQPR:$Qm, imm_operand_type:$imm6),
3836              "$Qd, $Qm, $imm6", vpred_r, "", []> {
3837  bits<4> Qd;
3838  bits<6> imm6;
3839
3840  let Inst{28} = U;
3841  let Inst{25-23} = 0b111;
3842  let Inst{22} = Qd{3};
3843  let Inst{21} = 0b1;
3844  let Inst{19-16} = imm6{3-0};
3845  let Inst{15-13} = Qd{2-0};
3846  let Inst{11-10} = 0b11;
3847  let Inst{9} = fsi;
3848  let Inst{8} = op;
3849  let Inst{7} = 0b0;
3850  let Inst{4} = 0b1;
3851
3852  let DecoderMethod = "DecodeMVEVCVTt1fp";
3853  let validForTailPredication = 1;
3854}
3855
3856class MVE_VCVT_imm_asmop<int Bits> : AsmOperandClass {
3857  let PredicateMethod = "isImmediate<1," # Bits # ">";
3858  let DiagnosticString =
3859      "MVE fixed-point immediate operand must be between 1 and " # Bits;
3860  let Name = "MVEVcvtImm" # Bits;
3861  let RenderMethod = "addImmOperands";
3862}
3863class MVE_VCVT_imm<int Bits>: Operand<i32> {
3864  let ParserMatchClass = MVE_VCVT_imm_asmop<Bits>;
3865  let EncoderMethod = "getNEONVcvtImm32OpValue";
3866  let DecoderMethod = "DecodeVCVTImmOperand";
3867}
3868
3869class MVE_VCVT_fix_f32<string suffix, bit U, bit op>
3870    : MVE_VCVT_fix<suffix, 0b1, U, op, MVE_VCVT_imm<32>> {
3871  let Inst{20} = imm6{4};
3872}
3873class MVE_VCVT_fix_f16<string suffix, bit U, bit op>
3874    : MVE_VCVT_fix<suffix, 0b0, U, op, MVE_VCVT_imm<16>> {
3875  let Inst{20} = 0b1;
3876}
3877
3878multiclass MVE_VCVT_fix_patterns<Instruction Inst, bit U, MVEVectorVTInfo DestVTI,
3879                                 MVEVectorVTInfo SrcVTI> {
3880  let Predicates = [HasMVEFloat] in {
3881    def : Pat<(DestVTI.Vec (int_arm_mve_vcvt_fix
3882                              (i32 U), (SrcVTI.Vec MQPR:$Qm), imm:$scale)),
3883              (DestVTI.Vec (Inst (SrcVTI.Vec MQPR:$Qm), imm:$scale))>;
3884    def : Pat<(DestVTI.Vec (int_arm_mve_vcvt_fix_predicated (i32 U),
3885                              (DestVTI.Vec MQPR:$inactive),
3886                              (SrcVTI.Vec MQPR:$Qm),
3887                              imm:$scale,
3888                              (DestVTI.Pred VCCR:$mask))),
3889              (DestVTI.Vec (Inst (SrcVTI.Vec MQPR:$Qm), imm:$scale,
3890                             ARMVCCThen, (DestVTI.Pred VCCR:$mask),
3891                             (DestVTI.Vec MQPR:$inactive)))>;
3892  }
3893}
3894
3895multiclass MVE_VCVT_fix_f32_m<bit U, bit op,
3896                              MVEVectorVTInfo DestVTI, MVEVectorVTInfo SrcVTI> {
3897  def "" : MVE_VCVT_fix_f32<DestVTI.Suffix#"."#SrcVTI.Suffix, U, op>;
3898  defm : MVE_VCVT_fix_patterns<!cast<Instruction>(NAME), U, DestVTI, SrcVTI>;
3899}
3900
3901multiclass MVE_VCVT_fix_f16_m<bit U, bit op,
3902                              MVEVectorVTInfo DestVTI, MVEVectorVTInfo SrcVTI> {
3903  def "" : MVE_VCVT_fix_f16<DestVTI.Suffix#"."#SrcVTI.Suffix, U, op>;
3904  defm : MVE_VCVT_fix_patterns<!cast<Instruction>(NAME), U, DestVTI, SrcVTI>;
3905}
3906
3907defm MVE_VCVTf16s16_fix : MVE_VCVT_fix_f16_m<0b0, 0b0, MVE_v8f16, MVE_v8s16>;
3908defm MVE_VCVTs16f16_fix : MVE_VCVT_fix_f16_m<0b0, 0b1, MVE_v8s16, MVE_v8f16>;
3909defm MVE_VCVTf16u16_fix : MVE_VCVT_fix_f16_m<0b1, 0b0, MVE_v8f16, MVE_v8u16>;
3910defm MVE_VCVTu16f16_fix : MVE_VCVT_fix_f16_m<0b1, 0b1, MVE_v8u16, MVE_v8f16>;
3911defm MVE_VCVTf32s32_fix : MVE_VCVT_fix_f32_m<0b0, 0b0, MVE_v4f32, MVE_v4s32>;
3912defm MVE_VCVTs32f32_fix : MVE_VCVT_fix_f32_m<0b0, 0b1, MVE_v4s32, MVE_v4f32>;
3913defm MVE_VCVTf32u32_fix : MVE_VCVT_fix_f32_m<0b1, 0b0, MVE_v4f32, MVE_v4u32>;
3914defm MVE_VCVTu32f32_fix : MVE_VCVT_fix_f32_m<0b1, 0b1, MVE_v4u32, MVE_v4f32>;
3915
3916class MVE_VCVT_fp_int_anpm<string suffix, bits<2> size, bit op, string anpm,
3917                bits<2> rm, list<dag> pattern=[]>
3918  : MVE_float<!strconcat("vcvt", anpm), suffix, (outs MQPR:$Qd),
3919              (ins MQPR:$Qm), "$Qd, $Qm", vpred_r, "", pattern> {
3920  bits<4> Qd;
3921
3922  let Inst{28} = 0b1;
3923  let Inst{25-23} = 0b111;
3924  let Inst{22} = Qd{3};
3925  let Inst{21-20} = 0b11;
3926  let Inst{19-18} = size;
3927  let Inst{17-16} = 0b11;
3928  let Inst{15-13} = Qd{2-0};
3929  let Inst{12-10} = 0b000;
3930  let Inst{9-8} = rm;
3931  let Inst{7} = op;
3932  let Inst{4} = 0b0;
3933  let validForTailPredication = 1;
3934}
3935
3936multiclass MVE_VCVT_fp_int_anpm_inner<MVEVectorVTInfo Int, MVEVectorVTInfo Flt,
3937                                      string anpm, bits<2> rm> {
3938  def "": MVE_VCVT_fp_int_anpm<Int.Suffix # "." # Flt.Suffix, Int.Size,
3939                               Int.Unsigned, anpm, rm>;
3940
3941  defvar Inst         = !cast<Instruction>(NAME);
3942  defvar IntrBaseName = "int_arm_mve_vcvt" # anpm;
3943  defvar UnpredIntr   = !cast<Intrinsic>(IntrBaseName);
3944  defvar PredIntr     = !cast<Intrinsic>(IntrBaseName # "_predicated");
3945
3946  let Predicates = [HasMVEFloat] in {
3947    def : Pat<(Int.Vec (UnpredIntr (i32 Int.Unsigned), (Flt.Vec MQPR:$in))),
3948              (Int.Vec (Inst (Flt.Vec MQPR:$in)))>;
3949
3950    def : Pat<(Int.Vec (PredIntr (i32 Int.Unsigned), (Int.Vec MQPR:$inactive),
3951                                 (Flt.Vec MQPR:$in), (Flt.Pred VCCR:$pred))),
3952              (Int.Vec (Inst (Flt.Vec MQPR:$in), ARMVCCThen,
3953                             (Flt.Pred VCCR:$pred), (Int.Vec MQPR:$inactive)))>;
3954  }
3955}
3956
3957multiclass MVE_VCVT_fp_int_anpm_outer<MVEVectorVTInfo Int,
3958                                      MVEVectorVTInfo Flt> {
3959  defm a : MVE_VCVT_fp_int_anpm_inner<Int, Flt, "a", 0b00>;
3960  defm n : MVE_VCVT_fp_int_anpm_inner<Int, Flt, "n", 0b01>;
3961  defm p : MVE_VCVT_fp_int_anpm_inner<Int, Flt, "p", 0b10>;
3962  defm m : MVE_VCVT_fp_int_anpm_inner<Int, Flt, "m", 0b11>;
3963}
3964
3965// This defines instructions such as MVE_VCVTu16f16a, with an explicit
3966// rounding-mode suffix on the mnemonic. The class below will define
3967// the bare MVE_VCVTu16f16 (with implied rounding toward zero).
3968defm MVE_VCVTs16f16 : MVE_VCVT_fp_int_anpm_outer<MVE_v8s16, MVE_v8f16>;
3969defm MVE_VCVTu16f16 : MVE_VCVT_fp_int_anpm_outer<MVE_v8u16, MVE_v8f16>;
3970defm MVE_VCVTs32f32 : MVE_VCVT_fp_int_anpm_outer<MVE_v4s32, MVE_v4f32>;
3971defm MVE_VCVTu32f32 : MVE_VCVT_fp_int_anpm_outer<MVE_v4u32, MVE_v4f32>;
3972
3973class MVE_VCVT_fp_int<string suffix, bits<2> size, bit toint, bit unsigned,
3974                      list<dag> pattern=[]>
3975  : MVE_float<"vcvt", suffix, (outs MQPR:$Qd),
3976              (ins MQPR:$Qm), "$Qd, $Qm", vpred_r, "", pattern> {
3977  bits<4> Qd;
3978
3979  let Inst{28} = 0b1;
3980  let Inst{25-23} = 0b111;
3981  let Inst{22} = Qd{3};
3982  let Inst{21-20} = 0b11;
3983  let Inst{19-18} = size;
3984  let Inst{17-16} = 0b11;
3985  let Inst{15-13} = Qd{2-0};
3986  let Inst{12-9} = 0b0011;
3987  let Inst{8} = toint;
3988  let Inst{7} = unsigned;
3989  let Inst{4} = 0b0;
3990  let validForTailPredication = 1;
3991}
3992
3993multiclass MVE_VCVT_fp_int_m<MVEVectorVTInfo Dest, MVEVectorVTInfo Src,
3994                             SDNode unpred_op> {
3995  defvar Unsigned = !or(!eq(Dest.SuffixLetter,"u"), !eq(Src.SuffixLetter,"u"));
3996  defvar ToInt = !eq(Src.SuffixLetter,"f");
3997
3998  def "" : MVE_VCVT_fp_int<Dest.Suffix # "." # Src.Suffix, Dest.Size,
3999                           ToInt, Unsigned>;
4000  defvar Inst = !cast<Instruction>(NAME);
4001
4002  let Predicates = [HasMVEFloat] in {
4003    def : Pat<(Dest.Vec (unpred_op (Src.Vec MQPR:$src))),
4004              (Dest.Vec (Inst (Src.Vec MQPR:$src)))>;
4005    def : Pat<(Dest.Vec (int_arm_mve_vcvt_fp_int_predicated
4006                             (Src.Vec MQPR:$src), (i32 Unsigned),
4007                             (Src.Pred VCCR:$mask), (Dest.Vec MQPR:$inactive))),
4008              (Dest.Vec (Inst (Src.Vec MQPR:$src), ARMVCCThen,
4009                              (Src.Pred VCCR:$mask),
4010                              (Dest.Vec MQPR:$inactive)))>;
4011  }
4012}
4013// The unsuffixed VCVT for float->int implicitly rounds toward zero,
4014// which I reflect here in the llvm instruction names
4015defm MVE_VCVTs16f16z : MVE_VCVT_fp_int_m<MVE_v8s16, MVE_v8f16, fp_to_sint>;
4016defm MVE_VCVTu16f16z : MVE_VCVT_fp_int_m<MVE_v8u16, MVE_v8f16, fp_to_uint>;
4017defm MVE_VCVTs32f32z : MVE_VCVT_fp_int_m<MVE_v4s32, MVE_v4f32, fp_to_sint>;
4018defm MVE_VCVTu32f32z : MVE_VCVT_fp_int_m<MVE_v4u32, MVE_v4f32, fp_to_uint>;
4019// Whereas VCVT for int->float rounds to nearest
4020defm MVE_VCVTf16s16n : MVE_VCVT_fp_int_m<MVE_v8f16, MVE_v8s16, sint_to_fp>;
4021defm MVE_VCVTf16u16n : MVE_VCVT_fp_int_m<MVE_v8f16, MVE_v8u16, uint_to_fp>;
4022defm MVE_VCVTf32s32n : MVE_VCVT_fp_int_m<MVE_v4f32, MVE_v4s32, sint_to_fp>;
4023defm MVE_VCVTf32u32n : MVE_VCVT_fp_int_m<MVE_v4f32, MVE_v4u32, uint_to_fp>;
4024
4025class MVE_VABSNEG_fp<string iname, string suffix, bits<2> size, bit negate,
4026                   list<dag> pattern=[]>
4027  : MVE_float<iname, suffix, (outs MQPR:$Qd),
4028              (ins MQPR:$Qm), "$Qd, $Qm", vpred_r, "", pattern> {
4029  bits<4> Qd;
4030
4031  let Inst{28} = 0b1;
4032  let Inst{25-23} = 0b111;
4033  let Inst{22} = Qd{3};
4034  let Inst{21-20} = 0b11;
4035  let Inst{19-18} = size;
4036  let Inst{17-16} = 0b01;
4037  let Inst{15-13} = Qd{2-0};
4038  let Inst{11-8} = 0b0111;
4039  let Inst{7} = negate;
4040  let Inst{4} = 0b0;
4041  let validForTailPredication = 1;
4042}
4043
4044multiclass MVE_VABSNEG_fp_m<string iname, SDNode unpred_op, Intrinsic pred_int,
4045                            MVEVectorVTInfo VTI, bit opcode> {
4046  def "" : MVE_VABSNEG_fp<iname, VTI.Suffix, VTI.Size, opcode>;
4047  defvar Inst = !cast<Instruction>(NAME);
4048
4049  let Predicates = [HasMVEInt] in {
4050    def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$v))),
4051              (VTI.Vec (Inst $v))>;
4052    def : Pat<(VTI.Vec (pred_int  (VTI.Vec MQPR:$v), (VTI.Pred VCCR:$mask),
4053                                  (VTI.Vec MQPR:$inactive))),
4054              (VTI.Vec (Inst $v, ARMVCCThen, $mask, $inactive))>;
4055  }
4056}
4057
4058defm MVE_VABSf16 : MVE_VABSNEG_fp_m<"vabs", fabs, int_arm_mve_abs_predicated,
4059                                    MVE_v8f16, 0>;
4060defm MVE_VABSf32 : MVE_VABSNEG_fp_m<"vabs", fabs, int_arm_mve_abs_predicated,
4061                                    MVE_v4f32, 0>;
4062defm MVE_VNEGf16 : MVE_VABSNEG_fp_m<"vneg", fneg, int_arm_mve_neg_predicated,
4063                                    MVE_v8f16, 1>;
4064defm MVE_VNEGf32 : MVE_VABSNEG_fp_m<"vneg", fneg, int_arm_mve_neg_predicated,
4065                                    MVE_v4f32, 1>;
4066
4067class MVE_VMAXMINNMA<string iname, string suffix, bit size, bit bit_12,
4068                     list<dag> pattern=[]>
4069  : MVE_f<(outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
4070          NoItinerary, iname, suffix, "$Qd, $Qm", vpred_n, "$Qd = $Qd_src",
4071          pattern> {
4072  bits<4> Qd;
4073  bits<4> Qm;
4074
4075  let Inst{28} = size;
4076  let Inst{25-23} = 0b100;
4077  let Inst{22} = Qd{3};
4078  let Inst{21-16} = 0b111111;
4079  let Inst{15-13} = Qd{2-0};
4080  let Inst{12} = bit_12;
4081  let Inst{11-6} = 0b111010;
4082  let Inst{5} = Qm{3};
4083  let Inst{4} = 0b0;
4084  let Inst{3-1} = Qm{2-0};
4085  let Inst{0} = 0b1;
4086
4087  let isCommutable = 1;
4088}
4089
4090multiclass MVE_VMAXMINNMA_m<string iname, MVEVectorVTInfo VTI,
4091                      SDNode unpred_op, Intrinsic pred_int,
4092                      bit bit_12> {
4093  def "" : MVE_VMAXMINNMA<iname, VTI.Suffix, VTI.Size{0}, bit_12>;
4094  defvar Inst = !cast<Instruction>(NAME);
4095
4096  let Predicates = [HasMVEInt] in {
4097    // Unpredicated v(max|min)nma
4098    def : Pat<(VTI.Vec (unpred_op (fabs (VTI.Vec MQPR:$Qd)),
4099                                  (fabs (VTI.Vec MQPR:$Qm)))),
4100              (VTI.Vec (Inst (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm)))>;
4101
4102    // Predicated v(max|min)nma
4103    def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm),
4104                            (VTI.Pred VCCR:$mask))),
4105              (VTI.Vec (Inst (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm),
4106                            ARMVCCThen, (VTI.Pred VCCR:$mask)))>;
4107  }
4108}
4109
4110multiclass MVE_VMAXNMA<MVEVectorVTInfo VTI, bit bit_12>
4111  : MVE_VMAXMINNMA_m<"vmaxnma", VTI, fmaxnum, int_arm_mve_vmaxnma_predicated, bit_12>;
4112
4113defm MVE_VMAXNMAf32 : MVE_VMAXNMA<MVE_v4f32, 0b0>;
4114defm MVE_VMAXNMAf16 : MVE_VMAXNMA<MVE_v8f16, 0b0>;
4115
4116multiclass MVE_VMINNMA<MVEVectorVTInfo VTI, bit bit_12>
4117  : MVE_VMAXMINNMA_m<"vminnma", VTI, fminnum, int_arm_mve_vminnma_predicated, bit_12>;
4118
4119defm MVE_VMINNMAf32 : MVE_VMINNMA<MVE_v4f32, 0b1>;
4120defm MVE_VMINNMAf16 : MVE_VMINNMA<MVE_v8f16, 0b1>;
4121
4122// end of MVE Floating Point instructions
4123
4124// start of MVE compares
4125
4126class MVE_VCMPqq<string suffix, bit bit_28, bits<2> bits_21_20,
4127                 VCMPPredicateOperand predtype, list<dag> pattern=[]>
4128  : MVE_p<(outs VCCR:$P0), (ins MQPR:$Qn, MQPR:$Qm, predtype:$fc),
4129           NoItinerary, "vcmp", suffix, "$fc, $Qn, $Qm", vpred_n, "", pattern> {
4130  // Base class for comparing two vector registers
4131  bits<3> fc;
4132  bits<4> Qn;
4133  bits<4> Qm;
4134
4135  let Inst{28} = bit_28;
4136  let Inst{25-22} = 0b1000;
4137  let Inst{21-20} = bits_21_20;
4138  let Inst{19-17} = Qn{2-0};
4139  let Inst{16-13} = 0b1000;
4140  let Inst{12} = fc{2};
4141  let Inst{11-8} = 0b1111;
4142  let Inst{7} = fc{0};
4143  let Inst{6} = 0b0;
4144  let Inst{5} = Qm{3};
4145  let Inst{4} = 0b0;
4146  let Inst{3-1} = Qm{2-0};
4147  let Inst{0} = fc{1};
4148
4149  let Constraints = "";
4150
4151  // We need a custom decoder method for these instructions because of
4152  // the output VCCR operand, which isn't encoded in the instruction
4153  // bits anywhere (there is only one choice for it) but has to be
4154  // included in the MC operands so that codegen will be able to track
4155  // its data flow between instructions, spill/reload it when
4156  // necessary, etc. There seems to be no way to get the Tablegen
4157  // decoder to emit an operand that isn't affected by any instruction
4158  // bit.
4159  let DecoderMethod = "DecodeMVEVCMP<false," # predtype.DecoderMethod # ">";
4160  let validForTailPredication = 1;
4161}
4162
4163class MVE_VCMPqqf<string suffix, bit size>
4164    : MVE_VCMPqq<suffix, size, 0b11, pred_basic_fp> {
4165  let Predicates = [HasMVEFloat];
4166}
4167
4168class MVE_VCMPqqi<string suffix, bits<2> size>
4169    : MVE_VCMPqq<suffix, 0b1, size, pred_basic_i> {
4170  let Inst{12} = 0b0;
4171  let Inst{0} = 0b0;
4172}
4173
4174class MVE_VCMPqqu<string suffix, bits<2> size>
4175    : MVE_VCMPqq<suffix, 0b1, size, pred_basic_u> {
4176  let Inst{12} = 0b0;
4177  let Inst{0} = 0b1;
4178}
4179
4180class MVE_VCMPqqs<string suffix, bits<2> size>
4181    : MVE_VCMPqq<suffix, 0b1, size, pred_basic_s> {
4182  let Inst{12} = 0b1;
4183}
4184
4185def MVE_VCMPf32 : MVE_VCMPqqf<"f32", 0b0>;
4186def MVE_VCMPf16 : MVE_VCMPqqf<"f16", 0b1>;
4187
4188def MVE_VCMPi8  : MVE_VCMPqqi<"i8",  0b00>;
4189def MVE_VCMPi16 : MVE_VCMPqqi<"i16", 0b01>;
4190def MVE_VCMPi32 : MVE_VCMPqqi<"i32", 0b10>;
4191
4192def MVE_VCMPu8  : MVE_VCMPqqu<"u8",  0b00>;
4193def MVE_VCMPu16 : MVE_VCMPqqu<"u16", 0b01>;
4194def MVE_VCMPu32 : MVE_VCMPqqu<"u32", 0b10>;
4195
4196def MVE_VCMPs8  : MVE_VCMPqqs<"s8",  0b00>;
4197def MVE_VCMPs16 : MVE_VCMPqqs<"s16", 0b01>;
4198def MVE_VCMPs32 : MVE_VCMPqqs<"s32", 0b10>;
4199
4200class MVE_VCMPqr<string suffix, bit bit_28, bits<2> bits_21_20,
4201                 VCMPPredicateOperand predtype, list<dag> pattern=[]>
4202  : MVE_p<(outs VCCR:$P0), (ins MQPR:$Qn, GPRwithZR:$Rm, predtype:$fc),
4203           NoItinerary, "vcmp", suffix, "$fc, $Qn, $Rm", vpred_n, "", pattern> {
4204  // Base class for comparing a vector register with a scalar
4205  bits<3> fc;
4206  bits<4> Qn;
4207  bits<4> Rm;
4208
4209  let Inst{28} = bit_28;
4210  let Inst{25-22} = 0b1000;
4211  let Inst{21-20} = bits_21_20;
4212  let Inst{19-17} = Qn{2-0};
4213  let Inst{16-13} = 0b1000;
4214  let Inst{12} = fc{2};
4215  let Inst{11-8} = 0b1111;
4216  let Inst{7} = fc{0};
4217  let Inst{6} = 0b1;
4218  let Inst{5} = fc{1};
4219  let Inst{4} = 0b0;
4220  let Inst{3-0} = Rm{3-0};
4221
4222  let Constraints = "";
4223  // Custom decoder method, for the same reason as MVE_VCMPqq
4224  let DecoderMethod = "DecodeMVEVCMP<true," # predtype.DecoderMethod # ">";
4225  let validForTailPredication = 1;
4226}
4227
4228class MVE_VCMPqrf<string suffix, bit size>
4229    : MVE_VCMPqr<suffix, size, 0b11, pred_basic_fp> {
4230  let Predicates = [HasMVEFloat];
4231}
4232
4233class MVE_VCMPqri<string suffix, bits<2> size>
4234    : MVE_VCMPqr<suffix, 0b1, size, pred_basic_i> {
4235  let Inst{12} = 0b0;
4236  let Inst{5} = 0b0;
4237}
4238
4239class MVE_VCMPqru<string suffix, bits<2> size>
4240    : MVE_VCMPqr<suffix, 0b1, size, pred_basic_u> {
4241  let Inst{12} = 0b0;
4242  let Inst{5} = 0b1;
4243}
4244
4245class MVE_VCMPqrs<string suffix, bits<2> size>
4246    : MVE_VCMPqr<suffix, 0b1, size, pred_basic_s> {
4247  let Inst{12} = 0b1;
4248}
4249
4250def MVE_VCMPf32r : MVE_VCMPqrf<"f32", 0b0>;
4251def MVE_VCMPf16r : MVE_VCMPqrf<"f16", 0b1>;
4252
4253def MVE_VCMPi8r  : MVE_VCMPqri<"i8",  0b00>;
4254def MVE_VCMPi16r : MVE_VCMPqri<"i16", 0b01>;
4255def MVE_VCMPi32r : MVE_VCMPqri<"i32", 0b10>;
4256
4257def MVE_VCMPu8r  : MVE_VCMPqru<"u8",  0b00>;
4258def MVE_VCMPu16r : MVE_VCMPqru<"u16", 0b01>;
4259def MVE_VCMPu32r : MVE_VCMPqru<"u32", 0b10>;
4260
4261def MVE_VCMPs8r  : MVE_VCMPqrs<"s8",  0b00>;
4262def MVE_VCMPs16r : MVE_VCMPqrs<"s16", 0b01>;
4263def MVE_VCMPs32r : MVE_VCMPqrs<"s32", 0b10>;
4264
4265multiclass unpred_vcmp_z<string suffix, PatLeaf fc> {
4266  def i8  : Pat<(v16i1 (ARMvcmpz (v16i8 MQPR:$v1), fc)),
4267                (v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), ZR, fc))>;
4268  def i16 : Pat<(v8i1 (ARMvcmpz (v8i16 MQPR:$v1), fc)),
4269                (v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), ZR, fc))>;
4270  def i32 : Pat<(v4i1 (ARMvcmpz (v4i32 MQPR:$v1), fc)),
4271                (v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), ZR, fc))>;
4272
4273  def : Pat<(v16i1 (and (v16i1 VCCR:$p1), (v16i1 (ARMvcmpz (v16i8 MQPR:$v1), fc)))),
4274            (v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>;
4275  def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmpz (v8i16 MQPR:$v1), fc)))),
4276            (v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>;
4277  def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmpz (v4i32 MQPR:$v1), fc)))),
4278            (v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>;
4279}
4280
4281multiclass unpred_vcmp_r<string suffix, PatLeaf fc> {
4282  def i8  : Pat<(v16i1 (ARMvcmp (v16i8 MQPR:$v1), (v16i8 MQPR:$v2), fc)),
4283                (v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8") (v16i8 MQPR:$v1), (v16i8 MQPR:$v2), fc))>;
4284  def i16 : Pat<(v8i1 (ARMvcmp (v8i16 MQPR:$v1), (v8i16 MQPR:$v2), fc)),
4285                (v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16") (v8i16 MQPR:$v1), (v8i16 MQPR:$v2), fc))>;
4286  def i32 : Pat<(v4i1 (ARMvcmp (v4i32 MQPR:$v1), (v4i32 MQPR:$v2), fc)),
4287                (v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32") (v4i32 MQPR:$v1), (v4i32 MQPR:$v2), fc))>;
4288
4289  def i8r  : Pat<(v16i1 (ARMvcmp (v16i8 MQPR:$v1), (v16i8 (ARMvdup rGPR:$v2)), fc)),
4290                 (v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), (i32 rGPR:$v2), fc))>;
4291  def i16r : Pat<(v8i1 (ARMvcmp (v8i16 MQPR:$v1), (v8i16 (ARMvdup rGPR:$v2)), fc)),
4292                 (v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), (i32 rGPR:$v2), fc))>;
4293  def i32r : Pat<(v4i1 (ARMvcmp (v4i32 MQPR:$v1), (v4i32 (ARMvdup rGPR:$v2)), fc)),
4294                 (v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), (i32 rGPR:$v2), fc))>;
4295
4296  def : Pat<(v16i1 (and (v16i1 VCCR:$p1), (v16i1 (ARMvcmp (v16i8 MQPR:$v1), (v16i8 MQPR:$v2), fc)))),
4297            (v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8") (v16i8 MQPR:$v1), (v16i8 MQPR:$v2), fc, ARMVCCThen, VCCR:$p1))>;
4298  def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmp (v8i16 MQPR:$v1), (v8i16 MQPR:$v2), fc)))),
4299            (v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16") (v8i16 MQPR:$v1), (v8i16 MQPR:$v2), fc, ARMVCCThen, VCCR:$p1))>;
4300  def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4i32 MQPR:$v1), (v4i32 MQPR:$v2), fc)))),
4301            (v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32") (v4i32 MQPR:$v1), (v4i32 MQPR:$v2), fc, ARMVCCThen, VCCR:$p1))>;
4302
4303  def : Pat<(v16i1 (and (v16i1 VCCR:$p1), (v16i1 (ARMvcmp (v16i8 MQPR:$v1), (v16i8 (ARMvdup rGPR:$v2)), fc)))),
4304            (v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), (i32 rGPR:$v2), fc, ARMVCCThen, VCCR:$p1))>;
4305  def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmp (v8i16 MQPR:$v1), (v8i16 (ARMvdup rGPR:$v2)), fc)))),
4306            (v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), (i32 rGPR:$v2), fc, ARMVCCThen, VCCR:$p1))>;
4307  def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4i32 MQPR:$v1), (v4i32 (ARMvdup rGPR:$v2)), fc)))),
4308            (v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), (i32 rGPR:$v2), fc, ARMVCCThen, VCCR:$p1))>;
4309}
4310
4311multiclass unpred_vcmpf_z<PatLeaf fc> {
4312  def f16 : Pat<(v8i1 (ARMvcmpz (v8f16 MQPR:$v1), fc)),
4313                (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, fc))>;
4314  def f32 : Pat<(v4i1 (ARMvcmpz (v4f32 MQPR:$v1), fc)),
4315                (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc))>;
4316
4317  def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmpz (v8f16 MQPR:$v1), fc)))),
4318            (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>;
4319  def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmpz (v4f32 MQPR:$v1), fc)))),
4320            (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>;
4321}
4322
4323multiclass unpred_vcmpf_r<int fc> {
4324  def : Pat<(v8i1 (ARMvcmp (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc)),
4325            (v8i1 (MVE_VCMPf16 (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc))>;
4326  def : Pat<(v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc)),
4327            (v4i1 (MVE_VCMPf32 (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc))>;
4328
4329  def : Pat<(v8i1 (ARMvcmp (v8f16 MQPR:$v1), (v8f16 (ARMvdup rGPR:$v2)), fc)),
4330            (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), (i32 rGPR:$v2), fc))>;
4331  def : Pat<(v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 (ARMvdup rGPR:$v2)), fc)),
4332            (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), (i32 rGPR:$v2), fc))>;
4333
4334  def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmp (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc)))),
4335            (v8i1 (MVE_VCMPf16 (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc, ARMVCCThen, VCCR:$p1))>;
4336  def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc)))),
4337            (v4i1 (MVE_VCMPf32 (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc, ARMVCCThen, VCCR:$p1))>;
4338
4339  def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmp (v8f16 MQPR:$v1), (v8f16 (ARMvdup rGPR:$v2)), fc)))),
4340            (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), (i32 rGPR:$v2), fc, ARMVCCThen, VCCR:$p1))>;
4341  def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 (ARMvdup rGPR:$v2)), fc)))),
4342            (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), (i32 rGPR:$v2), fc, ARMVCCThen, VCCR:$p1))>;
4343}
4344
4345let Predicates = [HasMVEInt] in {
4346  defm MVE_VCEQZ  : unpred_vcmp_z<"i", ARMCCeq>;
4347  defm MVE_VCNEZ  : unpred_vcmp_z<"i", ARMCCne>;
4348  defm MVE_VCGEZ  : unpred_vcmp_z<"s", ARMCCge>;
4349  defm MVE_VCLTZ  : unpred_vcmp_z<"s", ARMCClt>;
4350  defm MVE_VCGTZ  : unpred_vcmp_z<"s", ARMCCgt>;
4351  defm MVE_VCLEZ  : unpred_vcmp_z<"s", ARMCCle>;
4352  defm MVE_VCGTUZ : unpred_vcmp_z<"u", ARMCChi>;
4353  defm MVE_VCGEUZ : unpred_vcmp_z<"u", ARMCChs>;
4354
4355  defm MVE_VCEQ   : unpred_vcmp_r<"i", ARMCCeq>;
4356  defm MVE_VCNE   : unpred_vcmp_r<"i", ARMCCne>;
4357  defm MVE_VCGE   : unpred_vcmp_r<"s", ARMCCge>;
4358  defm MVE_VCLT   : unpred_vcmp_r<"s", ARMCClt>;
4359  defm MVE_VCGT   : unpred_vcmp_r<"s", ARMCCgt>;
4360  defm MVE_VCLE   : unpred_vcmp_r<"s", ARMCCle>;
4361  defm MVE_VCGTU  : unpred_vcmp_r<"u", ARMCChi>;
4362  defm MVE_VCGEU  : unpred_vcmp_r<"u", ARMCChs>;
4363}
4364
4365let Predicates = [HasMVEFloat] in {
4366  defm MVE_VFCEQZ  : unpred_vcmpf_z<ARMCCeq>;
4367  defm MVE_VFCNEZ  : unpred_vcmpf_z<ARMCCne>;
4368  defm MVE_VFCGEZ  : unpred_vcmpf_z<ARMCCge>;
4369  defm MVE_VFCLTZ  : unpred_vcmpf_z<ARMCClt>;
4370  defm MVE_VFCGTZ  : unpred_vcmpf_z<ARMCCgt>;
4371  defm MVE_VFCLEZ  : unpred_vcmpf_z<ARMCCle>;
4372
4373  defm MVE_VFCEQ   : unpred_vcmpf_r<ARMCCeq>;
4374  defm MVE_VFCNE   : unpred_vcmpf_r<ARMCCne>;
4375  defm MVE_VFCGE   : unpred_vcmpf_r<ARMCCge>;
4376  defm MVE_VFCLT   : unpred_vcmpf_r<ARMCClt>;
4377  defm MVE_VFCGT   : unpred_vcmpf_r<ARMCCgt>;
4378  defm MVE_VFCLE   : unpred_vcmpf_r<ARMCCle>;
4379}
4380
4381
4382// Extra "worst case" and/or/xor patterns, going into and out of GRP
4383multiclass two_predops<SDPatternOperator opnode, Instruction insn> {
4384  def v16i1 : Pat<(v16i1 (opnode (v16i1 VCCR:$p1), (v16i1 VCCR:$p2))),
4385                  (v16i1 (COPY_TO_REGCLASS
4386                           (insn (i32 (COPY_TO_REGCLASS (v16i1 VCCR:$p1), rGPR)),
4387                                 (i32 (COPY_TO_REGCLASS (v16i1 VCCR:$p2), rGPR))),
4388                           VCCR))>;
4389  def v8i1  : Pat<(v8i1 (opnode (v8i1 VCCR:$p1), (v8i1 VCCR:$p2))),
4390                  (v8i1 (COPY_TO_REGCLASS
4391                          (insn (i32 (COPY_TO_REGCLASS (v8i1 VCCR:$p1), rGPR)),
4392                                (i32 (COPY_TO_REGCLASS (v8i1 VCCR:$p2), rGPR))),
4393                          VCCR))>;
4394  def v4i1  : Pat<(v4i1 (opnode (v4i1 VCCR:$p1), (v4i1 VCCR:$p2))),
4395                  (v4i1 (COPY_TO_REGCLASS
4396                          (insn (i32 (COPY_TO_REGCLASS (v4i1 VCCR:$p1), rGPR)),
4397                                (i32 (COPY_TO_REGCLASS (v4i1 VCCR:$p2), rGPR))),
4398                          VCCR))>;
4399}
4400
4401let Predicates = [HasMVEInt] in {
4402  defm POR    : two_predops<or,  t2ORRrr>;
4403  defm PAND   : two_predops<and, t2ANDrr>;
4404  defm PEOR   : two_predops<xor, t2EORrr>;
4405}
4406
4407// Occasionally we need to cast between a i32 and a boolean vector, for
4408// example when moving between rGPR and VPR.P0 as part of predicate vector
4409// shuffles. We also sometimes need to cast between different predicate
4410// vector types (v4i1<>v8i1, etc.) also as part of lowering vector shuffles.
4411def predicate_cast : SDNode<"ARMISD::PREDICATE_CAST", SDTUnaryOp>;
4412
4413def load_align4 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
4414  return cast<LoadSDNode>(N)->getAlignment() >= 4;
4415}]>;
4416
4417let Predicates = [HasMVEInt] in {
4418  foreach VT = [ v4i1, v8i1, v16i1 ] in {
4419    def : Pat<(i32 (predicate_cast (VT VCCR:$src))),
4420              (i32 (COPY_TO_REGCLASS (VT VCCR:$src), VCCR))>;
4421    def : Pat<(VT  (predicate_cast (i32 VCCR:$src))),
4422              (VT  (COPY_TO_REGCLASS (i32 VCCR:$src), VCCR))>;
4423
4424    foreach VT2 = [ v4i1, v8i1, v16i1 ] in
4425      def : Pat<(VT  (predicate_cast (VT2 VCCR:$src))),
4426                (VT  (COPY_TO_REGCLASS (VT2 VCCR:$src), VCCR))>;
4427  }
4428
4429  // If we happen to be casting from a load we can convert that straight
4430  // into a predicate load, so long as the load is of the correct type.
4431  foreach VT = [ v4i1, v8i1, v16i1 ] in {
4432    def : Pat<(VT (predicate_cast (i32 (load_align4 taddrmode_imm7<2>:$addr)))),
4433              (VT (VLDR_P0_off taddrmode_imm7<2>:$addr))>;
4434  }
4435
4436  // Here we match the specific SDNode type 'ARMVectorRegCastImpl'
4437  // rather than the more general 'ARMVectorRegCast' which would also
4438  // match some bitconverts. If we use the latter in cases where the
4439  // input and output types are the same, the bitconvert gets elided
4440  // and we end up generating a nonsense match of nothing.
4441
4442  foreach VT = [ v16i8, v8i16, v8f16, v4i32, v4f32, v2i64, v2f64 ] in
4443    foreach VT2 = [ v16i8, v8i16, v8f16, v4i32, v4f32, v2i64, v2f64 ] in
4444      def : Pat<(VT (ARMVectorRegCastImpl (VT2 MQPR:$src))),
4445                (VT MQPR:$src)>;
4446}
4447
4448// end of MVE compares
4449
4450// start of MVE_qDest_qSrc
4451
4452class MVE_qDest_qSrc<string iname, string suffix, dag oops, dag iops,
4453                     string ops, vpred_ops vpred, string cstr,
4454                     list<dag> pattern=[]>
4455  : MVE_p<oops, iops, NoItinerary, iname, suffix,
4456          ops, vpred, cstr, pattern> {
4457  bits<4> Qd;
4458  bits<4> Qm;
4459
4460  let Inst{25-23} = 0b100;
4461  let Inst{22} = Qd{3};
4462  let Inst{15-13} = Qd{2-0};
4463  let Inst{11-9} = 0b111;
4464  let Inst{6} = 0b0;
4465  let Inst{5} = Qm{3};
4466  let Inst{4} = 0b0;
4467  let Inst{3-1} = Qm{2-0};
4468}
4469
4470class MVE_VQxDMLxDH<string iname, bit exch, bit round, bit subtract,
4471                    string suffix, bits<2> size, string cstr="", list<dag> pattern=[]>
4472  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
4473                   (ins MQPR:$Qd_src, MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
4474                   vpred_n, "$Qd = $Qd_src"#cstr, pattern> {
4475  bits<4> Qn;
4476
4477  let Inst{28} = subtract;
4478  let Inst{21-20} = size;
4479  let Inst{19-17} = Qn{2-0};
4480  let Inst{16} = 0b0;
4481  let Inst{12} = exch;
4482  let Inst{8} = 0b0;
4483  let Inst{7} = Qn{3};
4484  let Inst{0} = round;
4485}
4486
4487multiclass MVE_VQxDMLxDH_p<string iname, bit exch, bit round, bit subtract,
4488                           MVEVectorVTInfo VTI> {
4489  def "": MVE_VQxDMLxDH<iname, exch, round, subtract, VTI.Suffix, VTI.Size,
4490                        !if(!eq(VTI.LaneBits, 32), ",@earlyclobber $Qd", "")>;
4491  defvar Inst = !cast<Instruction>(NAME);
4492  defvar ConstParams = (? (i32 exch), (i32 round), (i32 subtract));
4493  defvar unpred_intr = int_arm_mve_vqdmlad;
4494  defvar pred_intr = int_arm_mve_vqdmlad_predicated;
4495
4496  def : Pat<(VTI.Vec !con((unpred_intr (VTI.Vec MQPR:$a), (VTI.Vec MQPR:$b),
4497                                       (VTI.Vec MQPR:$c)), ConstParams)),
4498            (VTI.Vec (Inst (VTI.Vec MQPR:$a), (VTI.Vec MQPR:$b),
4499                           (VTI.Vec MQPR:$c)))>;
4500  def : Pat<(VTI.Vec !con((pred_intr (VTI.Vec MQPR:$a), (VTI.Vec MQPR:$b),
4501                                     (VTI.Vec MQPR:$c)), ConstParams,
4502                          (? (VTI.Pred VCCR:$pred)))),
4503            (VTI.Vec (Inst (VTI.Vec MQPR:$a), (VTI.Vec MQPR:$b),
4504                           (VTI.Vec MQPR:$c),
4505                           ARMVCCThen, (VTI.Pred VCCR:$pred)))>;
4506}
4507
4508multiclass MVE_VQxDMLxDH_multi<string iname, bit exch,
4509                               bit round, bit subtract> {
4510  defm s8  : MVE_VQxDMLxDH_p<iname, exch, round, subtract, MVE_v16s8>;
4511  defm s16 : MVE_VQxDMLxDH_p<iname, exch, round, subtract, MVE_v8s16>;
4512  defm s32 : MVE_VQxDMLxDH_p<iname, exch, round, subtract, MVE_v4s32>;
4513}
4514
4515defm MVE_VQDMLADH   : MVE_VQxDMLxDH_multi<"vqdmladh",   0b0, 0b0, 0b0>;
4516defm MVE_VQDMLADHX  : MVE_VQxDMLxDH_multi<"vqdmladhx",  0b1, 0b0, 0b0>;
4517defm MVE_VQRDMLADH  : MVE_VQxDMLxDH_multi<"vqrdmladh",  0b0, 0b1, 0b0>;
4518defm MVE_VQRDMLADHX : MVE_VQxDMLxDH_multi<"vqrdmladhx", 0b1, 0b1, 0b0>;
4519defm MVE_VQDMLSDH   : MVE_VQxDMLxDH_multi<"vqdmlsdh",   0b0, 0b0, 0b1>;
4520defm MVE_VQDMLSDHX  : MVE_VQxDMLxDH_multi<"vqdmlsdhx",  0b1, 0b0, 0b1>;
4521defm MVE_VQRDMLSDH  : MVE_VQxDMLxDH_multi<"vqrdmlsdh",  0b0, 0b1, 0b1>;
4522defm MVE_VQRDMLSDHX : MVE_VQxDMLxDH_multi<"vqrdmlsdhx", 0b1, 0b1, 0b1>;
4523
4524class MVE_VCMUL<string iname, string suffix, bit size, string cstr="">
4525  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
4526                   (ins MQPR:$Qn, MQPR:$Qm, complexrotateop:$rot),
4527                   "$Qd, $Qn, $Qm, $rot", vpred_r, cstr, []> {
4528  bits<4> Qn;
4529  bits<2> rot;
4530
4531  let Inst{28} = size;
4532  let Inst{21-20} = 0b11;
4533  let Inst{19-17} = Qn{2-0};
4534  let Inst{16} = 0b0;
4535  let Inst{12} = rot{1};
4536  let Inst{8} = 0b0;
4537  let Inst{7} = Qn{3};
4538  let Inst{0} = rot{0};
4539
4540  let Predicates = [HasMVEFloat];
4541}
4542
4543multiclass MVE_VCMUL_m<string iname, MVEVectorVTInfo VTI,
4544                       bit size, string cstr=""> {
4545  def "" : MVE_VCMUL<iname, VTI.Suffix, size, cstr>;
4546  defvar Inst = !cast<Instruction>(NAME);
4547
4548  let Predicates = [HasMVEFloat] in {
4549    def : Pat<(VTI.Vec (int_arm_mve_vcmulq
4550                            imm:$rot, (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
4551              (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
4552                             imm:$rot))>;
4553
4554    def : Pat<(VTI.Vec (int_arm_mve_vcmulq_predicated
4555                            imm:$rot, (VTI.Vec MQPR:$inactive),
4556                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
4557                            (VTI.Pred VCCR:$mask))),
4558              (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
4559                             imm:$rot, ARMVCCThen, (VTI.Pred VCCR:$mask),
4560                             (VTI.Vec MQPR:$inactive)))>;
4561
4562  }
4563}
4564
4565defm MVE_VCMULf16 : MVE_VCMUL_m<"vcmul", MVE_v8f16, 0b0>;
4566defm MVE_VCMULf32 : MVE_VCMUL_m<"vcmul", MVE_v4f32, 0b1, "@earlyclobber $Qd">;
4567
4568class MVE_VMULL<string iname, string suffix, bit bit_28, bits<2> bits_21_20,
4569                bit T, string cstr, list<dag> pattern=[]>
4570  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
4571                   (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
4572                   vpred_r, cstr, pattern> {
4573  bits<4> Qd;
4574  bits<4> Qn;
4575  bits<4> Qm;
4576
4577  let Inst{28} = bit_28;
4578  let Inst{21-20} = bits_21_20;
4579  let Inst{19-17} = Qn{2-0};
4580  let Inst{16} = 0b1;
4581  let Inst{12} = T;
4582  let Inst{8} = 0b0;
4583  let Inst{7} = Qn{3};
4584  let Inst{0} = 0b0;
4585  let validForTailPredication = 1;
4586  let doubleWidthResult = 1;
4587}
4588
4589multiclass MVE_VMULL_m<MVEVectorVTInfo VTI,
4590                       SDNode unpred_op, Intrinsic pred_int,
4591                       bit Top, string cstr=""> {
4592  def "" : MVE_VMULL<"vmull" # !if(Top, "t", "b"), VTI.Suffix, VTI.Unsigned,
4593                     VTI.Size, Top, cstr>;
4594  defvar Inst = !cast<Instruction>(NAME);
4595
4596  let Predicates = [HasMVEInt] in {
4597    defvar uflag = !if(!eq(VTI.SuffixLetter, "p"), (?), (? (i32 VTI.Unsigned)));
4598
4599    // Unpredicated multiply
4600    def : Pat<(VTI.DblVec !con((unpred_op (VTI.Vec MQPR:$Qm),
4601                                          (VTI.Vec MQPR:$Qn)),
4602                               uflag, (? (i32 Top)))),
4603              (VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
4604
4605    // Predicated multiply
4606    def : Pat<(VTI.DblVec !con((pred_int (VTI.Vec MQPR:$Qm),
4607                                         (VTI.Vec MQPR:$Qn)),
4608                               uflag, (? (i32 Top), (VTI.DblPred VCCR:$mask),
4609                                         (VTI.DblVec MQPR:$inactive)))),
4610              (VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
4611                                ARMVCCThen, (VTI.DblPred VCCR:$mask),
4612                                (VTI.DblVec MQPR:$inactive)))>;
4613  }
4614}
4615
4616// For polynomial multiplies, the size bits take the unused value 0b11, and
4617// the unsigned bit switches to encoding the size.
4618
4619defm MVE_VMULLBs8  : MVE_VMULL_m<MVE_v16s8, int_arm_mve_vmull,
4620                                 int_arm_mve_mull_int_predicated, 0b0>;
4621defm MVE_VMULLTs8  : MVE_VMULL_m<MVE_v16s8, int_arm_mve_vmull,
4622                                 int_arm_mve_mull_int_predicated, 0b1>;
4623defm MVE_VMULLBs16 : MVE_VMULL_m<MVE_v8s16, int_arm_mve_vmull,
4624                                 int_arm_mve_mull_int_predicated, 0b0>;
4625defm MVE_VMULLTs16 : MVE_VMULL_m<MVE_v8s16, int_arm_mve_vmull,
4626                                 int_arm_mve_mull_int_predicated, 0b1>;
4627defm MVE_VMULLBs32 : MVE_VMULL_m<MVE_v4s32, int_arm_mve_vmull,
4628                                 int_arm_mve_mull_int_predicated, 0b0,
4629                                 "@earlyclobber $Qd">;
4630defm MVE_VMULLTs32 : MVE_VMULL_m<MVE_v4s32, int_arm_mve_vmull,
4631                                 int_arm_mve_mull_int_predicated, 0b1,
4632                                 "@earlyclobber $Qd">;
4633
4634defm MVE_VMULLBu8  : MVE_VMULL_m<MVE_v16u8, int_arm_mve_vmull,
4635                                 int_arm_mve_mull_int_predicated, 0b0>;
4636defm MVE_VMULLTu8  : MVE_VMULL_m<MVE_v16u8, int_arm_mve_vmull,
4637                                 int_arm_mve_mull_int_predicated, 0b1>;
4638defm MVE_VMULLBu16 : MVE_VMULL_m<MVE_v8u16, int_arm_mve_vmull,
4639                                 int_arm_mve_mull_int_predicated, 0b0>;
4640defm MVE_VMULLTu16 : MVE_VMULL_m<MVE_v8u16, int_arm_mve_vmull,
4641                                 int_arm_mve_mull_int_predicated, 0b1>;
4642defm MVE_VMULLBu32 : MVE_VMULL_m<MVE_v4u32, int_arm_mve_vmull,
4643                                 int_arm_mve_mull_int_predicated, 0b0,
4644                                 "@earlyclobber $Qd">;
4645defm MVE_VMULLTu32 : MVE_VMULL_m<MVE_v4u32, int_arm_mve_vmull,
4646                                 int_arm_mve_mull_int_predicated, 0b1,
4647                                 "@earlyclobber $Qd">;
4648
4649defm MVE_VMULLBp8  : MVE_VMULL_m<MVE_v16p8, int_arm_mve_vmull_poly,
4650                                 int_arm_mve_mull_poly_predicated, 0b0>;
4651defm MVE_VMULLTp8  : MVE_VMULL_m<MVE_v16p8, int_arm_mve_vmull_poly,
4652                                 int_arm_mve_mull_poly_predicated, 0b1>;
4653defm MVE_VMULLBp16 : MVE_VMULL_m<MVE_v8p16, int_arm_mve_vmull_poly,
4654                                 int_arm_mve_mull_poly_predicated, 0b0>;
4655defm MVE_VMULLTp16 : MVE_VMULL_m<MVE_v8p16, int_arm_mve_vmull_poly,
4656                                 int_arm_mve_mull_poly_predicated, 0b1>;
4657
4658let Predicates = [HasMVEInt] in {
4659  def : Pat<(v2i64 (ARMvmulls (v4i32 MQPR:$src1), (v4i32 MQPR:$src2))),
4660            (MVE_VMULLBs32 MQPR:$src1, MQPR:$src2)>;
4661  def : Pat<(v2i64 (ARMvmulls (v4i32 (ARMvrev64 (v4i32 MQPR:$src1))),
4662                              (v4i32 (ARMvrev64 (v4i32 MQPR:$src2))))),
4663            (MVE_VMULLTs32 MQPR:$src1, MQPR:$src2)>;
4664
4665  def : Pat<(mul (sext_inreg (v4i32 MQPR:$src1), v4i16),
4666                 (sext_inreg (v4i32 MQPR:$src2), v4i16)),
4667            (MVE_VMULLBs16 MQPR:$src1, MQPR:$src2)>;
4668  def : Pat<(mul (sext_inreg (v4i32 (ARMVectorRegCast (ARMvrev32 (v8i16 MQPR:$src1)))), v4i16),
4669                 (sext_inreg (v4i32 (ARMVectorRegCast (ARMvrev32 (v8i16 MQPR:$src2)))), v4i16)),
4670            (MVE_VMULLTs16 MQPR:$src1, MQPR:$src2)>;
4671
4672  def : Pat<(mul (sext_inreg (v8i16 MQPR:$src1), v8i8),
4673                 (sext_inreg (v8i16 MQPR:$src2), v8i8)),
4674            (MVE_VMULLBs8 MQPR:$src1, MQPR:$src2)>;
4675  def : Pat<(mul (sext_inreg (v8i16 (ARMVectorRegCast (ARMvrev16 (v16i8 MQPR:$src1)))), v8i8),
4676                 (sext_inreg (v8i16 (ARMVectorRegCast (ARMvrev16 (v16i8 MQPR:$src2)))), v8i8)),
4677            (MVE_VMULLTs8 MQPR:$src1, MQPR:$src2)>;
4678
4679  def : Pat<(v2i64 (ARMvmullu (v4i32 MQPR:$src1), (v4i32 MQPR:$src2))),
4680            (MVE_VMULLBu32 MQPR:$src1, MQPR:$src2)>;
4681  def : Pat<(v2i64 (ARMvmullu (v4i32 (ARMvrev64 (v4i32 MQPR:$src1))),
4682                              (v4i32 (ARMvrev64 (v4i32 MQPR:$src2))))),
4683            (MVE_VMULLTu32 MQPR:$src1, MQPR:$src2)>;
4684
4685  def : Pat<(mul (and (v4i32 MQPR:$src1), (v4i32 (ARMvmovImm (i32 0xCFF)))),
4686                 (and (v4i32 MQPR:$src2), (v4i32 (ARMvmovImm (i32 0xCFF))))),
4687            (MVE_VMULLBu16 MQPR:$src1, MQPR:$src2)>;
4688  def : Pat<(mul (and (v4i32 (ARMVectorRegCast (ARMvrev32 (v8i16 MQPR:$src1)))),
4689                      (v4i32 (ARMvmovImm (i32 0xCFF)))),
4690                 (and (v4i32 (ARMVectorRegCast (ARMvrev32 (v8i16 MQPR:$src2)))),
4691                      (v4i32 (ARMvmovImm (i32 0xCFF))))),
4692            (MVE_VMULLTu16 MQPR:$src1, MQPR:$src2)>;
4693
4694  def : Pat<(mul (ARMvbicImm (v8i16 MQPR:$src1), (i32 0xAFF)),
4695                 (ARMvbicImm (v8i16 MQPR:$src2), (i32 0xAFF))),
4696            (MVE_VMULLBu8 MQPR:$src1, MQPR:$src2)>;
4697  def : Pat<(mul (ARMvbicImm (v8i16 (ARMVectorRegCast (ARMvrev16 (v16i8 MQPR:$src1)))), (i32 0xAFF)),
4698                 (ARMvbicImm (v8i16 (ARMVectorRegCast (ARMvrev16 (v16i8 MQPR:$src2)))), (i32 0xAFF))),
4699            (MVE_VMULLTu8 MQPR:$src1, MQPR:$src2)>;
4700}
4701
4702class MVE_VxMULH<string iname, string suffix, bit U, bits<2> size, bit round,
4703                 list<dag> pattern=[]>
4704  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
4705                   (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
4706                   vpred_r, "", pattern> {
4707  bits<4> Qn;
4708
4709  let Inst{28} = U;
4710  let Inst{21-20} = size;
4711  let Inst{19-17} = Qn{2-0};
4712  let Inst{16} = 0b1;
4713  let Inst{12} = round;
4714  let Inst{8} = 0b0;
4715  let Inst{7} = Qn{3};
4716  let Inst{0} = 0b1;
4717}
4718
4719multiclass MVE_VxMULH_m<string iname, MVEVectorVTInfo VTI, SDNode unpred_op,
4720                        Intrinsic pred_int, bit round> {
4721  def "" : MVE_VxMULH<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, round>;
4722  defvar Inst = !cast<Instruction>(NAME);
4723
4724  let Predicates = [HasMVEInt] in {
4725    // Unpredicated multiply returning high bits
4726    def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
4727                            (i32 VTI.Unsigned))),
4728              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
4729
4730    // Predicated multiply returning high bits
4731    def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
4732                            (i32 VTI.Unsigned), (VTI.Pred VCCR:$mask),
4733                            (VTI.Vec MQPR:$inactive))),
4734              (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
4735                             ARMVCCThen, (VTI.Pred VCCR:$mask),
4736                             (VTI.Vec MQPR:$inactive)))>;
4737  }
4738}
4739
4740multiclass MVE_VMULT<string iname, MVEVectorVTInfo VTI, bit round>
4741  : MVE_VxMULH_m<iname, VTI, !if(round, int_arm_mve_vrmulh, int_arm_mve_vmulh),
4742                 !if(round, int_arm_mve_rmulh_predicated,
4743                            int_arm_mve_mulh_predicated),
4744                 round>;
4745
4746defm MVE_VMULHs8   : MVE_VMULT<"vmulh",  MVE_v16s8, 0b0>;
4747defm MVE_VMULHs16  : MVE_VMULT<"vmulh",  MVE_v8s16, 0b0>;
4748defm MVE_VMULHs32  : MVE_VMULT<"vmulh",  MVE_v4s32, 0b0>;
4749defm MVE_VMULHu8   : MVE_VMULT<"vmulh",  MVE_v16u8, 0b0>;
4750defm MVE_VMULHu16  : MVE_VMULT<"vmulh",  MVE_v8u16, 0b0>;
4751defm MVE_VMULHu32  : MVE_VMULT<"vmulh",  MVE_v4u32, 0b0>;
4752
4753defm MVE_VRMULHs8  : MVE_VMULT<"vrmulh", MVE_v16s8, 0b1>;
4754defm MVE_VRMULHs16 : MVE_VMULT<"vrmulh", MVE_v8s16, 0b1>;
4755defm MVE_VRMULHs32 : MVE_VMULT<"vrmulh", MVE_v4s32, 0b1>;
4756defm MVE_VRMULHu8  : MVE_VMULT<"vrmulh", MVE_v16u8, 0b1>;
4757defm MVE_VRMULHu16 : MVE_VMULT<"vrmulh", MVE_v8u16, 0b1>;
4758defm MVE_VRMULHu32 : MVE_VMULT<"vrmulh", MVE_v4u32, 0b1>;
4759
4760class MVE_VxMOVxN<string iname, string suffix, bit bit_28, bit bit_17,
4761                  bits<2> size, bit T, list<dag> pattern=[]>
4762  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
4763                   (ins MQPR:$Qd_src, MQPR:$Qm), "$Qd, $Qm",
4764                   vpred_n, "$Qd = $Qd_src", pattern> {
4765
4766  let Inst{28} = bit_28;
4767  let Inst{21-20} = 0b11;
4768  let Inst{19-18} = size;
4769  let Inst{17} = bit_17;
4770  let Inst{16} = 0b1;
4771  let Inst{12} = T;
4772  let Inst{8} = 0b0;
4773  let Inst{7} = !not(bit_17);
4774  let Inst{0} = 0b1;
4775  let validForTailPredication = 1;
4776  let retainsPreviousHalfElement = 1;
4777}
4778
4779multiclass MVE_VxMOVxN_halves<string iname, string suffix,
4780                              bit bit_28, bit bit_17, bits<2> size> {
4781  def bh : MVE_VxMOVxN<iname # "b", suffix, bit_28, bit_17, size, 0b0>;
4782  def th : MVE_VxMOVxN<iname # "t", suffix, bit_28, bit_17, size, 0b1>;
4783}
4784
4785defm MVE_VMOVNi16   : MVE_VxMOVxN_halves<"vmovn",   "i16", 0b1, 0b0, 0b00>;
4786defm MVE_VMOVNi32   : MVE_VxMOVxN_halves<"vmovn",   "i32", 0b1, 0b0, 0b01>;
4787defm MVE_VQMOVNs16  : MVE_VxMOVxN_halves<"vqmovn",  "s16", 0b0, 0b1, 0b00>;
4788defm MVE_VQMOVNs32  : MVE_VxMOVxN_halves<"vqmovn",  "s32", 0b0, 0b1, 0b01>;
4789defm MVE_VQMOVNu16  : MVE_VxMOVxN_halves<"vqmovn",  "u16", 0b1, 0b1, 0b00>;
4790defm MVE_VQMOVNu32  : MVE_VxMOVxN_halves<"vqmovn",  "u32", 0b1, 0b1, 0b01>;
4791defm MVE_VQMOVUNs16 : MVE_VxMOVxN_halves<"vqmovun", "s16", 0b0, 0b0, 0b00>;
4792defm MVE_VQMOVUNs32 : MVE_VxMOVxN_halves<"vqmovun", "s32", 0b0, 0b0, 0b01>;
4793
4794def MVEvmovn       : SDNode<"ARMISD::VMOVN", SDTARMVEXT>;
4795
4796multiclass MVE_VMOVN_p<Instruction Inst, bit top,
4797                       MVEVectorVTInfo VTI, MVEVectorVTInfo InVTI> {
4798  // Match the most obvious MVEvmovn(a,b,t), which overwrites the odd or even
4799  // lanes of a (depending on t) with the even lanes of b.
4800  def : Pat<(VTI.Vec (MVEvmovn (VTI.Vec MQPR:$Qd_src),
4801                               (VTI.Vec MQPR:$Qm), (i32 top))),
4802            (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src), (VTI.Vec MQPR:$Qm)))>;
4803
4804  if !not(top) then {
4805    // If we see MVEvmovn(a,ARMvrev(b),1), that wants to overwrite the odd
4806    // lanes of a with the odd lanes of b. In other words, the lanes we're
4807    // _keeping_ from a are the even ones. So we can flip it round and say that
4808    // this is the same as overwriting the even lanes of b with the even lanes
4809    // of a, i.e. it's a VMOVNB with the operands reversed.
4810    defvar vrev = !cast<SDNode>("ARMvrev" # InVTI.LaneBits);
4811    def : Pat<(VTI.Vec (MVEvmovn (VTI.Vec MQPR:$Qm),
4812                                 (VTI.Vec (vrev MQPR:$Qd_src)), (i32 1))),
4813              (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src), (VTI.Vec MQPR:$Qm)))>;
4814  }
4815
4816  // Match the IR intrinsic for a predicated VMOVN. This regards the Qm input
4817  // as having wider lanes that we're narrowing, instead of already-narrow
4818  // lanes that we're taking every other one of.
4819  def : Pat<(VTI.Vec (int_arm_mve_vmovn_predicated (VTI.Vec MQPR:$Qd_src),
4820                                  (InVTI.Vec MQPR:$Qm), (i32 top),
4821                                  (InVTI.Pred VCCR:$pred))),
4822            (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src),
4823                              (InVTI.Vec MQPR:$Qm),
4824                              ARMVCCThen, (InVTI.Pred VCCR:$pred)))>;
4825}
4826
4827defm : MVE_VMOVN_p<MVE_VMOVNi32bh, 0, MVE_v8i16, MVE_v4i32>;
4828defm : MVE_VMOVN_p<MVE_VMOVNi32th, 1, MVE_v8i16, MVE_v4i32>;
4829defm : MVE_VMOVN_p<MVE_VMOVNi16bh, 0, MVE_v16i8, MVE_v8i16>;
4830defm : MVE_VMOVN_p<MVE_VMOVNi16th, 1, MVE_v16i8, MVE_v8i16>;
4831
4832multiclass MVE_VQMOVN_p<Instruction Inst, bit outU, bit inU, bit top,
4833                        MVEVectorVTInfo VTI, MVEVectorVTInfo InVTI> {
4834  def : Pat<(VTI.Vec (int_arm_mve_vqmovn (VTI.Vec MQPR:$Qd_src),
4835                                  (InVTI.Vec MQPR:$Qm),
4836                                  (i32 outU), (i32 inU), (i32 top))),
4837            (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src),
4838                              (InVTI.Vec MQPR:$Qm)))>;
4839
4840  def : Pat<(VTI.Vec (int_arm_mve_vqmovn_predicated (VTI.Vec MQPR:$Qd_src),
4841                                  (InVTI.Vec MQPR:$Qm),
4842                                  (i32 outU), (i32 inU), (i32 top),
4843                                  (InVTI.Pred VCCR:$pred))),
4844            (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src),
4845                              (InVTI.Vec MQPR:$Qm),
4846                              ARMVCCThen, (InVTI.Pred VCCR:$pred)))>;
4847}
4848
4849defm : MVE_VQMOVN_p<MVE_VQMOVNs32bh,  0, 0, 0, MVE_v8i16, MVE_v4i32>;
4850defm : MVE_VQMOVN_p<MVE_VQMOVNs32th,  0, 0, 1, MVE_v8i16, MVE_v4i32>;
4851defm : MVE_VQMOVN_p<MVE_VQMOVNs16bh,  0, 0, 0, MVE_v16i8, MVE_v8i16>;
4852defm : MVE_VQMOVN_p<MVE_VQMOVNs16th,  0, 0, 1, MVE_v16i8, MVE_v8i16>;
4853defm : MVE_VQMOVN_p<MVE_VQMOVNu32bh,  1, 1, 0, MVE_v8i16, MVE_v4i32>;
4854defm : MVE_VQMOVN_p<MVE_VQMOVNu32th,  1, 1, 1, MVE_v8i16, MVE_v4i32>;
4855defm : MVE_VQMOVN_p<MVE_VQMOVNu16bh,  1, 1, 0, MVE_v16i8, MVE_v8i16>;
4856defm : MVE_VQMOVN_p<MVE_VQMOVNu16th,  1, 1, 1, MVE_v16i8, MVE_v8i16>;
4857defm : MVE_VQMOVN_p<MVE_VQMOVUNs32bh, 1, 0, 0, MVE_v8i16, MVE_v4i32>;
4858defm : MVE_VQMOVN_p<MVE_VQMOVUNs32th, 1, 0, 1, MVE_v8i16, MVE_v4i32>;
4859defm : MVE_VQMOVN_p<MVE_VQMOVUNs16bh, 1, 0, 0, MVE_v16i8, MVE_v8i16>;
4860defm : MVE_VQMOVN_p<MVE_VQMOVUNs16th, 1, 0, 1, MVE_v16i8, MVE_v8i16>;
4861
4862def SDTARMVMOVNQ : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
4863                                        SDTCisVec<2>, SDTCisVT<3, i32>]>;
4864def MVEvqmovns   : SDNode<"ARMISD::VQMOVNs", SDTARMVMOVNQ>;
4865def MVEvqmovnu   : SDNode<"ARMISD::VQMOVNu", SDTARMVMOVNQ>;
4866
4867let Predicates = [HasMVEInt] in {
4868  def : Pat<(v8i16 (MVEvqmovns (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), (i32 0))),
4869            (v8i16 (MVE_VQMOVNs32bh (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm)))>;
4870  def : Pat<(v8i16 (MVEvqmovns (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), (i32 1))),
4871            (v8i16 (MVE_VQMOVNs32th (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm)))>;
4872  def : Pat<(v16i8 (MVEvqmovns (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), (i32 0))),
4873            (v16i8 (MVE_VQMOVNs16bh (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm)))>;
4874  def : Pat<(v16i8 (MVEvqmovns (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), (i32 1))),
4875            (v16i8 (MVE_VQMOVNs16th (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm)))>;
4876
4877  def : Pat<(v8i16 (MVEvqmovnu (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), (i32 0))),
4878            (v8i16 (MVE_VQMOVNu32bh (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm)))>;
4879  def : Pat<(v8i16 (MVEvqmovnu (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), (i32 1))),
4880            (v8i16 (MVE_VQMOVNu32th (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm)))>;
4881  def : Pat<(v16i8 (MVEvqmovnu (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), (i32 0))),
4882            (v16i8 (MVE_VQMOVNu16bh (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm)))>;
4883  def : Pat<(v16i8 (MVEvqmovnu (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), (i32 1))),
4884            (v16i8 (MVE_VQMOVNu16th (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm)))>;
4885
4886  def : Pat<(v8i16 (MVEvqmovns (v8i16 MQPR:$Qd_src), (v4i32 (ARMvshrsImm (v4i32 MQPR:$Qm), imm0_31:$imm)), (i32 0))),
4887            (v8i16 (MVE_VQSHRNbhs32 (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), imm0_31:$imm))>;
4888  def : Pat<(v16i8 (MVEvqmovns (v16i8 MQPR:$Qd_src), (v8i16 (ARMvshrsImm (v8i16 MQPR:$Qm), imm0_15:$imm)), (i32 0))),
4889            (v16i8 (MVE_VQSHRNbhs16 (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), imm0_15:$imm))>;
4890  def : Pat<(v8i16 (MVEvqmovns (v8i16 MQPR:$Qd_src), (v4i32 (ARMvshrsImm (v4i32 MQPR:$Qm), imm0_31:$imm)), (i32 1))),
4891            (v8i16 (MVE_VQSHRNths32 (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), imm0_31:$imm))>;
4892  def : Pat<(v16i8 (MVEvqmovns (v16i8 MQPR:$Qd_src), (v8i16 (ARMvshrsImm (v8i16 MQPR:$Qm), imm0_15:$imm)), (i32 1))),
4893            (v16i8 (MVE_VQSHRNths16 (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), imm0_15:$imm))>;
4894
4895  def : Pat<(v8i16 (MVEvqmovnu (v8i16 MQPR:$Qd_src), (v4i32 (ARMvshruImm (v4i32 MQPR:$Qm), imm0_31:$imm)), (i32 0))),
4896            (v8i16 (MVE_VQSHRNbhu32 (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), imm0_31:$imm))>;
4897  def : Pat<(v16i8 (MVEvqmovnu (v16i8 MQPR:$Qd_src), (v8i16 (ARMvshruImm (v8i16 MQPR:$Qm), imm0_15:$imm)), (i32 0))),
4898            (v16i8 (MVE_VQSHRNbhu16 (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), imm0_15:$imm))>;
4899  def : Pat<(v8i16 (MVEvqmovnu (v8i16 MQPR:$Qd_src), (v4i32 (ARMvshruImm (v4i32 MQPR:$Qm), imm0_31:$imm)), (i32 1))),
4900            (v8i16 (MVE_VQSHRNthu32 (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), imm0_31:$imm))>;
4901  def : Pat<(v16i8 (MVEvqmovnu (v16i8 MQPR:$Qd_src), (v8i16 (ARMvshruImm (v8i16 MQPR:$Qm), imm0_15:$imm)), (i32 1))),
4902            (v16i8 (MVE_VQSHRNthu16 (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), imm0_15:$imm))>;
4903}
4904
4905class MVE_VCVT_ff<string iname, string suffix, bit op, bit T,
4906                  dag iops_extra, vpred_ops vpred, string cstr>
4907  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
4908                   !con(iops_extra, (ins MQPR:$Qm)), "$Qd, $Qm",
4909                   vpred, cstr, []> {
4910  let Inst{28} = op;
4911  let Inst{21-16} = 0b111111;
4912  let Inst{12} = T;
4913  let Inst{8-7} = 0b00;
4914  let Inst{0} = 0b1;
4915
4916  let Predicates = [HasMVEFloat];
4917  let retainsPreviousHalfElement = 1;
4918}
4919
4920def SDTARMVCVTL    : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
4921                                         SDTCisVT<2, i32>]>;
4922def MVEvcvtn       : SDNode<"ARMISD::VCVTN", SDTARMVMOVNQ>;
4923def MVEvcvtl       : SDNode<"ARMISD::VCVTL", SDTARMVCVTL>;
4924
4925multiclass MVE_VCVT_f2h_m<string iname, int half> {
4926  def "": MVE_VCVT_ff<iname, "f16.f32", 0b0, half,
4927                      (ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">;
4928  defvar Inst = !cast<Instruction>(NAME);
4929
4930  let Predicates = [HasMVEFloat] in {
4931    def : Pat<(v8f16 (int_arm_mve_vcvt_narrow
4932                         (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm), (i32 half))),
4933              (v8f16 (Inst (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm)))>;
4934    def : Pat<(v8f16 (int_arm_mve_vcvt_narrow_predicated
4935                         (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm), (i32 half),
4936                         (v4i1 VCCR:$mask))),
4937              (v8f16 (Inst (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm),
4938                           ARMVCCThen, (v4i1 VCCR:$mask)))>;
4939
4940    def : Pat<(v8f16 (MVEvcvtn (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm), (i32 half))),
4941              (v8f16 (Inst (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm)))>;
4942  }
4943}
4944
4945multiclass MVE_VCVT_h2f_m<string iname, int half> {
4946  def "": MVE_VCVT_ff<iname, "f32.f16", 0b1, half, (ins), vpred_r, "">;
4947  defvar Inst = !cast<Instruction>(NAME);
4948
4949  let Predicates = [HasMVEFloat] in {
4950    def : Pat<(v4f32 (int_arm_mve_vcvt_widen (v8f16 MQPR:$Qm), (i32 half))),
4951              (v4f32 (Inst (v8f16 MQPR:$Qm)))>;
4952    def : Pat<(v4f32 (int_arm_mve_vcvt_widen_predicated
4953                         (v4f32 MQPR:$inactive), (v8f16 MQPR:$Qm), (i32 half),
4954                         (v4i1 VCCR:$mask))),
4955              (v4f32 (Inst (v8f16 MQPR:$Qm), ARMVCCThen,
4956                           (v4i1 VCCR:$mask), (v4f32 MQPR:$inactive)))>;
4957
4958    def : Pat<(v4f32 (MVEvcvtl (v8f16 MQPR:$Qm), (i32 half))),
4959              (v4f32 (Inst (v8f16 MQPR:$Qm)))>;
4960  }
4961}
4962
4963defm MVE_VCVTf16f32bh : MVE_VCVT_f2h_m<"vcvtb", 0b0>;
4964defm MVE_VCVTf16f32th : MVE_VCVT_f2h_m<"vcvtt", 0b1>;
4965defm MVE_VCVTf32f16bh : MVE_VCVT_h2f_m<"vcvtb", 0b0>;
4966defm MVE_VCVTf32f16th : MVE_VCVT_h2f_m<"vcvtt", 0b1>;
4967
4968class MVE_VxCADD<string iname, string suffix, bits<2> size, bit halve,
4969                 string cstr="">
4970  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
4971                   (ins MQPR:$Qn, MQPR:$Qm, complexrotateopodd:$rot),
4972                   "$Qd, $Qn, $Qm, $rot", vpred_r, cstr, []> {
4973  bits<4> Qn;
4974  bit rot;
4975
4976  let Inst{28} = halve;
4977  let Inst{21-20} = size;
4978  let Inst{19-17} = Qn{2-0};
4979  let Inst{16} = 0b0;
4980  let Inst{12} = rot;
4981  let Inst{8} = 0b1;
4982  let Inst{7} = Qn{3};
4983  let Inst{0} = 0b0;
4984}
4985
4986multiclass MVE_VxCADD_m<string iname, MVEVectorVTInfo VTI,
4987                        bit halve, string cstr=""> {
4988  def "" : MVE_VxCADD<iname, VTI.Suffix, VTI.Size, halve, cstr>;
4989  defvar Inst = !cast<Instruction>(NAME);
4990
4991  let Predicates = [HasMVEInt] in {
4992    def : Pat<(VTI.Vec (int_arm_mve_vcaddq halve,
4993                            imm:$rot, (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
4994              (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
4995                             imm:$rot))>;
4996
4997    def : Pat<(VTI.Vec (int_arm_mve_vcaddq_predicated halve,
4998                            imm:$rot, (VTI.Vec MQPR:$inactive),
4999                            (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
5000                            (VTI.Pred VCCR:$mask))),
5001              (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
5002                             imm:$rot, ARMVCCThen, (VTI.Pred VCCR:$mask),
5003                             (VTI.Vec MQPR:$inactive)))>;
5004
5005  }
5006}
5007
5008defm MVE_VCADDi8   : MVE_VxCADD_m<"vcadd", MVE_v16i8, 0b1>;
5009defm MVE_VCADDi16  : MVE_VxCADD_m<"vcadd", MVE_v8i16, 0b1>;
5010defm MVE_VCADDi32  : MVE_VxCADD_m<"vcadd", MVE_v4i32, 0b1, "@earlyclobber $Qd">;
5011
5012defm MVE_VHCADDs8  : MVE_VxCADD_m<"vhcadd", MVE_v16s8, 0b0>;
5013defm MVE_VHCADDs16 : MVE_VxCADD_m<"vhcadd", MVE_v8s16, 0b0>;
5014defm MVE_VHCADDs32 : MVE_VxCADD_m<"vhcadd", MVE_v4s32, 0b0, "@earlyclobber $Qd">;
5015
5016class MVE_VADCSBC<string iname, bit I, bit subtract,
5017                  dag carryin, list<dag> pattern=[]>
5018  : MVE_qDest_qSrc<iname, "i32", (outs MQPR:$Qd, cl_FPSCR_NZCV:$carryout),
5019                   !con((ins MQPR:$Qn, MQPR:$Qm), carryin),
5020                   "$Qd, $Qn, $Qm", vpred_r, "", pattern> {
5021  bits<4> Qn;
5022
5023  let Inst{28} = subtract;
5024  let Inst{21-20} = 0b11;
5025  let Inst{19-17} = Qn{2-0};
5026  let Inst{16} = 0b0;
5027  let Inst{12} = I;
5028  let Inst{8} = 0b1;
5029  let Inst{7} = Qn{3};
5030  let Inst{0} = 0b0;
5031
5032  // Custom decoder method in order to add the FPSCR operand(s), which
5033  // Tablegen won't do right
5034  let DecoderMethod = "DecodeMVEVADCInstruction";
5035}
5036
5037def MVE_VADC  : MVE_VADCSBC<"vadc",  0b0, 0b0, (ins cl_FPSCR_NZCV:$carryin)>;
5038def MVE_VADCI : MVE_VADCSBC<"vadci", 0b1, 0b0, (ins)>;
5039
5040def MVE_VSBC  : MVE_VADCSBC<"vsbc",  0b0, 0b1, (ins cl_FPSCR_NZCV:$carryin)>;
5041def MVE_VSBCI : MVE_VADCSBC<"vsbci", 0b1, 0b1, (ins)>;
5042
5043class MVE_VQDMULL<string iname, string suffix, bit size, bit T,
5044                  string cstr="", list<dag> pattern=[]>
5045  : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
5046                   (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
5047                   vpred_r, cstr, pattern> {
5048  bits<4> Qn;
5049
5050  let Inst{28} = size;
5051  let Inst{21-20} = 0b11;
5052  let Inst{19-17} = Qn{2-0};
5053  let Inst{16} = 0b0;
5054  let Inst{12} = T;
5055  let Inst{8} = 0b1;
5056  let Inst{7} = Qn{3};
5057  let Inst{0} = 0b1;
5058  let validForTailPredication = 1;
5059  let doubleWidthResult = 1;
5060}
5061
5062multiclass MVE_VQDMULL_m<string iname, MVEVectorVTInfo VTI, bit size, bit T,
5063                         string cstr> {
5064  def "" : MVE_VQDMULL<iname, VTI.Suffix, size, T, cstr>;
5065  defvar Inst = !cast<Instruction>(NAME);
5066
5067  let Predicates = [HasMVEInt] in {
5068    // Unpredicated saturating multiply
5069    def : Pat<(VTI.DblVec (int_arm_mve_vqdmull (VTI.Vec MQPR:$Qm),
5070                                               (VTI.Vec MQPR:$Qn), (i32 T))),
5071              (VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
5072    // Predicated saturating multiply
5073    def : Pat<(VTI.DblVec (int_arm_mve_vqdmull_predicated
5074                                    (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
5075                                    (i32 T), (VTI.DblPred VCCR:$mask),
5076                                    (VTI.DblVec MQPR:$inactive))),
5077              (VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
5078                                ARMVCCThen, (VTI.DblPred VCCR:$mask),
5079                                (VTI.DblVec MQPR:$inactive)))>;
5080  }
5081}
5082
5083multiclass MVE_VQDMULL_halves<MVEVectorVTInfo VTI, bit size, string cstr=""> {
5084  defm bh : MVE_VQDMULL_m<"vqdmullb", VTI, size, 0b0, cstr>;
5085  defm th : MVE_VQDMULL_m<"vqdmullt", VTI, size, 0b1, cstr>;
5086}
5087
5088defm MVE_VQDMULLs16 : MVE_VQDMULL_halves<MVE_v8s16, 0b0>;
5089defm MVE_VQDMULLs32 : MVE_VQDMULL_halves<MVE_v4s32, 0b1, "@earlyclobber $Qd">;
5090
5091// end of mve_qDest_qSrc
5092
5093// start of mve_qDest_rSrc
5094
5095class MVE_qr_base<dag oops, dag iops, InstrItinClass itin, string iname,
5096                  string suffix, string ops, vpred_ops vpred, string cstr,
5097                  list<dag> pattern=[]>
5098   : MVE_p<oops, iops, NoItinerary, iname, suffix, ops, vpred, cstr, pattern> {
5099  bits<4> Qd;
5100  bits<4> Qn;
5101  bits<4> Rm;
5102
5103  let Inst{25-23} = 0b100;
5104  let Inst{22} = Qd{3};
5105  let Inst{19-17} = Qn{2-0};
5106  let Inst{15-13} = Qd{2-0};
5107  let Inst{11-9} = 0b111;
5108  let Inst{7} = Qn{3};
5109  let Inst{6} = 0b1;
5110  let Inst{4} = 0b0;
5111  let Inst{3-0} = Rm{3-0};
5112}
5113
5114class MVE_qDest_rSrc<string iname, string suffix, string cstr="", list<dag> pattern=[]>
5115  : MVE_qr_base<(outs MQPR:$Qd), (ins MQPR:$Qn, rGPR:$Rm),
5116          NoItinerary, iname, suffix, "$Qd, $Qn, $Rm", vpred_r, cstr,
5117           pattern>;
5118
5119class MVE_qDestSrc_rSrc<string iname, string suffix, list<dag> pattern=[]>
5120  : MVE_qr_base<(outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qn, rGPR:$Rm),
5121          NoItinerary, iname, suffix, "$Qd, $Qn, $Rm", vpred_n, "$Qd = $Qd_src",
5122           pattern>;
5123
5124class MVE_qDest_single_rSrc<string iname, string suffix, list<dag> pattern=[]>
5125  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qd_src, rGPR:$Rm), NoItinerary, iname,
5126          suffix, "$Qd, $Rm", vpred_n, "$Qd = $Qd_src", pattern> {
5127  bits<4> Qd;
5128  bits<4> Rm;
5129
5130  let Inst{22} = Qd{3};
5131  let Inst{15-13} = Qd{2-0};
5132  let Inst{3-0} = Rm{3-0};
5133}
5134
5135// Patterns for vector-scalar instructions with integer operands
5136multiclass MVE_vec_scalar_int_pat_m<Instruction inst, MVEVectorVTInfo VTI,
5137                                    SDNode unpred_op, SDNode pred_op,
5138                                    bit unpred_has_sign = 0,
5139                                    bit pred_has_sign = 0> {
5140  defvar UnpredSign = !if(unpred_has_sign, (? (i32 VTI.Unsigned)), (?));
5141  defvar PredSign = !if(pred_has_sign, (? (i32 VTI.Unsigned)), (?));
5142
5143  let Predicates = [HasMVEInt] in {
5144    // Unpredicated version
5145    def : Pat<(VTI.Vec !con((unpred_op (VTI.Vec MQPR:$Qm),
5146                                       (VTI.Vec (ARMvdup rGPR:$val))),
5147                            UnpredSign)),
5148              (VTI.Vec (inst (VTI.Vec MQPR:$Qm), (i32 rGPR:$val)))>;
5149    // Predicated version
5150    def : Pat<(VTI.Vec !con((pred_op (VTI.Vec MQPR:$Qm),
5151                                     (VTI.Vec (ARMvdup rGPR:$val))),
5152                            PredSign,
5153                            (pred_op (VTI.Pred VCCR:$mask),
5154                                     (VTI.Vec MQPR:$inactive)))),
5155              (VTI.Vec (inst (VTI.Vec MQPR:$Qm), (i32 rGPR:$val),
5156                             ARMVCCThen, (VTI.Pred VCCR:$mask),
5157                             (VTI.Vec MQPR:$inactive)))>;
5158  }
5159}
5160
5161class MVE_VADDSUB_qr<string iname, string suffix, bits<2> size,
5162                     bit bit_5, bit bit_12, bit bit_16, bit bit_28>
5163  : MVE_qDest_rSrc<iname, suffix, ""> {
5164
5165  let Inst{28} = bit_28;
5166  let Inst{21-20} = size;
5167  let Inst{16} = bit_16;
5168  let Inst{12} = bit_12;
5169  let Inst{8} = 0b1;
5170  let Inst{5} = bit_5;
5171  let validForTailPredication = 1;
5172}
5173
5174// Vector-scalar add/sub
5175multiclass MVE_VADDSUB_qr_m<string iname, MVEVectorVTInfo VTI, bit subtract,
5176                            SDNode Op, Intrinsic PredInt> {
5177  def "" : MVE_VADDSUB_qr<iname, VTI.Suffix, VTI.Size, 0b0, subtract, 0b1, 0b0>;
5178  let Predicates = [HasMVEInt] in {
5179    defm : MVE_TwoOpPatternDup<VTI, Op, PredInt, (? ), !cast<Instruction>(NAME), ARMimmAllZerosV>;
5180  }
5181}
5182
5183multiclass MVE_VADD_qr_m<MVEVectorVTInfo VTI>
5184  : MVE_VADDSUB_qr_m<"vadd", VTI, 0b0, add, int_arm_mve_add_predicated>;
5185
5186multiclass MVE_VSUB_qr_m<MVEVectorVTInfo VTI>
5187  : MVE_VADDSUB_qr_m<"vsub", VTI, 0b1, sub, int_arm_mve_sub_predicated>;
5188
5189defm MVE_VADD_qr_i8  : MVE_VADD_qr_m<MVE_v16i8>;
5190defm MVE_VADD_qr_i16 : MVE_VADD_qr_m<MVE_v8i16>;
5191defm MVE_VADD_qr_i32 : MVE_VADD_qr_m<MVE_v4i32>;
5192
5193defm MVE_VSUB_qr_i8  : MVE_VSUB_qr_m<MVE_v16i8>;
5194defm MVE_VSUB_qr_i16 : MVE_VSUB_qr_m<MVE_v8i16>;
5195defm MVE_VSUB_qr_i32 : MVE_VSUB_qr_m<MVE_v4i32>;
5196
5197// Vector-scalar saturating add/sub
5198multiclass MVE_VQADDSUB_qr_m<string iname, MVEVectorVTInfo VTI, bit subtract,
5199                             SDNode Op, Intrinsic PredInt> {
5200  def "" : MVE_VADDSUB_qr<iname, VTI.Suffix, VTI.Size, 0b1, subtract,
5201                          0b0, VTI.Unsigned>;
5202
5203  let Predicates = [HasMVEInt] in {
5204    defm : MVE_TwoOpPatternDup<VTI, Op, PredInt, (? (i32 VTI.Unsigned)),
5205                               !cast<Instruction>(NAME)>;
5206  }
5207}
5208
5209multiclass MVE_VQADD_qr_m<MVEVectorVTInfo VTI, SDNode Op>
5210  : MVE_VQADDSUB_qr_m<"vqadd", VTI, 0b0, Op, int_arm_mve_qadd_predicated>;
5211
5212multiclass MVE_VQSUB_qr_m<MVEVectorVTInfo VTI, SDNode Op>
5213  : MVE_VQADDSUB_qr_m<"vqsub", VTI, 0b1, Op, int_arm_mve_qsub_predicated>;
5214
5215defm MVE_VQADD_qr_s8  : MVE_VQADD_qr_m<MVE_v16s8, saddsat>;
5216defm MVE_VQADD_qr_s16 : MVE_VQADD_qr_m<MVE_v8s16, saddsat>;
5217defm MVE_VQADD_qr_s32 : MVE_VQADD_qr_m<MVE_v4s32, saddsat>;
5218defm MVE_VQADD_qr_u8  : MVE_VQADD_qr_m<MVE_v16u8, uaddsat>;
5219defm MVE_VQADD_qr_u16 : MVE_VQADD_qr_m<MVE_v8u16, uaddsat>;
5220defm MVE_VQADD_qr_u32 : MVE_VQADD_qr_m<MVE_v4u32, uaddsat>;
5221
5222defm MVE_VQSUB_qr_s8  : MVE_VQSUB_qr_m<MVE_v16s8, ssubsat>;
5223defm MVE_VQSUB_qr_s16 : MVE_VQSUB_qr_m<MVE_v8s16, ssubsat>;
5224defm MVE_VQSUB_qr_s32 : MVE_VQSUB_qr_m<MVE_v4s32, ssubsat>;
5225defm MVE_VQSUB_qr_u8  : MVE_VQSUB_qr_m<MVE_v16u8, usubsat>;
5226defm MVE_VQSUB_qr_u16 : MVE_VQSUB_qr_m<MVE_v8u16, usubsat>;
5227defm MVE_VQSUB_qr_u32 : MVE_VQSUB_qr_m<MVE_v4u32, usubsat>;
5228
5229class MVE_VQDMULL_qr<string iname, string suffix, bit size,
5230                     bit T, string cstr="", list<dag> pattern=[]>
5231  : MVE_qDest_rSrc<iname, suffix, cstr, pattern> {
5232
5233  let Inst{28} = size;
5234  let Inst{21-20} = 0b11;
5235  let Inst{16} = 0b0;
5236  let Inst{12} = T;
5237  let Inst{8} = 0b1;
5238  let Inst{5} = 0b1;
5239  let validForTailPredication = 1;
5240  let doubleWidthResult = 1;
5241}
5242
5243multiclass MVE_VQDMULL_qr_m<string iname, MVEVectorVTInfo VTI, bit size,
5244                            bit T, string cstr> {
5245  def "" : MVE_VQDMULL_qr<iname, VTI.Suffix, size, T, cstr>;
5246  defvar Inst = !cast<Instruction>(NAME);
5247
5248  let Predicates = [HasMVEInt] in {
5249    // Unpredicated saturating multiply
5250    def : Pat<(VTI.DblVec (int_arm_mve_vqdmull (VTI.Vec MQPR:$Qm),
5251                                               (VTI.Vec (ARMvdup rGPR:$val)),
5252                                               (i32 T))),
5253              (VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (i32 rGPR:$val)))>;
5254    // Predicated saturating multiply
5255    def : Pat<(VTI.DblVec (int_arm_mve_vqdmull_predicated
5256                                    (VTI.Vec MQPR:$Qm),
5257                                    (VTI.Vec (ARMvdup rGPR:$val)),
5258                                    (i32 T),
5259                                    (VTI.DblPred VCCR:$mask),
5260                                    (VTI.DblVec MQPR:$inactive))),
5261              (VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (i32 rGPR:$val),
5262                             ARMVCCThen, (VTI.DblPred VCCR:$mask),
5263                             (VTI.DblVec MQPR:$inactive)))>;
5264  }
5265}
5266
5267multiclass MVE_VQDMULL_qr_halves<MVEVectorVTInfo VTI, bit size, string cstr=""> {
5268  defm bh : MVE_VQDMULL_qr_m<"vqdmullb", VTI, size, 0b0, cstr>;
5269  defm th : MVE_VQDMULL_qr_m<"vqdmullt", VTI, size, 0b1, cstr>;
5270}
5271
5272defm MVE_VQDMULL_qr_s16 : MVE_VQDMULL_qr_halves<MVE_v8s16, 0b0>;
5273defm MVE_VQDMULL_qr_s32 : MVE_VQDMULL_qr_halves<MVE_v4s32, 0b1, "@earlyclobber $Qd">;
5274
5275class MVE_VxADDSUB_qr<string iname, string suffix,
5276                      bit bit_28, bits<2> bits_21_20, bit subtract,
5277                      list<dag> pattern=[]>
5278  : MVE_qDest_rSrc<iname, suffix, "", pattern> {
5279
5280  let Inst{28} = bit_28;
5281  let Inst{21-20} = bits_21_20;
5282  let Inst{16} = 0b0;
5283  let Inst{12} = subtract;
5284  let Inst{8} = 0b1;
5285  let Inst{5} = 0b0;
5286  let validForTailPredication = 1;
5287}
5288
5289multiclass MVE_VHADDSUB_qr_m<string iname, MVEVectorVTInfo VTI, bit subtract,
5290                             Intrinsic unpred_int, Intrinsic pred_int> {
5291  def "" : MVE_VxADDSUB_qr<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, subtract>;
5292  defm : MVE_vec_scalar_int_pat_m<!cast<Instruction>(NAME),
5293                                  VTI, unpred_int, pred_int, 1, 1>;
5294}
5295
5296multiclass MVE_VHADD_qr_m<MVEVectorVTInfo VTI> :
5297  MVE_VHADDSUB_qr_m<"vhadd", VTI, 0b0, int_arm_mve_vhadd,
5298                                       int_arm_mve_hadd_predicated>;
5299
5300multiclass MVE_VHSUB_qr_m<MVEVectorVTInfo VTI> :
5301  MVE_VHADDSUB_qr_m<"vhsub", VTI, 0b1, int_arm_mve_vhsub,
5302                                       int_arm_mve_hsub_predicated>;
5303
5304defm MVE_VHADD_qr_s8  : MVE_VHADD_qr_m<MVE_v16s8>;
5305defm MVE_VHADD_qr_s16 : MVE_VHADD_qr_m<MVE_v8s16>;
5306defm MVE_VHADD_qr_s32 : MVE_VHADD_qr_m<MVE_v4s32>;
5307defm MVE_VHADD_qr_u8  : MVE_VHADD_qr_m<MVE_v16u8>;
5308defm MVE_VHADD_qr_u16 : MVE_VHADD_qr_m<MVE_v8u16>;
5309defm MVE_VHADD_qr_u32 : MVE_VHADD_qr_m<MVE_v4u32>;
5310
5311defm MVE_VHSUB_qr_s8  : MVE_VHSUB_qr_m<MVE_v16s8>;
5312defm MVE_VHSUB_qr_s16 : MVE_VHSUB_qr_m<MVE_v8s16>;
5313defm MVE_VHSUB_qr_s32 : MVE_VHSUB_qr_m<MVE_v4s32>;
5314defm MVE_VHSUB_qr_u8  : MVE_VHSUB_qr_m<MVE_v16u8>;
5315defm MVE_VHSUB_qr_u16 : MVE_VHSUB_qr_m<MVE_v8u16>;
5316defm MVE_VHSUB_qr_u32 : MVE_VHSUB_qr_m<MVE_v4u32>;
5317
5318multiclass MVE_VADDSUB_qr_f<string iname, MVEVectorVTInfo VTI, bit subtract,
5319                            SDNode Op, Intrinsic PredInt> {
5320  def "" : MVE_VxADDSUB_qr<iname, VTI.Suffix, VTI.Size{0}, 0b11, subtract>;
5321  defm : MVE_TwoOpPatternDup<VTI, Op, PredInt, (? ),
5322                              !cast<Instruction>(NAME)>;
5323}
5324
5325let Predicates = [HasMVEFloat] in {
5326  defm MVE_VADD_qr_f32 : MVE_VADDSUB_qr_f<"vadd", MVE_v4f32, 0b0, fadd,
5327                                          int_arm_mve_add_predicated>;
5328  defm MVE_VADD_qr_f16 : MVE_VADDSUB_qr_f<"vadd", MVE_v8f16, 0b0, fadd,
5329                                          int_arm_mve_add_predicated>;
5330
5331  defm MVE_VSUB_qr_f32 : MVE_VADDSUB_qr_f<"vsub", MVE_v4f32, 0b1, fsub,
5332                                          int_arm_mve_sub_predicated>;
5333  defm MVE_VSUB_qr_f16 : MVE_VADDSUB_qr_f<"vsub", MVE_v8f16, 0b1, fsub,
5334                                          int_arm_mve_sub_predicated>;
5335}
5336
5337class MVE_VxSHL_qr<string iname, string suffix, bit U, bits<2> size,
5338                   bit bit_7, bit bit_17, list<dag> pattern=[]>
5339  : MVE_qDest_single_rSrc<iname, suffix, pattern> {
5340
5341  let Inst{28} = U;
5342  let Inst{25-23} = 0b100;
5343  let Inst{21-20} = 0b11;
5344  let Inst{19-18} = size;
5345  let Inst{17} = bit_17;
5346  let Inst{16} = 0b1;
5347  let Inst{12-8} = 0b11110;
5348  let Inst{7} = bit_7;
5349  let Inst{6-4} = 0b110;
5350  let validForTailPredication = 1;
5351}
5352
5353multiclass MVE_VxSHL_qr_p<string iname, MVEVectorVTInfo VTI, bit q, bit r> {
5354  def "" : MVE_VxSHL_qr<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, q, r>;
5355  defvar Inst = !cast<Instruction>(NAME);
5356
5357  def : Pat<(VTI.Vec (int_arm_mve_vshl_scalar
5358                         (VTI.Vec MQPR:$in), (i32 rGPR:$sh),
5359                         (i32 q), (i32 r), (i32 VTI.Unsigned))),
5360            (VTI.Vec (Inst (VTI.Vec MQPR:$in), (i32 rGPR:$sh)))>;
5361
5362  def : Pat<(VTI.Vec (int_arm_mve_vshl_scalar_predicated
5363                         (VTI.Vec MQPR:$in), (i32 rGPR:$sh),
5364                         (i32 q), (i32 r), (i32 VTI.Unsigned),
5365                         (VTI.Pred VCCR:$mask))),
5366            (VTI.Vec (Inst (VTI.Vec MQPR:$in), (i32 rGPR:$sh),
5367                           ARMVCCThen, (VTI.Pred VCCR:$mask)))>;
5368}
5369
5370multiclass MVE_VxSHL_qr_types<string iname, bit bit_7, bit bit_17> {
5371  defm s8  : MVE_VxSHL_qr_p<iname, MVE_v16s8, bit_7, bit_17>;
5372  defm s16 : MVE_VxSHL_qr_p<iname, MVE_v8s16, bit_7, bit_17>;
5373  defm s32 : MVE_VxSHL_qr_p<iname, MVE_v4s32, bit_7, bit_17>;
5374  defm u8  : MVE_VxSHL_qr_p<iname, MVE_v16u8, bit_7, bit_17>;
5375  defm u16 : MVE_VxSHL_qr_p<iname, MVE_v8u16, bit_7, bit_17>;
5376  defm u32 : MVE_VxSHL_qr_p<iname, MVE_v4u32, bit_7, bit_17>;
5377}
5378
5379defm MVE_VSHL_qr   : MVE_VxSHL_qr_types<"vshl",   0b0, 0b0>;
5380defm MVE_VRSHL_qr  : MVE_VxSHL_qr_types<"vrshl",  0b0, 0b1>;
5381defm MVE_VQSHL_qr  : MVE_VxSHL_qr_types<"vqshl",  0b1, 0b0>;
5382defm MVE_VQRSHL_qr : MVE_VxSHL_qr_types<"vqrshl", 0b1, 0b1>;
5383
5384let Predicates = [HasMVEInt] in {
5385  def : Pat<(v4i32 (ARMvshlu (v4i32 MQPR:$Qm), (v4i32 (ARMvdup rGPR:$Rm)))),
5386            (v4i32 (MVE_VSHL_qru32 (v4i32 MQPR:$Qm), rGPR:$Rm))>;
5387  def : Pat<(v8i16 (ARMvshlu (v8i16 MQPR:$Qm), (v8i16 (ARMvdup rGPR:$Rm)))),
5388            (v8i16 (MVE_VSHL_qru16 (v8i16 MQPR:$Qm), rGPR:$Rm))>;
5389  def : Pat<(v16i8 (ARMvshlu (v16i8 MQPR:$Qm), (v16i8 (ARMvdup rGPR:$Rm)))),
5390            (v16i8 (MVE_VSHL_qru8 (v16i8 MQPR:$Qm), rGPR:$Rm))>;
5391
5392  def : Pat<(v4i32 (ARMvshls (v4i32 MQPR:$Qm), (v4i32 (ARMvdup rGPR:$Rm)))),
5393            (v4i32 (MVE_VSHL_qrs32 (v4i32 MQPR:$Qm), rGPR:$Rm))>;
5394  def : Pat<(v8i16 (ARMvshls (v8i16 MQPR:$Qm), (v8i16 (ARMvdup rGPR:$Rm)))),
5395            (v8i16 (MVE_VSHL_qrs16 (v8i16 MQPR:$Qm), rGPR:$Rm))>;
5396  def : Pat<(v16i8 (ARMvshls (v16i8 MQPR:$Qm), (v16i8 (ARMvdup rGPR:$Rm)))),
5397            (v16i8 (MVE_VSHL_qrs8 (v16i8 MQPR:$Qm), rGPR:$Rm))>;
5398}
5399
5400class MVE_VBRSR<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
5401  : MVE_qDest_rSrc<iname, suffix, "", pattern> {
5402
5403  let Inst{28} = 0b1;
5404  let Inst{21-20} = size;
5405  let Inst{16} = 0b1;
5406  let Inst{12} = 0b1;
5407  let Inst{8} = 0b0;
5408  let Inst{5} = 0b1;
5409  let validForTailPredication = 1;
5410}
5411
5412def MVE_VBRSR8  : MVE_VBRSR<"vbrsr", "8", 0b00>;
5413def MVE_VBRSR16 : MVE_VBRSR<"vbrsr", "16", 0b01>;
5414def MVE_VBRSR32 : MVE_VBRSR<"vbrsr", "32", 0b10>;
5415
5416multiclass MVE_VBRSR_pat_m<MVEVectorVTInfo VTI, Instruction Inst> {
5417  // Unpredicated
5418  def : Pat<(VTI.Vec (int_arm_mve_vbrsr (VTI.Vec MQPR:$Qn), (i32 rGPR:$Rm))),
5419            (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (i32 rGPR:$Rm)))>;
5420  // Predicated
5421  def : Pat<(VTI.Vec (int_arm_mve_vbrsr_predicated
5422                          (VTI.Vec MQPR:$inactive),
5423                          (VTI.Vec MQPR:$Qn), (i32 rGPR:$Rm),
5424                          (VTI.Pred VCCR:$mask))),
5425            (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (i32 rGPR:$Rm),
5426                          ARMVCCThen, (VTI.Pred VCCR:$mask),
5427                          (VTI.Vec MQPR:$inactive)))>;
5428}
5429
5430let Predicates = [HasMVEInt] in {
5431  def : Pat<(v16i8 ( bitreverse (v16i8 MQPR:$val1))),
5432            (v16i8 ( MVE_VBRSR8 (v16i8 MQPR:$val1), (t2MOVi (i32 8)) ))>;
5433
5434  def : Pat<(v4i32 ( bitreverse (v4i32 MQPR:$val1))),
5435            (v4i32 ( MVE_VBRSR32 (v4i32 MQPR:$val1), (t2MOVi (i32 32)) ))>;
5436
5437  def : Pat<(v8i16 ( bitreverse (v8i16 MQPR:$val1))),
5438            (v8i16 ( MVE_VBRSR16 (v8i16 MQPR:$val1), (t2MOVi (i32 16)) ))>;
5439
5440  defm : MVE_VBRSR_pat_m<MVE_v16i8, MVE_VBRSR8>;
5441  defm : MVE_VBRSR_pat_m<MVE_v8i16, MVE_VBRSR16>;
5442  defm : MVE_VBRSR_pat_m<MVE_v4i32, MVE_VBRSR32>;
5443}
5444
5445let Predicates = [HasMVEFloat] in {
5446  defm : MVE_VBRSR_pat_m<MVE_v8f16, MVE_VBRSR16>;
5447  defm : MVE_VBRSR_pat_m<MVE_v4f32, MVE_VBRSR32>;
5448}
5449
5450class MVE_VMUL_qr_int<string iname, string suffix, bits<2> size>
5451  : MVE_qDest_rSrc<iname, suffix, ""> {
5452
5453  let Inst{28} = 0b0;
5454  let Inst{21-20} = size;
5455  let Inst{16} = 0b1;
5456  let Inst{12} = 0b1;
5457  let Inst{8} = 0b0;
5458  let Inst{5} = 0b1;
5459  let validForTailPredication = 1;
5460}
5461
5462multiclass MVE_VMUL_qr_int_m<MVEVectorVTInfo VTI> {
5463  def "" : MVE_VMUL_qr_int<"vmul", VTI.Suffix, VTI.Size>;
5464  let Predicates = [HasMVEInt] in {
5465    defm : MVE_TwoOpPatternDup<VTI, mul, int_arm_mve_mul_predicated, (? ),
5466                               !cast<Instruction>(NAME), ARMimmOneV>;
5467  }
5468}
5469
5470defm MVE_VMUL_qr_i8  : MVE_VMUL_qr_int_m<MVE_v16i8>;
5471defm MVE_VMUL_qr_i16 : MVE_VMUL_qr_int_m<MVE_v8i16>;
5472defm MVE_VMUL_qr_i32 : MVE_VMUL_qr_int_m<MVE_v4i32>;
5473
5474class MVE_VxxMUL_qr<string iname, string suffix,
5475                    bit bit_28, bits<2> bits_21_20, list<dag> pattern=[]>
5476  : MVE_qDest_rSrc<iname, suffix, "", pattern> {
5477
5478  let Inst{28} = bit_28;
5479  let Inst{21-20} = bits_21_20;
5480  let Inst{16} = 0b1;
5481  let Inst{12} = 0b0;
5482  let Inst{8} = 0b0;
5483  let Inst{5} = 0b1;
5484  let validForTailPredication = 1;
5485}
5486
5487multiclass MVE_VxxMUL_qr_m<string iname, MVEVectorVTInfo VTI, bit bit_28,
5488                           PatFrag Op, Intrinsic int_unpred, Intrinsic int_pred> {
5489  def "" : MVE_VxxMUL_qr<iname, VTI.Suffix, bit_28, VTI.Size>;
5490
5491  let Predicates = [HasMVEInt] in {
5492    defm : MVE_TwoOpPatternDup<VTI, Op, int_pred, (? ), !cast<Instruction>(NAME)>;
5493  }
5494  defm : MVE_vec_scalar_int_pat_m<!cast<Instruction>(NAME), VTI, int_unpred, int_pred>;
5495}
5496
5497multiclass MVE_VQDMULH_qr_m<MVEVectorVTInfo VTI> :
5498  MVE_VxxMUL_qr_m<"vqdmulh", VTI, 0b0, MVEvqdmulh,
5499                  int_arm_mve_vqdmulh, int_arm_mve_qdmulh_predicated>;
5500
5501multiclass MVE_VQRDMULH_qr_m<MVEVectorVTInfo VTI> :
5502  MVE_VxxMUL_qr_m<"vqrdmulh", VTI, 0b1, null_frag,
5503                  int_arm_mve_vqrdmulh, int_arm_mve_qrdmulh_predicated>;
5504
5505defm MVE_VQDMULH_qr_s8    : MVE_VQDMULH_qr_m<MVE_v16s8>;
5506defm MVE_VQDMULH_qr_s16   : MVE_VQDMULH_qr_m<MVE_v8s16>;
5507defm MVE_VQDMULH_qr_s32   : MVE_VQDMULH_qr_m<MVE_v4s32>;
5508
5509defm MVE_VQRDMULH_qr_s8   : MVE_VQRDMULH_qr_m<MVE_v16s8>;
5510defm MVE_VQRDMULH_qr_s16  : MVE_VQRDMULH_qr_m<MVE_v8s16>;
5511defm MVE_VQRDMULH_qr_s32  : MVE_VQRDMULH_qr_m<MVE_v4s32>;
5512
5513multiclass MVE_VxxMUL_qr_f_m<MVEVectorVTInfo VTI> {
5514  let validForTailPredication = 1 in
5515  def "" : MVE_VxxMUL_qr<"vmul", VTI.Suffix, VTI.Size{0}, 0b11>;
5516  defm : MVE_TwoOpPatternDup<VTI, fmul, int_arm_mve_mul_predicated, (? ),
5517                             !cast<Instruction>(NAME)>;
5518}
5519
5520let Predicates = [HasMVEFloat] in {
5521  defm MVE_VMUL_qr_f16   : MVE_VxxMUL_qr_f_m<MVE_v8f16>;
5522  defm MVE_VMUL_qr_f32   : MVE_VxxMUL_qr_f_m<MVE_v4f32>;
5523}
5524
5525class MVE_VFMAMLA_qr<string iname, string suffix,
5526                     bit bit_28, bits<2> bits_21_20, bit S,
5527                     list<dag> pattern=[]>
5528  : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
5529
5530  let Inst{28} = bit_28;
5531  let Inst{21-20} = bits_21_20;
5532  let Inst{16} = 0b1;
5533  let Inst{12} = S;
5534  let Inst{8} = 0b0;
5535  let Inst{5} = 0b0;
5536  let validForTailPredication = 1;
5537  let hasSideEffects = 0;
5538}
5539
5540multiclass MVE_VMLA_qr_multi<string iname, MVEVectorVTInfo VTI,
5541                             bit scalar_addend> {
5542  def "": MVE_VFMAMLA_qr<iname, VTI.Suffix, VTI.Unsigned, VTI.Size,
5543                         scalar_addend>;
5544  defvar Inst = !cast<Instruction>(NAME);
5545  defvar pred_int = !cast<Intrinsic>("int_arm_mve_" # iname # "_n_predicated");
5546  defvar v1   = (VTI.Vec MQPR:$v1);
5547  defvar v2   = (VTI.Vec MQPR:$v2);
5548  defvar vs   = (VTI.Vec (ARMvdup rGPR:$s));
5549  defvar s    = (i32 rGPR:$s);
5550  defvar pred = (VTI.Pred VCCR:$pred);
5551
5552  // The signed and unsigned variants of this instruction have different
5553  // encodings, but they're functionally identical. For the sake of
5554  // determinism, we generate only the unsigned variant.
5555  if VTI.Unsigned then let Predicates = [HasMVEInt] in {
5556    if scalar_addend then {
5557      def : Pat<(VTI.Vec (add (mul v1, v2), vs)),
5558                (VTI.Vec (Inst v1, v2, s))>;
5559    } else {
5560      def : Pat<(VTI.Vec (add (mul v2, vs), v1)),
5561                (VTI.Vec (Inst v1, v2, s))>;
5562    }
5563
5564    def : Pat<(VTI.Vec (pred_int v1, v2, s, pred)),
5565              (VTI.Vec (Inst v1, v2, s, ARMVCCThen, pred))>;
5566  }
5567}
5568
5569defm MVE_VMLA_qr_s8   : MVE_VMLA_qr_multi<"vmla", MVE_v16s8, 0b0>;
5570defm MVE_VMLA_qr_s16  : MVE_VMLA_qr_multi<"vmla", MVE_v8s16, 0b0>;
5571defm MVE_VMLA_qr_s32  : MVE_VMLA_qr_multi<"vmla", MVE_v4s32, 0b0>;
5572defm MVE_VMLA_qr_u8   : MVE_VMLA_qr_multi<"vmla", MVE_v16u8, 0b0>;
5573defm MVE_VMLA_qr_u16  : MVE_VMLA_qr_multi<"vmla", MVE_v8u16, 0b0>;
5574defm MVE_VMLA_qr_u32  : MVE_VMLA_qr_multi<"vmla", MVE_v4u32, 0b0>;
5575
5576defm MVE_VMLAS_qr_s8  : MVE_VMLA_qr_multi<"vmlas", MVE_v16s8, 0b1>;
5577defm MVE_VMLAS_qr_s16 : MVE_VMLA_qr_multi<"vmlas", MVE_v8s16, 0b1>;
5578defm MVE_VMLAS_qr_s32 : MVE_VMLA_qr_multi<"vmlas", MVE_v4s32, 0b1>;
5579defm MVE_VMLAS_qr_u8  : MVE_VMLA_qr_multi<"vmlas", MVE_v16u8, 0b1>;
5580defm MVE_VMLAS_qr_u16 : MVE_VMLA_qr_multi<"vmlas", MVE_v8u16, 0b1>;
5581defm MVE_VMLAS_qr_u32 : MVE_VMLA_qr_multi<"vmlas", MVE_v4u32, 0b1>;
5582
5583multiclass MVE_VFMA_qr_multi<string iname, MVEVectorVTInfo VTI,
5584                             bit scalar_addend> {
5585  def "": MVE_VFMAMLA_qr<iname, VTI.Suffix, VTI.Size{0}, 0b11, scalar_addend>;
5586  defvar Inst = !cast<Instruction>(NAME);
5587  defvar pred_int = int_arm_mve_fma_predicated;
5588  defvar v1   = (VTI.Vec MQPR:$v1);
5589  defvar v2   = (VTI.Vec MQPR:$v2);
5590  defvar vs   = (VTI.Vec (ARMvdup (i32 rGPR:$s)));
5591  defvar is   = (i32 rGPR:$s);
5592  defvar pred = (VTI.Pred VCCR:$pred);
5593
5594  let Predicates = [HasMVEFloat] in {
5595    if scalar_addend then {
5596      def : Pat<(VTI.Vec (fma v1, v2, vs)),
5597                (VTI.Vec (Inst v1, v2, is))>;
5598      def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
5599                                  (VTI.Vec (fma v1, v2, vs)),
5600                                  v1)),
5601                (VTI.Vec (Inst v1, v2, is, ARMVCCThen, $pred))>;
5602      def : Pat<(VTI.Vec (pred_int v1, v2, vs, pred)),
5603                (VTI.Vec (Inst v1, v2, is, ARMVCCThen, pred))>;
5604    } else {
5605      def : Pat<(VTI.Vec (fma v1, vs, v2)),
5606                (VTI.Vec (Inst v2, v1, is))>;
5607      def : Pat<(VTI.Vec (fma vs, v1, v2)),
5608                (VTI.Vec (Inst v2, v1, is))>;
5609      def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
5610                                  (VTI.Vec (fma vs, v2, v1)),
5611                                  v1)),
5612                (VTI.Vec (Inst v1, v2, is, ARMVCCThen, $pred))>;
5613      def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
5614                                  (VTI.Vec (fma v2, vs, v1)),
5615                                  v1)),
5616                (VTI.Vec (Inst v1, v2, is, ARMVCCThen, $pred))>;
5617      def : Pat<(VTI.Vec (pred_int v1, vs, v2, pred)),
5618                (VTI.Vec (Inst v2, v1, is, ARMVCCThen, pred))>;
5619      def : Pat<(VTI.Vec (pred_int vs, v1, v2, pred)),
5620                (VTI.Vec (Inst v2, v1, is, ARMVCCThen, pred))>;
5621    }
5622  }
5623}
5624
5625let Predicates = [HasMVEFloat] in {
5626  defm MVE_VFMA_qr_f16  : MVE_VFMA_qr_multi<"vfma",  MVE_v8f16, 0>;
5627  defm MVE_VFMA_qr_f32  : MVE_VFMA_qr_multi<"vfma",  MVE_v4f32, 0>;
5628  defm MVE_VFMA_qr_Sf16 : MVE_VFMA_qr_multi<"vfmas", MVE_v8f16, 1>;
5629  defm MVE_VFMA_qr_Sf32 : MVE_VFMA_qr_multi<"vfmas", MVE_v4f32, 1>;
5630}
5631
5632class MVE_VQDMLAH_qr<string iname, string suffix, bit U, bits<2> size,
5633                     bit bit_5, bit bit_12, list<dag> pattern=[]>
5634  : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
5635
5636  let Inst{28} = U;
5637  let Inst{21-20} = size;
5638  let Inst{16} = 0b0;
5639  let Inst{12} = bit_12;
5640  let Inst{8} = 0b0;
5641  let Inst{5} = bit_5;
5642}
5643
5644multiclass MVE_VQDMLAH_qr_multi<string iname, MVEVectorVTInfo VTI,
5645                                bit bit_5, bit bit_12> {
5646  def "": MVE_VQDMLAH_qr<iname, VTI.Suffix, 0b0, VTI.Size, bit_5, bit_12>;
5647  defvar Inst = !cast<Instruction>(NAME);
5648  defvar unpred_int = !cast<Intrinsic>("int_arm_mve_" # iname);
5649  defvar pred_int = !cast<Intrinsic>("int_arm_mve_" # iname # "_predicated");
5650
5651  let Predicates = [HasMVEInt] in {
5652    def : Pat<(VTI.Vec (unpred_int (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2),
5653                                   (i32 rGPR:$s))),
5654              (VTI.Vec (Inst       (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2),
5655                                   (i32 rGPR:$s)))>;
5656    def : Pat<(VTI.Vec (pred_int   (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2),
5657                                   (i32 rGPR:$s), (VTI.Pred VCCR:$pred))),
5658              (VTI.Vec (Inst       (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2),
5659                                   (i32 rGPR:$s), ARMVCCThen,
5660                                   (VTI.Pred VCCR:$pred)))>;
5661  }
5662}
5663
5664multiclass MVE_VQDMLAH_qr_types<string iname, bit bit_5, bit bit_12> {
5665  defm s8  : MVE_VQDMLAH_qr_multi<iname, MVE_v16s8, bit_5, bit_12>;
5666  defm s16 : MVE_VQDMLAH_qr_multi<iname, MVE_v8s16, bit_5, bit_12>;
5667  defm s32 : MVE_VQDMLAH_qr_multi<iname, MVE_v4s32, bit_5, bit_12>;
5668}
5669
5670defm MVE_VQDMLAH_qr   : MVE_VQDMLAH_qr_types<"vqdmlah",   0b1, 0b0>;
5671defm MVE_VQRDMLAH_qr  : MVE_VQDMLAH_qr_types<"vqrdmlah",  0b0, 0b0>;
5672defm MVE_VQDMLASH_qr  : MVE_VQDMLAH_qr_types<"vqdmlash",  0b1, 0b1>;
5673defm MVE_VQRDMLASH_qr : MVE_VQDMLAH_qr_types<"vqrdmlash", 0b0, 0b1>;
5674
5675class MVE_VxDUP<string iname, string suffix, bits<2> size, bit bit_12,
5676              list<dag> pattern=[]>
5677  : MVE_p<(outs MQPR:$Qd, tGPREven:$Rn),
5678          (ins tGPREven:$Rn_src, MVE_VIDUP_imm:$imm), NoItinerary,
5679          iname, suffix, "$Qd, $Rn, $imm", vpred_r, "$Rn = $Rn_src",
5680          pattern> {
5681  bits<4> Qd;
5682  bits<4> Rn;
5683  bits<2> imm;
5684
5685  let Inst{28} = 0b0;
5686  let Inst{25-23} = 0b100;
5687  let Inst{22} = Qd{3};
5688  let Inst{21-20} = size;
5689  let Inst{19-17} = Rn{3-1};
5690  let Inst{16} = 0b1;
5691  let Inst{15-13} = Qd{2-0};
5692  let Inst{12} = bit_12;
5693  let Inst{11-8} = 0b1111;
5694  let Inst{7} = imm{1};
5695  let Inst{6-1} = 0b110111;
5696  let Inst{0} = imm{0};
5697  let validForTailPredication = 1;
5698  let hasSideEffects = 0;
5699}
5700
5701def MVE_VIDUPu8  : MVE_VxDUP<"vidup", "u8",  0b00, 0b0>;
5702def MVE_VIDUPu16 : MVE_VxDUP<"vidup", "u16", 0b01, 0b0>;
5703def MVE_VIDUPu32 : MVE_VxDUP<"vidup", "u32", 0b10, 0b0>;
5704
5705def MVE_VDDUPu8  : MVE_VxDUP<"vddup", "u8",  0b00, 0b1>;
5706def MVE_VDDUPu16 : MVE_VxDUP<"vddup", "u16", 0b01, 0b1>;
5707def MVE_VDDUPu32 : MVE_VxDUP<"vddup", "u32", 0b10, 0b1>;
5708
5709class MVE_VxWDUP<string iname, string suffix, bits<2> size, bit bit_12,
5710                 list<dag> pattern=[]>
5711  : MVE_p<(outs MQPR:$Qd, tGPREven:$Rn),
5712          (ins tGPREven:$Rn_src, tGPROdd:$Rm, MVE_VIDUP_imm:$imm), NoItinerary,
5713          iname, suffix, "$Qd, $Rn, $Rm, $imm", vpred_r, "$Rn = $Rn_src",
5714          pattern> {
5715  bits<4> Qd;
5716  bits<4> Rm;
5717  bits<4> Rn;
5718  bits<2> imm;
5719
5720  let Inst{28} = 0b0;
5721  let Inst{25-23} = 0b100;
5722  let Inst{22} = Qd{3};
5723  let Inst{21-20} = size;
5724  let Inst{19-17} = Rn{3-1};
5725  let Inst{16} = 0b1;
5726  let Inst{15-13} = Qd{2-0};
5727  let Inst{12} = bit_12;
5728  let Inst{11-8} = 0b1111;
5729  let Inst{7} = imm{1};
5730  let Inst{6-4} = 0b110;
5731  let Inst{3-1} = Rm{3-1};
5732  let Inst{0} = imm{0};
5733  let validForTailPredication = 1;
5734  let hasSideEffects = 0;
5735}
5736
5737def MVE_VIWDUPu8  : MVE_VxWDUP<"viwdup", "u8",  0b00, 0b0>;
5738def MVE_VIWDUPu16 : MVE_VxWDUP<"viwdup", "u16", 0b01, 0b0>;
5739def MVE_VIWDUPu32 : MVE_VxWDUP<"viwdup", "u32", 0b10, 0b0>;
5740
5741def MVE_VDWDUPu8  : MVE_VxWDUP<"vdwdup", "u8",  0b00, 0b1>;
5742def MVE_VDWDUPu16 : MVE_VxWDUP<"vdwdup", "u16", 0b01, 0b1>;
5743def MVE_VDWDUPu32 : MVE_VxWDUP<"vdwdup", "u32", 0b10, 0b1>;
5744
5745let isReMaterializable = 1 in
5746class MVE_VCTPInst<string suffix, bits<2> size, list<dag> pattern=[]>
5747  : MVE_p<(outs VCCR:$P0), (ins rGPR:$Rn), NoItinerary, "vctp", suffix,
5748          "$Rn", vpred_n, "", pattern> {
5749  bits<4> Rn;
5750
5751  let Inst{28-27} = 0b10;
5752  let Inst{26-22} = 0b00000;
5753  let Inst{21-20} = size;
5754  let Inst{19-16} = Rn{3-0};
5755  let Inst{15-11} = 0b11101;
5756  let Inst{10-0}  = 0b00000000001;
5757  let Unpredictable{10-0} = 0b11111111111;
5758
5759  let Constraints = "";
5760  let DecoderMethod = "DecodeMveVCTP";
5761  let validForTailPredication = 1;
5762}
5763
5764multiclass MVE_VCTP<MVEVectorVTInfo VTI, Intrinsic intr> {
5765  def "": MVE_VCTPInst<VTI.BitsSuffix, VTI.Size>;
5766  defvar Inst = !cast<Instruction>(NAME);
5767
5768  let Predicates = [HasMVEInt] in {
5769    def : Pat<(intr rGPR:$Rn),
5770              (VTI.Pred (Inst rGPR:$Rn))>;
5771    def : Pat<(and (intr rGPR:$Rn), (VTI.Pred VCCR:$mask)),
5772              (VTI.Pred (Inst rGPR:$Rn, ARMVCCThen, VCCR:$mask))>;
5773  }
5774}
5775
5776defm MVE_VCTP8  : MVE_VCTP<MVE_v16i8, int_arm_mve_vctp8>;
5777defm MVE_VCTP16 : MVE_VCTP<MVE_v8i16, int_arm_mve_vctp16>;
5778defm MVE_VCTP32 : MVE_VCTP<MVE_v4i32, int_arm_mve_vctp32>;
5779defm MVE_VCTP64 : MVE_VCTP<MVE_v2i64, int_arm_mve_vctp64>;
5780
5781// end of mve_qDest_rSrc
5782
5783// start of coproc mov
5784
5785class MVE_VMOV_64bit<dag oops, dag iops, bit to_qreg, string ops, string cstr>
5786  : MVE_VMOV_lane_base<oops, !con(iops, (ins MVEPairVectorIndex2:$idx,
5787                                             MVEPairVectorIndex0:$idx2)),
5788                       NoItinerary, "vmov", "", ops, cstr, []> {
5789  bits<5> Rt;
5790  bits<5> Rt2;
5791  bits<4> Qd;
5792  bit idx;
5793  bit idx2;
5794
5795  let Inst{31-23} = 0b111011000;
5796  let Inst{22} = Qd{3};
5797  let Inst{21} = 0b0;
5798  let Inst{20} = to_qreg;
5799  let Inst{19-16} = Rt2{3-0};
5800  let Inst{15-13} = Qd{2-0};
5801  let Inst{12-5} = 0b01111000;
5802  let Inst{4} = idx2;
5803  let Inst{3-0} = Rt{3-0};
5804
5805  let hasSideEffects = 0;
5806}
5807
5808// The assembly syntax for these instructions mentions the vector
5809// register name twice, e.g.
5810//
5811//    vmov q2[2], q2[0], r0, r1
5812//    vmov r0, r1, q2[2], q2[0]
5813//
5814// which needs a bit of juggling with MC operand handling.
5815//
5816// For the move _into_ a vector register, the MC operand list also has
5817// to mention the register name twice: once as the output, and once as
5818// an extra input to represent where the unchanged half of the output
5819// register comes from (when this instruction is used in code
5820// generation). So we arrange that the first mention of the vector reg
5821// in the instruction is considered by the AsmMatcher to be the output
5822// ($Qd), and the second one is the input ($QdSrc). Binding them
5823// together with the existing 'tie' constraint is enough to enforce at
5824// register allocation time that they have to be the same register.
5825//
5826// For the move _from_ a vector register, there's no way to get round
5827// the fact that both instances of that register name have to be
5828// inputs. They have to be the same register again, but this time, we
5829// can't use a tie constraint, because that has to be between an
5830// output and an input operand. So this time, we have to arrange that
5831// the q-reg appears just once in the MC operand list, in spite of
5832// being mentioned twice in the asm syntax - which needs a custom
5833// AsmMatchConverter.
5834
5835def MVE_VMOV_q_rr : MVE_VMOV_64bit<(outs MQPR:$Qd),
5836                                   (ins MQPR:$QdSrc, rGPR:$Rt, rGPR:$Rt2),
5837                                   0b1, "$Qd$idx, $QdSrc$idx2, $Rt, $Rt2",
5838                                   "$Qd = $QdSrc"> {
5839  let DecoderMethod = "DecodeMVEVMOVDRegtoQ";
5840}
5841
5842def MVE_VMOV_rr_q : MVE_VMOV_64bit<(outs rGPR:$Rt, rGPR:$Rt2), (ins MQPR:$Qd),
5843                                   0b0, "$Rt, $Rt2, $Qd$idx, $Qd$idx2", ""> {
5844  let DecoderMethod = "DecodeMVEVMOVQtoDReg";
5845  let AsmMatchConverter = "cvtMVEVMOVQtoDReg";
5846}
5847
5848let Predicates = [HasMVEInt] in {
5849  // Double lane moves. There are a number of patterns here. We know that the
5850  // insertelt's will be in descending order by index, and need to match the 5
5851  // patterns that might contain 2-0 or 3-1 pairs. These are:
5852  // 3 2 1 0    -> vmovqrr 31; vmovqrr 20
5853  // 3 2 1      -> vmovqrr 31; vmov 2
5854  // 3 1        -> vmovqrr 31
5855  // 2 1 0      -> vmovqrr 20; vmov 1
5856  // 2 0        -> vmovqrr 20
5857  // The other potential patterns will be handled by single lane inserts.
5858  def : Pat<(insertelt (insertelt (insertelt (insertelt (v4i32 MQPR:$src1),
5859                                                        rGPR:$srcA, (i32 0)),
5860                                             rGPR:$srcB, (i32 1)),
5861                                  rGPR:$srcC, (i32 2)),
5862                       rGPR:$srcD, (i32 3)),
5863            (MVE_VMOV_q_rr (MVE_VMOV_q_rr MQPR:$src1, rGPR:$srcA, rGPR:$srcC, (i32 2), (i32 0)),
5864                           rGPR:$srcB, rGPR:$srcD, (i32 3), (i32 1))>;
5865  def : Pat<(insertelt (insertelt (insertelt (v4i32 MQPR:$src1),
5866                                             rGPR:$srcB, (i32 1)),
5867                                  rGPR:$srcC, (i32 2)),
5868                       rGPR:$srcD, (i32 3)),
5869            (MVE_VMOV_q_rr (MVE_VMOV_to_lane_32 MQPR:$src1, rGPR:$srcC, (i32 2)),
5870                           rGPR:$srcB, rGPR:$srcD, (i32 3), (i32 1))>;
5871  def : Pat<(insertelt (insertelt (v4i32 MQPR:$src1), rGPR:$srcA, (i32 1)), rGPR:$srcB, (i32 3)),
5872            (MVE_VMOV_q_rr MQPR:$src1, rGPR:$srcA, rGPR:$srcB, (i32 3), (i32 1))>;
5873  def : Pat<(insertelt (insertelt (insertelt (v4i32 MQPR:$src1),
5874                                             rGPR:$srcB, (i32 0)),
5875                                  rGPR:$srcC, (i32 1)),
5876                       rGPR:$srcD, (i32 2)),
5877            (MVE_VMOV_q_rr (MVE_VMOV_to_lane_32 MQPR:$src1, rGPR:$srcC, (i32 1)),
5878                           rGPR:$srcB, rGPR:$srcD, (i32 2), (i32 0))>;
5879  def : Pat<(insertelt (insertelt (v4i32 MQPR:$src1), rGPR:$srcA, (i32 0)), rGPR:$srcB, (i32 2)),
5880            (MVE_VMOV_q_rr MQPR:$src1, rGPR:$srcA, rGPR:$srcB, (i32 2), (i32 0))>;
5881}
5882
5883// end of coproc mov
5884
5885// start of MVE interleaving load/store
5886
5887// Base class for the family of interleaving/deinterleaving
5888// load/stores with names like VLD20.8 and VST43.32.
5889class MVE_vldst24_base<bit writeback, bit fourregs, bits<2> stage, bits<2> size,
5890                       bit load, dag Oops, dag loadIops, dag wbIops,
5891                       string iname, string ops,
5892                       string cstr, list<dag> pattern=[]>
5893  : MVE_MI<Oops, !con(loadIops, wbIops), NoItinerary, iname, ops, cstr, pattern> {
5894  bits<4> VQd;
5895  bits<4> Rn;
5896
5897  let Inst{31-22} = 0b1111110010;
5898  let Inst{21} = writeback;
5899  let Inst{20} = load;
5900  let Inst{19-16} = Rn;
5901  let Inst{15-13} = VQd{2-0};
5902  let Inst{12-9} = 0b1111;
5903  let Inst{8-7} = size;
5904  let Inst{6-5} = stage;
5905  let Inst{4-1} = 0b0000;
5906  let Inst{0} = fourregs;
5907
5908  let mayLoad = load;
5909  let mayStore = !eq(load,0);
5910  let hasSideEffects = 0;
5911  let validForTailPredication = load;
5912}
5913
5914// A parameter class used to encapsulate all the ways the writeback
5915// variants of VLD20 and friends differ from the non-writeback ones.
5916class MVE_vldst24_writeback<bit b, dag Oo, dag Io,
5917                            string sy="", string c="", string n=""> {
5918  bit writeback = b;
5919  dag Oops = Oo;
5920  dag Iops = Io;
5921  string syntax = sy;
5922  string cstr = c;
5923  string id_suffix = n;
5924}
5925
5926// Another parameter class that encapsulates the differences between VLD2x
5927// and VLD4x.
5928class MVE_vldst24_nvecs<int n, list<int> s, bit b, RegisterOperand vl> {
5929  int nvecs = n;
5930  list<int> stages = s;
5931  bit bit0 = b;
5932  RegisterOperand VecList = vl;
5933}
5934
5935// A third parameter class that distinguishes VLDnn.8 from .16 from .32.
5936class MVE_vldst24_lanesize<int i, bits<2> b> {
5937  int lanesize = i;
5938  bits<2> sizebits = b;
5939}
5940
5941// A base class for each direction of transfer: one for load, one for
5942// store. I can't make these a fourth independent parametric tuple
5943// class, because they have to take the nvecs tuple class as a
5944// parameter, in order to find the right VecList operand type.
5945
5946class MVE_vld24_base<MVE_vldst24_nvecs n, bits<2> pat, bits<2> size,
5947                     MVE_vldst24_writeback wb, string iname,
5948                     list<dag> pattern=[]>
5949  : MVE_vldst24_base<wb.writeback, n.bit0, pat, size, 1,
5950                     !con((outs n.VecList:$VQd), wb.Oops),
5951                     (ins n.VecList:$VQdSrc), wb.Iops,
5952                     iname, "$VQd, $Rn" # wb.syntax,
5953                     wb.cstr # ",$VQdSrc = $VQd", pattern>;
5954
5955class MVE_vst24_base<MVE_vldst24_nvecs n, bits<2> pat, bits<2> size,
5956                     MVE_vldst24_writeback wb, string iname,
5957                     list<dag> pattern=[]>
5958  : MVE_vldst24_base<wb.writeback, n.bit0, pat, size, 0,
5959                     wb.Oops, (ins n.VecList:$VQd), wb.Iops,
5960                     iname, "$VQd, $Rn" # wb.syntax,
5961                     wb.cstr, pattern>;
5962
5963// Actually define all the interleaving loads and stores, by a series
5964// of nested foreaches over number of vectors (VLD2/VLD4); stage
5965// within one of those series (VLDx0/VLDx1/VLDx2/VLDx3); size of
5966// vector lane; writeback or no writeback.
5967foreach n = [MVE_vldst24_nvecs<2, [0,1],     0, VecList2Q>,
5968             MVE_vldst24_nvecs<4, [0,1,2,3], 1, VecList4Q>] in
5969foreach stage = n.stages in
5970foreach s = [MVE_vldst24_lanesize< 8, 0b00>,
5971             MVE_vldst24_lanesize<16, 0b01>,
5972             MVE_vldst24_lanesize<32, 0b10>] in
5973foreach wb = [MVE_vldst24_writeback<
5974                1, (outs rGPR:$wb), (ins t2_nosp_addr_offset_none:$Rn),
5975                "!", "$Rn.base = $wb", "_wb">,
5976              MVE_vldst24_writeback<0, (outs), (ins t2_addr_offset_none:$Rn)>] in {
5977
5978  // For each case within all of those foreaches, define the actual
5979  // instructions. The def names are made by gluing together pieces
5980  // from all the parameter classes, and will end up being things like
5981  // MVE_VLD20_8 and MVE_VST43_16_wb.
5982
5983  def "MVE_VLD" # n.nvecs # stage # "_" # s.lanesize # wb.id_suffix
5984    : MVE_vld24_base<n, stage, s.sizebits, wb,
5985                     "vld" # n.nvecs # stage # "." # s.lanesize>;
5986
5987  def "MVE_VST" # n.nvecs # stage # "_" # s.lanesize # wb.id_suffix
5988    : MVE_vst24_base<n, stage, s.sizebits, wb,
5989                     "vst" # n.nvecs # stage # "." # s.lanesize>;
5990}
5991
5992def SDTARMVST2    : SDTypeProfile<1, 5, [SDTCisPtrTy<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVec<3>,
5993                                         SDTCisSameAs<3, 4>, SDTCisVT<5, i32>]>;
5994def SDTARMVST4    : SDTypeProfile<1, 7, [SDTCisPtrTy<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVec<3>,
5995                                         SDTCisSameAs<3, 4>, SDTCisSameAs<3, 5>,
5996                                         SDTCisSameAs<3, 6>, SDTCisVT<7, i32>]>;
5997def MVEVST2UPD       : SDNode<"ARMISD::VST2_UPD", SDTARMVST2, [SDNPHasChain]>;
5998def MVEVST4UPD       : SDNode<"ARMISD::VST4_UPD", SDTARMVST4, [SDNPHasChain]>;
5999
6000multiclass MVE_vst24_patterns<int lanesize, ValueType VT> {
6001  foreach stage = [0,1] in
6002    def : Pat<(int_arm_mve_vst2q i32:$addr,
6003                (VT MQPR:$v0), (VT MQPR:$v1), (i32 stage)),
6004              (!cast<Instruction>("MVE_VST2"#stage#"_"#lanesize)
6005                (REG_SEQUENCE QQPR, VT:$v0, qsub_0, VT:$v1, qsub_1),
6006                t2_addr_offset_none:$addr)>;
6007  foreach stage = [0,1] in
6008    def : Pat<(i32 (MVEVST2UPD i32:$addr, (i32 32),
6009                (VT MQPR:$v0), (VT MQPR:$v1), (i32 stage))),
6010              (i32 (!cast<Instruction>("MVE_VST2"#stage#"_"#lanesize#_wb)
6011                (REG_SEQUENCE QQPR, VT:$v0, qsub_0, VT:$v1, qsub_1),
6012                t2_addr_offset_none:$addr))>;
6013
6014  foreach stage = [0,1,2,3] in
6015    def : Pat<(int_arm_mve_vst4q i32:$addr,
6016                (VT MQPR:$v0), (VT MQPR:$v1),
6017                (VT MQPR:$v2), (VT MQPR:$v3), (i32 stage)),
6018              (!cast<Instruction>("MVE_VST4"#stage#"_"#lanesize)
6019                (REG_SEQUENCE QQQQPR, VT:$v0, qsub_0, VT:$v1, qsub_1,
6020                                      VT:$v2, qsub_2, VT:$v3, qsub_3),
6021                t2_addr_offset_none:$addr)>;
6022  foreach stage = [0,1,2,3] in
6023    def : Pat<(i32 (MVEVST4UPD i32:$addr, (i32 64),
6024                (VT MQPR:$v0), (VT MQPR:$v1),
6025                (VT MQPR:$v2), (VT MQPR:$v3), (i32 stage))),
6026              (i32 (!cast<Instruction>("MVE_VST4"#stage#"_"#lanesize#_wb)
6027                (REG_SEQUENCE QQQQPR, VT:$v0, qsub_0, VT:$v1, qsub_1,
6028                                      VT:$v2, qsub_2, VT:$v3, qsub_3),
6029                t2_addr_offset_none:$addr))>;
6030}
6031defm : MVE_vst24_patterns<8, v16i8>;
6032defm : MVE_vst24_patterns<16, v8i16>;
6033defm : MVE_vst24_patterns<32, v4i32>;
6034defm : MVE_vst24_patterns<16, v8f16>;
6035defm : MVE_vst24_patterns<32, v4f32>;
6036
6037// end of MVE interleaving load/store
6038
6039// start of MVE predicable load/store
6040
6041// A parameter class for the direction of transfer.
6042class MVE_ldst_direction<bit b, dag Oo, dag Io, string c=""> {
6043  bit load = b;
6044  dag Oops = Oo;
6045  dag Iops = Io;
6046  string cstr = c;
6047}
6048def MVE_ld: MVE_ldst_direction<1, (outs MQPR:$Qd), (ins), ",@earlyclobber $Qd">;
6049def MVE_st: MVE_ldst_direction<0, (outs), (ins MQPR:$Qd)>;
6050
6051// A parameter class for the size of memory access in a load.
6052class MVE_memsz<bits<2> e, int s, AddrMode m, string mn, list<string> types> {
6053  bits<2> encoding = e;         // opcode bit(s) for encoding
6054  int shift = s;                // shift applied to immediate load offset
6055  AddrMode AM = m;
6056
6057  // For instruction aliases: define the complete list of type
6058  // suffixes at this size, and the canonical ones for loads and
6059  // stores.
6060  string MnemonicLetter = mn;
6061  int TypeBits = !shl(8, s);
6062  string CanonLoadSuffix = ".u" # TypeBits;
6063  string CanonStoreSuffix = "." # TypeBits;
6064  list<string> suffixes = !foreach(letter, types, "." # letter # TypeBits);
6065}
6066
6067// Instances of MVE_memsz.
6068//
6069// (memD doesn't need an AddrMode, because those are only for
6070// contiguous loads, and memD is only used by gather/scatters.)
6071def MVE_memB: MVE_memsz<0b00, 0, AddrModeT2_i7,   "b", ["", "u", "s"]>;
6072def MVE_memH: MVE_memsz<0b01, 1, AddrModeT2_i7s2, "h", ["", "u", "s", "f"]>;
6073def MVE_memW: MVE_memsz<0b10, 2, AddrModeT2_i7s4, "w", ["", "u", "s", "f"]>;
6074def MVE_memD: MVE_memsz<0b11, 3, ?,               "d", ["", "u", "s", "f"]>;
6075
6076// This is the base class for all the MVE loads and stores other than
6077// the interleaving ones. All the non-interleaving loads/stores share
6078// the characteristic that they operate on just one vector register,
6079// so they are VPT-predicable.
6080//
6081// The predication operand is vpred_n, for both loads and stores. For
6082// store instructions, the reason is obvious: if there is no output
6083// register, there can't be a need for an input parameter giving the
6084// output register's previous value. Load instructions also don't need
6085// that input parameter, because unlike MVE data processing
6086// instructions, predicated loads are defined to set the inactive
6087// lanes of the output register to zero, instead of preserving their
6088// input values.
6089class MVE_VLDRSTR_base<MVE_ldst_direction dir, bit U, bit P, bit W, bit opc,
6090                       dag oops, dag iops, string asm, string suffix,
6091                       string ops, string cstr, list<dag> pattern=[]>
6092 : MVE_p<oops, iops, NoItinerary, asm, suffix, ops, vpred_n, cstr, pattern> {
6093  bits<3> Qd;
6094
6095  let Inst{28} = U;
6096  let Inst{25} = 0b0;
6097  let Inst{24} = P;
6098  let Inst{22} = 0b0;
6099  let Inst{21} = W;
6100  let Inst{20} = dir.load;
6101  let Inst{15-13} = Qd{2-0};
6102  let Inst{12} = opc;
6103  let Inst{11-9} = 0b111;
6104
6105  let mayLoad = dir.load;
6106  let mayStore = !eq(dir.load,0);
6107  let hasSideEffects = 0;
6108  let validForTailPredication = 1;
6109}
6110
6111// Contiguous load and store instructions. These come in two main
6112// categories: same-size loads/stores in which 128 bits of vector
6113// register is transferred to or from 128 bits of memory in the most
6114// obvious way, and widening loads / narrowing stores, in which the
6115// size of memory accessed is less than the size of a vector register,
6116// so the load instructions sign- or zero-extend each memory value
6117// into a wider vector lane, and the store instructions truncate
6118// correspondingly.
6119//
6120// The instruction mnemonics for these two classes look reasonably
6121// similar, but the actual encodings are different enough to need two
6122// separate base classes.
6123
6124// Contiguous, same size
6125class MVE_VLDRSTR_cs<MVE_ldst_direction dir, MVE_memsz memsz, bit P, bit W,
6126                     dag oops, dag iops, string asm, string suffix,
6127                     IndexMode im, string ops, string cstr>
6128  : MVE_VLDRSTR_base<dir, 0, P, W, 1, oops, iops, asm, suffix, ops, cstr> {
6129  bits<12> addr;
6130  let Inst{23} = addr{7};
6131  let Inst{19-16} = addr{11-8};
6132  let Inst{8-7} = memsz.encoding;
6133  let Inst{6-0} = addr{6-0};
6134}
6135
6136// Contiguous, widening/narrowing
6137class MVE_VLDRSTR_cw<MVE_ldst_direction dir, MVE_memsz memsz, bit U,
6138                     bit P, bit W, bits<2> size, dag oops, dag iops,
6139                     string asm, string suffix, IndexMode im,
6140                     string ops, string cstr>
6141  : MVE_VLDRSTR_base<dir, U, P, W, 0, oops, iops, asm, suffix, ops, cstr> {
6142  bits<11> addr;
6143  let Inst{23} = addr{7};
6144  let Inst{19} = memsz.encoding{0}; // enough to tell 16- from 32-bit
6145  let Inst{18-16} = addr{10-8};
6146  let Inst{8-7} = size;
6147  let Inst{6-0} = addr{6-0};
6148
6149  let IM = im;
6150}
6151
6152// Multiclass wrapper on each of the _cw and _cs base classes, to
6153// generate three writeback modes (none, preindex, postindex).
6154
6155multiclass MVE_VLDRSTR_cw_m<MVE_ldst_direction dir, MVE_memsz memsz,
6156                            string asm, string suffix, bit U, bits<2> size> {
6157  let AM = memsz.AM in {
6158    def "" : MVE_VLDRSTR_cw<
6159        dir, memsz, U, 1, 0, size,
6160        dir.Oops, !con(dir.Iops, (ins taddrmode_imm7<memsz.shift>:$addr)),
6161        asm, suffix, IndexModeNone, "$Qd, $addr", "">;
6162
6163    def _pre : MVE_VLDRSTR_cw<
6164        dir, memsz, U, 1, 1, size,
6165        !con((outs tGPR:$wb), dir.Oops),
6166        !con(dir.Iops, (ins taddrmode_imm7<memsz.shift>:$addr)),
6167        asm, suffix, IndexModePre, "$Qd, $addr!", "$addr.base = $wb"> {
6168      let DecoderMethod = "DecodeMVE_MEM_1_pre<"#memsz.shift#">";
6169    }
6170
6171    def _post : MVE_VLDRSTR_cw<
6172        dir, memsz, U, 0, 1, size,
6173        !con((outs tGPR:$wb), dir.Oops),
6174        !con(dir.Iops, (ins t_addr_offset_none:$Rn,
6175                            t2am_imm7_offset<memsz.shift>:$addr)),
6176        asm, suffix, IndexModePost, "$Qd, $Rn$addr", "$Rn.base = $wb"> {
6177      bits<4> Rn;
6178      let Inst{18-16} = Rn{2-0};
6179    }
6180  }
6181}
6182
6183multiclass MVE_VLDRSTR_cs_m<MVE_ldst_direction dir, MVE_memsz memsz,
6184                            string asm, string suffix> {
6185  let AM = memsz.AM in {
6186    def "" : MVE_VLDRSTR_cs<
6187        dir, memsz, 1, 0,
6188        dir.Oops, !con(dir.Iops, (ins t2addrmode_imm7<memsz.shift>:$addr)),
6189        asm, suffix, IndexModeNone, "$Qd, $addr", "">;
6190
6191    def _pre : MVE_VLDRSTR_cs<
6192        dir, memsz, 1, 1,
6193        !con((outs rGPR:$wb), dir.Oops),
6194        !con(dir.Iops, (ins t2addrmode_imm7_pre<memsz.shift>:$addr)),
6195        asm, suffix, IndexModePre, "$Qd, $addr!", "$addr.base = $wb"> {
6196      let DecoderMethod = "DecodeMVE_MEM_2_pre<"#memsz.shift#">";
6197    }
6198
6199    def _post : MVE_VLDRSTR_cs<
6200        dir, memsz, 0, 1,
6201        !con((outs rGPR:$wb), dir.Oops),
6202        // We need an !if here to select the base register class,
6203        // because it's legal to write back to SP in a load of this
6204        // type, but not in a store.
6205        !con(dir.Iops, (ins !if(dir.load, t2_addr_offset_none,
6206                                          t2_nosp_addr_offset_none):$Rn,
6207                            t2am_imm7_offset<memsz.shift>:$addr)),
6208        asm, suffix, IndexModePost, "$Qd, $Rn$addr", "$Rn.base = $wb"> {
6209      bits<4> Rn;
6210      let Inst{19-16} = Rn{3-0};
6211    }
6212  }
6213}
6214
6215// Now actually declare all the contiguous load/stores, via those
6216// multiclasses. The instruction ids coming out of this are the bare
6217// names shown in the defm, with _pre or _post appended for writeback,
6218// e.g. MVE_VLDRBS16, MVE_VSTRB16_pre, MVE_VSTRHU16_post.
6219
6220defm MVE_VLDRBS16: MVE_VLDRSTR_cw_m<MVE_ld, MVE_memB, "vldrb", "s16", 0, 0b01>;
6221defm MVE_VLDRBS32: MVE_VLDRSTR_cw_m<MVE_ld, MVE_memB, "vldrb", "s32", 0, 0b10>;
6222defm MVE_VLDRBU16: MVE_VLDRSTR_cw_m<MVE_ld, MVE_memB, "vldrb", "u16", 1, 0b01>;
6223defm MVE_VLDRBU32: MVE_VLDRSTR_cw_m<MVE_ld, MVE_memB, "vldrb", "u32", 1, 0b10>;
6224defm MVE_VLDRHS32: MVE_VLDRSTR_cw_m<MVE_ld, MVE_memH, "vldrh", "s32", 0, 0b10>;
6225defm MVE_VLDRHU32: MVE_VLDRSTR_cw_m<MVE_ld, MVE_memH, "vldrh", "u32", 1, 0b10>;
6226
6227defm MVE_VLDRBU8:  MVE_VLDRSTR_cs_m<MVE_ld, MVE_memB, "vldrb", "u8">;
6228defm MVE_VLDRHU16: MVE_VLDRSTR_cs_m<MVE_ld, MVE_memH, "vldrh", "u16">;
6229defm MVE_VLDRWU32: MVE_VLDRSTR_cs_m<MVE_ld, MVE_memW, "vldrw", "u32">;
6230
6231defm MVE_VSTRB16:  MVE_VLDRSTR_cw_m<MVE_st, MVE_memB, "vstrb", "16",  0, 0b01>;
6232defm MVE_VSTRB32:  MVE_VLDRSTR_cw_m<MVE_st, MVE_memB, "vstrb", "32",  0, 0b10>;
6233defm MVE_VSTRH32:  MVE_VLDRSTR_cw_m<MVE_st, MVE_memH, "vstrh", "32",  0, 0b10>;
6234
6235defm MVE_VSTRBU8 : MVE_VLDRSTR_cs_m<MVE_st, MVE_memB, "vstrb", "8">;
6236defm MVE_VSTRHU16: MVE_VLDRSTR_cs_m<MVE_st, MVE_memH, "vstrh", "16">;
6237defm MVE_VSTRWU32: MVE_VLDRSTR_cs_m<MVE_st, MVE_memW, "vstrw", "32">;
6238
6239// Gather loads / scatter stores whose address operand is of the form
6240// [Rn,Qm], i.e. a single GPR as the common base address, plus a
6241// vector of offset from it. ('Load/store this sequence of elements of
6242// the same array.')
6243//
6244// Like the contiguous family, these loads and stores can widen the
6245// loaded values / truncate the stored ones, or they can just
6246// load/store the same size of memory and vector lane. But unlike the
6247// contiguous family, there's no particular difference in encoding
6248// between those two cases.
6249//
6250// This family also comes with the option to scale the offset values
6251// in Qm by the size of the loaded memory (i.e. to treat them as array
6252// indices), or not to scale them (to treat them as plain byte offsets
6253// in memory, so that perhaps the loaded values are unaligned). The
6254// scaled instructions' address operand in assembly looks like
6255// [Rn,Qm,UXTW #2] or similar.
6256
6257// Base class.
6258class MVE_VLDRSTR_rq<MVE_ldst_direction dir, MVE_memsz memsz, bit U,
6259                     bits<2> size, bit os, string asm, string suffix, int shift>
6260  : MVE_VLDRSTR_base<dir, U, 0b0, 0b0, 0, dir.Oops,
6261                     !con(dir.Iops, (ins mve_addr_rq_shift<shift>:$addr)),
6262                     asm, suffix, "$Qd, $addr", dir.cstr> {
6263  bits<7> addr;
6264  let Inst{23} = 0b1;
6265  let Inst{19-16} = addr{6-3};
6266  let Inst{8-7} = size;
6267  let Inst{6} = memsz.encoding{1};
6268  let Inst{5} = 0;
6269  let Inst{4} = memsz.encoding{0};
6270  let Inst{3-1} = addr{2-0};
6271  let Inst{0} = os;
6272}
6273
6274// Multiclass that defines the scaled and unscaled versions of an
6275// instruction, when the memory size is wider than a byte. The scaled
6276// version gets the default name like MVE_VLDRBU16_rq; the unscaled /
6277// potentially unaligned version gets a "_u" suffix, e.g.
6278// MVE_VLDRBU16_rq_u.
6279multiclass MVE_VLDRSTR_rq_w<MVE_ldst_direction dir, MVE_memsz memsz,
6280                            string asm, string suffix, bit U, bits<2> size> {
6281  def _u : MVE_VLDRSTR_rq<dir, memsz, U, size, 0, asm, suffix, 0>;
6282  def "" : MVE_VLDRSTR_rq<dir, memsz, U, size, 1, asm, suffix, memsz.shift>;
6283}
6284
6285// Subclass of MVE_VLDRSTR_rq with the same API as that multiclass,
6286// for use when the memory size is one byte, so there's no 'scaled'
6287// version of the instruction at all. (This is encoded as if it were
6288// unscaled, but named in the default way with no _u suffix.)
6289class MVE_VLDRSTR_rq_b<MVE_ldst_direction dir, MVE_memsz memsz,
6290                       string asm, string suffix, bit U, bits<2> size>
6291  : MVE_VLDRSTR_rq<dir, memsz, U, size, 0, asm, suffix, 0>;
6292
6293// Multiclasses wrapping that to add ISel patterns for intrinsics.
6294multiclass MVE_VLDR_rq_w<MVE_memsz memsz, list<MVEVectorVTInfo> VTIs> {
6295  defm "": MVE_VLDRSTR_rq_w<MVE_ld, memsz, "vldr" # memsz.MnemonicLetter,
6296                            VTIs[0].Suffix, VTIs[0].Unsigned, VTIs[0].Size>;
6297  defvar Inst = !cast<Instruction>(NAME);
6298  defvar InstU = !cast<Instruction>(NAME # "_u");
6299
6300  foreach VTI = VTIs in
6301  foreach UnsignedFlag = !if(!eq(VTI.Size, memsz.encoding),
6302                             [0,1], [VTI.Unsigned]) in {
6303    def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, 0, UnsignedFlag)),
6304              (VTI.Vec (InstU GPR:$base, MQPR:$offsets))>;
6305    def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, memsz.shift, UnsignedFlag)),
6306              (VTI.Vec (Inst GPR:$base, MQPR:$offsets))>;
6307    def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, 0, UnsignedFlag, (VTI.Pred VCCR:$pred))),
6308              (VTI.Vec (InstU GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred))>;
6309    def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, memsz.shift, UnsignedFlag, (VTI.Pred VCCR:$pred))),
6310              (VTI.Vec (Inst GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred))>;
6311  }
6312}
6313multiclass MVE_VLDR_rq_b<list<MVEVectorVTInfo> VTIs> {
6314  def "": MVE_VLDRSTR_rq_b<MVE_ld, MVE_memB, "vldrb",
6315                           VTIs[0].Suffix, VTIs[0].Unsigned, VTIs[0].Size>;
6316  defvar Inst = !cast<Instruction>(NAME);
6317
6318  foreach VTI = VTIs in {
6319    def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), 8, 0, VTI.Unsigned)),
6320              (VTI.Vec (Inst GPR:$base, MQPR:$offsets))>;
6321    def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), 8, 0, VTI.Unsigned, (VTI.Pred VCCR:$pred))),
6322              (VTI.Vec (Inst GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred))>;
6323  }
6324}
6325multiclass MVE_VSTR_rq_w<MVE_memsz memsz, list<MVEVectorVTInfo> VTIs> {
6326  defm "": MVE_VLDRSTR_rq_w<MVE_st, memsz, "vstr" # memsz.MnemonicLetter,
6327                            VTIs[0].BitsSuffix, 0, VTIs[0].Size>;
6328  defvar Inst = !cast<Instruction>(NAME);
6329  defvar InstU = !cast<Instruction>(NAME # "_u");
6330
6331  foreach VTI = VTIs in {
6332    def : Pat<(int_arm_mve_vstr_scatter_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, 0),
6333              (InstU MQPR:$data, GPR:$base, MQPR:$offsets)>;
6334    def : Pat<(int_arm_mve_vstr_scatter_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, memsz.shift),
6335              (Inst MQPR:$data, GPR:$base, MQPR:$offsets)>;
6336    def : Pat<(int_arm_mve_vstr_scatter_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, 0, (VTI.Pred VCCR:$pred)),
6337              (InstU MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred)>;
6338    def : Pat<(int_arm_mve_vstr_scatter_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, memsz.shift, (VTI.Pred VCCR:$pred)),
6339              (Inst MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred)>;
6340  }
6341}
6342multiclass MVE_VSTR_rq_b<list<MVEVectorVTInfo> VTIs> {
6343  def "": MVE_VLDRSTR_rq_b<MVE_st, MVE_memB, "vstrb",
6344                           VTIs[0].BitsSuffix, 0, VTIs[0].Size>;
6345  defvar Inst = !cast<Instruction>(NAME);
6346
6347  foreach VTI = VTIs in {
6348    def : Pat<(int_arm_mve_vstr_scatter_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), 8, 0),
6349              (Inst MQPR:$data, GPR:$base, MQPR:$offsets)>;
6350    def : Pat<(int_arm_mve_vstr_scatter_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), 8, 0, (VTI.Pred VCCR:$pred)),
6351              (Inst MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred)>;
6352  }
6353}
6354
6355// Actually define all the loads and stores in this family.
6356
6357defm MVE_VLDRBU8_rq : MVE_VLDR_rq_b<[MVE_v16u8,MVE_v16s8]>;
6358defm MVE_VLDRBU16_rq: MVE_VLDR_rq_b<[MVE_v8u16]>;
6359defm MVE_VLDRBS16_rq: MVE_VLDR_rq_b<[MVE_v8s16]>;
6360defm MVE_VLDRBU32_rq: MVE_VLDR_rq_b<[MVE_v4u32]>;
6361defm MVE_VLDRBS32_rq: MVE_VLDR_rq_b<[MVE_v4s32]>;
6362
6363defm MVE_VLDRHU16_rq: MVE_VLDR_rq_w<MVE_memH, [MVE_v8u16,MVE_v8s16,MVE_v8f16]>;
6364defm MVE_VLDRHU32_rq: MVE_VLDR_rq_w<MVE_memH, [MVE_v4u32]>;
6365defm MVE_VLDRHS32_rq: MVE_VLDR_rq_w<MVE_memH, [MVE_v4s32]>;
6366defm MVE_VLDRWU32_rq: MVE_VLDR_rq_w<MVE_memW, [MVE_v4u32,MVE_v4s32,MVE_v4f32]>;
6367defm MVE_VLDRDU64_rq: MVE_VLDR_rq_w<MVE_memD, [MVE_v2u64,MVE_v2s64]>;
6368
6369defm MVE_VSTRB8_rq  : MVE_VSTR_rq_b<[MVE_v16i8]>;
6370defm MVE_VSTRB16_rq : MVE_VSTR_rq_b<[MVE_v8i16]>;
6371defm MVE_VSTRB32_rq : MVE_VSTR_rq_b<[MVE_v4i32]>;
6372
6373defm MVE_VSTRH16_rq : MVE_VSTR_rq_w<MVE_memH, [MVE_v8i16,MVE_v8f16]>;
6374defm MVE_VSTRH32_rq : MVE_VSTR_rq_w<MVE_memH, [MVE_v4i32]>;
6375defm MVE_VSTRW32_rq : MVE_VSTR_rq_w<MVE_memW, [MVE_v4i32,MVE_v4f32]>;
6376defm MVE_VSTRD64_rq : MVE_VSTR_rq_w<MVE_memD, [MVE_v2i64]>;
6377
6378// Gather loads / scatter stores whose address operand is of the form
6379// [Qm,#imm], i.e. a vector containing a full base address for each
6380// loaded item, plus an immediate offset applied consistently to all
6381// of them. ('Load/store the same field from this vector of pointers
6382// to a structure type.')
6383//
6384// This family requires the vector lane size to be at least 32 bits
6385// (so there's room for an address in each lane at all). It has no
6386// widening/narrowing variants. But it does support preindex
6387// writeback, in which the address vector is updated to hold the
6388// addresses actually loaded from.
6389
6390// Base class.
6391class MVE_VLDRSTR_qi<MVE_ldst_direction dir, MVE_memsz memsz, bit W, dag wbops,
6392                     string asm, string wbAsm, string suffix, string cstr = "">
6393  : MVE_VLDRSTR_base<dir, 1, 1, W, 1, !con(wbops, dir.Oops),
6394                     !con(dir.Iops, (ins mve_addr_q_shift<memsz.shift>:$addr)),
6395                     asm, suffix, "$Qd, $addr" # wbAsm, cstr # dir.cstr> {
6396  bits<11> addr;
6397  let Inst{23} = addr{7};
6398  let Inst{19-17} = addr{10-8};
6399  let Inst{16} = 0;
6400  let Inst{8} = memsz.encoding{0}; // enough to distinguish 32- from 64-bit
6401  let Inst{7} = 0;
6402  let Inst{6-0} = addr{6-0};
6403}
6404
6405// Multiclass that generates the non-writeback and writeback variants.
6406multiclass MVE_VLDRSTR_qi_m<MVE_ldst_direction dir, MVE_memsz memsz,
6407                            string asm, string suffix> {
6408  def ""   : MVE_VLDRSTR_qi<dir, memsz, 0, (outs),          asm, "",  suffix>;
6409  def _pre : MVE_VLDRSTR_qi<dir, memsz, 1, (outs MQPR:$wb), asm, "!", suffix,
6410                            "$addr.base = $wb"> {
6411    let DecoderMethod="DecodeMVE_MEM_3_pre<"#memsz.shift#">";
6412  }
6413}
6414
6415// Multiclasses wrapping that one, adding selection patterns for the
6416// non-writeback loads and all the stores. (The writeback loads must
6417// deliver multiple output values, so they have to be selected by C++
6418// code.)
6419multiclass MVE_VLDR_qi<MVE_memsz memsz, MVEVectorVTInfo AVTI,
6420                       list<MVEVectorVTInfo> DVTIs> {
6421  defm "" : MVE_VLDRSTR_qi_m<MVE_ld, memsz, "vldr" # memsz.MnemonicLetter,
6422                             "u" # memsz.TypeBits>;
6423  defvar Inst = !cast<Instruction>(NAME);
6424
6425  foreach DVTI = DVTIs in {
6426    def : Pat<(DVTI.Vec (int_arm_mve_vldr_gather_base
6427                 (AVTI.Vec MQPR:$addr), (i32 imm:$offset))),
6428              (DVTI.Vec (Inst (AVTI.Vec MQPR:$addr), (i32 imm:$offset)))>;
6429    def : Pat<(DVTI.Vec (int_arm_mve_vldr_gather_base_predicated
6430                 (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (AVTI.Pred VCCR:$pred))),
6431              (DVTI.Vec (Inst (AVTI.Vec MQPR:$addr), (i32 imm:$offset),
6432                        ARMVCCThen, VCCR:$pred))>;
6433  }
6434}
6435multiclass MVE_VSTR_qi<MVE_memsz memsz, MVEVectorVTInfo AVTI,
6436                       list<MVEVectorVTInfo> DVTIs> {
6437  defm "" : MVE_VLDRSTR_qi_m<MVE_st, memsz, "vstr" # memsz.MnemonicLetter,
6438                             !cast<string>(memsz.TypeBits)>;
6439  defvar Inst = !cast<Instruction>(NAME);
6440  defvar InstPre = !cast<Instruction>(NAME # "_pre");
6441
6442  foreach DVTI = DVTIs in {
6443    def : Pat<(int_arm_mve_vstr_scatter_base
6444                (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data)),
6445              (Inst (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr),
6446                    (i32 imm:$offset))>;
6447    def : Pat<(int_arm_mve_vstr_scatter_base_predicated
6448                (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data), (AVTI.Pred VCCR:$pred)),
6449              (Inst (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr),
6450                    (i32 imm:$offset), ARMVCCThen, VCCR:$pred)>;
6451    def : Pat<(AVTI.Vec (int_arm_mve_vstr_scatter_base_wb
6452                (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data))),
6453              (AVTI.Vec (InstPre (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr),
6454                                 (i32 imm:$offset)))>;
6455    def : Pat<(AVTI.Vec (int_arm_mve_vstr_scatter_base_wb_predicated
6456                (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data), (AVTI.Pred VCCR:$pred))),
6457              (AVTI.Vec (InstPre (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr),
6458                                 (i32 imm:$offset), ARMVCCThen, VCCR:$pred))>;
6459  }
6460}
6461
6462// Actual instruction definitions.
6463defm MVE_VLDRWU32_qi: MVE_VLDR_qi<MVE_memW, MVE_v4i32, [MVE_v4i32,MVE_v4f32]>;
6464defm MVE_VLDRDU64_qi: MVE_VLDR_qi<MVE_memD, MVE_v2i64, [MVE_v2i64,MVE_v2f64]>;
6465defm MVE_VSTRW32_qi:  MVE_VSTR_qi<MVE_memW, MVE_v4i32, [MVE_v4i32,MVE_v4f32]>;
6466defm MVE_VSTRD64_qi:  MVE_VSTR_qi<MVE_memD, MVE_v2i64, [MVE_v2i64,MVE_v2f64]>;
6467
6468// Define aliases for all the instructions where memory size and
6469// vector lane size are the same. These are mnemonic aliases, so they
6470// apply consistently across all of the above families - contiguous
6471// loads, and both the rq and qi types of gather/scatter.
6472//
6473// Rationale: As long as you're loading (for example) 16-bit memory
6474// values into 16-bit vector lanes, you can think of them as signed or
6475// unsigned integers, fp16 or just raw 16-bit blobs and it makes no
6476// difference. So we permit all of vldrh.16, vldrh.u16, vldrh.s16,
6477// vldrh.f16 and treat them all as equivalent to the canonical
6478// spelling (which happens to be .u16 for loads, and just .16 for
6479// stores).
6480
6481foreach vpt_cond = ["", "t", "e"] in
6482foreach memsz = [MVE_memB, MVE_memH, MVE_memW, MVE_memD] in
6483foreach suffix = memsz.suffixes in {
6484  // Define an alias with every suffix in the list, except for the one
6485  // used by the real Instruction record (i.e. the one that all the
6486  // rest are aliases *for*).
6487
6488  if !ne(suffix, memsz.CanonLoadSuffix) then {
6489    def : MnemonicAlias<
6490      "vldr" # memsz.MnemonicLetter # vpt_cond # suffix,
6491      "vldr" # memsz.MnemonicLetter # vpt_cond # memsz.CanonLoadSuffix>;
6492  }
6493
6494  if !ne(suffix, memsz.CanonStoreSuffix) then {
6495    def : MnemonicAlias<
6496      "vstr" # memsz.MnemonicLetter # vpt_cond # suffix,
6497      "vstr" # memsz.MnemonicLetter # vpt_cond # memsz.CanonStoreSuffix>;
6498  }
6499}
6500
6501// end of MVE predicable load/store
6502
6503class MVE_VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> pattern=[]>
6504  : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
6505  bits<3> fc;
6506  bits<4> Mk;
6507  bits<3> Qn;
6508
6509  let Inst{31-23} = 0b111111100;
6510  let Inst{22} = Mk{3};
6511  let Inst{21-20} = size;
6512  let Inst{19-17} = Qn{2-0};
6513  let Inst{16} = 0b1;
6514  let Inst{15-13} = Mk{2-0};
6515  let Inst{12} = fc{2};
6516  let Inst{11-8} = 0b1111;
6517  let Inst{7} = fc{0};
6518  let Inst{4} = 0b0;
6519
6520  let Defs = [VPR];
6521  let validForTailPredication=1;
6522}
6523
6524class MVE_VPTt1<string suffix, bits<2> size, dag iops>
6525  : MVE_VPT<suffix, size, iops, "$fc, $Qn, $Qm"> {
6526  bits<4> Qm;
6527  bits<4> Mk;
6528
6529  let Inst{6} = 0b0;
6530  let Inst{5} = Qm{3};
6531  let Inst{3-1} = Qm{2-0};
6532  let Inst{0} = fc{1};
6533}
6534
6535class MVE_VPTt1i<string suffix, bits<2> size>
6536 : MVE_VPTt1<suffix, size,
6537           (ins vpt_mask:$Mk, MQPR:$Qn, MQPR:$Qm, pred_basic_i:$fc)> {
6538  let Inst{12} = 0b0;
6539  let Inst{0} = 0b0;
6540}
6541
6542def MVE_VPTv4i32 : MVE_VPTt1i<"i32", 0b10>;
6543def MVE_VPTv8i16 : MVE_VPTt1i<"i16", 0b01>;
6544def MVE_VPTv16i8 : MVE_VPTt1i<"i8", 0b00>;
6545
6546class MVE_VPTt1u<string suffix, bits<2> size>
6547 : MVE_VPTt1<suffix, size,
6548           (ins vpt_mask:$Mk, MQPR:$Qn, MQPR:$Qm, pred_basic_u:$fc)> {
6549  let Inst{12} = 0b0;
6550  let Inst{0} = 0b1;
6551}
6552
6553def MVE_VPTv4u32 : MVE_VPTt1u<"u32", 0b10>;
6554def MVE_VPTv8u16 : MVE_VPTt1u<"u16", 0b01>;
6555def MVE_VPTv16u8 : MVE_VPTt1u<"u8", 0b00>;
6556
6557class MVE_VPTt1s<string suffix, bits<2> size>
6558 : MVE_VPTt1<suffix, size,
6559           (ins vpt_mask:$Mk, MQPR:$Qn, MQPR:$Qm, pred_basic_s:$fc)> {
6560  let Inst{12} = 0b1;
6561}
6562
6563def MVE_VPTv4s32 : MVE_VPTt1s<"s32", 0b10>;
6564def MVE_VPTv8s16 : MVE_VPTt1s<"s16", 0b01>;
6565def MVE_VPTv16s8 : MVE_VPTt1s<"s8", 0b00>;
6566
6567class MVE_VPTt2<string suffix, bits<2> size, dag iops>
6568  : MVE_VPT<suffix, size, iops,
6569          "$fc, $Qn, $Rm"> {
6570  bits<4> Rm;
6571  bits<3> fc;
6572  bits<4> Mk;
6573
6574  let Inst{6} = 0b1;
6575  let Inst{5} = fc{1};
6576  let Inst{3-0} = Rm{3-0};
6577}
6578
6579class MVE_VPTt2i<string suffix, bits<2> size>
6580  : MVE_VPTt2<suffix, size,
6581            (ins vpt_mask:$Mk, MQPR:$Qn, GPRwithZR:$Rm, pred_basic_i:$fc)> {
6582  let Inst{12} = 0b0;
6583  let Inst{5} = 0b0;
6584}
6585
6586def MVE_VPTv4i32r : MVE_VPTt2i<"i32", 0b10>;
6587def MVE_VPTv8i16r : MVE_VPTt2i<"i16", 0b01>;
6588def MVE_VPTv16i8r : MVE_VPTt2i<"i8", 0b00>;
6589
6590class MVE_VPTt2u<string suffix, bits<2> size>
6591  : MVE_VPTt2<suffix, size,
6592            (ins vpt_mask:$Mk, MQPR:$Qn, GPRwithZR:$Rm, pred_basic_u:$fc)> {
6593  let Inst{12} = 0b0;
6594  let Inst{5} = 0b1;
6595}
6596
6597def MVE_VPTv4u32r : MVE_VPTt2u<"u32", 0b10>;
6598def MVE_VPTv8u16r : MVE_VPTt2u<"u16", 0b01>;
6599def MVE_VPTv16u8r : MVE_VPTt2u<"u8", 0b00>;
6600
6601class MVE_VPTt2s<string suffix, bits<2> size>
6602  : MVE_VPTt2<suffix, size,
6603            (ins vpt_mask:$Mk, MQPR:$Qn, GPRwithZR:$Rm, pred_basic_s:$fc)> {
6604  let Inst{12} = 0b1;
6605}
6606
6607def MVE_VPTv4s32r : MVE_VPTt2s<"s32", 0b10>;
6608def MVE_VPTv8s16r : MVE_VPTt2s<"s16", 0b01>;
6609def MVE_VPTv16s8r : MVE_VPTt2s<"s8", 0b00>;
6610
6611
6612class MVE_VPTf<string suffix, bit size, dag iops, string asm, list<dag> pattern=[]>
6613  : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm,
6614            "", pattern> {
6615  bits<3> fc;
6616  bits<4> Mk;
6617  bits<3> Qn;
6618
6619  let Inst{31-29} = 0b111;
6620  let Inst{28} = size;
6621  let Inst{27-23} = 0b11100;
6622  let Inst{22} = Mk{3};
6623  let Inst{21-20} = 0b11;
6624  let Inst{19-17} = Qn{2-0};
6625  let Inst{16} = 0b1;
6626  let Inst{15-13} = Mk{2-0};
6627  let Inst{12} = fc{2};
6628  let Inst{11-8} = 0b1111;
6629  let Inst{7} = fc{0};
6630  let Inst{4} = 0b0;
6631
6632  let Defs = [VPR];
6633  let Predicates = [HasMVEFloat];
6634  let validForTailPredication=1;
6635}
6636
6637class MVE_VPTft1<string suffix, bit size>
6638  : MVE_VPTf<suffix, size, (ins vpt_mask:$Mk, MQPR:$Qn, MQPR:$Qm, pred_basic_fp:$fc),
6639          "$fc, $Qn, $Qm"> {
6640  bits<3> fc;
6641  bits<4> Qm;
6642
6643  let Inst{6} = 0b0;
6644  let Inst{5} = Qm{3};
6645  let Inst{3-1} = Qm{2-0};
6646  let Inst{0} = fc{1};
6647}
6648
6649def MVE_VPTv4f32         : MVE_VPTft1<"f32", 0b0>;
6650def MVE_VPTv8f16         : MVE_VPTft1<"f16", 0b1>;
6651
6652class MVE_VPTft2<string suffix, bit size>
6653  : MVE_VPTf<suffix, size, (ins vpt_mask:$Mk, MQPR:$Qn, GPRwithZR:$Rm, pred_basic_fp:$fc),
6654          "$fc, $Qn, $Rm"> {
6655  bits<3> fc;
6656  bits<4> Rm;
6657
6658  let Inst{6} = 0b1;
6659  let Inst{5} = fc{1};
6660  let Inst{3-0} = Rm{3-0};
6661}
6662
6663def MVE_VPTv4f32r        : MVE_VPTft2<"f32", 0b0>;
6664def MVE_VPTv8f16r        : MVE_VPTft2<"f16", 0b1>;
6665
6666def MVE_VPST : MVE_MI<(outs ), (ins vpt_mask:$Mk), NoItinerary,
6667       !strconcat("vpst", "${Mk}"), "", "", []> {
6668  bits<4> Mk;
6669
6670  let Inst{31-23} = 0b111111100;
6671  let Inst{22} = Mk{3};
6672  let Inst{21-16} = 0b110001;
6673  let Inst{15-13} = Mk{2-0};
6674  let Inst{12-0} = 0b0111101001101;
6675  let Unpredictable{12} = 0b1;
6676  let Unpredictable{7} = 0b1;
6677  let Unpredictable{5} = 0b1;
6678
6679  let Uses = [VPR];
6680  let validForTailPredication = 1;
6681}
6682
6683def MVE_VPSEL : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), NoItinerary,
6684                      "vpsel", "", "$Qd, $Qn, $Qm", vpred_n, "", []> {
6685  bits<4> Qn;
6686  bits<4> Qd;
6687  bits<4> Qm;
6688
6689  let Inst{28} = 0b1;
6690  let Inst{25-23} = 0b100;
6691  let Inst{22} = Qd{3};
6692  let Inst{21-20} = 0b11;
6693  let Inst{19-17} = Qn{2-0};
6694  let Inst{16} = 0b1;
6695  let Inst{15-13} = Qd{2-0};
6696  let Inst{12-9} = 0b0111;
6697  let Inst{8} = 0b1;
6698  let Inst{7} = Qn{3};
6699  let Inst{6} = 0b0;
6700  let Inst{5} = Qm{3};
6701  let Inst{4} = 0b0;
6702  let Inst{3-1} = Qm{2-0};
6703  let Inst{0} = 0b1;
6704}
6705
6706foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32",
6707                  "i8", "i16", "i32",       "f16", "f32"] in
6708def : MVEInstAlias<"vpsel${vp}." # suffix # "\t$Qd, $Qn, $Qm",
6709                   (MVE_VPSEL MQPR:$Qd, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
6710
6711let Predicates = [HasMVEInt] in {
6712  def : Pat<(v16i8 (vselect (v16i1 VCCR:$pred), (v16i8 MQPR:$v1), (v16i8 MQPR:$v2))),
6713            (v16i8 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred))>;
6714  def : Pat<(v8i16 (vselect (v8i1 VCCR:$pred), (v8i16 MQPR:$v1), (v8i16 MQPR:$v2))),
6715            (v8i16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred))>;
6716  def : Pat<(v4i32 (vselect (v4i1 VCCR:$pred), (v4i32 MQPR:$v1), (v4i32 MQPR:$v2))),
6717            (v4i32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred))>;
6718
6719  def : Pat<(v8f16 (vselect (v8i1 VCCR:$pred), (v8f16 MQPR:$v1), (v8f16 MQPR:$v2))),
6720            (v8f16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred))>;
6721  def : Pat<(v4f32 (vselect (v4i1 VCCR:$pred), (v4f32 MQPR:$v1), (v4f32 MQPR:$v2))),
6722            (v4f32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred))>;
6723
6724  def : Pat<(v16i8 (vselect (v16i8 MQPR:$pred), (v16i8 MQPR:$v1), (v16i8 MQPR:$v2))),
6725            (v16i8 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone,
6726                              (MVE_VCMPi8 (v16i8 MQPR:$pred), (MVE_VMOVimmi8 0), ARMCCne)))>;
6727  def : Pat<(v8i16 (vselect (v8i16 MQPR:$pred), (v8i16 MQPR:$v1), (v8i16 MQPR:$v2))),
6728            (v8i16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone,
6729                              (MVE_VCMPi16 (v8i16 MQPR:$pred), (MVE_VMOVimmi16 0), ARMCCne)))>;
6730  def : Pat<(v4i32 (vselect (v4i32 MQPR:$pred), (v4i32 MQPR:$v1), (v4i32 MQPR:$v2))),
6731            (v4i32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone,
6732                              (MVE_VCMPi32 (v4i32 MQPR:$pred), (MVE_VMOVimmi32 0), ARMCCne)))>;
6733
6734  def : Pat<(v8f16 (vselect (v8i16 MQPR:$pred), (v8f16 MQPR:$v1), (v8f16 MQPR:$v2))),
6735            (v8f16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone,
6736                              (MVE_VCMPi16 (v8i16 MQPR:$pred), (MVE_VMOVimmi16 0), ARMCCne)))>;
6737  def : Pat<(v4f32 (vselect (v4i32 MQPR:$pred), (v4f32 MQPR:$v1), (v4f32 MQPR:$v2))),
6738            (v4f32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone,
6739                              (MVE_VCMPi32 (v4i32 MQPR:$pred), (MVE_VMOVimmi32 0), ARMCCne)))>;
6740
6741  // Pred <-> Int
6742  def : Pat<(v16i8 (zext  (v16i1 VCCR:$pred))),
6743            (v16i8 (MVE_VPSEL (MVE_VMOVimmi8 1), (MVE_VMOVimmi8 0), ARMVCCNone, VCCR:$pred))>;
6744  def : Pat<(v8i16 (zext  (v8i1  VCCR:$pred))),
6745            (v8i16 (MVE_VPSEL (MVE_VMOVimmi16 1), (MVE_VMOVimmi16 0), ARMVCCNone, VCCR:$pred))>;
6746  def : Pat<(v4i32 (zext  (v4i1  VCCR:$pred))),
6747            (v4i32 (MVE_VPSEL (MVE_VMOVimmi32 1), (MVE_VMOVimmi32 0), ARMVCCNone, VCCR:$pred))>;
6748
6749  def : Pat<(v16i8 (sext  (v16i1 VCCR:$pred))),
6750            (v16i8 (MVE_VPSEL (MVE_VMOVimmi8 255), (MVE_VMOVimmi8 0), ARMVCCNone, VCCR:$pred))>;
6751  def : Pat<(v8i16 (sext  (v8i1  VCCR:$pred))),
6752            (v8i16 (MVE_VPSEL (MVE_VMOVimmi8 255), (MVE_VMOVimmi16 0), ARMVCCNone, VCCR:$pred))>;
6753  def : Pat<(v4i32 (sext  (v4i1  VCCR:$pred))),
6754            (v4i32 (MVE_VPSEL (MVE_VMOVimmi8 255), (MVE_VMOVimmi32 0), ARMVCCNone, VCCR:$pred))>;
6755
6756  def : Pat<(v16i8 (anyext  (v16i1 VCCR:$pred))),
6757            (v16i8 (MVE_VPSEL (MVE_VMOVimmi8 1), (MVE_VMOVimmi8 0), ARMVCCNone, VCCR:$pred))>;
6758  def : Pat<(v8i16 (anyext  (v8i1  VCCR:$pred))),
6759            (v8i16 (MVE_VPSEL (MVE_VMOVimmi16 1), (MVE_VMOVimmi16 0), ARMVCCNone, VCCR:$pred))>;
6760  def : Pat<(v4i32 (anyext  (v4i1  VCCR:$pred))),
6761            (v4i32 (MVE_VPSEL (MVE_VMOVimmi32 1), (MVE_VMOVimmi32 0), ARMVCCNone, VCCR:$pred))>;
6762}
6763
6764let Predicates = [HasMVEFloat] in {
6765  // Pred <-> Float
6766  // 112 is 1.0 in float
6767  def : Pat<(v4f32 (uint_to_fp (v4i1 VCCR:$pred))),
6768            (v4f32 (MVE_VPSEL (v4f32 (MVE_VMOVimmf32 112)), (v4f32 (MVE_VMOVimmi32 0)), ARMVCCNone, VCCR:$pred))>;
6769  // 2620 in 1.0 in half
6770  def : Pat<(v8f16 (uint_to_fp (v8i1 VCCR:$pred))),
6771            (v8f16 (MVE_VPSEL (v8f16 (MVE_VMOVimmi16 2620)), (v8f16 (MVE_VMOVimmi16 0)), ARMVCCNone, VCCR:$pred))>;
6772  // 240 is -1.0 in float
6773  def : Pat<(v4f32 (sint_to_fp (v4i1 VCCR:$pred))),
6774            (v4f32 (MVE_VPSEL (v4f32 (MVE_VMOVimmf32 240)), (v4f32 (MVE_VMOVimmi32 0)), ARMVCCNone, VCCR:$pred))>;
6775  // 2748 is -1.0 in half
6776  def : Pat<(v8f16 (sint_to_fp (v8i1 VCCR:$pred))),
6777            (v8f16 (MVE_VPSEL (v8f16 (MVE_VMOVimmi16 2748)), (v8f16 (MVE_VMOVimmi16 0)), ARMVCCNone, VCCR:$pred))>;
6778
6779  def : Pat<(v4i1 (fp_to_uint (v4f32 MQPR:$v1))),
6780            (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, ARMCCne))>;
6781  def : Pat<(v8i1 (fp_to_uint (v8f16 MQPR:$v1))),
6782            (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, ARMCCne))>;
6783  def : Pat<(v4i1 (fp_to_sint (v4f32 MQPR:$v1))),
6784            (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, ARMCCne))>;
6785  def : Pat<(v8i1 (fp_to_sint (v8f16 MQPR:$v1))),
6786            (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, ARMCCne))>;
6787}
6788
6789def MVE_VPNOT : MVE_p<(outs VCCR:$P0), (ins VCCR:$P0_in), NoItinerary,
6790                      "vpnot", "", "", vpred_n, "", []> {
6791  let Inst{31-0} = 0b11111110001100010000111101001101;
6792  let Unpredictable{19-17} = 0b111;
6793  let Unpredictable{12} = 0b1;
6794  let Unpredictable{7} = 0b1;
6795  let Unpredictable{5} = 0b1;
6796
6797  let Constraints = "";
6798  let DecoderMethod = "DecodeMVEVPNOT";
6799}
6800
6801let Predicates = [HasMVEInt] in {
6802  def : Pat<(v4i1 (xor (v4i1 VCCR:$pred), (v4i1 (predicate_cast (i32 65535))))),
6803            (v4i1 (MVE_VPNOT (v4i1 VCCR:$pred)))>;
6804  def : Pat<(v8i1 (xor (v8i1 VCCR:$pred), (v8i1 (predicate_cast (i32 65535))))),
6805            (v8i1 (MVE_VPNOT (v8i1 VCCR:$pred)))>;
6806  def : Pat<(v16i1 (xor (v16i1 VCCR:$pred), (v16i1 (predicate_cast (i32 65535))))),
6807            (v16i1 (MVE_VPNOT (v16i1 VCCR:$pred)))>;
6808}
6809
6810
6811class MVE_loltp_start<dag iops, string asm, string ops, bits<2> size>
6812  : t2LOL<(outs GPRlr:$LR), iops, asm, ops> {
6813  bits<4> Rn;
6814  let Predicates = [HasMVEInt];
6815  let Inst{22} = 0b0;
6816  let Inst{21-20} = size;
6817  let Inst{19-16} = Rn{3-0};
6818  let Inst{12} = 0b0;
6819}
6820
6821class MVE_DLSTP<string asm, bits<2> size>
6822  : MVE_loltp_start<(ins rGPR:$Rn), asm, "$LR, $Rn", size> {
6823  let Inst{13} = 0b1;
6824  let Inst{11-1} = 0b00000000000;
6825  let Unpredictable{10-1} = 0b1111111111;
6826}
6827
6828class MVE_WLSTP<string asm, bits<2> size>
6829  : MVE_loltp_start<(ins rGPR:$Rn, wlslabel_u11:$label),
6830                    asm, "$LR, $Rn, $label", size> {
6831  bits<11> label;
6832  let Inst{13} = 0b0;
6833  let Inst{11} = label{0};
6834  let Inst{10-1} = label{10-1};
6835  let isBranch = 1;
6836  let isTerminator = 1;
6837}
6838
6839def MVE_DLSTP_8  : MVE_DLSTP<"dlstp.8",  0b00>;
6840def MVE_DLSTP_16 : MVE_DLSTP<"dlstp.16", 0b01>;
6841def MVE_DLSTP_32 : MVE_DLSTP<"dlstp.32", 0b10>;
6842def MVE_DLSTP_64 : MVE_DLSTP<"dlstp.64", 0b11>;
6843
6844def MVE_WLSTP_8  : MVE_WLSTP<"wlstp.8",  0b00>;
6845def MVE_WLSTP_16 : MVE_WLSTP<"wlstp.16", 0b01>;
6846def MVE_WLSTP_32 : MVE_WLSTP<"wlstp.32", 0b10>;
6847def MVE_WLSTP_64 : MVE_WLSTP<"wlstp.64", 0b11>;
6848
6849class MVE_loltp_end<dag oops, dag iops, string asm, string ops>
6850  : t2LOL<oops, iops, asm, ops> {
6851  let Predicates = [HasMVEInt];
6852  let Inst{22-21} = 0b00;
6853  let Inst{19-16} = 0b1111;
6854  let Inst{12} = 0b0;
6855}
6856
6857def MVE_LETP : MVE_loltp_end<(outs GPRlr:$LRout),
6858                             (ins GPRlr:$LRin, lelabel_u11:$label),
6859                             "letp", "$LRin, $label"> {
6860  bits<11> label;
6861  let Inst{20} = 0b1;
6862  let Inst{13} = 0b0;
6863  let Inst{11} = label{0};
6864  let Inst{10-1} = label{10-1};
6865  let isBranch = 1;
6866  let isTerminator = 1;
6867}
6868
6869def MVE_LCTP : MVE_loltp_end<(outs), (ins pred:$p), "lctp${p}", ""> {
6870  let Inst{20} = 0b0;
6871  let Inst{13} = 0b1;
6872  let Inst{11-1} = 0b00000000000;
6873  let Unpredictable{21-20} = 0b11;
6874  let Unpredictable{11-1} = 0b11111111111;
6875}
6876
6877
6878//===----------------------------------------------------------------------===//
6879// Patterns
6880//===----------------------------------------------------------------------===//
6881
6882// PatFrags for loads and stores. Often trying to keep semi-consistent names.
6883
6884def aligned32_pre_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
6885                                  (pre_store node:$val, node:$ptr, node:$offset), [{
6886  return cast<StoreSDNode>(N)->getAlignment() >= 4;
6887}]>;
6888def aligned32_post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
6889                                   (post_store node:$val, node:$ptr, node:$offset), [{
6890  return cast<StoreSDNode>(N)->getAlignment() >= 4;
6891}]>;
6892def aligned16_pre_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
6893                                  (pre_store node:$val, node:$ptr, node:$offset), [{
6894  return cast<StoreSDNode>(N)->getAlignment() >= 2;
6895}]>;
6896def aligned16_post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
6897                                   (post_store node:$val, node:$ptr, node:$offset), [{
6898  return cast<StoreSDNode>(N)->getAlignment() >= 2;
6899}]>;
6900
6901
6902def aligned_maskedloadvi8 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
6903                                    (masked_ld node:$ptr, undef, node:$pred, node:$passthru), [{
6904  auto *Ld = cast<MaskedLoadSDNode>(N);
6905  return Ld->getMemoryVT().getScalarType() == MVT::i8;
6906}]>;
6907def aligned_sextmaskedloadvi8 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
6908                                        (aligned_maskedloadvi8 node:$ptr, node:$pred, node:$passthru), [{
6909  return cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
6910}]>;
6911def aligned_zextmaskedloadvi8 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
6912                                        (aligned_maskedloadvi8 node:$ptr, node:$pred, node:$passthru), [{
6913  return cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
6914}]>;
6915def aligned_extmaskedloadvi8 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
6916                                       (aligned_maskedloadvi8 node:$ptr, node:$pred, node:$passthru), [{
6917  auto *Ld = cast<MaskedLoadSDNode>(N);
6918  EVT ScalarVT = Ld->getMemoryVT().getScalarType();
6919  return ScalarVT.isInteger() && Ld->getExtensionType() == ISD::EXTLOAD;
6920}]>;
6921def aligned_maskedloadvi16: PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
6922                                    (masked_ld node:$ptr, undef, node:$pred, node:$passthru), [{
6923  auto *Ld = cast<MaskedLoadSDNode>(N);
6924  EVT ScalarVT = Ld->getMemoryVT().getScalarType();
6925  return (ScalarVT == MVT::i16 || ScalarVT == MVT::f16) && Ld->getAlignment() >= 2;
6926}]>;
6927def aligned_sextmaskedloadvi16 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
6928                                         (aligned_maskedloadvi16 node:$ptr, node:$pred, node:$passthru), [{
6929  return cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
6930}]>;
6931def aligned_zextmaskedloadvi16 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
6932                                         (aligned_maskedloadvi16 node:$ptr, node:$pred, node:$passthru), [{
6933  return cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
6934}]>;
6935def aligned_extmaskedloadvi16 : PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
6936                                        (aligned_maskedloadvi16 node:$ptr, node:$pred, node:$passthru), [{
6937  auto *Ld = cast<MaskedLoadSDNode>(N);
6938  EVT ScalarVT = Ld->getMemoryVT().getScalarType();
6939  return ScalarVT.isInteger() && Ld->getExtensionType() == ISD::EXTLOAD;
6940}]>;
6941def aligned_maskedloadvi32: PatFrag<(ops node:$ptr, node:$pred, node:$passthru),
6942                                    (masked_ld node:$ptr, undef, node:$pred, node:$passthru), [{
6943  auto *Ld = cast<MaskedLoadSDNode>(N);
6944  EVT ScalarVT = Ld->getMemoryVT().getScalarType();
6945  return (ScalarVT == MVT::i32 || ScalarVT == MVT::f32) && Ld->getAlignment() >= 4;
6946}]>;
6947
6948def aligned_maskedstvi8 : PatFrag<(ops node:$val, node:$ptr, node:$pred),
6949                                  (masked_st node:$val, node:$ptr, undef, node:$pred), [{
6950  return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
6951}]>;
6952def aligned_maskedstvi16 : PatFrag<(ops node:$val, node:$ptr, node:$pred),
6953                                   (masked_st node:$val, node:$ptr, undef, node:$pred), [{
6954  auto *St = cast<MaskedStoreSDNode>(N);
6955  EVT ScalarVT = St->getMemoryVT().getScalarType();
6956  return (ScalarVT == MVT::i16 || ScalarVT == MVT::f16) && St->getAlignment() >= 2;
6957}]>;
6958def aligned_maskedstvi32 : PatFrag<(ops node:$val, node:$ptr, node:$pred),
6959                                   (masked_st node:$val, node:$ptr, undef, node:$pred), [{
6960  auto *St = cast<MaskedStoreSDNode>(N);
6961  EVT ScalarVT = St->getMemoryVT().getScalarType();
6962  return (ScalarVT == MVT::i32 || ScalarVT == MVT::f32) && St->getAlignment() >= 4;
6963}]>;
6964
6965def pre_maskedstore : PatFrag<(ops node:$val, node:$base, node:$offset, node:$mask),
6966                              (masked_st node:$val, node:$base, node:$offset, node:$mask), [{
6967  ISD::MemIndexedMode AM = cast<MaskedStoreSDNode>(N)->getAddressingMode();
6968  return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
6969}]>;
6970def post_maskedstore : PatFrag<(ops node:$val, node:$base, node:$offset, node:$mask),
6971                               (masked_st node:$val, node:$base, node:$offset, node:$mask), [{
6972  ISD::MemIndexedMode AM = cast<MaskedStoreSDNode>(N)->getAddressingMode();
6973  return AM == ISD::POST_INC || AM == ISD::POST_DEC;
6974}]>;
6975def aligned_pre_maskedstorevi8 : PatFrag<(ops node:$val, node:$ptr, node:$offset, node:$mask),
6976                                         (pre_maskedstore node:$val, node:$ptr, node:$offset, node:$mask), [{
6977  return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
6978}]>;
6979def aligned_post_maskedstorevi8 : PatFrag<(ops node:$val, node:$ptr, node:$offset, node:$mask),
6980                                          (post_maskedstore node:$val, node:$ptr, node:$offset, node:$mask), [{
6981  return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
6982}]>;
6983def aligned_pre_maskedstorevi16 : PatFrag<(ops node:$val, node:$ptr, node:$offset, node:$mask),
6984                                          (pre_maskedstore node:$val, node:$ptr, node:$offset, node:$mask), [{
6985  auto *St = cast<MaskedStoreSDNode>(N);
6986  EVT ScalarVT = St->getMemoryVT().getScalarType();
6987  return (ScalarVT == MVT::i16 || ScalarVT == MVT::f16) && St->getAlignment() >= 2;
6988}]>;
6989def aligned_post_maskedstorevi16 : PatFrag<(ops node:$val, node:$ptr, node:$offset, node:$mask),
6990                                           (post_maskedstore node:$val, node:$ptr, node:$offset, node:$mask), [{
6991  auto *St = cast<MaskedStoreSDNode>(N);
6992  EVT ScalarVT = St->getMemoryVT().getScalarType();
6993  return (ScalarVT == MVT::i16 || ScalarVT == MVT::f16) && St->getAlignment() >= 2;
6994}]>;
6995def aligned_pre_maskedstorevi32 : PatFrag<(ops node:$val, node:$ptr, node:$offset, node:$mask),
6996                                          (pre_maskedstore node:$val, node:$ptr, node:$offset, node:$mask), [{
6997  auto *St = cast<MaskedStoreSDNode>(N);
6998  EVT ScalarVT = St->getMemoryVT().getScalarType();
6999  return (ScalarVT == MVT::i32 || ScalarVT == MVT::f32) && St->getAlignment() >= 4;
7000}]>;
7001def aligned_post_maskedstorevi32 : PatFrag<(ops node:$val, node:$ptr, node:$offset, node:$mask),
7002                                           (post_maskedstore node:$val, node:$ptr, node:$offset, node:$mask), [{
7003  auto *St = cast<MaskedStoreSDNode>(N);
7004  EVT ScalarVT = St->getMemoryVT().getScalarType();
7005  return (ScalarVT == MVT::i32 || ScalarVT == MVT::f32) && St->getAlignment() >= 4;
7006}]>;
7007
7008
7009// PatFrags for "Aligned" extending / truncating
7010
7011def aligned_extloadvi8  : PatFrag<(ops node:$ptr), (extloadvi8 node:$ptr)>;
7012def aligned_sextloadvi8 : PatFrag<(ops node:$ptr), (sextloadvi8 node:$ptr)>;
7013def aligned_zextloadvi8 : PatFrag<(ops node:$ptr), (zextloadvi8 node:$ptr)>;
7014
7015def aligned_truncstvi8 : PatFrag<(ops node:$val, node:$ptr),
7016                                 (truncstorevi8 node:$val, node:$ptr)>;
7017def aligned_post_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset),
7018                                      (post_truncstvi8 node:$val, node:$base, node:$offset)>;
7019def aligned_pre_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset),
7020                                     (pre_truncstvi8 node:$val, node:$base, node:$offset)>;
7021
7022let MinAlignment = 2 in {
7023  def aligned_extloadvi16  : PatFrag<(ops node:$ptr), (extloadvi16 node:$ptr)>;
7024  def aligned_sextloadvi16 : PatFrag<(ops node:$ptr), (sextloadvi16 node:$ptr)>;
7025  def aligned_zextloadvi16 : PatFrag<(ops node:$ptr), (zextloadvi16 node:$ptr)>;
7026
7027  def aligned_truncstvi16 : PatFrag<(ops node:$val, node:$ptr),
7028                                    (truncstorevi16 node:$val, node:$ptr)>;
7029  def aligned_post_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset),
7030                                         (post_truncstvi16 node:$val, node:$base, node:$offset)>;
7031  def aligned_pre_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset),
7032                                        (pre_truncstvi16 node:$val, node:$base, node:$offset)>;
7033}
7034
7035def truncmaskedst : PatFrag<(ops node:$val, node:$base, node:$pred),
7036                            (masked_st node:$val, node:$base, undef, node:$pred), [{
7037  return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
7038}]>;
7039def aligned_truncmaskedstvi8 : PatFrag<(ops node:$val, node:$base, node:$pred),
7040                                       (truncmaskedst node:$val, node:$base, node:$pred), [{
7041  return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
7042}]>;
7043def aligned_truncmaskedstvi16 : PatFrag<(ops node:$val, node:$base, node:$pred),
7044                                        (truncmaskedst node:$val, node:$base, node:$pred), [{
7045  auto *St = cast<MaskedStoreSDNode>(N);
7046  EVT ScalarVT = St->getMemoryVT().getScalarType();
7047  return (ScalarVT == MVT::i16 || ScalarVT == MVT::f16) && St->getAlignment() >= 2;
7048}]>;
7049def pre_truncmaskedst : PatFrag<(ops node:$val, node:$base, node:$offset, node:$pred),
7050                                (masked_st node:$val, node:$base, node:$offset, node:$pred), [{
7051  ISD::MemIndexedMode AM = cast<MaskedStoreSDNode>(N)->getAddressingMode();
7052  return cast<MaskedStoreSDNode>(N)->isTruncatingStore() && (AM == ISD::PRE_INC || AM == ISD::PRE_DEC);
7053}]>;
7054def aligned_pre_truncmaskedstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset, node:$pred),
7055                                           (pre_truncmaskedst node:$val, node:$base, node:$offset, node:$pred), [{
7056  return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
7057}]>;
7058def aligned_pre_truncmaskedstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset, node:$pred),
7059                                            (pre_truncmaskedst node:$val, node:$base, node:$offset, node:$pred), [{
7060  auto *St = cast<MaskedStoreSDNode>(N);
7061  EVT ScalarVT = St->getMemoryVT().getScalarType();
7062  return (ScalarVT == MVT::i16 || ScalarVT == MVT::f16) && St->getAlignment() >= 2;
7063}]>;
7064def post_truncmaskedst : PatFrag<(ops node:$val, node:$base, node:$offset, node:$postd),
7065                                 (masked_st node:$val, node:$base, node:$offset, node:$postd), [{
7066  ISD::MemIndexedMode AM = cast<MaskedStoreSDNode>(N)->getAddressingMode();
7067  return cast<MaskedStoreSDNode>(N)->isTruncatingStore() && (AM == ISD::POST_INC || AM == ISD::POST_DEC);
7068}]>;
7069def aligned_post_truncmaskedstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset, node:$postd),
7070                                            (post_truncmaskedst node:$val, node:$base, node:$offset, node:$postd), [{
7071  return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
7072}]>;
7073def aligned_post_truncmaskedstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset, node:$postd),
7074                                             (post_truncmaskedst node:$val, node:$base, node:$offset, node:$postd), [{
7075  auto *St = cast<MaskedStoreSDNode>(N);
7076  EVT ScalarVT = St->getMemoryVT().getScalarType();
7077  return (ScalarVT == MVT::i16 || ScalarVT == MVT::f16) && St->getAlignment() >= 2;
7078}]>;
7079
7080// Load/store patterns
7081
7082class MVE_vector_store_typed<ValueType Ty, Instruction RegImmInst,
7083                             PatFrag StoreKind, int shift>
7084  : Pat<(StoreKind (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr),
7085        (RegImmInst (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr)>;
7086
7087class MVE_vector_maskedstore_typed<ValueType Ty, Instruction RegImmInst,
7088                                   PatFrag StoreKind, int shift>
7089  : Pat<(StoreKind (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr, VCCR:$pred),
7090        (RegImmInst (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr, ARMVCCThen, VCCR:$pred)>;
7091
7092multiclass MVE_vector_store<Instruction RegImmInst, PatFrag StoreKind,
7093                            int shift> {
7094  def : MVE_vector_store_typed<v16i8, RegImmInst, StoreKind, shift>;
7095  def : MVE_vector_store_typed<v8i16, RegImmInst, StoreKind, shift>;
7096  def : MVE_vector_store_typed<v8f16, RegImmInst, StoreKind, shift>;
7097  def : MVE_vector_store_typed<v4i32, RegImmInst, StoreKind, shift>;
7098  def : MVE_vector_store_typed<v4f32, RegImmInst, StoreKind, shift>;
7099  def : MVE_vector_store_typed<v2i64, RegImmInst, StoreKind, shift>;
7100  def : MVE_vector_store_typed<v2f64, RegImmInst, StoreKind, shift>;
7101}
7102
7103class MVE_vector_load_typed<ValueType Ty, Instruction RegImmInst,
7104                            PatFrag LoadKind, int shift>
7105  : Pat<(Ty (LoadKind t2addrmode_imm7<shift>:$addr)),
7106        (Ty (RegImmInst t2addrmode_imm7<shift>:$addr))>;
7107
7108class MVE_vector_maskedload_typed<ValueType Ty, Instruction RegImmInst,
7109                                  PatFrag LoadKind, int shift>
7110  : Pat<(Ty (LoadKind t2addrmode_imm7<shift>:$addr, VCCR:$pred, (Ty (ARMvmovImm (i32 0))))),
7111        (Ty (RegImmInst t2addrmode_imm7<shift>:$addr, ARMVCCThen, VCCR:$pred))>;
7112
7113multiclass MVE_vector_load<Instruction RegImmInst, PatFrag LoadKind,
7114                           int shift> {
7115  def : MVE_vector_load_typed<v16i8, RegImmInst, LoadKind, shift>;
7116  def : MVE_vector_load_typed<v8i16, RegImmInst, LoadKind, shift>;
7117  def : MVE_vector_load_typed<v8f16, RegImmInst, LoadKind, shift>;
7118  def : MVE_vector_load_typed<v4i32, RegImmInst, LoadKind, shift>;
7119  def : MVE_vector_load_typed<v4f32, RegImmInst, LoadKind, shift>;
7120  def : MVE_vector_load_typed<v2i64, RegImmInst, LoadKind, shift>;
7121  def : MVE_vector_load_typed<v2f64, RegImmInst, LoadKind, shift>;
7122}
7123
7124class MVE_vector_offset_store_typed<ValueType Ty, Instruction Opcode,
7125                                    PatFrag StoreKind, int shift>
7126  : Pat<(StoreKind (Ty MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<shift>:$addr),
7127        (Opcode MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<shift>:$addr)>;
7128
7129class MVE_vector_offset_maskedstore_typed<ValueType Ty, Instruction Opcode,
7130                                          PatFrag StoreKind, int shift>
7131  : Pat<(StoreKind (Ty MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<shift>:$addr, VCCR:$pred),
7132        (Opcode MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<shift>:$addr, ARMVCCThen, VCCR:$pred)>;
7133
7134multiclass MVE_vector_offset_store<Instruction RegImmInst, PatFrag StoreKind,
7135                                   int shift> {
7136  def : MVE_vector_offset_store_typed<v16i8, RegImmInst, StoreKind, shift>;
7137  def : MVE_vector_offset_store_typed<v8i16, RegImmInst, StoreKind, shift>;
7138  def : MVE_vector_offset_store_typed<v8f16, RegImmInst, StoreKind, shift>;
7139  def : MVE_vector_offset_store_typed<v4i32, RegImmInst, StoreKind, shift>;
7140  def : MVE_vector_offset_store_typed<v4f32, RegImmInst, StoreKind, shift>;
7141  def : MVE_vector_offset_store_typed<v2i64, RegImmInst, StoreKind, shift>;
7142  def : MVE_vector_offset_store_typed<v2f64, RegImmInst, StoreKind, shift>;
7143}
7144
7145
7146let Predicates = [HasMVEInt, IsLE] in {
7147  // Stores
7148  defm : MVE_vector_store<MVE_VSTRBU8, byte_alignedstore, 0>;
7149  defm : MVE_vector_store<MVE_VSTRHU16, hword_alignedstore, 1>;
7150  defm : MVE_vector_store<MVE_VSTRWU32, alignedstore32, 2>;
7151
7152  // Loads
7153  defm : MVE_vector_load<MVE_VLDRBU8, byte_alignedload, 0>;
7154  defm : MVE_vector_load<MVE_VLDRHU16, hword_alignedload, 1>;
7155  defm : MVE_vector_load<MVE_VLDRWU32, alignedload32, 2>;
7156
7157  // Pre/post inc stores
7158  defm : MVE_vector_offset_store<MVE_VSTRBU8_pre, pre_store, 0>;
7159  defm : MVE_vector_offset_store<MVE_VSTRBU8_post, post_store, 0>;
7160  defm : MVE_vector_offset_store<MVE_VSTRHU16_pre, aligned16_pre_store, 1>;
7161  defm : MVE_vector_offset_store<MVE_VSTRHU16_post, aligned16_post_store, 1>;
7162  defm : MVE_vector_offset_store<MVE_VSTRWU32_pre, aligned32_pre_store, 2>;
7163  defm : MVE_vector_offset_store<MVE_VSTRWU32_post, aligned32_post_store, 2>;
7164}
7165
7166let Predicates = [HasMVEInt, IsBE] in {
7167  // Aligned Stores
7168  def : MVE_vector_store_typed<v16i8, MVE_VSTRBU8, store, 0>;
7169  def : MVE_vector_store_typed<v8i16, MVE_VSTRHU16, alignedstore16, 1>;
7170  def : MVE_vector_store_typed<v8f16, MVE_VSTRHU16, alignedstore16, 1>;
7171  def : MVE_vector_store_typed<v4i32, MVE_VSTRWU32, alignedstore32, 2>;
7172  def : MVE_vector_store_typed<v4f32, MVE_VSTRWU32, alignedstore32, 2>;
7173
7174  // Aligned Loads
7175  def : MVE_vector_load_typed<v16i8, MVE_VLDRBU8, load, 0>;
7176  def : MVE_vector_load_typed<v8i16, MVE_VLDRHU16, alignedload16, 1>;
7177  def : MVE_vector_load_typed<v8f16, MVE_VLDRHU16, alignedload16, 1>;
7178  def : MVE_vector_load_typed<v4i32, MVE_VLDRWU32, alignedload32, 2>;
7179  def : MVE_vector_load_typed<v4f32, MVE_VLDRWU32, alignedload32, 2>;
7180
7181  // Other unaligned loads/stores need to go though a VREV
7182  def : Pat<(v2f64 (load t2addrmode_imm7<0>:$addr)),
7183            (v2f64 (MVE_VREV64_8 (MVE_VLDRBU8 t2addrmode_imm7<0>:$addr)))>;
7184  def : Pat<(v2i64 (load t2addrmode_imm7<0>:$addr)),
7185            (v2i64 (MVE_VREV64_8 (MVE_VLDRBU8 t2addrmode_imm7<0>:$addr)))>;
7186  def : Pat<(v4i32 (load t2addrmode_imm7<0>:$addr)),
7187            (v4i32 (MVE_VREV32_8 (MVE_VLDRBU8 t2addrmode_imm7<0>:$addr)))>;
7188  def : Pat<(v4f32 (load t2addrmode_imm7<0>:$addr)),
7189            (v4f32 (MVE_VREV32_8 (MVE_VLDRBU8 t2addrmode_imm7<0>:$addr)))>;
7190  def : Pat<(v8i16 (load t2addrmode_imm7<0>:$addr)),
7191            (v8i16 (MVE_VREV16_8 (MVE_VLDRBU8 t2addrmode_imm7<0>:$addr)))>;
7192  def : Pat<(v8f16 (load t2addrmode_imm7<0>:$addr)),
7193            (v8f16 (MVE_VREV16_8 (MVE_VLDRBU8 t2addrmode_imm7<0>:$addr)))>;
7194  def : Pat<(store (v2f64 MQPR:$val), t2addrmode_imm7<0>:$addr),
7195            (MVE_VSTRBU8 (MVE_VREV64_8 MQPR:$val), t2addrmode_imm7<0>:$addr)>;
7196  def : Pat<(store (v2i64 MQPR:$val), t2addrmode_imm7<0>:$addr),
7197            (MVE_VSTRBU8 (MVE_VREV64_8 MQPR:$val), t2addrmode_imm7<0>:$addr)>;
7198  def : Pat<(store (v4i32 MQPR:$val), t2addrmode_imm7<0>:$addr),
7199            (MVE_VSTRBU8 (MVE_VREV32_8 MQPR:$val), t2addrmode_imm7<0>:$addr)>;
7200  def : Pat<(store (v4f32 MQPR:$val), t2addrmode_imm7<0>:$addr),
7201            (MVE_VSTRBU8 (MVE_VREV32_8 MQPR:$val), t2addrmode_imm7<0>:$addr)>;
7202  def : Pat<(store (v8i16 MQPR:$val), t2addrmode_imm7<0>:$addr),
7203            (MVE_VSTRBU8 (MVE_VREV16_8 MQPR:$val), t2addrmode_imm7<0>:$addr)>;
7204  def : Pat<(store (v8f16 MQPR:$val), t2addrmode_imm7<0>:$addr),
7205            (MVE_VSTRBU8 (MVE_VREV16_8 MQPR:$val), t2addrmode_imm7<0>:$addr)>;
7206
7207  // Pre/Post inc stores
7208  def : MVE_vector_offset_store_typed<v16i8, MVE_VSTRBU8_pre, pre_store, 0>;
7209  def : MVE_vector_offset_store_typed<v16i8, MVE_VSTRBU8_post, post_store, 0>;
7210  def : MVE_vector_offset_store_typed<v8i16, MVE_VSTRHU16_pre, aligned16_pre_store, 1>;
7211  def : MVE_vector_offset_store_typed<v8i16, MVE_VSTRHU16_post, aligned16_post_store, 1>;
7212  def : MVE_vector_offset_store_typed<v8f16, MVE_VSTRHU16_pre, aligned16_pre_store, 1>;
7213  def : MVE_vector_offset_store_typed<v8f16, MVE_VSTRHU16_post, aligned16_post_store, 1>;
7214  def : MVE_vector_offset_store_typed<v4i32, MVE_VSTRWU32_pre, aligned32_pre_store, 2>;
7215  def : MVE_vector_offset_store_typed<v4i32, MVE_VSTRWU32_post, aligned32_post_store, 2>;
7216  def : MVE_vector_offset_store_typed<v4f32, MVE_VSTRWU32_pre, aligned32_pre_store, 2>;
7217  def : MVE_vector_offset_store_typed<v4f32, MVE_VSTRWU32_post, aligned32_post_store, 2>;
7218}
7219
7220let Predicates = [HasMVEInt] in {
7221  // Aligned masked store, shared between LE and BE
7222  def : MVE_vector_maskedstore_typed<v16i8, MVE_VSTRBU8, aligned_maskedstvi8, 0>;
7223  def : MVE_vector_maskedstore_typed<v8i16, MVE_VSTRHU16, aligned_maskedstvi16, 1>;
7224  def : MVE_vector_maskedstore_typed<v8f16, MVE_VSTRHU16, aligned_maskedstvi16, 1>;
7225  def : MVE_vector_maskedstore_typed<v4i32, MVE_VSTRWU32, aligned_maskedstvi32, 2>;
7226  def : MVE_vector_maskedstore_typed<v4f32, MVE_VSTRWU32, aligned_maskedstvi32, 2>;
7227
7228  // Pre/Post inc masked stores
7229  def : MVE_vector_offset_maskedstore_typed<v16i8, MVE_VSTRBU8_pre, aligned_pre_maskedstorevi8, 0>;
7230  def : MVE_vector_offset_maskedstore_typed<v16i8, MVE_VSTRBU8_post, aligned_post_maskedstorevi8, 0>;
7231  def : MVE_vector_offset_maskedstore_typed<v8i16, MVE_VSTRHU16_pre, aligned_pre_maskedstorevi16, 1>;
7232  def : MVE_vector_offset_maskedstore_typed<v8i16, MVE_VSTRHU16_post, aligned_post_maskedstorevi16, 1>;
7233  def : MVE_vector_offset_maskedstore_typed<v8f16, MVE_VSTRHU16_pre, aligned_pre_maskedstorevi16, 1>;
7234  def : MVE_vector_offset_maskedstore_typed<v8f16, MVE_VSTRHU16_post, aligned_post_maskedstorevi16, 1>;
7235  def : MVE_vector_offset_maskedstore_typed<v4i32, MVE_VSTRWU32_pre, aligned_pre_maskedstorevi32, 2>;
7236  def : MVE_vector_offset_maskedstore_typed<v4i32, MVE_VSTRWU32_post, aligned_post_maskedstorevi32, 2>;
7237  def : MVE_vector_offset_maskedstore_typed<v4f32, MVE_VSTRWU32_pre, aligned_pre_maskedstorevi32, 2>;
7238  def : MVE_vector_offset_maskedstore_typed<v4f32, MVE_VSTRWU32_post, aligned_post_maskedstorevi32, 2>;
7239
7240  // Aligned masked loads
7241  def : MVE_vector_maskedload_typed<v16i8, MVE_VLDRBU8, aligned_maskedloadvi8, 0>;
7242  def : MVE_vector_maskedload_typed<v8i16, MVE_VLDRHU16, aligned_maskedloadvi16, 1>;
7243  def : MVE_vector_maskedload_typed<v8f16, MVE_VLDRHU16, aligned_maskedloadvi16, 1>;
7244  def : MVE_vector_maskedload_typed<v4i32, MVE_VLDRWU32, aligned_maskedloadvi32, 2>;
7245  def : MVE_vector_maskedload_typed<v4f32, MVE_VLDRWU32, aligned_maskedloadvi32, 2>;
7246}
7247
7248// Widening/Narrowing Loads/Stores
7249
7250multiclass MVEExtLoadStore<Instruction LoadSInst, Instruction LoadUInst, string StoreInst,
7251                         string Amble, ValueType VT, int Shift> {
7252  // Trunc stores
7253  def : Pat<(!cast<PatFrag>("aligned_truncst"#Amble) (VT MQPR:$val), taddrmode_imm7<Shift>:$addr),
7254            (!cast<Instruction>(StoreInst) MQPR:$val, taddrmode_imm7<Shift>:$addr)>;
7255  def : Pat<(!cast<PatFrag>("aligned_post_truncst"#Amble) (VT MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<Shift>:$addr),
7256            (!cast<Instruction>(StoreInst#"_post") MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<Shift>:$addr)>;
7257  def : Pat<(!cast<PatFrag>("aligned_pre_truncst"#Amble) (VT MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<Shift>:$addr),
7258            (!cast<Instruction>(StoreInst#"_pre") MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<Shift>:$addr)>;
7259
7260  // Masked trunc stores
7261  def : Pat<(!cast<PatFrag>("aligned_truncmaskedst"#Amble) (VT MQPR:$val), taddrmode_imm7<Shift>:$addr, VCCR:$pred),
7262            (!cast<Instruction>(StoreInst) MQPR:$val, taddrmode_imm7<Shift>:$addr, ARMVCCThen, VCCR:$pred)>;
7263  def : Pat<(!cast<PatFrag>("aligned_post_truncmaskedst"#Amble) (VT MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<Shift>:$addr, VCCR:$pred),
7264            (!cast<Instruction>(StoreInst#"_post") MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<Shift>:$addr, ARMVCCThen, VCCR:$pred)>;
7265  def : Pat<(!cast<PatFrag>("aligned_pre_truncmaskedst"#Amble) (VT MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<Shift>:$addr, VCCR:$pred),
7266            (!cast<Instruction>(StoreInst#"_pre") MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<Shift>:$addr, ARMVCCThen, VCCR:$pred)>;
7267
7268  // Ext loads
7269  def : Pat<(VT (!cast<PatFrag>("aligned_extload"#Amble) taddrmode_imm7<Shift>:$addr)),
7270            (VT (LoadUInst taddrmode_imm7<Shift>:$addr))>;
7271  def : Pat<(VT (!cast<PatFrag>("aligned_sextload"#Amble) taddrmode_imm7<Shift>:$addr)),
7272            (VT (LoadSInst taddrmode_imm7<Shift>:$addr))>;
7273  def : Pat<(VT (!cast<PatFrag>("aligned_zextload"#Amble) taddrmode_imm7<Shift>:$addr)),
7274            (VT (LoadUInst taddrmode_imm7<Shift>:$addr))>;
7275
7276  // Masked ext loads
7277  def : Pat<(VT (!cast<PatFrag>("aligned_extmaskedload"#Amble) taddrmode_imm7<Shift>:$addr, VCCR:$pred, (VT (ARMvmovImm (i32 0))))),
7278            (VT (LoadUInst taddrmode_imm7<Shift>:$addr, ARMVCCThen, VCCR:$pred))>;
7279  def : Pat<(VT (!cast<PatFrag>("aligned_sextmaskedload"#Amble) taddrmode_imm7<Shift>:$addr, VCCR:$pred, (VT (ARMvmovImm (i32 0))))),
7280            (VT (LoadSInst taddrmode_imm7<Shift>:$addr, ARMVCCThen, VCCR:$pred))>;
7281  def : Pat<(VT (!cast<PatFrag>("aligned_zextmaskedload"#Amble) taddrmode_imm7<Shift>:$addr, VCCR:$pred, (VT (ARMvmovImm (i32 0))))),
7282            (VT (LoadUInst taddrmode_imm7<Shift>:$addr, ARMVCCThen, VCCR:$pred))>;
7283}
7284
7285let Predicates = [HasMVEInt] in {
7286  defm : MVEExtLoadStore<MVE_VLDRBS16, MVE_VLDRBU16, "MVE_VSTRB16", "vi8", v8i16, 0>;
7287  defm : MVEExtLoadStore<MVE_VLDRBS32, MVE_VLDRBU32, "MVE_VSTRB32", "vi8", v4i32, 0>;
7288  defm : MVEExtLoadStore<MVE_VLDRHS32, MVE_VLDRHU32, "MVE_VSTRH32", "vi16", v4i32, 1>;
7289}
7290
7291
7292// Bit convert patterns
7293
7294let Predicates = [HasMVEInt] in {
7295  def : Pat<(v2f64 (bitconvert (v2i64 MQPR:$src))), (v2f64 MQPR:$src)>;
7296  def : Pat<(v2i64 (bitconvert (v2f64 MQPR:$src))), (v2i64 MQPR:$src)>;
7297
7298  def : Pat<(v4i32 (bitconvert (v4f32 MQPR:$src))), (v4i32 MQPR:$src)>;
7299  def : Pat<(v4f32 (bitconvert (v4i32 MQPR:$src))), (v4f32 MQPR:$src)>;
7300
7301  def : Pat<(v8i16 (bitconvert (v8f16 MQPR:$src))), (v8i16  MQPR:$src)>;
7302  def : Pat<(v8f16 (bitconvert (v8i16 MQPR:$src))), (v8f16  MQPR:$src)>;
7303}
7304
7305let Predicates = [IsLE,HasMVEInt] in {
7306  def : Pat<(v2f64 (bitconvert (v4f32 MQPR:$src))), (v2f64 MQPR:$src)>;
7307  def : Pat<(v2f64 (bitconvert (v4i32 MQPR:$src))), (v2f64 MQPR:$src)>;
7308  def : Pat<(v2f64 (bitconvert (v8f16 MQPR:$src))), (v2f64 MQPR:$src)>;
7309  def : Pat<(v2f64 (bitconvert (v8i16 MQPR:$src))), (v2f64 MQPR:$src)>;
7310  def : Pat<(v2f64 (bitconvert (v16i8 MQPR:$src))), (v2f64 MQPR:$src)>;
7311
7312  def : Pat<(v2i64 (bitconvert (v4f32 MQPR:$src))), (v2i64 MQPR:$src)>;
7313  def : Pat<(v2i64 (bitconvert (v4i32 MQPR:$src))), (v2i64 MQPR:$src)>;
7314  def : Pat<(v2i64 (bitconvert (v8f16 MQPR:$src))), (v2i64 MQPR:$src)>;
7315  def : Pat<(v2i64 (bitconvert (v8i16 MQPR:$src))), (v2i64 MQPR:$src)>;
7316  def : Pat<(v2i64 (bitconvert (v16i8 MQPR:$src))), (v2i64 MQPR:$src)>;
7317
7318  def : Pat<(v4f32 (bitconvert (v2f64 MQPR:$src))), (v4f32 MQPR:$src)>;
7319  def : Pat<(v4f32 (bitconvert (v2i64 MQPR:$src))), (v4f32 MQPR:$src)>;
7320  def : Pat<(v4f32 (bitconvert (v8f16 MQPR:$src))), (v4f32 MQPR:$src)>;
7321  def : Pat<(v4f32 (bitconvert (v8i16 MQPR:$src))), (v4f32 MQPR:$src)>;
7322  def : Pat<(v4f32 (bitconvert (v16i8 MQPR:$src))), (v4f32 MQPR:$src)>;
7323
7324  def : Pat<(v4i32 (bitconvert (v2f64 MQPR:$src))), (v4i32 MQPR:$src)>;
7325  def : Pat<(v4i32 (bitconvert (v2i64 MQPR:$src))), (v4i32 MQPR:$src)>;
7326  def : Pat<(v4i32 (bitconvert (v8f16 MQPR:$src))), (v4i32 MQPR:$src)>;
7327  def : Pat<(v4i32 (bitconvert (v8i16 MQPR:$src))), (v4i32 MQPR:$src)>;
7328  def : Pat<(v4i32 (bitconvert (v16i8 MQPR:$src))), (v4i32 MQPR:$src)>;
7329
7330  def : Pat<(v8f16 (bitconvert (v2f64 MQPR:$src))), (v8f16 MQPR:$src)>;
7331  def : Pat<(v8f16 (bitconvert (v2i64 MQPR:$src))), (v8f16 MQPR:$src)>;
7332  def : Pat<(v8f16 (bitconvert (v4f32 MQPR:$src))), (v8f16 MQPR:$src)>;
7333  def : Pat<(v8f16 (bitconvert (v4i32 MQPR:$src))), (v8f16 MQPR:$src)>;
7334  def : Pat<(v8f16 (bitconvert (v16i8 MQPR:$src))), (v8f16 MQPR:$src)>;
7335
7336  def : Pat<(v8i16 (bitconvert (v2f64 MQPR:$src))), (v8i16 MQPR:$src)>;
7337  def : Pat<(v8i16 (bitconvert (v2i64 MQPR:$src))), (v8i16 MQPR:$src)>;
7338  def : Pat<(v8i16 (bitconvert (v4f32 MQPR:$src))), (v8i16 MQPR:$src)>;
7339  def : Pat<(v8i16 (bitconvert (v4i32 MQPR:$src))), (v8i16 MQPR:$src)>;
7340  def : Pat<(v8i16 (bitconvert (v16i8 MQPR:$src))), (v8i16 MQPR:$src)>;
7341
7342  def : Pat<(v16i8 (bitconvert (v2f64 MQPR:$src))), (v16i8 MQPR:$src)>;
7343  def : Pat<(v16i8 (bitconvert (v2i64 MQPR:$src))), (v16i8 MQPR:$src)>;
7344  def : Pat<(v16i8 (bitconvert (v4f32 MQPR:$src))), (v16i8 MQPR:$src)>;
7345  def : Pat<(v16i8 (bitconvert (v4i32 MQPR:$src))), (v16i8 MQPR:$src)>;
7346  def : Pat<(v16i8 (bitconvert (v8f16 MQPR:$src))), (v16i8 MQPR:$src)>;
7347  def : Pat<(v16i8 (bitconvert (v8i16 MQPR:$src))), (v16i8 MQPR:$src)>;
7348}
7349
7350let Predicates = [IsBE,HasMVEInt] in {
7351  def : Pat<(v2f64 (bitconvert (v4f32 MQPR:$src))), (v2f64 (MVE_VREV64_32 MQPR:$src))>;
7352  def : Pat<(v2f64 (bitconvert (v4i32 MQPR:$src))), (v2f64 (MVE_VREV64_32 MQPR:$src))>;
7353  def : Pat<(v2f64 (bitconvert (v8f16 MQPR:$src))), (v2f64 (MVE_VREV64_16 MQPR:$src))>;
7354  def : Pat<(v2f64 (bitconvert (v8i16 MQPR:$src))), (v2f64 (MVE_VREV64_16 MQPR:$src))>;
7355  def : Pat<(v2f64 (bitconvert (v16i8 MQPR:$src))), (v2f64 (MVE_VREV64_8 MQPR:$src))>;
7356
7357  def : Pat<(v2i64 (bitconvert (v4f32 MQPR:$src))), (v2i64 (MVE_VREV64_32 MQPR:$src))>;
7358  def : Pat<(v2i64 (bitconvert (v4i32 MQPR:$src))), (v2i64 (MVE_VREV64_32 MQPR:$src))>;
7359  def : Pat<(v2i64 (bitconvert (v8f16 MQPR:$src))), (v2i64 (MVE_VREV64_16 MQPR:$src))>;
7360  def : Pat<(v2i64 (bitconvert (v8i16 MQPR:$src))), (v2i64 (MVE_VREV64_16 MQPR:$src))>;
7361  def : Pat<(v2i64 (bitconvert (v16i8 MQPR:$src))), (v2i64 (MVE_VREV64_8 MQPR:$src))>;
7362
7363  def : Pat<(v4f32 (bitconvert (v2f64 MQPR:$src))), (v4f32 (MVE_VREV64_32 MQPR:$src))>;
7364  def : Pat<(v4f32 (bitconvert (v2i64 MQPR:$src))), (v4f32 (MVE_VREV64_32 MQPR:$src))>;
7365  def : Pat<(v4f32 (bitconvert (v8f16 MQPR:$src))), (v4f32 (MVE_VREV32_16 MQPR:$src))>;
7366  def : Pat<(v4f32 (bitconvert (v8i16 MQPR:$src))), (v4f32 (MVE_VREV32_16 MQPR:$src))>;
7367  def : Pat<(v4f32 (bitconvert (v16i8 MQPR:$src))), (v4f32 (MVE_VREV32_8 MQPR:$src))>;
7368
7369  def : Pat<(v4i32 (bitconvert (v2f64 MQPR:$src))), (v4i32 (MVE_VREV64_32 MQPR:$src))>;
7370  def : Pat<(v4i32 (bitconvert (v2i64 MQPR:$src))), (v4i32 (MVE_VREV64_32 MQPR:$src))>;
7371  def : Pat<(v4i32 (bitconvert (v8f16 MQPR:$src))), (v4i32 (MVE_VREV32_16 MQPR:$src))>;
7372  def : Pat<(v4i32 (bitconvert (v8i16 MQPR:$src))), (v4i32 (MVE_VREV32_16 MQPR:$src))>;
7373  def : Pat<(v4i32 (bitconvert (v16i8 MQPR:$src))), (v4i32 (MVE_VREV32_8 MQPR:$src))>;
7374
7375  def : Pat<(v8f16 (bitconvert (v2f64 MQPR:$src))), (v8f16 (MVE_VREV64_16 MQPR:$src))>;
7376  def : Pat<(v8f16 (bitconvert (v2i64 MQPR:$src))), (v8f16 (MVE_VREV64_16 MQPR:$src))>;
7377  def : Pat<(v8f16 (bitconvert (v4f32 MQPR:$src))), (v8f16 (MVE_VREV32_16 MQPR:$src))>;
7378  def : Pat<(v8f16 (bitconvert (v4i32 MQPR:$src))), (v8f16 (MVE_VREV32_16 MQPR:$src))>;
7379  def : Pat<(v8f16 (bitconvert (v16i8 MQPR:$src))), (v8f16 (MVE_VREV16_8 MQPR:$src))>;
7380
7381  def : Pat<(v8i16 (bitconvert (v2f64 MQPR:$src))), (v8i16 (MVE_VREV64_16 MQPR:$src))>;
7382  def : Pat<(v8i16 (bitconvert (v2i64 MQPR:$src))), (v8i16 (MVE_VREV64_16 MQPR:$src))>;
7383  def : Pat<(v8i16 (bitconvert (v4f32 MQPR:$src))), (v8i16 (MVE_VREV32_16 MQPR:$src))>;
7384  def : Pat<(v8i16 (bitconvert (v4i32 MQPR:$src))), (v8i16 (MVE_VREV32_16 MQPR:$src))>;
7385  def : Pat<(v8i16 (bitconvert (v16i8 MQPR:$src))), (v8i16 (MVE_VREV16_8 MQPR:$src))>;
7386
7387  def : Pat<(v16i8 (bitconvert (v2f64 MQPR:$src))), (v16i8 (MVE_VREV64_8 MQPR:$src))>;
7388  def : Pat<(v16i8 (bitconvert (v2i64 MQPR:$src))), (v16i8 (MVE_VREV64_8 MQPR:$src))>;
7389  def : Pat<(v16i8 (bitconvert (v4f32 MQPR:$src))), (v16i8 (MVE_VREV32_8 MQPR:$src))>;
7390  def : Pat<(v16i8 (bitconvert (v4i32 MQPR:$src))), (v16i8 (MVE_VREV32_8 MQPR:$src))>;
7391  def : Pat<(v16i8 (bitconvert (v8f16 MQPR:$src))), (v16i8 (MVE_VREV16_8 MQPR:$src))>;
7392  def : Pat<(v16i8 (bitconvert (v8i16 MQPR:$src))), (v16i8 (MVE_VREV16_8 MQPR:$src))>;
7393}
7394