1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the ARM instructions in TableGen format. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// ARM specific DAG Nodes. 15// 16 17// Type profiles. 18def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 19 SDTCisVT<1, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21def SDT_ARMStructByVal : SDTypeProfile<0, 4, 22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 24 25def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 26 27def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 28 29def SDT_ARMCMov : SDTypeProfile<1, 3, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 31 SDTCisVT<3, i32>]>; 32 33def SDT_ARMBrcond : SDTypeProfile<0, 2, 34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 35 36def SDT_ARMBrJT : SDTypeProfile<0, 2, 37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 38 39def SDT_ARMBr2JT : SDTypeProfile<0, 3, 40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 41 SDTCisVT<2, i32>]>; 42 43def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 44 [SDTCisVT<0, i32>, 45 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 46 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 47 SDTCisVT<5, OtherVT>]>; 48 49def SDT_ARMAnd : SDTypeProfile<1, 2, 50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 51 SDTCisVT<2, i32>]>; 52 53def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 54 55def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 57 58def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 59def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 60 SDTCisInt<2>]>; 61def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 62def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>; 63 64def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 65 66def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 67 SDTCisInt<1>]>; 68 69def SDT_ARMTCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>; 70 71def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 73 74def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 75 76def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 77 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 78 SDTCisVT<4, i32>]>; 79 80def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 81 [SDTCisSameAs<0, 2>, 82 SDTCisSameAs<0, 3>, 83 SDTCisInt<0>, SDTCisVT<1, i32>]>; 84 85// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 86def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 87 [SDTCisSameAs<0, 2>, 88 SDTCisSameAs<0, 3>, 89 SDTCisInt<0>, 90 SDTCisVT<1, i32>, 91 SDTCisVT<4, i32>]>; 92 93def SDT_LongMac : SDTypeProfile<2, 4, [SDTCisVT<0, i32>, 94 SDTCisSameAs<0, 1>, 95 SDTCisSameAs<0, 2>, 96 SDTCisSameAs<0, 3>, 97 SDTCisSameAs<0, 4>, 98 SDTCisSameAs<0, 5>]>; 99 100// ARMlsll, ARMlsrl, ARMasrl 101def SDT_ARMIntShiftParts : SDTypeProfile<2, 3, [SDTCisSameAs<0, 1>, 102 SDTCisSameAs<0, 2>, 103 SDTCisSameAs<0, 3>, 104 SDTCisInt<0>, 105 SDTCisInt<4>]>; 106 107def ARMSmlald : SDNode<"ARMISD::SMLALD", SDT_LongMac>; 108def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>; 109def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>; 110def ARMSmlsldx : SDNode<"ARMISD::SMLSLDX", SDT_LongMac>; 111 112def SDT_ARMCSel : SDTypeProfile<1, 3, 113 [SDTCisSameAs<0, 1>, 114 SDTCisSameAs<0, 2>, 115 SDTCisInt<3>, 116 SDTCisVT<3, i32>]>; 117 118def ARMcsinv : SDNode<"ARMISD::CSINV", SDT_ARMCSel, [SDNPOptInGlue]>; 119def ARMcsneg : SDNode<"ARMISD::CSNEG", SDT_ARMCSel, [SDNPOptInGlue]>; 120def ARMcsinc : SDNode<"ARMISD::CSINC", SDT_ARMCSel, [SDNPOptInGlue]>; 121 122def SDT_MulHSR : SDTypeProfile<1, 3, [SDTCisVT<0,i32>, 123 SDTCisSameAs<0, 1>, 124 SDTCisSameAs<0, 2>, 125 SDTCisSameAs<0, 3>]>; 126 127def ARMsmmlar : SDNode<"ARMISD::SMMLAR", SDT_MulHSR>; 128def ARMsmmlsr : SDNode<"ARMISD::SMMLSR", SDT_MulHSR>; 129 130// Node definitions. 131def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 132def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 133def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>; 134 135def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 136 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 137def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 138 [SDNPHasChain, SDNPSideEffect, 139 SDNPOptInGlue, SDNPOutGlue]>; 140def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 141 SDT_ARMStructByVal, 142 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 143 SDNPMayStore, SDNPMayLoad]>; 144 145def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 147 SDNPVariadic]>; 148def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 149 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 150 SDNPVariadic]>; 151def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 152 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 153 SDNPVariadic]>; 154 155def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 156 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 157def ARMseretflag : SDNode<"ARMISD::SERET_FLAG", SDTNone, 158 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 159def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 161def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 162 [SDNPInGlue]>; 163def ARMsubs : SDNode<"ARMISD::SUBS", SDTIntBinOp, [SDNPOutGlue]>; 164 165def ARMssat : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>; 166 167def ARMusat : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>; 168 169def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 170 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 171 172def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 173 [SDNPHasChain]>; 174def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 175 [SDNPHasChain]>; 176 177def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 178 [SDNPHasChain]>; 179 180def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 181 [SDNPOutGlue]>; 182 183def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 184 [SDNPOutGlue]>; 185 186def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 187 [SDNPOutGlue, SDNPCommutative]>; 188 189def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 190 191def ARMasrl : SDNode<"ARMISD::ASRL", SDT_ARMIntShiftParts, []>; 192def ARMlsrl : SDNode<"ARMISD::LSRL", SDT_ARMIntShiftParts, []>; 193def ARMlsll : SDNode<"ARMISD::LSLL", SDT_ARMIntShiftParts, []>; 194 195def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 196def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 197def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 198 199def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 200 [SDNPCommutative]>; 201def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 202def ARMlsls : SDNode<"ARMISD::LSLS", SDTBinaryArithWithFlags>; 203def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 204def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 205 206def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 207def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 208 SDT_ARMEH_SJLJ_Setjmp, 209 [SDNPHasChain, SDNPSideEffect]>; 210def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 211 SDT_ARMEH_SJLJ_Longjmp, 212 [SDNPHasChain, SDNPSideEffect]>; 213def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH", 214 SDT_ARMEH_SJLJ_SetupDispatch, 215 [SDNPHasChain, SDNPSideEffect]>; 216 217def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 218 [SDNPHasChain, SDNPSideEffect]>; 219def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 220 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 221 222def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 223 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 224 225def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 226 227def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY, 228 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 229 SDNPMayStore, SDNPMayLoad]>; 230 231def ARMsmulwb : SDNode<"ARMISD::SMULWB", SDTIntBinOp, []>; 232def ARMsmulwt : SDNode<"ARMISD::SMULWT", SDTIntBinOp, []>; 233def ARMsmlalbb : SDNode<"ARMISD::SMLALBB", SDT_LongMac, []>; 234def ARMsmlalbt : SDNode<"ARMISD::SMLALBT", SDT_LongMac, []>; 235def ARMsmlaltb : SDNode<"ARMISD::SMLALTB", SDT_LongMac, []>; 236def ARMsmlaltt : SDNode<"ARMISD::SMLALTT", SDT_LongMac, []>; 237 238def ARMqadd8b : SDNode<"ARMISD::QADD8b", SDT_ARMAnd, []>; 239def ARMqsub8b : SDNode<"ARMISD::QSUB8b", SDT_ARMAnd, []>; 240def ARMqadd16b : SDNode<"ARMISD::QADD16b", SDT_ARMAnd, []>; 241def ARMqsub16b : SDNode<"ARMISD::QSUB16b", SDT_ARMAnd, []>; 242 243def ARMuqadd8b : SDNode<"ARMISD::UQADD8b", SDT_ARMAnd, []>; 244def ARMuqsub8b : SDNode<"ARMISD::UQSUB8b", SDT_ARMAnd, []>; 245def ARMuqadd16b : SDNode<"ARMISD::UQADD16b", SDT_ARMAnd, []>; 246def ARMuqsub16b : SDNode<"ARMISD::UQSUB16b", SDT_ARMAnd, []>; 247 248def SDT_ARMldrd : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 249def ARMldrd : SDNode<"ARMISD::LDRD", SDT_ARMldrd, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 250 251def SDT_ARMstrd : SDTypeProfile<0, 3, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 252def ARMstrd : SDNode<"ARMISD::STRD", SDT_ARMstrd, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 253 254// Vector operations shared between NEON and MVE 255 256def ARMvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>; 257 258// VDUPLANE can produce a quad-register result from a double-register source, 259// so the result is not constrained to match the source. 260def ARMvduplane : SDNode<"ARMISD::VDUPLANE", 261 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 262 SDTCisVT<2, i32>]>>; 263 264def SDTARMVIDUP : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisVT<1, i32>, 265 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 266def ARMvidup : SDNode<"ARMISD::VIDUP", SDTARMVIDUP>; 267 268def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>; 269def ARMvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>; 270def ARMvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>; 271def ARMvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>; 272 273def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVec<1>, 274 SDTCisVT<2, i32>]>; 275def ARMvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>; 276def ARMvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>; 277 278def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>; 279def ARMvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>; 280def ARMvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>; 281def ARMvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>; 282 283def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 284 SDTCisVT<2, i32>]>; 285def ARMvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>; 286def ARMvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>; 287 288def SDTARMVSHIMM : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 289 SDTCisVT<2, i32>]>; 290def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 291 SDTCisSameAs<0, 2>,]>; 292def ARMvshlImm : SDNode<"ARMISD::VSHLIMM", SDTARMVSHIMM>; 293def ARMvshrsImm : SDNode<"ARMISD::VSHRsIMM", SDTARMVSHIMM>; 294def ARMvshruImm : SDNode<"ARMISD::VSHRuIMM", SDTARMVSHIMM>; 295def ARMvshls : SDNode<"ARMISD::VSHLs", SDTARMVSH>; 296def ARMvshlu : SDNode<"ARMISD::VSHLu", SDTARMVSH>; 297 298def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, 299 SDTCisSameAs<1, 2>]>; 300def ARMvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>; 301def ARMvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>; 302 303def SDTARMVCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, 304 SDTCisInt<3>]>; 305def SDTARMVCMPZ : SDTypeProfile<1, 2, [SDTCisInt<2>]>; 306 307def ARMvcmp : SDNode<"ARMISD::VCMP", SDTARMVCMP>; 308def ARMvcmpz : SDNode<"ARMISD::VCMPZ", SDTARMVCMPZ>; 309 310// 'VECTOR_REG_CAST' is an operation that reinterprets the contents of a 311// vector register as a different vector type, without changing the contents of 312// the register. It differs from 'bitconvert' in that bitconvert reinterprets 313// the _memory_ storage format of the vector, whereas VECTOR_REG_CAST 314// reinterprets the _register_ format - and in big-endian, the memory and 315// register formats are different, so they are different operations. 316// 317// For example, 'VECTOR_REG_CAST' between v8i16 and v16i8 will map the LSB of 318// the zeroth i16 lane to the zeroth i8 lane, regardless of system endianness, 319// whereas 'bitconvert' will map it to the high byte in big-endian mode, 320// because that's what (MVE) VSTRH.16 followed by VLDRB.8 would do. So the 321// bitconvert would have to emit a VREV16.8 instruction, whereas the 322// VECTOR_REG_CAST emits no code at all if the vector is already in a register. 323def ARMVectorRegCastImpl : SDNode<"ARMISD::VECTOR_REG_CAST", SDTUnaryOp>; 324 325// In little-endian, VECTOR_REG_CAST is often turned into bitconvert during 326// lowering (because in that situation they're identical). So an isel pattern 327// that needs to match something that's _logically_ a VECTOR_REG_CAST must 328// _physically_ match a different node type depending on endianness. 329// 330// This 'PatFrags' instance is a centralized facility to make that easy. It 331// matches VECTOR_REG_CAST in either endianness, and also bitconvert in the 332// endianness where it's equivalent. 333def ARMVectorRegCast: PatFrags< 334 (ops node:$x), [(ARMVectorRegCastImpl node:$x), (bitconvert node:$x)], [{ 335 // Reject a match against bitconvert (aka ISD::BITCAST) if big-endian 336 return !(CurDAG->getDataLayout().isBigEndian() && 337 N->getOpcode() == ISD::BITCAST); 338 }]>; 339 340//===----------------------------------------------------------------------===// 341// ARM Flag Definitions. 342 343class RegConstraint<string C> { 344 string Constraints = C; 345} 346 347// ARMCC condition codes. See ARMCC::CondCodes 348def ARMCCeq : PatLeaf<(i32 0)>; 349def ARMCCne : PatLeaf<(i32 1)>; 350def ARMCChs : PatLeaf<(i32 2)>; 351def ARMCClo : PatLeaf<(i32 3)>; 352def ARMCCmi : PatLeaf<(i32 4)>; 353def ARMCCpl : PatLeaf<(i32 5)>; 354def ARMCCvs : PatLeaf<(i32 6)>; 355def ARMCCvc : PatLeaf<(i32 7)>; 356def ARMCChi : PatLeaf<(i32 8)>; 357def ARMCCls : PatLeaf<(i32 9)>; 358def ARMCCge : PatLeaf<(i32 10)>; 359def ARMCClt : PatLeaf<(i32 11)>; 360def ARMCCgt : PatLeaf<(i32 12)>; 361def ARMCCle : PatLeaf<(i32 13)>; 362def ARMCCal : PatLeaf<(i32 14)>; 363 364// VCC predicates. See ARMVCC::VPTCodes 365def ARMVCCNone : PatLeaf<(i32 0)>; 366def ARMVCCThen : PatLeaf<(i32 1)>; 367def ARMVCCElse : PatLeaf<(i32 2)>; 368 369//===----------------------------------------------------------------------===// 370// ARM specific transformation functions and pattern fragments. 371// 372 373// imm_neg_XFORM - Return the negation of an i32 immediate value. 374def imm_neg_XFORM : SDNodeXForm<imm, [{ 375 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32); 376}]>; 377 378// imm_not_XFORM - Return the complement of a i32 immediate value. 379def imm_not_XFORM : SDNodeXForm<imm, [{ 380 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32); 381}]>; 382 383// asr_imm_XFORM - Returns a shift immediate with bit {5} set to 1 384def asr_imm_XFORM : SDNodeXForm<imm, [{ 385 return CurDAG->getTargetConstant(0x20 | N->getZExtValue(), SDLoc(N), MVT:: i32); 386}]>; 387 388/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 389def imm16_31 : ImmLeaf<i32, [{ 390 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 391}]>; 392 393// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 394def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 395 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 396}]>; 397 398def sext_bottom_16 : PatFrag<(ops node:$a), 399 (sext_inreg node:$a, i16)>; 400def sext_top_16 : PatFrag<(ops node:$a), 401 (i32 (sra node:$a, (i32 16)))>; 402 403def bb_mul : PatFrag<(ops node:$a, node:$b), 404 (mul (sext_bottom_16 node:$a), (sext_bottom_16 node:$b))>; 405def bt_mul : PatFrag<(ops node:$a, node:$b), 406 (mul (sext_bottom_16 node:$a), (sra node:$b, (i32 16)))>; 407def tb_mul : PatFrag<(ops node:$a, node:$b), 408 (mul (sra node:$a, (i32 16)), (sext_bottom_16 node:$b))>; 409def tt_mul : PatFrag<(ops node:$a, node:$b), 410 (mul (sra node:$a, (i32 16)), (sra node:$b, (i32 16)))>; 411 412/// Split a 32-bit immediate into two 16 bit parts. 413def hi16 : SDNodeXForm<imm, [{ 414 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N), 415 MVT::i32); 416}]>; 417 418def lo16AllZero : PatLeaf<(i32 imm), [{ 419 // Returns true if all low 16-bits are 0. 420 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 421}], hi16>; 422 423class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 424class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 425 426// An 'and' node with a single use. 427def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 428 return N->hasOneUse(); 429}]>; 430 431// An 'xor' node with a single use. 432def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 433 return N->hasOneUse(); 434}]>; 435 436// An 'fmul' node with a single use. 437def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 438 return N->hasOneUse(); 439}]>; 440 441// An 'fadd' node which checks for single non-hazardous use. 442def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 443 return hasNoVMLxHazardUse(N); 444}]>; 445 446// An 'fsub' node which checks for single non-hazardous use. 447def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 448 return hasNoVMLxHazardUse(N); 449}]>; 450 451def imm_even : ImmLeaf<i32, [{ return (Imm & 1) == 0; }]>; 452def imm_odd : ImmLeaf<i32, [{ return (Imm & 1) == 1; }]>; 453 454def asr_imm : ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }], asr_imm_XFORM>; 455 456//===----------------------------------------------------------------------===// 457// NEON/MVE pattern fragments 458// 459 460// Extract D sub-registers of Q registers. 461def DSubReg_i8_reg : SDNodeXForm<imm, [{ 462 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 463 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, SDLoc(N), 464 MVT::i32); 465}]>; 466def DSubReg_i16_reg : SDNodeXForm<imm, [{ 467 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 468 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, SDLoc(N), 469 MVT::i32); 470}]>; 471def DSubReg_i32_reg : SDNodeXForm<imm, [{ 472 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 473 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, SDLoc(N), 474 MVT::i32); 475}]>; 476def DSubReg_f64_reg : SDNodeXForm<imm, [{ 477 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 478 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), SDLoc(N), 479 MVT::i32); 480}]>; 481 482// Extract S sub-registers of Q/D registers. 483def SSubReg_f32_reg : SDNodeXForm<imm, [{ 484 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering"); 485 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), SDLoc(N), 486 MVT::i32); 487}]>; 488 489// Extract S sub-registers of Q/D registers containing a given f16/bf16 lane. 490def SSubReg_f16_reg : SDNodeXForm<imm, [{ 491 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering"); 492 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue()/2, SDLoc(N), 493 MVT::i32); 494}]>; 495 496// Translate lane numbers from Q registers to D subregs. 497def SubReg_i8_lane : SDNodeXForm<imm, [{ 498 return CurDAG->getTargetConstant(N->getZExtValue() & 7, SDLoc(N), MVT::i32); 499}]>; 500def SubReg_i16_lane : SDNodeXForm<imm, [{ 501 return CurDAG->getTargetConstant(N->getZExtValue() & 3, SDLoc(N), MVT::i32); 502}]>; 503def SubReg_i32_lane : SDNodeXForm<imm, [{ 504 return CurDAG->getTargetConstant(N->getZExtValue() & 1, SDLoc(N), MVT::i32); 505}]>; 506 507 508def ARMimmAllZerosV: PatLeaf<(bitconvert (v4i32 (ARMvmovImm (i32 0))))>; 509def ARMimmAllZerosD: PatLeaf<(bitconvert (v2i32 (ARMvmovImm (i32 0))))>; 510def ARMimmAllOnesV: PatLeaf<(bitconvert (v16i8 (ARMvmovImm (i32 0xEFF))))>; 511def ARMimmAllOnesD: PatLeaf<(bitconvert (v8i8 (ARMvmovImm (i32 0xEFF))))>; 512 513def ARMimmOneV: PatLeaf<(ARMvmovImm (i32 timm)), [{ 514 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0)); 515 unsigned EltBits = 0; 516 uint64_t EltVal = ARM_AM::decodeVMOVModImm(ConstVal->getZExtValue(), EltBits); 517 return (EltBits == N->getValueType(0).getScalarSizeInBits() && EltVal == 0x01); 518}]>; 519 520 521//===----------------------------------------------------------------------===// 522// Operand Definitions. 523// 524 525// Immediate operands with a shared generic asm render method. 526class ImmAsmOperand<int Low, int High> : AsmOperandClass { 527 let RenderMethod = "addImmOperands"; 528 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 529 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 530} 531 532class ImmAsmOperandMinusOne<int Low, int High> : AsmOperandClass { 533 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 534 let DiagnosticType = "ImmRange" # Low # "_" # High; 535 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 536} 537 538// Operands that are part of a memory addressing mode. 539class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; } 540 541// Branch target. 542// FIXME: rename brtarget to t2_brtarget 543def brtarget : Operand<OtherVT> { 544 let EncoderMethod = "getBranchTargetOpValue"; 545 let OperandType = "OPERAND_PCREL"; 546 let DecoderMethod = "DecodeT2BROperand"; 547} 548 549// Branches targeting ARM-mode must be divisible by 4 if they're a raw 550// immediate. 551def ARMBranchTarget : AsmOperandClass { 552 let Name = "ARMBranchTarget"; 553} 554 555// Branches targeting Thumb-mode must be divisible by 2 if they're a raw 556// immediate. 557def ThumbBranchTarget : AsmOperandClass { 558 let Name = "ThumbBranchTarget"; 559} 560 561def arm_br_target : Operand<OtherVT> { 562 let ParserMatchClass = ARMBranchTarget; 563 let EncoderMethod = "getARMBranchTargetOpValue"; 564 let OperandType = "OPERAND_PCREL"; 565} 566 567// Call target for ARM. Handles conditional/unconditional 568// FIXME: rename bl_target to t2_bltarget? 569def arm_bl_target : Operand<i32> { 570 let ParserMatchClass = ARMBranchTarget; 571 let EncoderMethod = "getARMBLTargetOpValue"; 572 let OperandType = "OPERAND_PCREL"; 573} 574 575// Target for BLX *from* ARM mode. 576def arm_blx_target : Operand<i32> { 577 let ParserMatchClass = ThumbBranchTarget; 578 let EncoderMethod = "getARMBLXTargetOpValue"; 579 let OperandType = "OPERAND_PCREL"; 580} 581 582// A list of registers separated by comma. Used by load/store multiple. 583def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 584def reglist : Operand<i32> { 585 let EncoderMethod = "getRegisterListOpValue"; 586 let ParserMatchClass = RegListAsmOperand; 587 let PrintMethod = "printRegisterList"; 588 let DecoderMethod = "DecodeRegListOperand"; 589} 590 591// A list of general purpose registers and APSR separated by comma. 592// Used by CLRM 593def RegListWithAPSRAsmOperand : AsmOperandClass { let Name = "RegListWithAPSR"; } 594def reglist_with_apsr : Operand<i32> { 595 let EncoderMethod = "getRegisterListOpValue"; 596 let ParserMatchClass = RegListWithAPSRAsmOperand; 597 let PrintMethod = "printRegisterList"; 598 let DecoderMethod = "DecodeRegListOperand"; 599} 600 601def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 602 603def DPRRegListAsmOperand : AsmOperandClass { 604 let Name = "DPRRegList"; 605 let DiagnosticType = "DPR_RegList"; 606} 607def dpr_reglist : Operand<i32> { 608 let EncoderMethod = "getRegisterListOpValue"; 609 let ParserMatchClass = DPRRegListAsmOperand; 610 let PrintMethod = "printRegisterList"; 611 let DecoderMethod = "DecodeDPRRegListOperand"; 612} 613 614def SPRRegListAsmOperand : AsmOperandClass { 615 let Name = "SPRRegList"; 616 let DiagnosticString = "operand must be a list of registers in range [s0, s31]"; 617} 618def spr_reglist : Operand<i32> { 619 let EncoderMethod = "getRegisterListOpValue"; 620 let ParserMatchClass = SPRRegListAsmOperand; 621 let PrintMethod = "printRegisterList"; 622 let DecoderMethod = "DecodeSPRRegListOperand"; 623} 624 625def FPSRegListWithVPRAsmOperand : AsmOperandClass { let Name = 626 "FPSRegListWithVPR"; } 627def fp_sreglist_with_vpr : Operand<i32> { 628 let EncoderMethod = "getRegisterListOpValue"; 629 let ParserMatchClass = FPSRegListWithVPRAsmOperand; 630 let PrintMethod = "printRegisterList"; 631} 632def FPDRegListWithVPRAsmOperand : AsmOperandClass { let Name = 633 "FPDRegListWithVPR"; } 634def fp_dreglist_with_vpr : Operand<i32> { 635 let EncoderMethod = "getRegisterListOpValue"; 636 let ParserMatchClass = FPDRegListWithVPRAsmOperand; 637 let PrintMethod = "printRegisterList"; 638} 639 640// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 641def cpinst_operand : Operand<i32> { 642 let PrintMethod = "printCPInstOperand"; 643} 644 645// Local PC labels. 646def pclabel : Operand<i32> { 647 let PrintMethod = "printPCLabel"; 648} 649 650// ADR instruction labels. 651def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 652def adrlabel : Operand<i32> { 653 let EncoderMethod = "getAdrLabelOpValue"; 654 let ParserMatchClass = AdrLabelAsmOperand; 655 let PrintMethod = "printAdrLabelOperand<0>"; 656} 657 658def neon_vcvt_imm32 : Operand<i32> { 659 let EncoderMethod = "getNEONVcvtImm32OpValue"; 660 let DecoderMethod = "DecodeVCVTImmOperand"; 661} 662 663// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 664def rot_imm_XFORM: SDNodeXForm<imm, [{ 665 switch (N->getZExtValue()){ 666 default: llvm_unreachable(nullptr); 667 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); 668 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32); 669 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32); 670 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32); 671 } 672}]>; 673def RotImmAsmOperand : AsmOperandClass { 674 let Name = "RotImm"; 675 let ParserMethod = "parseRotImm"; 676} 677def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 678 int32_t v = N->getZExtValue(); 679 return v == 8 || v == 16 || v == 24; }], 680 rot_imm_XFORM> { 681 let PrintMethod = "printRotImmOperand"; 682 let ParserMatchClass = RotImmAsmOperand; 683} 684 685// Power-of-two operand for MVE VIDUP and friends, which encode 686// {1,2,4,8} as its log to base 2, i.e. as {0,1,2,3} respectively 687def MVE_VIDUP_imm_asmoperand : AsmOperandClass { 688 let Name = "VIDUP_imm"; 689 let PredicateMethod = "isPowerTwoInRange<1,8>"; 690 let RenderMethod = "addPowerTwoOperands"; 691 let DiagnosticString = "vector increment immediate must be 1, 2, 4 or 8"; 692} 693def MVE_VIDUP_imm : Operand<i32> { 694 let EncoderMethod = "getPowerTwoOpValue"; 695 let DecoderMethod = "DecodePowerTwoOperand<0,3>"; 696 let ParserMatchClass = MVE_VIDUP_imm_asmoperand; 697} 698 699// Pair vector indexing 700class MVEPairVectorIndexOperand<string start, string end> : AsmOperandClass { 701 let Name = "MVEPairVectorIndex"#start; 702 let RenderMethod = "addMVEPairVectorIndexOperands"; 703 let PredicateMethod = "isMVEPairVectorIndex<"#start#", "#end#">"; 704} 705 706class MVEPairVectorIndex<string opval> : Operand<i32> { 707 let PrintMethod = "printVectorIndex"; 708 let EncoderMethod = "getMVEPairVectorIndexOpValue<"#opval#">"; 709 let DecoderMethod = "DecodeMVEPairVectorIndexOperand<"#opval#">"; 710 let MIOperandInfo = (ops i32imm); 711} 712 713def MVEPairVectorIndex0 : MVEPairVectorIndex<"0"> { 714 let ParserMatchClass = MVEPairVectorIndexOperand<"0", "1">; 715} 716 717def MVEPairVectorIndex2 : MVEPairVectorIndex<"2"> { 718 let ParserMatchClass = MVEPairVectorIndexOperand<"2", "3">; 719} 720 721// Vector indexing 722class MVEVectorIndexOperand<int NumLanes> : AsmOperandClass { 723 let Name = "MVEVectorIndex"#NumLanes; 724 let RenderMethod = "addMVEVectorIndexOperands"; 725 let PredicateMethod = "isVectorIndexInRange<"#NumLanes#">"; 726} 727 728class MVEVectorIndex<int NumLanes> : Operand<i32> { 729 let PrintMethod = "printVectorIndex"; 730 let ParserMatchClass = MVEVectorIndexOperand<NumLanes>; 731 let MIOperandInfo = (ops i32imm); 732} 733 734// shift_imm: An integer that encodes a shift amount and the type of shift 735// (asr or lsl). The 6-bit immediate encodes as: 736// {5} 0 ==> lsl 737// 1 asr 738// {4-0} imm5 shift amount. 739// asr #32 encoded as imm5 == 0. 740def ShifterImmAsmOperand : AsmOperandClass { 741 let Name = "ShifterImm"; 742 let ParserMethod = "parseShifterImm"; 743} 744def shift_imm : Operand<i32> { 745 let PrintMethod = "printShiftImmOperand"; 746 let ParserMatchClass = ShifterImmAsmOperand; 747} 748 749// shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm. 750def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 751def so_reg_reg : Operand<i32>, // reg reg imm 752 ComplexPattern<i32, 3, "SelectRegShifterOperand", 753 [shl, srl, sra, rotr]> { 754 let EncoderMethod = "getSORegRegOpValue"; 755 let PrintMethod = "printSORegRegOperand"; 756 let DecoderMethod = "DecodeSORegRegOperand"; 757 let ParserMatchClass = ShiftedRegAsmOperand; 758 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 759} 760 761def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 762def so_reg_imm : Operand<i32>, // reg imm 763 ComplexPattern<i32, 2, "SelectImmShifterOperand", 764 [shl, srl, sra, rotr]> { 765 let EncoderMethod = "getSORegImmOpValue"; 766 let PrintMethod = "printSORegImmOperand"; 767 let DecoderMethod = "DecodeSORegImmOperand"; 768 let ParserMatchClass = ShiftedImmAsmOperand; 769 let MIOperandInfo = (ops GPR, i32imm); 770} 771 772// FIXME: Does this need to be distinct from so_reg? 773def shift_so_reg_reg : Operand<i32>, // reg reg imm 774 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 775 [shl,srl,sra,rotr]> { 776 let EncoderMethod = "getSORegRegOpValue"; 777 let PrintMethod = "printSORegRegOperand"; 778 let DecoderMethod = "DecodeSORegRegOperand"; 779 let ParserMatchClass = ShiftedRegAsmOperand; 780 let MIOperandInfo = (ops GPR, GPR, i32imm); 781} 782 783// FIXME: Does this need to be distinct from so_reg? 784def shift_so_reg_imm : Operand<i32>, // reg reg imm 785 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 786 [shl,srl,sra,rotr]> { 787 let EncoderMethod = "getSORegImmOpValue"; 788 let PrintMethod = "printSORegImmOperand"; 789 let DecoderMethod = "DecodeSORegImmOperand"; 790 let ParserMatchClass = ShiftedImmAsmOperand; 791 let MIOperandInfo = (ops GPR, i32imm); 792} 793 794// mod_imm: match a 32-bit immediate operand, which can be encoded into 795// a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM 796// - "Modified Immediate Constants"). Within the MC layer we keep this 797// immediate in its encoded form. 798def ModImmAsmOperand: AsmOperandClass { 799 let Name = "ModImm"; 800 let ParserMethod = "parseModImm"; 801} 802def mod_imm : Operand<i32>, ImmLeaf<i32, [{ 803 return ARM_AM::getSOImmVal(Imm) != -1; 804 }]> { 805 let EncoderMethod = "getModImmOpValue"; 806 let PrintMethod = "printModImmOperand"; 807 let ParserMatchClass = ModImmAsmOperand; 808} 809 810// Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder 811// method and such, as they are only used on aliases (Pat<> and InstAlias<>). 812// The actual parsing, encoding, decoding are handled by the destination 813// instructions, which use mod_imm. 814 815def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; } 816def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{ 817 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 818 }], imm_not_XFORM> { 819 let ParserMatchClass = ModImmNotAsmOperand; 820} 821 822def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; } 823def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 824 unsigned Value = -(unsigned)N->getZExtValue(); 825 return Value && ARM_AM::getSOImmVal(Value) != -1; 826 }], imm_neg_XFORM> { 827 let ParserMatchClass = ModImmNegAsmOperand; 828} 829 830/// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal() 831def arm_i32imm : IntImmLeaf<i32, [{ 832 if (Subtarget->useMovt()) 833 return true; 834 if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue())) 835 return true; 836 return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue()); 837}]>; 838 839/// imm0_1 predicate - Immediate in the range [0,1]. 840def Imm0_1AsmOperand: ImmAsmOperand<0,1> { let Name = "Imm0_1"; } 841def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 842 843/// imm0_3 predicate - Immediate in the range [0,3]. 844def Imm0_3AsmOperand: ImmAsmOperand<0,3> { let Name = "Imm0_3"; } 845def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 846 847/// imm0_7 predicate - Immediate in the range [0,7]. 848def Imm0_7AsmOperand: ImmAsmOperand<0,7> { 849 let Name = "Imm0_7"; 850} 851def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 852 return Imm >= 0 && Imm < 8; 853}]> { 854 let ParserMatchClass = Imm0_7AsmOperand; 855} 856 857/// imm8_255 predicate - Immediate in the range [8,255]. 858def Imm8_255AsmOperand: ImmAsmOperand<8,255> { let Name = "Imm8_255"; } 859def imm8_255 : Operand<i32>, ImmLeaf<i32, [{ 860 return Imm >= 8 && Imm < 256; 861}]> { 862 let ParserMatchClass = Imm8_255AsmOperand; 863} 864 865/// imm8 predicate - Immediate is exactly 8. 866def Imm8AsmOperand: ImmAsmOperand<8,8> { let Name = "Imm8"; } 867def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 868 let ParserMatchClass = Imm8AsmOperand; 869} 870 871/// imm16 predicate - Immediate is exactly 16. 872def Imm16AsmOperand: ImmAsmOperand<16,16> { let Name = "Imm16"; } 873def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 874 let ParserMatchClass = Imm16AsmOperand; 875} 876 877/// imm32 predicate - Immediate is exactly 32. 878def Imm32AsmOperand: ImmAsmOperand<32,32> { let Name = "Imm32"; } 879def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 880 let ParserMatchClass = Imm32AsmOperand; 881} 882 883def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>; 884 885/// imm1_7 predicate - Immediate in the range [1,7]. 886def Imm1_7AsmOperand: ImmAsmOperand<1,7> { let Name = "Imm1_7"; } 887def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 888 let ParserMatchClass = Imm1_7AsmOperand; 889} 890 891/// imm1_15 predicate - Immediate in the range [1,15]. 892def Imm1_15AsmOperand: ImmAsmOperand<1,15> { let Name = "Imm1_15"; } 893def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 894 let ParserMatchClass = Imm1_15AsmOperand; 895} 896 897/// imm1_31 predicate - Immediate in the range [1,31]. 898def Imm1_31AsmOperand: ImmAsmOperand<1,31> { let Name = "Imm1_31"; } 899def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 900 let ParserMatchClass = Imm1_31AsmOperand; 901} 902 903/// imm0_15 predicate - Immediate in the range [0,15]. 904def Imm0_15AsmOperand: ImmAsmOperand<0,15> { 905 let Name = "Imm0_15"; 906} 907def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 908 return Imm >= 0 && Imm < 16; 909}]> { 910 let ParserMatchClass = Imm0_15AsmOperand; 911} 912 913/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 914def Imm0_31AsmOperand: ImmAsmOperand<0,31> { let Name = "Imm0_31"; } 915def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 916 return Imm >= 0 && Imm < 32; 917}]> { 918 let ParserMatchClass = Imm0_31AsmOperand; 919} 920 921/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 922def Imm0_32AsmOperand: ImmAsmOperand<0,32> { let Name = "Imm0_32"; } 923def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 924 return Imm >= 0 && Imm < 33; 925}]> { 926 let ParserMatchClass = Imm0_32AsmOperand; 927} 928 929/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 930def Imm0_63AsmOperand: ImmAsmOperand<0,63> { let Name = "Imm0_63"; } 931def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 932 return Imm >= 0 && Imm < 64; 933}]> { 934 let ParserMatchClass = Imm0_63AsmOperand; 935} 936 937/// imm0_239 predicate - Immediate in the range [0,239]. 938def Imm0_239AsmOperand : ImmAsmOperand<0,239> { 939 let Name = "Imm0_239"; 940} 941def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 942 let ParserMatchClass = Imm0_239AsmOperand; 943} 944 945/// imm0_255 predicate - Immediate in the range [0,255]. 946def Imm0_255AsmOperand : ImmAsmOperand<0,255> { let Name = "Imm0_255"; } 947def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 948 let ParserMatchClass = Imm0_255AsmOperand; 949} 950 951/// imm0_65535 - An immediate is in the range [0,65535]. 952def Imm0_65535AsmOperand: ImmAsmOperand<0,65535> { let Name = "Imm0_65535"; } 953def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 954 return Imm >= 0 && Imm < 65536; 955}]> { 956 let ParserMatchClass = Imm0_65535AsmOperand; 957} 958 959// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 960def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 961 return -Imm >= 0 && -Imm < 65536; 962}]>; 963 964// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 965// a relocatable expression. 966// 967// FIXME: This really needs a Thumb version separate from the ARM version. 968// While the range is the same, and can thus use the same match class, 969// the encoding is different so it should have a different encoder method. 970def Imm0_65535ExprAsmOperand: AsmOperandClass { 971 let Name = "Imm0_65535Expr"; 972 let RenderMethod = "addImmOperands"; 973 let DiagnosticString = "operand must be an immediate in the range [0,0xffff] or a relocatable expression"; 974} 975 976def imm0_65535_expr : Operand<i32> { 977 let EncoderMethod = "getHiLo16ImmOpValue"; 978 let ParserMatchClass = Imm0_65535ExprAsmOperand; 979} 980 981def Imm256_65535ExprAsmOperand: ImmAsmOperand<256,65535> { let Name = "Imm256_65535Expr"; } 982def imm256_65535_expr : Operand<i32> { 983 let ParserMatchClass = Imm256_65535ExprAsmOperand; 984} 985 986/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 987def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> { 988 let Name = "Imm24bit"; 989 let DiagnosticString = "operand must be an immediate in the range [0,0xffffff]"; 990} 991def imm24b : Operand<i32>, ImmLeaf<i32, [{ 992 return Imm >= 0 && Imm <= 0xffffff; 993}]> { 994 let ParserMatchClass = Imm24bitAsmOperand; 995} 996 997 998/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 999/// e.g., 0xf000ffff 1000def BitfieldAsmOperand : AsmOperandClass { 1001 let Name = "Bitfield"; 1002 let ParserMethod = "parseBitfield"; 1003} 1004 1005def bf_inv_mask_imm : Operand<i32>, 1006 PatLeaf<(imm), [{ 1007 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 1008}] > { 1009 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 1010 let PrintMethod = "printBitfieldInvMaskImmOperand"; 1011 let DecoderMethod = "DecodeBitfieldMaskOperand"; 1012 let ParserMatchClass = BitfieldAsmOperand; 1013 let GISelPredicateCode = [{ 1014 // There's better methods of implementing this check. IntImmLeaf<> would be 1015 // equivalent and have less boilerplate but we need a test for C++ 1016 // predicates and this one causes new rules to be imported into GlobalISel 1017 // without requiring additional features first. 1018 const auto &MO = MI.getOperand(1); 1019 if (!MO.isCImm()) 1020 return false; 1021 return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); 1022 }]; 1023} 1024 1025def imm1_32_XFORM: SDNodeXForm<imm, [{ 1026 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 1027 MVT::i32); 1028}]>; 1029def Imm1_32AsmOperand: ImmAsmOperandMinusOne<1,32> { 1030 let Name = "Imm1_32"; 1031} 1032def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 1033 uint64_t Imm = N->getZExtValue(); 1034 return Imm > 0 && Imm <= 32; 1035 }], 1036 imm1_32_XFORM> { 1037 let PrintMethod = "printImmPlusOneOperand"; 1038 let ParserMatchClass = Imm1_32AsmOperand; 1039} 1040 1041def imm1_16_XFORM: SDNodeXForm<imm, [{ 1042 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 1043 MVT::i32); 1044}]>; 1045def Imm1_16AsmOperand: ImmAsmOperandMinusOne<1,16> { let Name = "Imm1_16"; } 1046def imm1_16 : Operand<i32>, ImmLeaf<i32, [{ 1047 return Imm > 0 && Imm <= 16; 1048 }], 1049 imm1_16_XFORM> { 1050 let PrintMethod = "printImmPlusOneOperand"; 1051 let ParserMatchClass = Imm1_16AsmOperand; 1052} 1053 1054def MVEShiftImm1_7AsmOperand: ImmAsmOperand<1,7> { 1055 let Name = "MVEShiftImm1_7"; 1056 // Reason we're doing this is because instruction vshll.s8 t1 encoding 1057 // accepts 1,7 but the t2 encoding accepts 8. By doing this we can get a 1058 // better diagnostic message if someone uses bigger immediate than the t1/t2 1059 // encodings allow. 1060 let DiagnosticString = "operand must be an immediate in the range [1,8]"; 1061} 1062def mve_shift_imm1_7 : Operand<i32>, 1063 // SelectImmediateInRange / isScaledConstantInRange uses a 1064 // half-open interval, so the parameters <1,8> mean 1-7 inclusive 1065 ComplexPattern<i32, 1, "SelectImmediateInRange<1,8>", [], []> { 1066 let ParserMatchClass = MVEShiftImm1_7AsmOperand; 1067 let EncoderMethod = "getMVEShiftImmOpValue"; 1068} 1069 1070def MVEShiftImm1_15AsmOperand: ImmAsmOperand<1,15> { 1071 let Name = "MVEShiftImm1_15"; 1072 // Reason we're doing this is because instruction vshll.s16 t1 encoding 1073 // accepts 1,15 but the t2 encoding accepts 16. By doing this we can get a 1074 // better diagnostic message if someone uses bigger immediate than the t1/t2 1075 // encodings allow. 1076 let DiagnosticString = "operand must be an immediate in the range [1,16]"; 1077} 1078def mve_shift_imm1_15 : Operand<i32>, 1079 // SelectImmediateInRange / isScaledConstantInRange uses a 1080 // half-open interval, so the parameters <1,16> mean 1-15 inclusive 1081 ComplexPattern<i32, 1, "SelectImmediateInRange<1,16>", [], []> { 1082 let ParserMatchClass = MVEShiftImm1_15AsmOperand; 1083 let EncoderMethod = "getMVEShiftImmOpValue"; 1084} 1085 1086// Define ARM specific addressing modes. 1087// addrmode_imm12 := reg +/- imm12 1088// 1089def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 1090class AddrMode_Imm12 : MemOperand, 1091 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 1092 // 12-bit immediate operand. Note that instructions using this encode 1093 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 1094 // immediate values are as normal. 1095 1096 let EncoderMethod = "getAddrModeImm12OpValue"; 1097 let DecoderMethod = "DecodeAddrModeImm12Operand"; 1098 let ParserMatchClass = MemImm12OffsetAsmOperand; 1099 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 1100} 1101 1102def addrmode_imm12 : AddrMode_Imm12 { 1103 let PrintMethod = "printAddrModeImm12Operand<false>"; 1104} 1105 1106def addrmode_imm12_pre : AddrMode_Imm12 { 1107 let PrintMethod = "printAddrModeImm12Operand<true>"; 1108} 1109 1110// ldst_so_reg := reg +/- reg shop imm 1111// 1112def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 1113def ldst_so_reg : MemOperand, 1114 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 1115 let EncoderMethod = "getLdStSORegOpValue"; 1116 // FIXME: Simplify the printer 1117 let PrintMethod = "printAddrMode2Operand"; 1118 let DecoderMethod = "DecodeSORegMemOperand"; 1119 let ParserMatchClass = MemRegOffsetAsmOperand; 1120 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 1121} 1122 1123// postidx_imm8 := +/- [0,255] 1124// 1125// 9 bit value: 1126// {8} 1 is imm8 is non-negative. 0 otherwise. 1127// {7-0} [0,255] imm8 value. 1128def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 1129def postidx_imm8 : MemOperand { 1130 let PrintMethod = "printPostIdxImm8Operand"; 1131 let ParserMatchClass = PostIdxImm8AsmOperand; 1132 let MIOperandInfo = (ops i32imm); 1133} 1134 1135// postidx_imm8s4 := +/- [0,1020] 1136// 1137// 9 bit value: 1138// {8} 1 is imm8 is non-negative. 0 otherwise. 1139// {7-0} [0,255] imm8 value, scaled by 4. 1140def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 1141def postidx_imm8s4 : MemOperand { 1142 let PrintMethod = "printPostIdxImm8s4Operand"; 1143 let ParserMatchClass = PostIdxImm8s4AsmOperand; 1144 let MIOperandInfo = (ops i32imm); 1145} 1146 1147 1148// postidx_reg := +/- reg 1149// 1150def PostIdxRegAsmOperand : AsmOperandClass { 1151 let Name = "PostIdxReg"; 1152 let ParserMethod = "parsePostIdxReg"; 1153} 1154def postidx_reg : MemOperand { 1155 let EncoderMethod = "getPostIdxRegOpValue"; 1156 let DecoderMethod = "DecodePostIdxReg"; 1157 let PrintMethod = "printPostIdxRegOperand"; 1158 let ParserMatchClass = PostIdxRegAsmOperand; 1159 let MIOperandInfo = (ops GPRnopc, i32imm); 1160} 1161 1162def PostIdxRegShiftedAsmOperand : AsmOperandClass { 1163 let Name = "PostIdxRegShifted"; 1164 let ParserMethod = "parsePostIdxReg"; 1165} 1166def am2offset_reg : MemOperand, 1167 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 1168 [], [SDNPWantRoot]> { 1169 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1170 let PrintMethod = "printAddrMode2OffsetOperand"; 1171 // When using this for assembly, it's always as a post-index offset. 1172 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 1173 let MIOperandInfo = (ops GPRnopc, i32imm); 1174} 1175 1176// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 1177// the GPR is purely vestigal at this point. 1178def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 1179def am2offset_imm : MemOperand, 1180 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 1181 [], [SDNPWantRoot]> { 1182 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1183 let PrintMethod = "printAddrMode2OffsetOperand"; 1184 let ParserMatchClass = AM2OffsetImmAsmOperand; 1185 let MIOperandInfo = (ops GPRnopc, i32imm); 1186} 1187 1188 1189// addrmode3 := reg +/- reg 1190// addrmode3 := reg +/- imm8 1191// 1192// FIXME: split into imm vs. reg versions. 1193def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 1194class AddrMode3 : MemOperand, 1195 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 1196 let EncoderMethod = "getAddrMode3OpValue"; 1197 let ParserMatchClass = AddrMode3AsmOperand; 1198 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 1199} 1200 1201def addrmode3 : AddrMode3 1202{ 1203 let PrintMethod = "printAddrMode3Operand<false>"; 1204} 1205 1206def addrmode3_pre : AddrMode3 1207{ 1208 let PrintMethod = "printAddrMode3Operand<true>"; 1209} 1210 1211// FIXME: split into imm vs. reg versions. 1212// FIXME: parser method to handle +/- register. 1213def AM3OffsetAsmOperand : AsmOperandClass { 1214 let Name = "AM3Offset"; 1215 let ParserMethod = "parseAM3Offset"; 1216} 1217def am3offset : MemOperand, 1218 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 1219 [], [SDNPWantRoot]> { 1220 let EncoderMethod = "getAddrMode3OffsetOpValue"; 1221 let PrintMethod = "printAddrMode3OffsetOperand"; 1222 let ParserMatchClass = AM3OffsetAsmOperand; 1223 let MIOperandInfo = (ops GPR, i32imm); 1224} 1225 1226// ldstm_mode := {ia, ib, da, db} 1227// 1228def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 1229 let EncoderMethod = "getLdStmModeOpValue"; 1230 let PrintMethod = "printLdStmModeOperand"; 1231} 1232 1233// addrmode5 := reg +/- imm8*4 1234// 1235def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 1236class AddrMode5 : MemOperand, 1237 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 1238 let EncoderMethod = "getAddrMode5OpValue"; 1239 let DecoderMethod = "DecodeAddrMode5Operand"; 1240 let ParserMatchClass = AddrMode5AsmOperand; 1241 let MIOperandInfo = (ops GPR:$base, i32imm); 1242} 1243 1244def addrmode5 : AddrMode5 { 1245 let PrintMethod = "printAddrMode5Operand<false>"; 1246} 1247 1248def addrmode5_pre : AddrMode5 { 1249 let PrintMethod = "printAddrMode5Operand<true>"; 1250} 1251 1252// addrmode5fp16 := reg +/- imm8*2 1253// 1254def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; } 1255class AddrMode5FP16 : MemOperand, 1256 ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> { 1257 let EncoderMethod = "getAddrMode5FP16OpValue"; 1258 let DecoderMethod = "DecodeAddrMode5FP16Operand"; 1259 let ParserMatchClass = AddrMode5FP16AsmOperand; 1260 let MIOperandInfo = (ops GPR:$base, i32imm); 1261} 1262 1263def addrmode5fp16 : AddrMode5FP16 { 1264 let PrintMethod = "printAddrMode5FP16Operand<false>"; 1265} 1266 1267// addrmode6 := reg with optional alignment 1268// 1269def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 1270def addrmode6 : MemOperand, 1271 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1272 let PrintMethod = "printAddrMode6Operand"; 1273 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1274 let EncoderMethod = "getAddrMode6AddressOpValue"; 1275 let DecoderMethod = "DecodeAddrMode6Operand"; 1276 let ParserMatchClass = AddrMode6AsmOperand; 1277} 1278 1279def am6offset : MemOperand, 1280 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 1281 [], [SDNPWantRoot]> { 1282 let PrintMethod = "printAddrMode6OffsetOperand"; 1283 let MIOperandInfo = (ops GPR); 1284 let EncoderMethod = "getAddrMode6OffsetOpValue"; 1285 let DecoderMethod = "DecodeGPRRegisterClass"; 1286} 1287 1288// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 1289// (single element from one lane) for size 32. 1290def addrmode6oneL32 : MemOperand, 1291 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1292 let PrintMethod = "printAddrMode6Operand"; 1293 let MIOperandInfo = (ops GPR:$addr, i32imm); 1294 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 1295} 1296 1297// Base class for addrmode6 with specific alignment restrictions. 1298class AddrMode6Align : MemOperand, 1299 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1300 let PrintMethod = "printAddrMode6Operand"; 1301 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1302 let EncoderMethod = "getAddrMode6AddressOpValue"; 1303 let DecoderMethod = "DecodeAddrMode6Operand"; 1304} 1305 1306// Special version of addrmode6 to handle no allowed alignment encoding for 1307// VLD/VST instructions and checking the alignment is not specified. 1308def AddrMode6AlignNoneAsmOperand : AsmOperandClass { 1309 let Name = "AlignedMemoryNone"; 1310 let DiagnosticString = "alignment must be omitted"; 1311} 1312def addrmode6alignNone : AddrMode6Align { 1313 // The alignment specifier can only be omitted. 1314 let ParserMatchClass = AddrMode6AlignNoneAsmOperand; 1315} 1316 1317// Special version of addrmode6 to handle 16-bit alignment encoding for 1318// VLD/VST instructions and checking the alignment value. 1319def AddrMode6Align16AsmOperand : AsmOperandClass { 1320 let Name = "AlignedMemory16"; 1321 let DiagnosticString = "alignment must be 16 or omitted"; 1322} 1323def addrmode6align16 : AddrMode6Align { 1324 // The alignment specifier can only be 16 or omitted. 1325 let ParserMatchClass = AddrMode6Align16AsmOperand; 1326} 1327 1328// Special version of addrmode6 to handle 32-bit alignment encoding for 1329// VLD/VST instructions and checking the alignment value. 1330def AddrMode6Align32AsmOperand : AsmOperandClass { 1331 let Name = "AlignedMemory32"; 1332 let DiagnosticString = "alignment must be 32 or omitted"; 1333} 1334def addrmode6align32 : AddrMode6Align { 1335 // The alignment specifier can only be 32 or omitted. 1336 let ParserMatchClass = AddrMode6Align32AsmOperand; 1337} 1338 1339// Special version of addrmode6 to handle 64-bit alignment encoding for 1340// VLD/VST instructions and checking the alignment value. 1341def AddrMode6Align64AsmOperand : AsmOperandClass { 1342 let Name = "AlignedMemory64"; 1343 let DiagnosticString = "alignment must be 64 or omitted"; 1344} 1345def addrmode6align64 : AddrMode6Align { 1346 // The alignment specifier can only be 64 or omitted. 1347 let ParserMatchClass = AddrMode6Align64AsmOperand; 1348} 1349 1350// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1351// for VLD/VST instructions and checking the alignment value. 1352def AddrMode6Align64or128AsmOperand : AsmOperandClass { 1353 let Name = "AlignedMemory64or128"; 1354 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1355} 1356def addrmode6align64or128 : AddrMode6Align { 1357 // The alignment specifier can only be 64, 128 or omitted. 1358 let ParserMatchClass = AddrMode6Align64or128AsmOperand; 1359} 1360 1361// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment 1362// encoding for VLD/VST instructions and checking the alignment value. 1363def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { 1364 let Name = "AlignedMemory64or128or256"; 1365 let DiagnosticString = "alignment must be 64, 128, 256 or omitted"; 1366} 1367def addrmode6align64or128or256 : AddrMode6Align { 1368 // The alignment specifier can only be 64, 128, 256 or omitted. 1369 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand; 1370} 1371 1372// Special version of addrmode6 to handle alignment encoding for VLD-dup 1373// instructions, specifically VLD4-dup. 1374def addrmode6dup : MemOperand, 1375 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1376 let PrintMethod = "printAddrMode6Operand"; 1377 let MIOperandInfo = (ops GPR:$addr, i32imm); 1378 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1379 // FIXME: This is close, but not quite right. The alignment specifier is 1380 // different. 1381 let ParserMatchClass = AddrMode6AsmOperand; 1382} 1383 1384// Base class for addrmode6dup with specific alignment restrictions. 1385class AddrMode6DupAlign : MemOperand, 1386 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1387 let PrintMethod = "printAddrMode6Operand"; 1388 let MIOperandInfo = (ops GPR:$addr, i32imm); 1389 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1390} 1391 1392// Special version of addrmode6 to handle no allowed alignment encoding for 1393// VLD-dup instruction and checking the alignment is not specified. 1394def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { 1395 let Name = "DupAlignedMemoryNone"; 1396 let DiagnosticString = "alignment must be omitted"; 1397} 1398def addrmode6dupalignNone : AddrMode6DupAlign { 1399 // The alignment specifier can only be omitted. 1400 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand; 1401} 1402 1403// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup 1404// instruction and checking the alignment value. 1405def AddrMode6dupAlign16AsmOperand : AsmOperandClass { 1406 let Name = "DupAlignedMemory16"; 1407 let DiagnosticString = "alignment must be 16 or omitted"; 1408} 1409def addrmode6dupalign16 : AddrMode6DupAlign { 1410 // The alignment specifier can only be 16 or omitted. 1411 let ParserMatchClass = AddrMode6dupAlign16AsmOperand; 1412} 1413 1414// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup 1415// instruction and checking the alignment value. 1416def AddrMode6dupAlign32AsmOperand : AsmOperandClass { 1417 let Name = "DupAlignedMemory32"; 1418 let DiagnosticString = "alignment must be 32 or omitted"; 1419} 1420def addrmode6dupalign32 : AddrMode6DupAlign { 1421 // The alignment specifier can only be 32 or omitted. 1422 let ParserMatchClass = AddrMode6dupAlign32AsmOperand; 1423} 1424 1425// Special version of addrmode6 to handle 64-bit alignment encoding for VLD 1426// instructions and checking the alignment value. 1427def AddrMode6dupAlign64AsmOperand : AsmOperandClass { 1428 let Name = "DupAlignedMemory64"; 1429 let DiagnosticString = "alignment must be 64 or omitted"; 1430} 1431def addrmode6dupalign64 : AddrMode6DupAlign { 1432 // The alignment specifier can only be 64 or omitted. 1433 let ParserMatchClass = AddrMode6dupAlign64AsmOperand; 1434} 1435 1436// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1437// for VLD instructions and checking the alignment value. 1438def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { 1439 let Name = "DupAlignedMemory64or128"; 1440 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1441} 1442def addrmode6dupalign64or128 : AddrMode6DupAlign { 1443 // The alignment specifier can only be 64, 128 or omitted. 1444 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand; 1445} 1446 1447// addrmodepc := pc + reg 1448// 1449def addrmodepc : MemOperand, 1450 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1451 let PrintMethod = "printAddrModePCOperand"; 1452 let MIOperandInfo = (ops GPR, i32imm); 1453} 1454 1455// addr_offset_none := reg 1456// 1457def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1458def addr_offset_none : MemOperand, 1459 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1460 let PrintMethod = "printAddrMode7Operand"; 1461 let DecoderMethod = "DecodeAddrMode7Operand"; 1462 let ParserMatchClass = MemNoOffsetAsmOperand; 1463 let MIOperandInfo = (ops GPR:$base); 1464} 1465 1466// t_addr_offset_none := reg [r0-r7] 1467def MemNoOffsetTAsmOperand : AsmOperandClass { let Name = "MemNoOffsetT"; } 1468def t_addr_offset_none : MemOperand { 1469 let PrintMethod = "printAddrMode7Operand"; 1470 let DecoderMethod = "DecodetGPRRegisterClass"; 1471 let ParserMatchClass = MemNoOffsetTAsmOperand; 1472 let MIOperandInfo = (ops tGPR:$base); 1473} 1474 1475def nohash_imm : Operand<i32> { 1476 let PrintMethod = "printNoHashImmediate"; 1477} 1478 1479def CoprocNumAsmOperand : AsmOperandClass { 1480 let Name = "CoprocNum"; 1481 let ParserMethod = "parseCoprocNumOperand"; 1482} 1483def p_imm : Operand<i32> { 1484 let PrintMethod = "printPImmediate"; 1485 let ParserMatchClass = CoprocNumAsmOperand; 1486 let DecoderMethod = "DecodeCoprocessor"; 1487} 1488 1489def CoprocRegAsmOperand : AsmOperandClass { 1490 let Name = "CoprocReg"; 1491 let ParserMethod = "parseCoprocRegOperand"; 1492} 1493def c_imm : Operand<i32> { 1494 let PrintMethod = "printCImmediate"; 1495 let ParserMatchClass = CoprocRegAsmOperand; 1496} 1497def CoprocOptionAsmOperand : AsmOperandClass { 1498 let Name = "CoprocOption"; 1499 let ParserMethod = "parseCoprocOptionOperand"; 1500} 1501def coproc_option_imm : Operand<i32> { 1502 let PrintMethod = "printCoprocOptionImm"; 1503 let ParserMatchClass = CoprocOptionAsmOperand; 1504} 1505 1506//===----------------------------------------------------------------------===// 1507 1508include "ARMInstrFormats.td" 1509 1510//===----------------------------------------------------------------------===// 1511// Multiclass helpers... 1512// 1513 1514/// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a 1515/// binop that produces a value. 1516let TwoOperandAliasConstraint = "$Rn = $Rd" in 1517multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1518 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1519 SDPatternOperator opnode, bit Commutable = 0> { 1520 // The register-immediate version is re-materializable. This is useful 1521 // in particular for taking the address of a local. 1522 let isReMaterializable = 1 in { 1523 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1524 iii, opc, "\t$Rd, $Rn, $imm", 1525 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>, 1526 Sched<[WriteALU, ReadALU]> { 1527 bits<4> Rd; 1528 bits<4> Rn; 1529 bits<12> imm; 1530 let Inst{25} = 1; 1531 let Inst{19-16} = Rn; 1532 let Inst{15-12} = Rd; 1533 let Inst{11-0} = imm; 1534 } 1535 } 1536 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1537 iir, opc, "\t$Rd, $Rn, $Rm", 1538 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1539 Sched<[WriteALU, ReadALU, ReadALU]> { 1540 bits<4> Rd; 1541 bits<4> Rn; 1542 bits<4> Rm; 1543 let Inst{25} = 0; 1544 let isCommutable = Commutable; 1545 let Inst{19-16} = Rn; 1546 let Inst{15-12} = Rd; 1547 let Inst{11-4} = 0b00000000; 1548 let Inst{3-0} = Rm; 1549 } 1550 1551 def rsi : AsI1<opcod, (outs GPR:$Rd), 1552 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1553 iis, opc, "\t$Rd, $Rn, $shift", 1554 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1555 Sched<[WriteALUsi, ReadALU]> { 1556 bits<4> Rd; 1557 bits<4> Rn; 1558 bits<12> shift; 1559 let Inst{25} = 0; 1560 let Inst{19-16} = Rn; 1561 let Inst{15-12} = Rd; 1562 let Inst{11-5} = shift{11-5}; 1563 let Inst{4} = 0; 1564 let Inst{3-0} = shift{3-0}; 1565 } 1566 1567 def rsr : AsI1<opcod, (outs GPR:$Rd), 1568 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1569 iis, opc, "\t$Rd, $Rn, $shift", 1570 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1571 Sched<[WriteALUsr, ReadALUsr]> { 1572 bits<4> Rd; 1573 bits<4> Rn; 1574 bits<12> shift; 1575 let Inst{25} = 0; 1576 let Inst{19-16} = Rn; 1577 let Inst{15-12} = Rd; 1578 let Inst{11-8} = shift{11-8}; 1579 let Inst{7} = 0; 1580 let Inst{6-5} = shift{6-5}; 1581 let Inst{4} = 1; 1582 let Inst{3-0} = shift{3-0}; 1583 } 1584} 1585 1586/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1587/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1588/// it is equivalent to the AsI1_bin_irs counterpart. 1589let TwoOperandAliasConstraint = "$Rn = $Rd" in 1590multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1591 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1592 SDNode opnode> { 1593 // The register-immediate version is re-materializable. This is useful 1594 // in particular for taking the address of a local. 1595 let isReMaterializable = 1 in { 1596 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1597 iii, opc, "\t$Rd, $Rn, $imm", 1598 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>, 1599 Sched<[WriteALU, ReadALU]> { 1600 bits<4> Rd; 1601 bits<4> Rn; 1602 bits<12> imm; 1603 let Inst{25} = 1; 1604 let Inst{19-16} = Rn; 1605 let Inst{15-12} = Rd; 1606 let Inst{11-0} = imm; 1607 } 1608 } 1609 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1610 iir, opc, "\t$Rd, $Rn, $Rm", 1611 [/* pattern left blank */]>, 1612 Sched<[WriteALU, ReadALU, ReadALU]> { 1613 bits<4> Rd; 1614 bits<4> Rn; 1615 bits<4> Rm; 1616 let Inst{11-4} = 0b00000000; 1617 let Inst{25} = 0; 1618 let Inst{3-0} = Rm; 1619 let Inst{15-12} = Rd; 1620 let Inst{19-16} = Rn; 1621 } 1622 1623 def rsi : AsI1<opcod, (outs GPR:$Rd), 1624 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1625 iis, opc, "\t$Rd, $Rn, $shift", 1626 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1627 Sched<[WriteALUsi, ReadALU]> { 1628 bits<4> Rd; 1629 bits<4> Rn; 1630 bits<12> shift; 1631 let Inst{25} = 0; 1632 let Inst{19-16} = Rn; 1633 let Inst{15-12} = Rd; 1634 let Inst{11-5} = shift{11-5}; 1635 let Inst{4} = 0; 1636 let Inst{3-0} = shift{3-0}; 1637 } 1638 1639 def rsr : AsI1<opcod, (outs GPR:$Rd), 1640 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1641 iis, opc, "\t$Rd, $Rn, $shift", 1642 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1643 Sched<[WriteALUsr, ReadALUsr]> { 1644 bits<4> Rd; 1645 bits<4> Rn; 1646 bits<12> shift; 1647 let Inst{25} = 0; 1648 let Inst{19-16} = Rn; 1649 let Inst{15-12} = Rd; 1650 let Inst{11-8} = shift{11-8}; 1651 let Inst{7} = 0; 1652 let Inst{6-5} = shift{6-5}; 1653 let Inst{4} = 1; 1654 let Inst{3-0} = shift{3-0}; 1655 } 1656} 1657 1658/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1659/// 1660/// These opcodes will be converted to the real non-S opcodes by 1661/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1662let hasPostISelHook = 1, Defs = [CPSR] in { 1663multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1664 InstrItinClass iis, SDNode opnode, 1665 bit Commutable = 0> { 1666 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1667 4, iii, 1668 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>, 1669 Sched<[WriteALU, ReadALU]>; 1670 1671 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1672 4, iir, 1673 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1674 Sched<[WriteALU, ReadALU, ReadALU]> { 1675 let isCommutable = Commutable; 1676 } 1677 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1678 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1679 4, iis, 1680 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1681 so_reg_imm:$shift))]>, 1682 Sched<[WriteALUsi, ReadALU]>; 1683 1684 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1685 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1686 4, iis, 1687 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1688 so_reg_reg:$shift))]>, 1689 Sched<[WriteALUSsr, ReadALUsr]>; 1690} 1691} 1692 1693/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1694/// operands are reversed. 1695let hasPostISelHook = 1, Defs = [CPSR] in { 1696multiclass AsI1_rbin_s_is<InstrItinClass iii, 1697 InstrItinClass iis, SDNode opnode> { 1698 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1699 4, iii, 1700 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>, 1701 Sched<[WriteALU, ReadALU]>; 1702 1703 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1704 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1705 4, iis, 1706 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1707 GPR:$Rn))]>, 1708 Sched<[WriteALUsi, ReadALU]>; 1709 1710 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1711 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1712 4, iis, 1713 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1714 GPR:$Rn))]>, 1715 Sched<[WriteALUSsr, ReadALUsr]>; 1716} 1717} 1718 1719/// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test 1720/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1721/// a explicit result, only implicitly set CPSR. 1722let isCompare = 1, Defs = [CPSR] in { 1723multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1724 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1725 SDPatternOperator opnode, bit Commutable = 0, 1726 string rrDecoderMethod = ""> { 1727 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii, 1728 opc, "\t$Rn, $imm", 1729 [(opnode GPR:$Rn, mod_imm:$imm)]>, 1730 Sched<[WriteCMP, ReadALU]> { 1731 bits<4> Rn; 1732 bits<12> imm; 1733 let Inst{25} = 1; 1734 let Inst{20} = 1; 1735 let Inst{19-16} = Rn; 1736 let Inst{15-12} = 0b0000; 1737 let Inst{11-0} = imm; 1738 1739 let Unpredictable{15-12} = 0b1111; 1740 } 1741 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1742 opc, "\t$Rn, $Rm", 1743 [(opnode GPR:$Rn, GPR:$Rm)]>, 1744 Sched<[WriteCMP, ReadALU, ReadALU]> { 1745 bits<4> Rn; 1746 bits<4> Rm; 1747 let isCommutable = Commutable; 1748 let Inst{25} = 0; 1749 let Inst{20} = 1; 1750 let Inst{19-16} = Rn; 1751 let Inst{15-12} = 0b0000; 1752 let Inst{11-4} = 0b00000000; 1753 let Inst{3-0} = Rm; 1754 let DecoderMethod = rrDecoderMethod; 1755 1756 let Unpredictable{15-12} = 0b1111; 1757 } 1758 def rsi : AI1<opcod, (outs), 1759 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1760 opc, "\t$Rn, $shift", 1761 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1762 Sched<[WriteCMPsi, ReadALU]> { 1763 bits<4> Rn; 1764 bits<12> shift; 1765 let Inst{25} = 0; 1766 let Inst{20} = 1; 1767 let Inst{19-16} = Rn; 1768 let Inst{15-12} = 0b0000; 1769 let Inst{11-5} = shift{11-5}; 1770 let Inst{4} = 0; 1771 let Inst{3-0} = shift{3-0}; 1772 1773 let Unpredictable{15-12} = 0b1111; 1774 } 1775 def rsr : AI1<opcod, (outs), 1776 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1777 opc, "\t$Rn, $shift", 1778 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1779 Sched<[WriteCMPsr, ReadALU]> { 1780 bits<4> Rn; 1781 bits<12> shift; 1782 let Inst{25} = 0; 1783 let Inst{20} = 1; 1784 let Inst{19-16} = Rn; 1785 let Inst{15-12} = 0b0000; 1786 let Inst{11-8} = shift{11-8}; 1787 let Inst{7} = 0; 1788 let Inst{6-5} = shift{6-5}; 1789 let Inst{4} = 1; 1790 let Inst{3-0} = shift{3-0}; 1791 1792 let Unpredictable{15-12} = 0b1111; 1793 } 1794 1795} 1796} 1797 1798/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1799/// register and one whose operand is a register rotated by 8/16/24. 1800/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1801class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1802 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1803 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1804 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1805 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1806 bits<4> Rd; 1807 bits<4> Rm; 1808 bits<2> rot; 1809 let Inst{19-16} = 0b1111; 1810 let Inst{15-12} = Rd; 1811 let Inst{11-10} = rot; 1812 let Inst{3-0} = Rm; 1813} 1814 1815class AI_ext_rrot_np<bits<8> opcod, string opc> 1816 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1817 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1818 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1819 bits<2> rot; 1820 let Inst{19-16} = 0b1111; 1821 let Inst{11-10} = rot; 1822 } 1823 1824/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1825/// register and one whose operand is a register rotated by 8/16/24. 1826class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1827 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1828 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1829 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1830 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1831 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1832 bits<4> Rd; 1833 bits<4> Rm; 1834 bits<4> Rn; 1835 bits<2> rot; 1836 let Inst{19-16} = Rn; 1837 let Inst{15-12} = Rd; 1838 let Inst{11-10} = rot; 1839 let Inst{9-4} = 0b000111; 1840 let Inst{3-0} = Rm; 1841} 1842 1843class AI_exta_rrot_np<bits<8> opcod, string opc> 1844 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1845 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1846 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1847 bits<4> Rn; 1848 bits<2> rot; 1849 let Inst{19-16} = Rn; 1850 let Inst{11-10} = rot; 1851} 1852 1853/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1854let TwoOperandAliasConstraint = "$Rn = $Rd" in 1855multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode, 1856 bit Commutable = 0> { 1857 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1858 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1859 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1860 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>, 1861 Requires<[IsARM]>, 1862 Sched<[WriteALU, ReadALU]> { 1863 bits<4> Rd; 1864 bits<4> Rn; 1865 bits<12> imm; 1866 let Inst{25} = 1; 1867 let Inst{15-12} = Rd; 1868 let Inst{19-16} = Rn; 1869 let Inst{11-0} = imm; 1870 } 1871 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1872 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1873 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1874 Requires<[IsARM]>, 1875 Sched<[WriteALU, ReadALU, ReadALU]> { 1876 bits<4> Rd; 1877 bits<4> Rn; 1878 bits<4> Rm; 1879 let Inst{11-4} = 0b00000000; 1880 let Inst{25} = 0; 1881 let isCommutable = Commutable; 1882 let Inst{3-0} = Rm; 1883 let Inst{15-12} = Rd; 1884 let Inst{19-16} = Rn; 1885 } 1886 def rsi : AsI1<opcod, (outs GPR:$Rd), 1887 (ins GPR:$Rn, so_reg_imm:$shift), 1888 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1889 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1890 Requires<[IsARM]>, 1891 Sched<[WriteALUsi, ReadALU]> { 1892 bits<4> Rd; 1893 bits<4> Rn; 1894 bits<12> shift; 1895 let Inst{25} = 0; 1896 let Inst{19-16} = Rn; 1897 let Inst{15-12} = Rd; 1898 let Inst{11-5} = shift{11-5}; 1899 let Inst{4} = 0; 1900 let Inst{3-0} = shift{3-0}; 1901 } 1902 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1903 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1904 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1905 [(set GPRnopc:$Rd, CPSR, 1906 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1907 Requires<[IsARM]>, 1908 Sched<[WriteALUsr, ReadALUsr]> { 1909 bits<4> Rd; 1910 bits<4> Rn; 1911 bits<12> shift; 1912 let Inst{25} = 0; 1913 let Inst{19-16} = Rn; 1914 let Inst{15-12} = Rd; 1915 let Inst{11-8} = shift{11-8}; 1916 let Inst{7} = 0; 1917 let Inst{6-5} = shift{6-5}; 1918 let Inst{4} = 1; 1919 let Inst{3-0} = shift{3-0}; 1920 } 1921 } 1922} 1923 1924/// AI1_rsc_irs - Define instructions and patterns for rsc 1925let TwoOperandAliasConstraint = "$Rn = $Rd" in 1926multiclass AI1_rsc_irs<bits<4> opcod, string opc, SDNode opnode> { 1927 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1928 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1929 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1930 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>, 1931 Requires<[IsARM]>, 1932 Sched<[WriteALU, ReadALU]> { 1933 bits<4> Rd; 1934 bits<4> Rn; 1935 bits<12> imm; 1936 let Inst{25} = 1; 1937 let Inst{15-12} = Rd; 1938 let Inst{19-16} = Rn; 1939 let Inst{11-0} = imm; 1940 } 1941 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1942 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1943 [/* pattern left blank */]>, 1944 Sched<[WriteALU, ReadALU, ReadALU]> { 1945 bits<4> Rd; 1946 bits<4> Rn; 1947 bits<4> Rm; 1948 let Inst{11-4} = 0b00000000; 1949 let Inst{25} = 0; 1950 let Inst{3-0} = Rm; 1951 let Inst{15-12} = Rd; 1952 let Inst{19-16} = Rn; 1953 } 1954 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1955 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1956 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1957 Requires<[IsARM]>, 1958 Sched<[WriteALUsi, ReadALU]> { 1959 bits<4> Rd; 1960 bits<4> Rn; 1961 bits<12> shift; 1962 let Inst{25} = 0; 1963 let Inst{19-16} = Rn; 1964 let Inst{15-12} = Rd; 1965 let Inst{11-5} = shift{11-5}; 1966 let Inst{4} = 0; 1967 let Inst{3-0} = shift{3-0}; 1968 } 1969 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1970 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1971 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1972 Requires<[IsARM]>, 1973 Sched<[WriteALUsr, ReadALUsr]> { 1974 bits<4> Rd; 1975 bits<4> Rn; 1976 bits<12> shift; 1977 let Inst{25} = 0; 1978 let Inst{19-16} = Rn; 1979 let Inst{15-12} = Rd; 1980 let Inst{11-8} = shift{11-8}; 1981 let Inst{7} = 0; 1982 let Inst{6-5} = shift{6-5}; 1983 let Inst{4} = 1; 1984 let Inst{3-0} = shift{3-0}; 1985 } 1986 } 1987} 1988 1989let canFoldAsLoad = 1, isReMaterializable = 1 in { 1990multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1991 InstrItinClass iir, PatFrag opnode> { 1992 // Note: We use the complex addrmode_imm12 rather than just an input 1993 // GPR and a constrained immediate so that we can use this to match 1994 // frame index references and avoid matching constant pool references. 1995 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1996 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1997 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1998 bits<4> Rt; 1999 bits<17> addr; 2000 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2001 let Inst{19-16} = addr{16-13}; // Rn 2002 let Inst{15-12} = Rt; 2003 let Inst{11-0} = addr{11-0}; // imm12 2004 } 2005 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 2006 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 2007 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 2008 bits<4> Rt; 2009 bits<17> shift; 2010 let shift{4} = 0; // Inst{4} = 0 2011 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2012 let Inst{19-16} = shift{16-13}; // Rn 2013 let Inst{15-12} = Rt; 2014 let Inst{11-0} = shift{11-0}; 2015 } 2016} 2017} 2018 2019let canFoldAsLoad = 1, isReMaterializable = 1 in { 2020multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 2021 InstrItinClass iir, PatFrag opnode> { 2022 // Note: We use the complex addrmode_imm12 rather than just an input 2023 // GPR and a constrained immediate so that we can use this to match 2024 // frame index references and avoid matching constant pool references. 2025 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 2026 (ins addrmode_imm12:$addr), 2027 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 2028 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 2029 bits<4> Rt; 2030 bits<17> addr; 2031 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2032 let Inst{19-16} = addr{16-13}; // Rn 2033 let Inst{15-12} = Rt; 2034 let Inst{11-0} = addr{11-0}; // imm12 2035 } 2036 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 2037 (ins ldst_so_reg:$shift), 2038 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 2039 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 2040 bits<4> Rt; 2041 bits<17> shift; 2042 let shift{4} = 0; // Inst{4} = 0 2043 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2044 let Inst{19-16} = shift{16-13}; // Rn 2045 let Inst{15-12} = Rt; 2046 let Inst{11-0} = shift{11-0}; 2047 } 2048} 2049} 2050 2051 2052multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 2053 InstrItinClass iir, PatFrag opnode> { 2054 // Note: We use the complex addrmode_imm12 rather than just an input 2055 // GPR and a constrained immediate so that we can use this to match 2056 // frame index references and avoid matching constant pool references. 2057 def i12 : AI2ldst<0b010, 0, isByte, (outs), 2058 (ins GPR:$Rt, addrmode_imm12:$addr), 2059 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 2060 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 2061 bits<4> Rt; 2062 bits<17> addr; 2063 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2064 let Inst{19-16} = addr{16-13}; // Rn 2065 let Inst{15-12} = Rt; 2066 let Inst{11-0} = addr{11-0}; // imm12 2067 } 2068 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 2069 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 2070 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 2071 bits<4> Rt; 2072 bits<17> shift; 2073 let shift{4} = 0; // Inst{4} = 0 2074 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2075 let Inst{19-16} = shift{16-13}; // Rn 2076 let Inst{15-12} = Rt; 2077 let Inst{11-0} = shift{11-0}; 2078 } 2079} 2080 2081multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 2082 InstrItinClass iir, PatFrag opnode> { 2083 // Note: We use the complex addrmode_imm12 rather than just an input 2084 // GPR and a constrained immediate so that we can use this to match 2085 // frame index references and avoid matching constant pool references. 2086 def i12 : AI2ldst<0b010, 0, isByte, (outs), 2087 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 2088 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 2089 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 2090 bits<4> Rt; 2091 bits<17> addr; 2092 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2093 let Inst{19-16} = addr{16-13}; // Rn 2094 let Inst{15-12} = Rt; 2095 let Inst{11-0} = addr{11-0}; // imm12 2096 } 2097 def rs : AI2ldst<0b011, 0, isByte, (outs), 2098 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 2099 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 2100 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 2101 bits<4> Rt; 2102 bits<17> shift; 2103 let shift{4} = 0; // Inst{4} = 0 2104 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2105 let Inst{19-16} = shift{16-13}; // Rn 2106 let Inst{15-12} = Rt; 2107 let Inst{11-0} = shift{11-0}; 2108 } 2109} 2110 2111 2112//===----------------------------------------------------------------------===// 2113// Instructions 2114//===----------------------------------------------------------------------===// 2115 2116//===----------------------------------------------------------------------===// 2117// Miscellaneous Instructions. 2118// 2119 2120/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 2121/// the function. The first operand is the ID# for this instruction, the second 2122/// is the index into the MachineConstantPool that this is, the third is the 2123/// size in bytes of this constant pool entry. 2124let hasSideEffects = 0, isNotDuplicable = 1, hasNoSchedulingInfo = 1 in 2125def CONSTPOOL_ENTRY : 2126PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2127 i32imm:$size), NoItinerary, []>; 2128 2129/// A jumptable consisting of direct 32-bit addresses of the destination basic 2130/// blocks (either absolute, or relative to the start of the jump-table in PIC 2131/// mode). Used mostly in ARM and Thumb-1 modes. 2132def JUMPTABLE_ADDRS : 2133PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2134 i32imm:$size), NoItinerary, []>; 2135 2136/// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables 2137/// that cannot be optimised to use TBB or TBH. 2138def JUMPTABLE_INSTS : 2139PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2140 i32imm:$size), NoItinerary, []>; 2141 2142/// A jumptable consisting of 8-bit unsigned integers representing offsets from 2143/// a TBB instruction. 2144def JUMPTABLE_TBB : 2145PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2146 i32imm:$size), NoItinerary, []>; 2147 2148/// A jumptable consisting of 16-bit unsigned integers representing offsets from 2149/// a TBH instruction. 2150def JUMPTABLE_TBH : 2151PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2152 i32imm:$size), NoItinerary, []>; 2153 2154 2155// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 2156// from removing one half of the matched pairs. That breaks PEI, which assumes 2157// these will always be in pairs, and asserts if it finds otherwise. Better way? 2158let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 2159def ADJCALLSTACKUP : 2160PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 2161 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 2162 2163def ADJCALLSTACKDOWN : 2164PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2, pred:$p), NoItinerary, 2165 [(ARMcallseq_start timm:$amt, timm:$amt2)]>; 2166} 2167 2168def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 2169 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>, 2170 Requires<[IsARM, HasV6]> { 2171 bits<8> imm; 2172 let Inst{27-8} = 0b00110010000011110000; 2173 let Inst{7-0} = imm; 2174 let DecoderMethod = "DecodeHINTInstruction"; 2175} 2176 2177def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>; 2178def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>; 2179def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>; 2180def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>; 2181def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>; 2182def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 2183def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>; 2184def : InstAlias<"csdb$p", (HINT 20, pred:$p)>, Requires<[IsARM, HasV6K]>; 2185 2186def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 2187 "\t$Rd, $Rn, $Rm", 2188 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>, 2189 Requires<[IsARM, HasV6]> { 2190 bits<4> Rd; 2191 bits<4> Rn; 2192 bits<4> Rm; 2193 let Inst{3-0} = Rm; 2194 let Inst{15-12} = Rd; 2195 let Inst{19-16} = Rn; 2196 let Inst{27-20} = 0b01101000; 2197 let Inst{7-4} = 0b1011; 2198 let Inst{11-8} = 0b1111; 2199 let Unpredictable{11-8} = 0b1111; 2200} 2201 2202// The 16-bit operand $val can be used by a debugger to store more information 2203// about the breakpoint. 2204def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2205 "bkpt", "\t$val", []>, Requires<[IsARM]> { 2206 bits<16> val; 2207 let Inst{3-0} = val{3-0}; 2208 let Inst{19-8} = val{15-4}; 2209 let Inst{27-20} = 0b00010010; 2210 let Inst{31-28} = 0xe; // AL 2211 let Inst{7-4} = 0b0111; 2212} 2213// default immediate for breakpoint mnemonic 2214def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>; 2215 2216def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2217 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 2218 bits<16> val; 2219 let Inst{3-0} = val{3-0}; 2220 let Inst{19-8} = val{15-4}; 2221 let Inst{27-20} = 0b00010000; 2222 let Inst{31-28} = 0xe; // AL 2223 let Inst{7-4} = 0b0111; 2224} 2225 2226// Change Processor State 2227// FIXME: We should use InstAlias to handle the optional operands. 2228class CPS<dag iops, string asm_ops> 2229 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 2230 []>, Requires<[IsARM]> { 2231 bits<2> imod; 2232 bits<3> iflags; 2233 bits<5> mode; 2234 bit M; 2235 2236 let Inst{31-28} = 0b1111; 2237 let Inst{27-20} = 0b00010000; 2238 let Inst{19-18} = imod; 2239 let Inst{17} = M; // Enabled if mode is set; 2240 let Inst{16-9} = 0b00000000; 2241 let Inst{8-6} = iflags; 2242 let Inst{5} = 0; 2243 let Inst{4-0} = mode; 2244} 2245 2246let DecoderMethod = "DecodeCPSInstruction" in { 2247let M = 1 in 2248 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 2249 "$imod\t$iflags, $mode">; 2250let mode = 0, M = 0 in 2251 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 2252 2253let imod = 0, iflags = 0, M = 1 in 2254 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 2255} 2256 2257// Preload signals the memory system of possible future data/instruction access. 2258multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 2259 2260 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, 2261 IIC_Preload, !strconcat(opc, "\t$addr"), 2262 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 2263 Sched<[WritePreLd]> { 2264 bits<4> Rt; 2265 bits<17> addr; 2266 let Inst{31-26} = 0b111101; 2267 let Inst{25} = 0; // 0 for immediate form 2268 let Inst{24} = data; 2269 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2270 let Inst{22} = read; 2271 let Inst{21-20} = 0b01; 2272 let Inst{19-16} = addr{16-13}; // Rn 2273 let Inst{15-12} = 0b1111; 2274 let Inst{11-0} = addr{11-0}; // imm12 2275 } 2276 2277 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 2278 !strconcat(opc, "\t$shift"), 2279 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 2280 Sched<[WritePreLd]> { 2281 bits<17> shift; 2282 let Inst{31-26} = 0b111101; 2283 let Inst{25} = 1; // 1 for register form 2284 let Inst{24} = data; 2285 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2286 let Inst{22} = read; 2287 let Inst{21-20} = 0b01; 2288 let Inst{19-16} = shift{16-13}; // Rn 2289 let Inst{15-12} = 0b1111; 2290 let Inst{11-0} = shift{11-0}; 2291 let Inst{4} = 0; 2292 } 2293} 2294 2295defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 2296defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 2297defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 2298 2299def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 2300 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 2301 bits<1> end; 2302 let Inst{31-10} = 0b1111000100000001000000; 2303 let Inst{9} = end; 2304 let Inst{8-0} = 0; 2305} 2306 2307def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 2308 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> { 2309 bits<4> opt; 2310 let Inst{27-4} = 0b001100100000111100001111; 2311 let Inst{3-0} = opt; 2312} 2313 2314// A8.8.247 UDF - Undefined (Encoding A1) 2315def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, 2316 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { 2317 bits<16> imm16; 2318 let Inst{31-28} = 0b1110; // AL 2319 let Inst{27-25} = 0b011; 2320 let Inst{24-20} = 0b11111; 2321 let Inst{19-8} = imm16{15-4}; 2322 let Inst{7-4} = 0b1111; 2323 let Inst{3-0} = imm16{3-0}; 2324} 2325 2326/* 2327 * A5.4 Permanently UNDEFINED instructions. 2328 * 2329 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 2330 * Other UDF encodings generate SIGILL. 2331 * 2332 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 2333 * Encoding A1: 2334 * 1110 0111 1111 iiii iiii iiii 1111 iiii 2335 * Encoding T1: 2336 * 1101 1110 iiii iiii 2337 * It uses the following encoding: 2338 * 1110 0111 1111 1110 1101 1110 1111 0000 2339 * - In ARM: UDF #60896; 2340 * - In Thumb: UDF #254 followed by a branch-to-self. 2341 */ 2342let isBarrier = 1, isTerminator = 1 in 2343def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 2344 "trap", [(trap)]>, 2345 Requires<[IsARM,UseNaClTrap]> { 2346 let Inst = 0xe7fedef0; 2347} 2348let isBarrier = 1, isTerminator = 1 in 2349def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 2350 "trap", [(trap)]>, 2351 Requires<[IsARM,DontUseNaClTrap]> { 2352 let Inst = 0xe7ffdefe; 2353} 2354 2355def : Pat<(debugtrap), (BKPT 0)>, Requires<[IsARM, HasV5T]>; 2356def : Pat<(debugtrap), (UDF 254)>, Requires<[IsARM, NoV5T]>; 2357 2358// Address computation and loads and stores in PIC mode. 2359let isNotDuplicable = 1 in { 2360def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 2361 4, IIC_iALUr, 2362 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 2363 Sched<[WriteALU, ReadALU]>; 2364 2365let AddedComplexity = 10 in { 2366def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 2367 4, IIC_iLoad_r, 2368 [(set GPR:$dst, (load addrmodepc:$addr))]>; 2369 2370def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2371 4, IIC_iLoad_bh_r, 2372 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 2373 2374def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2375 4, IIC_iLoad_bh_r, 2376 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 2377 2378def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2379 4, IIC_iLoad_bh_r, 2380 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 2381 2382def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2383 4, IIC_iLoad_bh_r, 2384 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 2385} 2386let AddedComplexity = 10 in { 2387def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2388 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 2389 2390def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2391 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 2392 addrmodepc:$addr)]>; 2393 2394def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2395 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 2396} 2397} // isNotDuplicable = 1 2398 2399 2400// LEApcrel - Load a pc-relative address into a register without offending the 2401// assembler. 2402let hasSideEffects = 0, isReMaterializable = 1 in 2403// The 'adr' mnemonic encodes differently if the label is before or after 2404// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 2405// know until then which form of the instruction will be used. 2406def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 2407 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 2408 Sched<[WriteALU, ReadALU]> { 2409 bits<4> Rd; 2410 bits<14> label; 2411 let Inst{27-25} = 0b001; 2412 let Inst{24} = 0; 2413 let Inst{23-22} = label{13-12}; 2414 let Inst{21} = 0; 2415 let Inst{20} = 0; 2416 let Inst{19-16} = 0b1111; 2417 let Inst{15-12} = Rd; 2418 let Inst{11-0} = label{11-0}; 2419} 2420 2421let hasSideEffects = 1 in { 2422def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 2423 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2424 2425def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 2426 (ins i32imm:$label, pred:$p), 2427 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2428} 2429 2430//===----------------------------------------------------------------------===// 2431// Control Flow Instructions. 2432// 2433 2434let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 2435 // ARMV4T and above 2436 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2437 "bx", "\tlr", [(ARMretflag)]>, 2438 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2439 let Inst{27-0} = 0b0001001011111111111100011110; 2440 } 2441 2442 // ARMV4 only 2443 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2444 "mov", "\tpc, lr", [(ARMretflag)]>, 2445 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 2446 let Inst{27-0} = 0b0001101000001111000000001110; 2447 } 2448 2449 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 2450 // the user-space one). 2451 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 2452 4, IIC_Br, 2453 [(ARMintretflag imm:$offset)]>; 2454} 2455 2456// Indirect branches 2457let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 2458 // ARMV4T and above 2459 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 2460 [(brind GPR:$dst)]>, 2461 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2462 bits<4> dst; 2463 let Inst{31-4} = 0b1110000100101111111111110001; 2464 let Inst{3-0} = dst; 2465 } 2466 2467 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 2468 "bx", "\t$dst", [/* pattern left blank */]>, 2469 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2470 bits<4> dst; 2471 let Inst{27-4} = 0b000100101111111111110001; 2472 let Inst{3-0} = dst; 2473 } 2474} 2475 2476// SP is marked as a use to prevent stack-pointer assignments that appear 2477// immediately before calls from potentially appearing dead. 2478let isCall = 1, 2479 // FIXME: Do we really need a non-predicated version? If so, it should 2480 // at least be a pseudo instruction expanding to the predicated version 2481 // at MC lowering time. 2482 Defs = [LR], Uses = [SP] in { 2483 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func), 2484 IIC_Br, "bl\t$func", 2485 [(ARMcall tglobaladdr:$func)]>, 2486 Requires<[IsARM]>, Sched<[WriteBrL]> { 2487 let Inst{31-28} = 0b1110; 2488 bits<24> func; 2489 let Inst{23-0} = func; 2490 let DecoderMethod = "DecodeBranchImmInstruction"; 2491 } 2492 2493 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func), 2494 IIC_Br, "bl", "\t$func", 2495 [(ARMcall_pred tglobaladdr:$func)]>, 2496 Requires<[IsARM]>, Sched<[WriteBrL]> { 2497 bits<24> func; 2498 let Inst{23-0} = func; 2499 let DecoderMethod = "DecodeBranchImmInstruction"; 2500 } 2501 2502 // ARMv5T and above 2503 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, IIC_Br, "blx\t$func", []>, 2504 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2505 bits<4> func; 2506 let Inst{31-4} = 0b1110000100101111111111110011; 2507 let Inst{3-0} = func; 2508 } 2509 def BLX_noip : ARMPseudoExpand<(outs), (ins GPRnoip:$func), 2510 4, IIC_Br, [], (BLX GPR:$func)>, 2511 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]>; 2512 2513 2514 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2515 IIC_Br, "blx", "\t$func", []>, 2516 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2517 bits<4> func; 2518 let Inst{27-4} = 0b000100101111111111110011; 2519 let Inst{3-0} = func; 2520 } 2521 def BLX_pred_noip : ARMPseudoExpand<(outs), (ins GPRnoip:$func), 2522 4, IIC_Br, [], 2523 (BLX_pred GPR:$func, (ops 14, zero_reg))>, 2524 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]>; 2525 2526 2527 // ARMv4T 2528 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2529 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2530 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2531 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2532 2533 // ARMv4 2534 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2535 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2536 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2537 2538 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2539 // return stack predictor. 2540 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins arm_bl_target:$func), 2541 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2542 Requires<[IsARM]>, Sched<[WriteBr]>; 2543 2544 // push lr before the call 2545 def BL_PUSHLR : ARMPseudoInst<(outs), (ins GPRlr:$ra, arm_bl_target:$func), 2546 4, IIC_Br, 2547 []>, 2548 Requires<[IsARM]>, Sched<[WriteBr]>; 2549} 2550 2551def : ARMPat<(ARMcall GPR:$func), (BLX $func)>, 2552 Requires<[IsARM, HasV5T, NoSLSBLRMitigation]>; 2553def : ARMPat<(ARMcall GPRnoip:$func), (BLX_noip $func)>, 2554 Requires<[IsARM, HasV5T, SLSBLRMitigation]>; 2555def : ARMPat<(ARMcall_pred GPR:$func), (BLX_pred $func)>, 2556 Requires<[IsARM, HasV5T, NoSLSBLRMitigation]>; 2557def : ARMPat<(ARMcall_pred GPRnoip:$func), (BLX_pred_noip $func)>, 2558 Requires<[IsARM, HasV5T, SLSBLRMitigation]>; 2559 2560 2561let isBranch = 1, isTerminator = 1 in { 2562 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2563 // a two-value operand where a dag node expects two operands. :( 2564 def Bcc : ABI<0b1010, (outs), (ins arm_br_target:$target), 2565 IIC_Br, "b", "\t$target", 2566 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2567 Sched<[WriteBr]> { 2568 bits<24> target; 2569 let Inst{23-0} = target; 2570 let DecoderMethod = "DecodeBranchImmInstruction"; 2571 } 2572 2573 let isBarrier = 1 in { 2574 // B is "predicable" since it's just a Bcc with an 'always' condition. 2575 let isPredicable = 1 in 2576 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2577 // should be sufficient. 2578 // FIXME: Is B really a Barrier? That doesn't seem right. 2579 def B : ARMPseudoExpand<(outs), (ins arm_br_target:$target), 4, IIC_Br, 2580 [(br bb:$target)], (Bcc arm_br_target:$target, 2581 (ops 14, zero_reg))>, 2582 Sched<[WriteBr]>; 2583 2584 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in { 2585 def BR_JTr : ARMPseudoInst<(outs), 2586 (ins GPR:$target, i32imm:$jt), 2587 0, IIC_Br, 2588 [(ARMbrjt GPR:$target, tjumptable:$jt)]>, 2589 Sched<[WriteBr]>; 2590 def BR_JTm_i12 : ARMPseudoInst<(outs), 2591 (ins addrmode_imm12:$target, i32imm:$jt), 2592 0, IIC_Br, 2593 [(ARMbrjt (i32 (load addrmode_imm12:$target)), 2594 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2595 def BR_JTm_rs : ARMPseudoInst<(outs), 2596 (ins ldst_so_reg:$target, i32imm:$jt), 2597 0, IIC_Br, 2598 [(ARMbrjt (i32 (load ldst_so_reg:$target)), 2599 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2600 def BR_JTadd : ARMPseudoInst<(outs), 2601 (ins GPR:$target, GPR:$idx, i32imm:$jt), 2602 0, IIC_Br, 2603 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>, 2604 Sched<[WriteBrTbl]>; 2605 } // isNotDuplicable = 1, isIndirectBranch = 1 2606 } // isBarrier = 1 2607 2608} 2609 2610// BLX (immediate) 2611def BLXi : AXI<(outs), (ins arm_blx_target:$target), BrMiscFrm, NoItinerary, 2612 "blx\t$target", []>, 2613 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2614 let Inst{31-25} = 0b1111101; 2615 bits<25> target; 2616 let Inst{23-0} = target{24-1}; 2617 let Inst{24} = target{0}; 2618 let isCall = 1; 2619} 2620 2621// Branch and Exchange Jazelle 2622def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2623 [/* pattern left blank */]>, Sched<[WriteBr]> { 2624 bits<4> func; 2625 let Inst{23-20} = 0b0010; 2626 let Inst{19-8} = 0xfff; 2627 let Inst{7-4} = 0b0010; 2628 let Inst{3-0} = func; 2629 let isBranch = 1; 2630 let isIndirectBranch = 1; 2631} 2632 2633// Tail calls. 2634 2635let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2636 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, i32imm:$SPDiff), IIC_Br, []>, 2637 Sched<[WriteBr]>; 2638 2639 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, i32imm:$SPDiff), IIC_Br, []>, 2640 Sched<[WriteBr]>; 2641 2642 def TAILJMPd : ARMPseudoExpand<(outs), (ins arm_br_target:$dst), 2643 4, IIC_Br, [], 2644 (Bcc arm_br_target:$dst, (ops 14, zero_reg))>, 2645 Requires<[IsARM]>, Sched<[WriteBr]>; 2646 2647 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2648 4, IIC_Br, [], 2649 (BX GPR:$dst)>, Sched<[WriteBr]>, 2650 Requires<[IsARM, HasV4T]>; 2651} 2652 2653// Secure Monitor Call is a system instruction. 2654def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2655 []>, Requires<[IsARM, HasTrustZone]> { 2656 bits<4> opt; 2657 let Inst{23-4} = 0b01100000000000000111; 2658 let Inst{3-0} = opt; 2659} 2660def : MnemonicAlias<"smi", "smc">; 2661 2662// Supervisor Call (Software Interrupt) 2663let isCall = 1, Uses = [SP] in { 2664def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2665 Sched<[WriteBr]> { 2666 bits<24> svc; 2667 let Inst{23-0} = svc; 2668} 2669} 2670 2671// Store Return State 2672class SRSI<bit wb, string asm> 2673 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2674 NoItinerary, asm, "", []> { 2675 bits<5> mode; 2676 let Inst{31-28} = 0b1111; 2677 let Inst{27-25} = 0b100; 2678 let Inst{22} = 1; 2679 let Inst{21} = wb; 2680 let Inst{20} = 0; 2681 let Inst{19-16} = 0b1101; // SP 2682 let Inst{15-5} = 0b00000101000; 2683 let Inst{4-0} = mode; 2684} 2685 2686def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2687 let Inst{24-23} = 0; 2688} 2689def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2690 let Inst{24-23} = 0; 2691} 2692def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2693 let Inst{24-23} = 0b10; 2694} 2695def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2696 let Inst{24-23} = 0b10; 2697} 2698def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2699 let Inst{24-23} = 0b01; 2700} 2701def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2702 let Inst{24-23} = 0b01; 2703} 2704def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2705 let Inst{24-23} = 0b11; 2706} 2707def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2708 let Inst{24-23} = 0b11; 2709} 2710 2711def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2712def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2713 2714def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2715def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2716 2717def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2718def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2719 2720def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2721def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2722 2723// Return From Exception 2724class RFEI<bit wb, string asm> 2725 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2726 NoItinerary, asm, "", []> { 2727 bits<4> Rn; 2728 let Inst{31-28} = 0b1111; 2729 let Inst{27-25} = 0b100; 2730 let Inst{22} = 0; 2731 let Inst{21} = wb; 2732 let Inst{20} = 1; 2733 let Inst{19-16} = Rn; 2734 let Inst{15-0} = 0xa00; 2735} 2736 2737def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2738 let Inst{24-23} = 0; 2739} 2740def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2741 let Inst{24-23} = 0; 2742} 2743def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2744 let Inst{24-23} = 0b10; 2745} 2746def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2747 let Inst{24-23} = 0b10; 2748} 2749def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2750 let Inst{24-23} = 0b01; 2751} 2752def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2753 let Inst{24-23} = 0b01; 2754} 2755def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2756 let Inst{24-23} = 0b11; 2757} 2758def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2759 let Inst{24-23} = 0b11; 2760} 2761 2762// Hypervisor Call is a system instruction 2763let isCall = 1 in { 2764def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary, 2765 "hvc", "\t$imm", []>, 2766 Requires<[IsARM, HasVirtualization]> { 2767 bits<16> imm; 2768 2769 // Even though HVC isn't predicable, it's encoding includes a condition field. 2770 // The instruction is undefined if the condition field is 0xf otherwise it is 2771 // unpredictable if it isn't condition AL (0xe). 2772 let Inst{31-28} = 0b1110; 2773 let Unpredictable{31-28} = 0b1111; 2774 let Inst{27-24} = 0b0001; 2775 let Inst{23-20} = 0b0100; 2776 let Inst{19-8} = imm{15-4}; 2777 let Inst{7-4} = 0b0111; 2778 let Inst{3-0} = imm{3-0}; 2779} 2780} 2781 2782// Return from exception in Hypervisor mode. 2783let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 2784def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>, 2785 Requires<[IsARM, HasVirtualization]> { 2786 let Inst{23-0} = 0b011000000000000001101110; 2787} 2788 2789//===----------------------------------------------------------------------===// 2790// Load / Store Instructions. 2791// 2792 2793// Load 2794 2795 2796defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, load>; 2797defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2798 zextloadi8>; 2799defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, store>; 2800defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2801 truncstorei8>; 2802 2803// Special LDR for loads from non-pc-relative constpools. 2804let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0, 2805 isReMaterializable = 1, isCodeGenOnly = 1 in 2806def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2807 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2808 []> { 2809 bits<4> Rt; 2810 bits<17> addr; 2811 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2812 let Inst{19-16} = 0b1111; 2813 let Inst{15-12} = Rt; 2814 let Inst{11-0} = addr{11-0}; // imm12 2815} 2816 2817// Loads with zero extension 2818def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2819 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2820 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2821 2822// Loads with sign extension 2823def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2824 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2825 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2826 2827def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2828 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2829 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2830 2831let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { 2832 // Load doubleword 2833 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), 2834 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, 2835 Requires<[IsARM, HasV5TE]>; 2836} 2837 2838let mayLoad = 1, hasSideEffects = 0, hasNoSchedulingInfo = 1 in { 2839def LOADDUAL : ARMPseudoInst<(outs GPRPairOp:$Rt), (ins addrmode3:$addr), 2840 64, IIC_iLoad_d_r, []>, 2841 Requires<[IsARM, HasV5TE]> { 2842 let AM = AddrMode3; 2843} 2844} 2845 2846def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2847 NoItinerary, "lda", "\t$Rt, $addr", []>; 2848def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2849 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2850def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2851 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2852 2853// Indexed loads 2854multiclass AI2_ldridx<bit isByte, string opc, 2855 InstrItinClass iii, InstrItinClass iir> { 2856 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2857 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2858 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2859 bits<17> addr; 2860 let Inst{25} = 0; 2861 let Inst{23} = addr{12}; 2862 let Inst{19-16} = addr{16-13}; 2863 let Inst{11-0} = addr{11-0}; 2864 let DecoderMethod = "DecodeLDRPreImm"; 2865 } 2866 2867 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2868 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2869 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2870 bits<17> addr; 2871 let Inst{25} = 1; 2872 let Inst{23} = addr{12}; 2873 let Inst{19-16} = addr{16-13}; 2874 let Inst{11-0} = addr{11-0}; 2875 let Inst{4} = 0; 2876 let DecoderMethod = "DecodeLDRPreReg"; 2877 } 2878 2879 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2880 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2881 IndexModePost, LdFrm, iir, 2882 opc, "\t$Rt, $addr, $offset", 2883 "$addr.base = $Rn_wb", []> { 2884 // {12} isAdd 2885 // {11-0} imm12/Rm 2886 bits<14> offset; 2887 bits<4> addr; 2888 let Inst{25} = 1; 2889 let Inst{23} = offset{12}; 2890 let Inst{19-16} = addr; 2891 let Inst{11-0} = offset{11-0}; 2892 let Inst{4} = 0; 2893 2894 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2895 } 2896 2897 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2898 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2899 IndexModePost, LdFrm, iii, 2900 opc, "\t$Rt, $addr, $offset", 2901 "$addr.base = $Rn_wb", []> { 2902 // {12} isAdd 2903 // {11-0} imm12/Rm 2904 bits<14> offset; 2905 bits<4> addr; 2906 let Inst{25} = 0; 2907 let Inst{23} = offset{12}; 2908 let Inst{19-16} = addr; 2909 let Inst{11-0} = offset{11-0}; 2910 2911 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2912 } 2913 2914} 2915 2916let mayLoad = 1, hasSideEffects = 0 in { 2917// FIXME: for LDR_PRE_REG etc. the itinerary should be either IIC_iLoad_ru or 2918// IIC_iLoad_siu depending on whether it the offset register is shifted. 2919defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2920defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2921} 2922 2923multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2924 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2925 (ins addrmode3_pre:$addr), IndexModePre, 2926 LdMiscFrm, itin, 2927 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2928 bits<14> addr; 2929 let Inst{23} = addr{8}; // U bit 2930 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2931 let Inst{19-16} = addr{12-9}; // Rn 2932 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2933 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2934 let DecoderMethod = "DecodeAddrMode3Instruction"; 2935 } 2936 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2937 (ins addr_offset_none:$addr, am3offset:$offset), 2938 IndexModePost, LdMiscFrm, itin, 2939 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2940 []> { 2941 bits<10> offset; 2942 bits<4> addr; 2943 let Inst{23} = offset{8}; // U bit 2944 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2945 let Inst{19-16} = addr; 2946 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2947 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2948 let DecoderMethod = "DecodeAddrMode3Instruction"; 2949 } 2950} 2951 2952let mayLoad = 1, hasSideEffects = 0 in { 2953defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2954defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2955defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2956let hasExtraDefRegAllocReq = 1 in { 2957def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2958 (ins addrmode3_pre:$addr), IndexModePre, 2959 LdMiscFrm, IIC_iLoad_d_ru, 2960 "ldrd", "\t$Rt, $Rt2, $addr!", 2961 "$addr.base = $Rn_wb", []> { 2962 bits<14> addr; 2963 let Inst{23} = addr{8}; // U bit 2964 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2965 let Inst{19-16} = addr{12-9}; // Rn 2966 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2967 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2968 let DecoderMethod = "DecodeAddrMode3Instruction"; 2969} 2970def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2971 (ins addr_offset_none:$addr, am3offset:$offset), 2972 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2973 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2974 "$addr.base = $Rn_wb", []> { 2975 bits<10> offset; 2976 bits<4> addr; 2977 let Inst{23} = offset{8}; // U bit 2978 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2979 let Inst{19-16} = addr; 2980 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2981 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2982 let DecoderMethod = "DecodeAddrMode3Instruction"; 2983} 2984} // hasExtraDefRegAllocReq = 1 2985} // mayLoad = 1, hasSideEffects = 0 2986 2987// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2988let mayLoad = 1, hasSideEffects = 0 in { 2989def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2990 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2991 IndexModePost, LdFrm, IIC_iLoad_ru, 2992 "ldrt", "\t$Rt, $addr, $offset", 2993 "$addr.base = $Rn_wb", []> { 2994 // {12} isAdd 2995 // {11-0} imm12/Rm 2996 bits<14> offset; 2997 bits<4> addr; 2998 let Inst{25} = 1; 2999 let Inst{23} = offset{12}; 3000 let Inst{21} = 1; // overwrite 3001 let Inst{19-16} = addr; 3002 let Inst{11-5} = offset{11-5}; 3003 let Inst{4} = 0; 3004 let Inst{3-0} = offset{3-0}; 3005 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3006} 3007 3008def LDRT_POST_IMM 3009 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 3010 (ins addr_offset_none:$addr, am2offset_imm:$offset), 3011 IndexModePost, LdFrm, IIC_iLoad_ru, 3012 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3013 // {12} isAdd 3014 // {11-0} imm12/Rm 3015 bits<14> offset; 3016 bits<4> addr; 3017 let Inst{25} = 0; 3018 let Inst{23} = offset{12}; 3019 let Inst{21} = 1; // overwrite 3020 let Inst{19-16} = addr; 3021 let Inst{11-0} = offset{11-0}; 3022 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3023} 3024 3025def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 3026 (ins addr_offset_none:$addr, am2offset_reg:$offset), 3027 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 3028 "ldrbt", "\t$Rt, $addr, $offset", 3029 "$addr.base = $Rn_wb", []> { 3030 // {12} isAdd 3031 // {11-0} imm12/Rm 3032 bits<14> offset; 3033 bits<4> addr; 3034 let Inst{25} = 1; 3035 let Inst{23} = offset{12}; 3036 let Inst{21} = 1; // overwrite 3037 let Inst{19-16} = addr; 3038 let Inst{11-5} = offset{11-5}; 3039 let Inst{4} = 0; 3040 let Inst{3-0} = offset{3-0}; 3041 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3042} 3043 3044def LDRBT_POST_IMM 3045 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 3046 (ins addr_offset_none:$addr, am2offset_imm:$offset), 3047 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 3048 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3049 // {12} isAdd 3050 // {11-0} imm12/Rm 3051 bits<14> offset; 3052 bits<4> addr; 3053 let Inst{25} = 0; 3054 let Inst{23} = offset{12}; 3055 let Inst{21} = 1; // overwrite 3056 let Inst{19-16} = addr; 3057 let Inst{11-0} = offset{11-0}; 3058 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3059} 3060 3061multiclass AI3ldrT<bits<4> op, string opc> { 3062 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 3063 (ins addr_offset_none:$addr, postidx_imm8:$offset), 3064 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 3065 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 3066 bits<9> offset; 3067 let Inst{23} = offset{8}; 3068 let Inst{22} = 1; 3069 let Inst{11-8} = offset{7-4}; 3070 let Inst{3-0} = offset{3-0}; 3071 } 3072 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 3073 (ins addr_offset_none:$addr, postidx_reg:$Rm), 3074 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 3075 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 3076 bits<5> Rm; 3077 let Inst{23} = Rm{4}; 3078 let Inst{22} = 0; 3079 let Inst{11-8} = 0; 3080 let Unpredictable{11-8} = 0b1111; 3081 let Inst{3-0} = Rm{3-0}; 3082 let DecoderMethod = "DecodeLDR"; 3083 } 3084 3085 def ii : ARMAsmPseudo<!strconcat(opc, "${p} $Rt, $addr"), 3086 (ins addr_offset_none:$addr, pred:$p), (outs GPR:$Rt)>; 3087} 3088 3089defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 3090defm LDRHT : AI3ldrT<0b1011, "ldrht">; 3091defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 3092} 3093 3094def LDRT_POST 3095 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 3096 (outs GPR:$Rt)>; 3097 3098def LDRBT_POST 3099 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 3100 (outs GPR:$Rt)>; 3101 3102// Pseudo instruction ldr Rt, =immediate 3103def LDRConstPool 3104 : ARMAsmPseudo<"ldr${q} $Rt, $immediate", 3105 (ins const_pool_asm_imm:$immediate, pred:$q), 3106 (outs GPR:$Rt)>; 3107 3108// Store 3109 3110// Stores with truncate 3111def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 3112 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 3113 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 3114 3115// Store doubleword 3116let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 3117 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 3118 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, 3119 Requires<[IsARM, HasV5TE]> { 3120 let Inst{21} = 0; 3121 } 3122} 3123 3124let mayStore = 1, hasSideEffects = 0, hasNoSchedulingInfo = 1 in { 3125def STOREDUAL : ARMPseudoInst<(outs), (ins GPRPairOp:$Rt, addrmode3:$addr), 3126 64, IIC_iStore_d_r, []>, 3127 Requires<[IsARM, HasV5TE]> { 3128 let AM = AddrMode3; 3129} 3130} 3131 3132// Indexed stores 3133multiclass AI2_stridx<bit isByte, string opc, 3134 InstrItinClass iii, InstrItinClass iir> { 3135 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 3136 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 3137 StFrm, iii, 3138 opc, "\t$Rt, $addr!", 3139 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3140 bits<17> addr; 3141 let Inst{25} = 0; 3142 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 3143 let Inst{19-16} = addr{16-13}; // Rn 3144 let Inst{11-0} = addr{11-0}; // imm12 3145 let DecoderMethod = "DecodeSTRPreImm"; 3146 } 3147 3148 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 3149 (ins GPR:$Rt, ldst_so_reg:$addr), 3150 IndexModePre, StFrm, iir, 3151 opc, "\t$Rt, $addr!", 3152 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3153 bits<17> addr; 3154 let Inst{25} = 1; 3155 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 3156 let Inst{19-16} = addr{16-13}; // Rn 3157 let Inst{11-0} = addr{11-0}; 3158 let Inst{4} = 0; // Inst{4} = 0 3159 let DecoderMethod = "DecodeSTRPreReg"; 3160 } 3161 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 3162 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3163 IndexModePost, StFrm, iir, 3164 opc, "\t$Rt, $addr, $offset", 3165 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3166 // {12} isAdd 3167 // {11-0} imm12/Rm 3168 bits<14> offset; 3169 bits<4> addr; 3170 let Inst{25} = 1; 3171 let Inst{23} = offset{12}; 3172 let Inst{19-16} = addr; 3173 let Inst{11-0} = offset{11-0}; 3174 let Inst{4} = 0; 3175 3176 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3177 } 3178 3179 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 3180 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3181 IndexModePost, StFrm, iii, 3182 opc, "\t$Rt, $addr, $offset", 3183 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3184 // {12} isAdd 3185 // {11-0} imm12/Rm 3186 bits<14> offset; 3187 bits<4> addr; 3188 let Inst{25} = 0; 3189 let Inst{23} = offset{12}; 3190 let Inst{19-16} = addr; 3191 let Inst{11-0} = offset{11-0}; 3192 3193 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3194 } 3195} 3196 3197let mayStore = 1, hasSideEffects = 0 in { 3198// FIXME: for STR_PRE_REG etc. the itinerary should be either IIC_iStore_ru or 3199// IIC_iStore_siu depending on whether it the offset register is shifted. 3200defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 3201defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 3202} 3203 3204def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 3205 am2offset_reg:$offset), 3206 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 3207 am2offset_reg:$offset)>; 3208def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 3209 am2offset_imm:$offset), 3210 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3211 am2offset_imm:$offset)>; 3212def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3213 am2offset_reg:$offset), 3214 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 3215 am2offset_reg:$offset)>; 3216def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3217 am2offset_imm:$offset), 3218 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3219 am2offset_imm:$offset)>; 3220 3221// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 3222// put the patterns on the instruction definitions directly as ISel wants 3223// the address base and offset to be separate operands, not a single 3224// complex operand like we represent the instructions themselves. The 3225// pseudos map between the two. 3226let usesCustomInserter = 1, 3227 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 3228def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3229 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3230 4, IIC_iStore_ru, 3231 [(set GPR:$Rn_wb, 3232 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3233def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3234 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3235 4, IIC_iStore_ru, 3236 [(set GPR:$Rn_wb, 3237 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3238def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3239 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3240 4, IIC_iStore_ru, 3241 [(set GPR:$Rn_wb, 3242 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3243def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3244 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3245 4, IIC_iStore_ru, 3246 [(set GPR:$Rn_wb, 3247 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3248def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3249 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 3250 4, IIC_iStore_ru, 3251 [(set GPR:$Rn_wb, 3252 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 3253} 3254 3255 3256 3257def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 3258 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 3259 StMiscFrm, IIC_iStore_bh_ru, 3260 "strh", "\t$Rt, $addr!", 3261 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3262 bits<14> addr; 3263 let Inst{23} = addr{8}; // U bit 3264 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3265 let Inst{19-16} = addr{12-9}; // Rn 3266 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3267 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3268 let DecoderMethod = "DecodeAddrMode3Instruction"; 3269} 3270 3271def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 3272 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 3273 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 3274 "strh", "\t$Rt, $addr, $offset", 3275 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", 3276 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 3277 addr_offset_none:$addr, 3278 am3offset:$offset))]> { 3279 bits<10> offset; 3280 bits<4> addr; 3281 let Inst{23} = offset{8}; // U bit 3282 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3283 let Inst{19-16} = addr; 3284 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3285 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3286 let DecoderMethod = "DecodeAddrMode3Instruction"; 3287} 3288 3289let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 3290def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 3291 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 3292 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 3293 "strd", "\t$Rt, $Rt2, $addr!", 3294 "$addr.base = $Rn_wb", []> { 3295 bits<14> addr; 3296 let Inst{23} = addr{8}; // U bit 3297 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3298 let Inst{19-16} = addr{12-9}; // Rn 3299 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3300 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3301 let DecoderMethod = "DecodeAddrMode3Instruction"; 3302} 3303 3304def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 3305 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 3306 am3offset:$offset), 3307 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 3308 "strd", "\t$Rt, $Rt2, $addr, $offset", 3309 "$addr.base = $Rn_wb", []> { 3310 bits<10> offset; 3311 bits<4> addr; 3312 let Inst{23} = offset{8}; // U bit 3313 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3314 let Inst{19-16} = addr; 3315 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3316 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3317 let DecoderMethod = "DecodeAddrMode3Instruction"; 3318} 3319} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 3320 3321// STRT, STRBT, and STRHT 3322 3323def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3324 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3325 IndexModePost, StFrm, IIC_iStore_bh_ru, 3326 "strbt", "\t$Rt, $addr, $offset", 3327 "$addr.base = $Rn_wb", []> { 3328 // {12} isAdd 3329 // {11-0} imm12/Rm 3330 bits<14> offset; 3331 bits<4> addr; 3332 let Inst{25} = 1; 3333 let Inst{23} = offset{12}; 3334 let Inst{21} = 1; // overwrite 3335 let Inst{19-16} = addr; 3336 let Inst{11-5} = offset{11-5}; 3337 let Inst{4} = 0; 3338 let Inst{3-0} = offset{3-0}; 3339 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3340} 3341 3342def STRBT_POST_IMM 3343 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3344 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3345 IndexModePost, StFrm, IIC_iStore_bh_ru, 3346 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3347 // {12} isAdd 3348 // {11-0} imm12/Rm 3349 bits<14> offset; 3350 bits<4> addr; 3351 let Inst{25} = 0; 3352 let Inst{23} = offset{12}; 3353 let Inst{21} = 1; // overwrite 3354 let Inst{19-16} = addr; 3355 let Inst{11-0} = offset{11-0}; 3356 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3357} 3358 3359def STRBT_POST 3360 : ARMAsmPseudo<"strbt${q} $Rt, $addr", 3361 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3362 3363let mayStore = 1, hasSideEffects = 0 in { 3364def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3365 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3366 IndexModePost, StFrm, IIC_iStore_ru, 3367 "strt", "\t$Rt, $addr, $offset", 3368 "$addr.base = $Rn_wb", []> { 3369 // {12} isAdd 3370 // {11-0} imm12/Rm 3371 bits<14> offset; 3372 bits<4> addr; 3373 let Inst{25} = 1; 3374 let Inst{23} = offset{12}; 3375 let Inst{21} = 1; // overwrite 3376 let Inst{19-16} = addr; 3377 let Inst{11-5} = offset{11-5}; 3378 let Inst{4} = 0; 3379 let Inst{3-0} = offset{3-0}; 3380 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3381} 3382 3383def STRT_POST_IMM 3384 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3385 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3386 IndexModePost, StFrm, IIC_iStore_ru, 3387 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3388 // {12} isAdd 3389 // {11-0} imm12/Rm 3390 bits<14> offset; 3391 bits<4> addr; 3392 let Inst{25} = 0; 3393 let Inst{23} = offset{12}; 3394 let Inst{21} = 1; // overwrite 3395 let Inst{19-16} = addr; 3396 let Inst{11-0} = offset{11-0}; 3397 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3398} 3399} 3400 3401def STRT_POST 3402 : ARMAsmPseudo<"strt${q} $Rt, $addr", 3403 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3404 3405multiclass AI3strT<bits<4> op, string opc> { 3406 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3407 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 3408 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3409 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 3410 bits<9> offset; 3411 let Inst{23} = offset{8}; 3412 let Inst{22} = 1; 3413 let Inst{11-8} = offset{7-4}; 3414 let Inst{3-0} = offset{3-0}; 3415 } 3416 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3417 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 3418 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3419 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 3420 bits<5> Rm; 3421 let Inst{23} = Rm{4}; 3422 let Inst{22} = 0; 3423 let Inst{11-8} = 0; 3424 let Inst{3-0} = Rm{3-0}; 3425 } 3426} 3427 3428 3429defm STRHT : AI3strT<0b1011, "strht">; 3430 3431def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3432 NoItinerary, "stl", "\t$Rt, $addr", []>; 3433def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3434 NoItinerary, "stlb", "\t$Rt, $addr", []>; 3435def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3436 NoItinerary, "stlh", "\t$Rt, $addr", []>; 3437 3438//===----------------------------------------------------------------------===// 3439// Load / store multiple Instructions. 3440// 3441 3442multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 3443 InstrItinClass itin, InstrItinClass itin_upd> { 3444 // IA is the default, so no need for an explicit suffix on the 3445 // mnemonic here. Without it is the canonical spelling. 3446 def IA : 3447 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3448 IndexModeNone, f, itin, 3449 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 3450 let Inst{24-23} = 0b01; // Increment After 3451 let Inst{22} = P_bit; 3452 let Inst{21} = 0; // No writeback 3453 let Inst{20} = L_bit; 3454 } 3455 def IA_UPD : 3456 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3457 IndexModeUpd, f, itin_upd, 3458 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3459 let Inst{24-23} = 0b01; // Increment After 3460 let Inst{22} = P_bit; 3461 let Inst{21} = 1; // Writeback 3462 let Inst{20} = L_bit; 3463 3464 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3465 } 3466 def DA : 3467 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3468 IndexModeNone, f, itin, 3469 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 3470 let Inst{24-23} = 0b00; // Decrement After 3471 let Inst{22} = P_bit; 3472 let Inst{21} = 0; // No writeback 3473 let Inst{20} = L_bit; 3474 } 3475 def DA_UPD : 3476 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3477 IndexModeUpd, f, itin_upd, 3478 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3479 let Inst{24-23} = 0b00; // Decrement After 3480 let Inst{22} = P_bit; 3481 let Inst{21} = 1; // Writeback 3482 let Inst{20} = L_bit; 3483 3484 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3485 } 3486 def DB : 3487 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3488 IndexModeNone, f, itin, 3489 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 3490 let Inst{24-23} = 0b10; // Decrement Before 3491 let Inst{22} = P_bit; 3492 let Inst{21} = 0; // No writeback 3493 let Inst{20} = L_bit; 3494 } 3495 def DB_UPD : 3496 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3497 IndexModeUpd, f, itin_upd, 3498 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3499 let Inst{24-23} = 0b10; // Decrement Before 3500 let Inst{22} = P_bit; 3501 let Inst{21} = 1; // Writeback 3502 let Inst{20} = L_bit; 3503 3504 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3505 } 3506 def IB : 3507 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3508 IndexModeNone, f, itin, 3509 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 3510 let Inst{24-23} = 0b11; // Increment Before 3511 let Inst{22} = P_bit; 3512 let Inst{21} = 0; // No writeback 3513 let Inst{20} = L_bit; 3514 } 3515 def IB_UPD : 3516 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3517 IndexModeUpd, f, itin_upd, 3518 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3519 let Inst{24-23} = 0b11; // Increment Before 3520 let Inst{22} = P_bit; 3521 let Inst{21} = 1; // Writeback 3522 let Inst{20} = L_bit; 3523 3524 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3525 } 3526} 3527 3528let hasSideEffects = 0 in { 3529 3530let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in 3531defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 3532 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">; 3533 3534let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3535defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 3536 IIC_iStore_mu>, 3537 ComplexDeprecationPredicate<"ARMStore">; 3538 3539} // hasSideEffects 3540 3541// FIXME: remove when we have a way to marking a MI with these properties. 3542// FIXME: Should pc be an implicit operand like PICADD, etc? 3543let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3544 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3545def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3546 reglist:$regs, variable_ops), 3547 4, IIC_iLoad_mBr, [], 3548 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3549 RegConstraint<"$Rn = $wb">; 3550 3551let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3552defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 3553 IIC_iLoad_mu>; 3554 3555let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3556defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 3557 IIC_iStore_mu>; 3558 3559 3560 3561//===----------------------------------------------------------------------===// 3562// Move Instructions. 3563// 3564 3565let hasSideEffects = 0, isMoveReg = 1 in 3566def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 3567 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3568 bits<4> Rd; 3569 bits<4> Rm; 3570 3571 let Inst{19-16} = 0b0000; 3572 let Inst{11-4} = 0b00000000; 3573 let Inst{25} = 0; 3574 let Inst{3-0} = Rm; 3575 let Inst{15-12} = Rd; 3576} 3577 3578// A version for the smaller set of tail call registers. 3579let hasSideEffects = 0 in 3580def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 3581 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3582 bits<4> Rd; 3583 bits<4> Rm; 3584 3585 let Inst{11-4} = 0b00000000; 3586 let Inst{25} = 0; 3587 let Inst{3-0} = Rm; 3588 let Inst{15-12} = Rd; 3589} 3590 3591def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 3592 DPSoRegRegFrm, IIC_iMOVsr, 3593 "mov", "\t$Rd, $src", 3594 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 3595 Sched<[WriteALU]> { 3596 bits<4> Rd; 3597 bits<12> src; 3598 let Inst{15-12} = Rd; 3599 let Inst{19-16} = 0b0000; 3600 let Inst{11-8} = src{11-8}; 3601 let Inst{7} = 0; 3602 let Inst{6-5} = src{6-5}; 3603 let Inst{4} = 1; 3604 let Inst{3-0} = src{3-0}; 3605 let Inst{25} = 0; 3606} 3607 3608def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3609 DPSoRegImmFrm, IIC_iMOVsr, 3610 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3611 UnaryDP, Sched<[WriteALU]> { 3612 bits<4> Rd; 3613 bits<12> src; 3614 let Inst{15-12} = Rd; 3615 let Inst{19-16} = 0b0000; 3616 let Inst{11-5} = src{11-5}; 3617 let Inst{4} = 0; 3618 let Inst{3-0} = src{3-0}; 3619 let Inst{25} = 0; 3620} 3621 3622let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3623def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi, 3624 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP, 3625 Sched<[WriteALU]> { 3626 bits<4> Rd; 3627 bits<12> imm; 3628 let Inst{25} = 1; 3629 let Inst{15-12} = Rd; 3630 let Inst{19-16} = 0b0000; 3631 let Inst{11-0} = imm; 3632} 3633 3634let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3635def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3636 DPFrm, IIC_iMOVi, 3637 "movw", "\t$Rd, $imm", 3638 [(set GPR:$Rd, imm0_65535:$imm)]>, 3639 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3640 bits<4> Rd; 3641 bits<16> imm; 3642 let Inst{15-12} = Rd; 3643 let Inst{11-0} = imm{11-0}; 3644 let Inst{19-16} = imm{15-12}; 3645 let Inst{20} = 0; 3646 let Inst{25} = 1; 3647 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3648} 3649 3650def : InstAlias<"mov${p} $Rd, $imm", 3651 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>, 3652 Requires<[IsARM, HasV6T2]>; 3653 3654def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3655 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3656 Sched<[WriteALU]>; 3657 3658let Constraints = "$src = $Rd" in { 3659def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3660 (ins GPR:$src, imm0_65535_expr:$imm), 3661 DPFrm, IIC_iMOVi, 3662 "movt", "\t$Rd, $imm", 3663 [(set GPRnopc:$Rd, 3664 (or (and GPR:$src, 0xffff), 3665 lo16AllZero:$imm))]>, UnaryDP, 3666 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3667 bits<4> Rd; 3668 bits<16> imm; 3669 let Inst{15-12} = Rd; 3670 let Inst{11-0} = imm{11-0}; 3671 let Inst{19-16} = imm{15-12}; 3672 let Inst{20} = 0; 3673 let Inst{25} = 1; 3674 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3675} 3676 3677def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3678 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3679 Sched<[WriteALU]>; 3680 3681} // Constraints 3682 3683def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3684 Requires<[IsARM, HasV6T2]>; 3685 3686let Uses = [CPSR] in 3687def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3688 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3689 Requires<[IsARM]>, Sched<[WriteALU]>; 3690 3691// These aren't really mov instructions, but we have to define them this way 3692// due to flag operands. 3693 3694let Defs = [CPSR] in { 3695def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3696 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3697 Sched<[WriteALU]>, Requires<[IsARM]>; 3698def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3699 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3700 Sched<[WriteALU]>, Requires<[IsARM]>; 3701} 3702 3703//===----------------------------------------------------------------------===// 3704// Extend Instructions. 3705// 3706 3707// Sign extenders 3708 3709def SXTB : AI_ext_rrot<0b01101010, 3710 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3711def SXTH : AI_ext_rrot<0b01101011, 3712 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3713 3714def SXTAB : AI_exta_rrot<0b01101010, 3715 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3716def SXTAH : AI_exta_rrot<0b01101011, 3717 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3718 3719def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)), 3720 (SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3721def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), 3722 i16)), 3723 (SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3724 3725def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3726def : ARMV6Pat<(int_arm_sxtb16 GPR:$Src), 3727 (SXTB16 GPR:$Src, 0)>; 3728def : ARMV6Pat<(int_arm_sxtb16 (rotr GPR:$Src, rot_imm:$rot)), 3729 (SXTB16 GPR:$Src, rot_imm:$rot)>; 3730 3731def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3732def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, GPR:$RHS), 3733 (SXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3734def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)), 3735 (SXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>; 3736 3737// Zero extenders 3738 3739let AddedComplexity = 16 in { 3740def UXTB : AI_ext_rrot<0b01101110, 3741 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3742def UXTH : AI_ext_rrot<0b01101111, 3743 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3744def UXTB16 : AI_ext_rrot<0b01101100, 3745 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3746 3747// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3748// The transformation should probably be done as a combiner action 3749// instead so we can include a check for masking back in the upper 3750// eight bits of the source into the lower eight bits of the result. 3751//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3752// (UXTB16r_rot GPR:$Src, 3)>; 3753def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3754 (UXTB16 GPR:$Src, 1)>; 3755def : ARMV6Pat<(int_arm_uxtb16 GPR:$Src), 3756 (UXTB16 GPR:$Src, 0)>; 3757def : ARMV6Pat<(int_arm_uxtb16 (rotr GPR:$Src, rot_imm:$rot)), 3758 (UXTB16 GPR:$Src, rot_imm:$rot)>; 3759 3760def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3761 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3762def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3763 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3764 3765def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)), 3766 (UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3767def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)), 3768 (UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3769} 3770 3771// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3772def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3773def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, GPR:$RHS), 3774 (UXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3775def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)), 3776 (UXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>; 3777 3778 3779def SBFX : I<(outs GPRnopc:$Rd), 3780 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3781 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3782 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3783 Requires<[IsARM, HasV6T2]> { 3784 bits<4> Rd; 3785 bits<4> Rn; 3786 bits<5> lsb; 3787 bits<5> width; 3788 let Inst{27-21} = 0b0111101; 3789 let Inst{6-4} = 0b101; 3790 let Inst{20-16} = width; 3791 let Inst{15-12} = Rd; 3792 let Inst{11-7} = lsb; 3793 let Inst{3-0} = Rn; 3794} 3795 3796def UBFX : I<(outs GPRnopc:$Rd), 3797 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3798 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3799 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3800 Requires<[IsARM, HasV6T2]> { 3801 bits<4> Rd; 3802 bits<4> Rn; 3803 bits<5> lsb; 3804 bits<5> width; 3805 let Inst{27-21} = 0b0111111; 3806 let Inst{6-4} = 0b101; 3807 let Inst{20-16} = width; 3808 let Inst{15-12} = Rd; 3809 let Inst{11-7} = lsb; 3810 let Inst{3-0} = Rn; 3811} 3812 3813//===----------------------------------------------------------------------===// 3814// Arithmetic Instructions. 3815// 3816 3817let isAdd = 1 in 3818defm ADD : AsI1_bin_irs<0b0100, "add", 3819 IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>; 3820defm SUB : AsI1_bin_irs<0b0010, "sub", 3821 IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>; 3822 3823// ADD and SUB with 's' bit set. 3824// 3825// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3826// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3827// AdjustInstrPostInstrSelection where we determine whether or not to 3828// set the "s" bit based on CPSR liveness. 3829// 3830// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3831// support for an optional CPSR definition that corresponds to the DAG 3832// node's second value. We can then eliminate the implicit def of CPSR. 3833let isAdd = 1 in 3834defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>; 3835defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3836 3837def : ARMPat<(ARMsubs GPR:$Rn, mod_imm:$imm), (SUBSri $Rn, mod_imm:$imm)>; 3838def : ARMPat<(ARMsubs GPR:$Rn, GPR:$Rm), (SUBSrr $Rn, $Rm)>; 3839def : ARMPat<(ARMsubs GPR:$Rn, so_reg_imm:$shift), 3840 (SUBSrsi $Rn, so_reg_imm:$shift)>; 3841def : ARMPat<(ARMsubs GPR:$Rn, so_reg_reg:$shift), 3842 (SUBSrsr $Rn, so_reg_reg:$shift)>; 3843 3844 3845let isAdd = 1 in 3846defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>; 3847defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>; 3848 3849defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3850 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3851 sub>; 3852 3853// FIXME: Eliminate them if we can write def : Pat patterns which defines 3854// CPSR and the implicit def of CPSR is not needed. 3855defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUsr, ARMsubc>; 3856 3857defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>; 3858 3859// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3860// The assume-no-carry-in form uses the negation of the input since add/sub 3861// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3862// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3863// details. 3864def : ARMPat<(add GPR:$src, mod_imm_neg:$imm), 3865 (SUBri GPR:$src, mod_imm_neg:$imm)>; 3866def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm), 3867 (SUBSri GPR:$src, mod_imm_neg:$imm)>; 3868 3869def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3870 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3871 Requires<[IsARM, HasV6T2]>; 3872def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3873 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3874 Requires<[IsARM, HasV6T2]>; 3875 3876// The with-carry-in form matches bitwise not instead of the negation. 3877// Effectively, the inverse interpretation of the carry flag already accounts 3878// for part of the negation. 3879def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR), 3880 (SBCri GPR:$src, mod_imm_not:$imm)>; 3881def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3882 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>, 3883 Requires<[IsARM, HasV6T2]>; 3884 3885// Note: These are implemented in C++ code, because they have to generate 3886// ADD/SUBrs instructions, which use a complex pattern that a xform function 3887// cannot produce. 3888// (mul X, 2^n+1) -> (add (X << n), X) 3889// (mul X, 2^n-1) -> (rsb X, (X << n)) 3890 3891// ARM Arithmetic Instruction 3892// GPR:$dst = GPR:$a op GPR:$b 3893class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3894 list<dag> pattern = [], 3895 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3896 string asm = "\t$Rd, $Rn, $Rm"> 3897 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3898 Sched<[WriteALU, ReadALU, ReadALU]> { 3899 bits<4> Rn; 3900 bits<4> Rd; 3901 bits<4> Rm; 3902 let Inst{27-20} = op27_20; 3903 let Inst{11-4} = op11_4; 3904 let Inst{19-16} = Rn; 3905 let Inst{15-12} = Rd; 3906 let Inst{3-0} = Rm; 3907 3908 let Unpredictable{11-8} = 0b1111; 3909} 3910 3911// Wrappers around the AAI class 3912class AAIRevOpr<bits<8> op27_20, bits<8> op11_4, string opc, 3913 list<dag> pattern = []> 3914 : AAI<op27_20, op11_4, opc, 3915 pattern, 3916 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3917 "\t$Rd, $Rm, $Rn">; 3918 3919class AAIIntrinsic<bits<8> op27_20, bits<8> op11_4, string opc, 3920 Intrinsic intrinsic> 3921 : AAI<op27_20, op11_4, opc, 3922 [(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>; 3923 3924// Saturating add/subtract 3925let hasSideEffects = 1 in { 3926def QADD8 : AAIIntrinsic<0b01100010, 0b11111001, "qadd8", int_arm_qadd8>; 3927def QADD16 : AAIIntrinsic<0b01100010, 0b11110001, "qadd16", int_arm_qadd16>; 3928def QSUB16 : AAIIntrinsic<0b01100010, 0b11110111, "qsub16", int_arm_qsub16>; 3929def QSUB8 : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>; 3930 3931def QDADD : AAIRevOpr<0b00010100, 0b00000101, "qdadd", 3932 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, 3933 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>; 3934def QDSUB : AAIRevOpr<0b00010110, 0b00000101, "qdsub", 3935 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, 3936 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>; 3937def QSUB : AAIRevOpr<0b00010010, 0b00000101, "qsub", 3938 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>; 3939let DecoderMethod = "DecodeQADDInstruction" in 3940 def QADD : AAIRevOpr<0b00010000, 0b00000101, "qadd", 3941 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>; 3942} 3943 3944def : ARMV5TEPat<(saddsat GPR:$a, GPR:$b), 3945 (QADD GPR:$a, GPR:$b)>; 3946def : ARMV5TEPat<(ssubsat GPR:$a, GPR:$b), 3947 (QSUB GPR:$a, GPR:$b)>; 3948def : ARMV5TEPat<(saddsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)), 3949 (QDADD rGPR:$Rm, rGPR:$Rn)>; 3950def : ARMV5TEPat<(ssubsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)), 3951 (QDSUB rGPR:$Rm, rGPR:$Rn)>; 3952 3953def : ARMV6Pat<(ARMqadd8b rGPR:$Rm, rGPR:$Rn), 3954 (QADD8 rGPR:$Rm, rGPR:$Rn)>; 3955def : ARMV6Pat<(ARMqsub8b rGPR:$Rm, rGPR:$Rn), 3956 (QSUB8 rGPR:$Rm, rGPR:$Rn)>; 3957def : ARMV6Pat<(ARMqadd16b rGPR:$Rm, rGPR:$Rn), 3958 (QADD16 rGPR:$Rm, rGPR:$Rn)>; 3959def : ARMV6Pat<(ARMqsub16b rGPR:$Rm, rGPR:$Rn), 3960 (QSUB16 rGPR:$Rm, rGPR:$Rn)>; 3961 3962def UQADD16 : AAIIntrinsic<0b01100110, 0b11110001, "uqadd16", int_arm_uqadd16>; 3963def UQADD8 : AAIIntrinsic<0b01100110, 0b11111001, "uqadd8", int_arm_uqadd8>; 3964def UQSUB16 : AAIIntrinsic<0b01100110, 0b11110111, "uqsub16", int_arm_uqsub16>; 3965def UQSUB8 : AAIIntrinsic<0b01100110, 0b11111111, "uqsub8", int_arm_uqsub8>; 3966def QASX : AAIIntrinsic<0b01100010, 0b11110011, "qasx", int_arm_qasx>; 3967def QSAX : AAIIntrinsic<0b01100010, 0b11110101, "qsax", int_arm_qsax>; 3968def UQASX : AAIIntrinsic<0b01100110, 0b11110011, "uqasx", int_arm_uqasx>; 3969def UQSAX : AAIIntrinsic<0b01100110, 0b11110101, "uqsax", int_arm_uqsax>; 3970 3971def : ARMV6Pat<(ARMuqadd8b rGPR:$Rm, rGPR:$Rn), 3972 (UQADD8 rGPR:$Rm, rGPR:$Rn)>; 3973def : ARMV6Pat<(ARMuqsub8b rGPR:$Rm, rGPR:$Rn), 3974 (UQSUB8 rGPR:$Rm, rGPR:$Rn)>; 3975def : ARMV6Pat<(ARMuqadd16b rGPR:$Rm, rGPR:$Rn), 3976 (UQADD16 rGPR:$Rm, rGPR:$Rn)>; 3977def : ARMV6Pat<(ARMuqsub16b rGPR:$Rm, rGPR:$Rn), 3978 (UQSUB16 rGPR:$Rm, rGPR:$Rn)>; 3979 3980 3981// Signed/Unsigned add/subtract 3982 3983def SASX : AAIIntrinsic<0b01100001, 0b11110011, "sasx", int_arm_sasx>; 3984def SADD16 : AAIIntrinsic<0b01100001, 0b11110001, "sadd16", int_arm_sadd16>; 3985def SADD8 : AAIIntrinsic<0b01100001, 0b11111001, "sadd8", int_arm_sadd8>; 3986def SSAX : AAIIntrinsic<0b01100001, 0b11110101, "ssax", int_arm_ssax>; 3987def SSUB16 : AAIIntrinsic<0b01100001, 0b11110111, "ssub16", int_arm_ssub16>; 3988def SSUB8 : AAIIntrinsic<0b01100001, 0b11111111, "ssub8", int_arm_ssub8>; 3989def UASX : AAIIntrinsic<0b01100101, 0b11110011, "uasx", int_arm_uasx>; 3990def UADD16 : AAIIntrinsic<0b01100101, 0b11110001, "uadd16", int_arm_uadd16>; 3991def UADD8 : AAIIntrinsic<0b01100101, 0b11111001, "uadd8", int_arm_uadd8>; 3992def USAX : AAIIntrinsic<0b01100101, 0b11110101, "usax", int_arm_usax>; 3993def USUB16 : AAIIntrinsic<0b01100101, 0b11110111, "usub16", int_arm_usub16>; 3994def USUB8 : AAIIntrinsic<0b01100101, 0b11111111, "usub8", int_arm_usub8>; 3995 3996// Signed/Unsigned halving add/subtract 3997 3998def SHASX : AAIIntrinsic<0b01100011, 0b11110011, "shasx", int_arm_shasx>; 3999def SHADD16 : AAIIntrinsic<0b01100011, 0b11110001, "shadd16", int_arm_shadd16>; 4000def SHADD8 : AAIIntrinsic<0b01100011, 0b11111001, "shadd8", int_arm_shadd8>; 4001def SHSAX : AAIIntrinsic<0b01100011, 0b11110101, "shsax", int_arm_shsax>; 4002def SHSUB16 : AAIIntrinsic<0b01100011, 0b11110111, "shsub16", int_arm_shsub16>; 4003def SHSUB8 : AAIIntrinsic<0b01100011, 0b11111111, "shsub8", int_arm_shsub8>; 4004def UHASX : AAIIntrinsic<0b01100111, 0b11110011, "uhasx", int_arm_uhasx>; 4005def UHADD16 : AAIIntrinsic<0b01100111, 0b11110001, "uhadd16", int_arm_uhadd16>; 4006def UHADD8 : AAIIntrinsic<0b01100111, 0b11111001, "uhadd8", int_arm_uhadd8>; 4007def UHSAX : AAIIntrinsic<0b01100111, 0b11110101, "uhsax", int_arm_uhsax>; 4008def UHSUB16 : AAIIntrinsic<0b01100111, 0b11110111, "uhsub16", int_arm_uhsub16>; 4009def UHSUB8 : AAIIntrinsic<0b01100111, 0b11111111, "uhsub8", int_arm_uhsub8>; 4010 4011// Unsigned Sum of Absolute Differences [and Accumulate]. 4012 4013def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4014 MulFrm /* for convenience */, NoItinerary, "usad8", 4015 "\t$Rd, $Rn, $Rm", 4016 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>, 4017 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 4018 bits<4> Rd; 4019 bits<4> Rn; 4020 bits<4> Rm; 4021 let Inst{27-20} = 0b01111000; 4022 let Inst{15-12} = 0b1111; 4023 let Inst{7-4} = 0b0001; 4024 let Inst{19-16} = Rd; 4025 let Inst{11-8} = Rm; 4026 let Inst{3-0} = Rn; 4027} 4028def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4029 MulFrm /* for convenience */, NoItinerary, "usada8", 4030 "\t$Rd, $Rn, $Rm, $Ra", 4031 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4032 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 4033 bits<4> Rd; 4034 bits<4> Rn; 4035 bits<4> Rm; 4036 bits<4> Ra; 4037 let Inst{27-20} = 0b01111000; 4038 let Inst{7-4} = 0b0001; 4039 let Inst{19-16} = Rd; 4040 let Inst{15-12} = Ra; 4041 let Inst{11-8} = Rm; 4042 let Inst{3-0} = Rn; 4043} 4044 4045// Signed/Unsigned saturate 4046def SSAT : AI<(outs GPRnopc:$Rd), 4047 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 4048 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>, 4049 Requires<[IsARM,HasV6]>{ 4050 bits<4> Rd; 4051 bits<5> sat_imm; 4052 bits<4> Rn; 4053 bits<8> sh; 4054 let Inst{27-21} = 0b0110101; 4055 let Inst{5-4} = 0b01; 4056 let Inst{20-16} = sat_imm; 4057 let Inst{15-12} = Rd; 4058 let Inst{11-7} = sh{4-0}; 4059 let Inst{6} = sh{5}; 4060 let Inst{3-0} = Rn; 4061} 4062 4063def SSAT16 : AI<(outs GPRnopc:$Rd), 4064 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 4065 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>, 4066 Requires<[IsARM,HasV6]>{ 4067 bits<4> Rd; 4068 bits<4> sat_imm; 4069 bits<4> Rn; 4070 let Inst{27-20} = 0b01101010; 4071 let Inst{11-4} = 0b11110011; 4072 let Inst{15-12} = Rd; 4073 let Inst{19-16} = sat_imm; 4074 let Inst{3-0} = Rn; 4075} 4076 4077def USAT : AI<(outs GPRnopc:$Rd), 4078 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 4079 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>, 4080 Requires<[IsARM,HasV6]> { 4081 bits<4> Rd; 4082 bits<5> sat_imm; 4083 bits<4> Rn; 4084 bits<8> sh; 4085 let Inst{27-21} = 0b0110111; 4086 let Inst{5-4} = 0b01; 4087 let Inst{15-12} = Rd; 4088 let Inst{11-7} = sh{4-0}; 4089 let Inst{6} = sh{5}; 4090 let Inst{20-16} = sat_imm; 4091 let Inst{3-0} = Rn; 4092} 4093 4094def USAT16 : AI<(outs GPRnopc:$Rd), 4095 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 4096 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>, 4097 Requires<[IsARM,HasV6]>{ 4098 bits<4> Rd; 4099 bits<4> sat_imm; 4100 bits<4> Rn; 4101 let Inst{27-20} = 0b01101110; 4102 let Inst{11-4} = 0b11110011; 4103 let Inst{15-12} = Rd; 4104 let Inst{19-16} = sat_imm; 4105 let Inst{3-0} = Rn; 4106} 4107 4108def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos), 4109 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>; 4110def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos), 4111 (USAT imm0_31:$pos, GPRnopc:$a, 0)>; 4112def : ARMPat<(ARMssat GPRnopc:$Rn, imm0_31:$imm), 4113 (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 4114def : ARMPat<(ARMusat GPRnopc:$Rn, imm0_31:$imm), 4115 (USAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 4116def : ARMV6Pat<(int_arm_ssat16 GPRnopc:$a, imm1_16:$pos), 4117 (SSAT16 imm1_16:$pos, GPRnopc:$a)>; 4118def : ARMV6Pat<(int_arm_usat16 GPRnopc:$a, imm0_15:$pos), 4119 (USAT16 imm0_15:$pos, GPRnopc:$a)>; 4120def : ARMV6Pat<(int_arm_ssat (shl GPRnopc:$a, imm0_31:$shft), imm1_32:$pos), 4121 (SSAT imm1_32:$pos, GPRnopc:$a, imm0_31:$shft)>; 4122def : ARMV6Pat<(int_arm_ssat (sra GPRnopc:$a, asr_imm:$shft), imm1_32:$pos), 4123 (SSAT imm1_32:$pos, GPRnopc:$a, asr_imm:$shft)>; 4124def : ARMV6Pat<(int_arm_usat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos), 4125 (USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>; 4126def : ARMV6Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos), 4127 (USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>; 4128def : ARMPat<(ARMssat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos), 4129 (SSAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>; 4130def : ARMPat<(ARMssat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos), 4131 (SSAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>; 4132def : ARMPat<(ARMusat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos), 4133 (USAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>; 4134def : ARMPat<(ARMusat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos), 4135 (USAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>; 4136 4137 4138//===----------------------------------------------------------------------===// 4139// Bitwise Instructions. 4140// 4141 4142defm AND : AsI1_bin_irs<0b0000, "and", 4143 IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>; 4144defm ORR : AsI1_bin_irs<0b1100, "orr", 4145 IIC_iBITi, IIC_iBITr, IIC_iBITsr, or, 1>; 4146defm EOR : AsI1_bin_irs<0b0001, "eor", 4147 IIC_iBITi, IIC_iBITr, IIC_iBITsr, xor, 1>; 4148defm BIC : AsI1_bin_irs<0b1110, "bic", 4149 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 4150 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 4151 4152// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 4153// like in the actual instruction encoding. The complexity of mapping the mask 4154// to the lsb/msb pair should be handled by ISel, not encapsulated in the 4155// instruction description. 4156def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 4157 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 4158 "bfc", "\t$Rd, $imm", "$src = $Rd", 4159 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 4160 Requires<[IsARM, HasV6T2]> { 4161 bits<4> Rd; 4162 bits<10> imm; 4163 let Inst{27-21} = 0b0111110; 4164 let Inst{6-0} = 0b0011111; 4165 let Inst{15-12} = Rd; 4166 let Inst{11-7} = imm{4-0}; // lsb 4167 let Inst{20-16} = imm{9-5}; // msb 4168} 4169 4170// A8.6.18 BFI - Bitfield insert (Encoding A1) 4171def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 4172 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 4173 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 4174 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 4175 bf_inv_mask_imm:$imm))]>, 4176 Requires<[IsARM, HasV6T2]> { 4177 bits<4> Rd; 4178 bits<4> Rn; 4179 bits<10> imm; 4180 let Inst{27-21} = 0b0111110; 4181 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 4182 let Inst{15-12} = Rd; 4183 let Inst{11-7} = imm{4-0}; // lsb 4184 let Inst{20-16} = imm{9-5}; // width 4185 let Inst{3-0} = Rn; 4186} 4187 4188def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 4189 "mvn", "\t$Rd, $Rm", 4190 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 4191 bits<4> Rd; 4192 bits<4> Rm; 4193 let Inst{25} = 0; 4194 let Inst{19-16} = 0b0000; 4195 let Inst{11-4} = 0b00000000; 4196 let Inst{15-12} = Rd; 4197 let Inst{3-0} = Rm; 4198 4199 let Unpredictable{19-16} = 0b1111; 4200} 4201def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 4202 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 4203 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 4204 Sched<[WriteALU]> { 4205 bits<4> Rd; 4206 bits<12> shift; 4207 let Inst{25} = 0; 4208 let Inst{19-16} = 0b0000; 4209 let Inst{15-12} = Rd; 4210 let Inst{11-5} = shift{11-5}; 4211 let Inst{4} = 0; 4212 let Inst{3-0} = shift{3-0}; 4213 4214 let Unpredictable{19-16} = 0b1111; 4215} 4216def MVNsr : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift), 4217 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 4218 [(set GPRnopc:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 4219 Sched<[WriteALU]> { 4220 bits<4> Rd; 4221 bits<12> shift; 4222 let Inst{25} = 0; 4223 let Inst{19-16} = 0b0000; 4224 let Inst{15-12} = Rd; 4225 let Inst{11-8} = shift{11-8}; 4226 let Inst{7} = 0; 4227 let Inst{6-5} = shift{6-5}; 4228 let Inst{4} = 1; 4229 let Inst{3-0} = shift{3-0}; 4230 4231 let Unpredictable{19-16} = 0b1111; 4232} 4233let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 4234def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, 4235 IIC_iMVNi, "mvn", "\t$Rd, $imm", 4236 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 4237 bits<4> Rd; 4238 bits<12> imm; 4239 let Inst{25} = 1; 4240 let Inst{19-16} = 0b0000; 4241 let Inst{15-12} = Rd; 4242 let Inst{11-0} = imm; 4243} 4244 4245let AddedComplexity = 1 in 4246def : ARMPat<(and GPR:$src, mod_imm_not:$imm), 4247 (BICri GPR:$src, mod_imm_not:$imm)>; 4248 4249//===----------------------------------------------------------------------===// 4250// Multiply Instructions. 4251// 4252class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4253 string opc, string asm, list<dag> pattern> 4254 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4255 bits<4> Rd; 4256 bits<4> Rm; 4257 bits<4> Rn; 4258 let Inst{19-16} = Rd; 4259 let Inst{11-8} = Rm; 4260 let Inst{3-0} = Rn; 4261} 4262class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4263 string opc, string asm, list<dag> pattern> 4264 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4265 bits<4> RdLo; 4266 bits<4> RdHi; 4267 bits<4> Rm; 4268 bits<4> Rn; 4269 let Inst{19-16} = RdHi; 4270 let Inst{15-12} = RdLo; 4271 let Inst{11-8} = Rm; 4272 let Inst{3-0} = Rn; 4273} 4274class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4275 string opc, string asm, list<dag> pattern> 4276 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4277 bits<4> RdLo; 4278 bits<4> RdHi; 4279 bits<4> Rm; 4280 bits<4> Rn; 4281 let Inst{19-16} = RdHi; 4282 let Inst{15-12} = RdLo; 4283 let Inst{11-8} = Rm; 4284 let Inst{3-0} = Rn; 4285} 4286 4287// FIXME: The v5 pseudos are only necessary for the additional Constraint 4288// property. Remove them when it's possible to add those properties 4289// on an individual MachineInstr, not just an instruction description. 4290let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 4291def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 4292 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4293 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 4294 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 4295 Requires<[IsARM, HasV6]>, 4296 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4297 let Inst{15-12} = 0b0000; 4298 let Unpredictable{15-12} = 0b1111; 4299} 4300 4301let Constraints = "@earlyclobber $Rd" in 4302def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 4303 pred:$p, cc_out:$s), 4304 4, IIC_iMUL32, 4305 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 4306 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 4307 Requires<[IsARM, NoV6, UseMulOps]>, 4308 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4309} 4310 4311def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), 4312 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), 4313 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 4314 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, 4315 Requires<[IsARM, HasV6, UseMulOps]>, 4316 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4317 bits<4> Ra; 4318 let Inst{15-12} = Ra; 4319} 4320 4321let Constraints = "@earlyclobber $Rd" in 4322def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), 4323 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 4324 pred:$p, cc_out:$s), 4, IIC_iMAC32, 4325 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], 4326 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, 4327 Requires<[IsARM, NoV6]>, 4328 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4329 4330def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4331 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 4332 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 4333 Requires<[IsARM, HasV6T2, UseMulOps]>, 4334 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4335 bits<4> Rd; 4336 bits<4> Rm; 4337 bits<4> Rn; 4338 bits<4> Ra; 4339 let Inst{19-16} = Rd; 4340 let Inst{15-12} = Ra; 4341 let Inst{11-8} = Rm; 4342 let Inst{3-0} = Rn; 4343} 4344 4345// Extra precision multiplies with low / high results 4346let hasSideEffects = 0 in { 4347let isCommutable = 1 in { 4348def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 4349 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4350 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", 4351 [(set GPR:$RdLo, GPR:$RdHi, 4352 (smullohi GPR:$Rn, GPR:$Rm))]>, 4353 Requires<[IsARM, HasV6]>, 4354 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4355 4356def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 4357 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4358 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", 4359 [(set GPR:$RdLo, GPR:$RdHi, 4360 (umullohi GPR:$Rn, GPR:$Rm))]>, 4361 Requires<[IsARM, HasV6]>, 4362 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL]>; 4363 4364let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 4365def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4366 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4367 4, IIC_iMUL64, 4368 [(set GPR:$RdLo, GPR:$RdHi, 4369 (smullohi GPR:$Rn, GPR:$Rm))], 4370 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4371 Requires<[IsARM, NoV6]>, 4372 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4373 4374def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4375 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4376 4, IIC_iMUL64, 4377 [(set GPR:$RdLo, GPR:$RdHi, 4378 (umullohi GPR:$Rn, GPR:$Rm))], 4379 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4380 Requires<[IsARM, NoV6]>, 4381 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4382} 4383} 4384 4385// Multiply + accumulate 4386def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 4387 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4388 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4389 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4390 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4391def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 4392 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4393 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4394 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4395 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4396 4397def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 4398 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4399 IIC_iMAC64, 4400 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4401 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4402 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> { 4403 bits<4> RdLo; 4404 bits<4> RdHi; 4405 bits<4> Rm; 4406 bits<4> Rn; 4407 let Inst{19-16} = RdHi; 4408 let Inst{15-12} = RdLo; 4409 let Inst{11-8} = Rm; 4410 let Inst{3-0} = Rn; 4411} 4412 4413let Constraints = 4414 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 4415def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4416 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4417 4, IIC_iMAC64, [], 4418 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4419 pred:$p, cc_out:$s)>, 4420 Requires<[IsARM, NoV6]>, 4421 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4422def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4423 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4424 4, IIC_iMAC64, [], 4425 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4426 pred:$p, cc_out:$s)>, 4427 Requires<[IsARM, NoV6]>, 4428 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4429} 4430 4431} // hasSideEffects 4432 4433// Most significant word multiply 4434def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4435 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 4436 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 4437 Requires<[IsARM, HasV6]>, 4438 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4439 let Inst{15-12} = 0b1111; 4440} 4441 4442def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4443 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", 4444 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>, 4445 Requires<[IsARM, HasV6]>, 4446 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4447 let Inst{15-12} = 0b1111; 4448} 4449 4450def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 4451 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4452 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 4453 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 4454 Requires<[IsARM, HasV6, UseMulOps]>, 4455 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4456 4457def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 4458 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4459 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", 4460 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4461 Requires<[IsARM, HasV6]>, 4462 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4463 4464def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 4465 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4466 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 4467 Requires<[IsARM, HasV6, UseMulOps]>, 4468 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4469 4470def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 4471 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4472 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", 4473 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4474 Requires<[IsARM, HasV6]>, 4475 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4476 4477multiclass AI_smul<string opc> { 4478 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4479 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 4480 [(set GPR:$Rd, (bb_mul GPR:$Rn, GPR:$Rm))]>, 4481 Requires<[IsARM, HasV5TE]>, 4482 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4483 4484 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4485 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 4486 [(set GPR:$Rd, (bt_mul GPR:$Rn, GPR:$Rm))]>, 4487 Requires<[IsARM, HasV5TE]>, 4488 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4489 4490 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4491 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 4492 [(set GPR:$Rd, (tb_mul GPR:$Rn, GPR:$Rm))]>, 4493 Requires<[IsARM, HasV5TE]>, 4494 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4495 4496 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4497 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 4498 [(set GPR:$Rd, (tt_mul GPR:$Rn, GPR:$Rm))]>, 4499 Requires<[IsARM, HasV5TE]>, 4500 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4501 4502 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4503 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 4504 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>, 4505 Requires<[IsARM, HasV5TE]>, 4506 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4507 4508 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4509 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 4510 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>, 4511 Requires<[IsARM, HasV5TE]>, 4512 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4513} 4514 4515 4516multiclass AI_smla<string opc> { 4517 let DecoderMethod = "DecodeSMLAInstruction" in { 4518 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 4519 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4520 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 4521 [(set GPRnopc:$Rd, (add GPR:$Ra, 4522 (bb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4523 Requires<[IsARM, HasV5TE, UseMulOps]>, 4524 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4525 4526 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 4527 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4528 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 4529 [(set GPRnopc:$Rd, (add GPR:$Ra, 4530 (bt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4531 Requires<[IsARM, HasV5TE, UseMulOps]>, 4532 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4533 4534 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 4535 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4536 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 4537 [(set GPRnopc:$Rd, (add GPR:$Ra, 4538 (tb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4539 Requires<[IsARM, HasV5TE, UseMulOps]>, 4540 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4541 4542 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 4543 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4544 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 4545 [(set GPRnopc:$Rd, (add GPR:$Ra, 4546 (tt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4547 Requires<[IsARM, HasV5TE, UseMulOps]>, 4548 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4549 4550 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 4551 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4552 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 4553 [(set GPRnopc:$Rd, 4554 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4555 Requires<[IsARM, HasV5TE, UseMulOps]>, 4556 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4557 4558 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 4559 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4560 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 4561 [(set GPRnopc:$Rd, 4562 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4563 Requires<[IsARM, HasV5TE, UseMulOps]>, 4564 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4565 } 4566} 4567 4568defm SMUL : AI_smul<"smul">; 4569defm SMLA : AI_smla<"smla">; 4570 4571// Halfword multiply accumulate long: SMLAL<x><y>. 4572class SMLAL<bits<2> opc1, string asm> 4573 : AMulxyI64<0b0001010, opc1, 4574 (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4575 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4576 IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4577 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4578 Requires<[IsARM, HasV5TE]>, 4579 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4580 4581def SMLALBB : SMLAL<0b00, "smlalbb">; 4582def SMLALBT : SMLAL<0b10, "smlalbt">; 4583def SMLALTB : SMLAL<0b01, "smlaltb">; 4584def SMLALTT : SMLAL<0b11, "smlaltt">; 4585 4586def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4587 (SMLALBB $Rn, $Rm, $RLo, $RHi)>; 4588def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4589 (SMLALBT $Rn, $Rm, $RLo, $RHi)>; 4590def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4591 (SMLALTB $Rn, $Rm, $RLo, $RHi)>; 4592def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4593 (SMLALTT $Rn, $Rm, $RLo, $RHi)>; 4594 4595// Helper class for AI_smld. 4596class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 4597 InstrItinClass itin, string opc, string asm> 4598 : AI<oops, iops, MulFrm, itin, opc, asm, []>, 4599 Requires<[IsARM, HasV6]> { 4600 bits<4> Rn; 4601 bits<4> Rm; 4602 let Inst{27-23} = 0b01110; 4603 let Inst{22} = long; 4604 let Inst{21-20} = 0b00; 4605 let Inst{11-8} = Rm; 4606 let Inst{7} = 0; 4607 let Inst{6} = sub; 4608 let Inst{5} = swap; 4609 let Inst{4} = 1; 4610 let Inst{3-0} = Rn; 4611} 4612class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 4613 InstrItinClass itin, string opc, string asm> 4614 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4615 bits<4> Rd; 4616 let Inst{15-12} = 0b1111; 4617 let Inst{19-16} = Rd; 4618} 4619class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 4620 InstrItinClass itin, string opc, string asm> 4621 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4622 bits<4> Ra; 4623 bits<4> Rd; 4624 let Inst{19-16} = Rd; 4625 let Inst{15-12} = Ra; 4626} 4627class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 4628 InstrItinClass itin, string opc, string asm> 4629 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4630 bits<4> RdLo; 4631 bits<4> RdHi; 4632 let Inst{19-16} = RdHi; 4633 let Inst{15-12} = RdLo; 4634} 4635 4636multiclass AI_smld<bit sub, string opc> { 4637 4638 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 4639 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4640 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">, 4641 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4642 4643 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 4644 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4645 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">, 4646 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4647 4648 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4649 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4650 NoItinerary, 4651 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">, 4652 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4653 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4654 4655 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4656 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4657 NoItinerary, 4658 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">, 4659 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4660 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4661} 4662 4663defm SMLA : AI_smld<0, "smla">; 4664defm SMLS : AI_smld<1, "smls">; 4665 4666def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4667 (SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4668def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4669 (SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4670def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4671 (SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4672def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4673 (SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4674def : ARMV6Pat<(ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4675 (SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4676def : ARMV6Pat<(ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4677 (SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4678def : ARMV6Pat<(ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4679 (SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4680def : ARMV6Pat<(ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4681 (SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4682 4683multiclass AI_sdml<bit sub, string opc> { 4684 4685 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 4686 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">, 4687 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4688 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 4689 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">, 4690 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4691} 4692 4693defm SMUA : AI_sdml<0, "smua">; 4694defm SMUS : AI_sdml<1, "smus">; 4695 4696def : ARMV6Pat<(int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm), 4697 (SMUAD GPRnopc:$Rn, GPRnopc:$Rm)>; 4698def : ARMV6Pat<(int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm), 4699 (SMUADX GPRnopc:$Rn, GPRnopc:$Rm)>; 4700def : ARMV6Pat<(int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm), 4701 (SMUSD GPRnopc:$Rn, GPRnopc:$Rm)>; 4702def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm), 4703 (SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)>; 4704 4705//===----------------------------------------------------------------------===// 4706// Division Instructions (ARMv7-A with virtualization extension) 4707// 4708def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4709 "sdiv", "\t$Rd, $Rn, $Rm", 4710 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 4711 Requires<[IsARM, HasDivideInARM]>, 4712 Sched<[WriteDIV]>; 4713 4714def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4715 "udiv", "\t$Rd, $Rn, $Rm", 4716 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 4717 Requires<[IsARM, HasDivideInARM]>, 4718 Sched<[WriteDIV]>; 4719 4720//===----------------------------------------------------------------------===// 4721// Misc. Arithmetic Instructions. 4722// 4723 4724def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 4725 IIC_iUNAr, "clz", "\t$Rd, $Rm", 4726 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 4727 Sched<[WriteALU]>; 4728 4729def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4730 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 4731 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>, 4732 Requires<[IsARM, HasV6T2]>, 4733 Sched<[WriteALU]>; 4734 4735def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4736 IIC_iUNAr, "rev", "\t$Rd, $Rm", 4737 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 4738 Sched<[WriteALU]>; 4739 4740let AddedComplexity = 5 in 4741def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4742 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 4743 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 4744 Requires<[IsARM, HasV6]>, 4745 Sched<[WriteALU]>; 4746 4747def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), 4748 (REV16 (LDRH addrmode3:$addr))>; 4749def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), 4750 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; 4751 4752let AddedComplexity = 5 in 4753def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4754 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 4755 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 4756 Requires<[IsARM, HasV6]>, 4757 Sched<[WriteALU]>; 4758 4759def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 4760 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 4761 (REVSH GPR:$Rm)>; 4762 4763def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 4764 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 4765 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 4766 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 4767 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4768 0xFFFF0000)))]>, 4769 Requires<[IsARM, HasV6]>, 4770 Sched<[WriteALUsi, ReadALU]>; 4771 4772// Alternate cases for PKHBT where identities eliminate some nodes. 4773def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 4774 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 4775def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 4776 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 4777 4778// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4779// will match the pattern below. 4780def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4781 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4782 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4783 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4784 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4785 0xFFFF)))]>, 4786 Requires<[IsARM, HasV6]>, 4787 Sched<[WriteALUsi, ReadALU]>; 4788 4789// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4790// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4791// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4792// pkhtb src1, src2, asr (17..31). 4793def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4794 (srl GPRnopc:$src2, imm16:$sh)), 4795 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4796def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4797 (sra GPRnopc:$src2, imm16_31:$sh)), 4798 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4799def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4800 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4801 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4802 4803//===----------------------------------------------------------------------===// 4804// CRC Instructions 4805// 4806// Polynomials: 4807// + CRC32{B,H,W} 0x04C11DB7 4808// + CRC32C{B,H,W} 0x1EDC6F41 4809// 4810 4811class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4812 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4813 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4814 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4815 Requires<[IsARM, HasV8, HasCRC]> { 4816 bits<4> Rd; 4817 bits<4> Rn; 4818 bits<4> Rm; 4819 4820 let Inst{31-28} = 0b1110; 4821 let Inst{27-23} = 0b00010; 4822 let Inst{22-21} = sz; 4823 let Inst{20} = 0; 4824 let Inst{19-16} = Rn; 4825 let Inst{15-12} = Rd; 4826 let Inst{11-10} = 0b00; 4827 let Inst{9} = C; 4828 let Inst{8} = 0; 4829 let Inst{7-4} = 0b0100; 4830 let Inst{3-0} = Rm; 4831 4832 let Unpredictable{11-8} = 0b1101; 4833} 4834 4835def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4836def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4837def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4838def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4839def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4840def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4841 4842//===----------------------------------------------------------------------===// 4843// ARMv8.1a Privilege Access Never extension 4844// 4845// SETPAN #imm1 4846 4847def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan", 4848 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> { 4849 bits<1> imm; 4850 4851 let Inst{31-28} = 0b1111; 4852 let Inst{27-20} = 0b00010001; 4853 let Inst{19-16} = 0b0000; 4854 let Inst{15-10} = 0b000000; 4855 let Inst{9} = imm; 4856 let Inst{8} = 0b0; 4857 let Inst{7-4} = 0b0000; 4858 let Inst{3-0} = 0b0000; 4859 4860 let Unpredictable{19-16} = 0b1111; 4861 let Unpredictable{15-10} = 0b111111; 4862 let Unpredictable{8} = 0b1; 4863 let Unpredictable{3-0} = 0b1111; 4864} 4865 4866//===----------------------------------------------------------------------===// 4867// Comparison Instructions... 4868// 4869 4870defm CMP : AI1_cmp_irs<0b1010, "cmp", 4871 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, ARMcmp>; 4872 4873// ARMcmpZ can re-use the above instruction definitions. 4874def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm), 4875 (CMPri GPR:$src, mod_imm:$imm)>; 4876def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4877 (CMPrr GPR:$src, GPR:$rhs)>; 4878def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4879 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4880def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4881 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4882 4883// CMN register-integer 4884let isCompare = 1, Defs = [CPSR] in { 4885def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi, 4886 "cmn", "\t$Rn, $imm", 4887 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>, 4888 Sched<[WriteCMP, ReadALU]> { 4889 bits<4> Rn; 4890 bits<12> imm; 4891 let Inst{25} = 1; 4892 let Inst{20} = 1; 4893 let Inst{19-16} = Rn; 4894 let Inst{15-12} = 0b0000; 4895 let Inst{11-0} = imm; 4896 4897 let Unpredictable{15-12} = 0b1111; 4898} 4899 4900// CMN register-register/shift 4901def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4902 "cmn", "\t$Rn, $Rm", 4903 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4904 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4905 bits<4> Rn; 4906 bits<4> Rm; 4907 let isCommutable = 1; 4908 let Inst{25} = 0; 4909 let Inst{20} = 1; 4910 let Inst{19-16} = Rn; 4911 let Inst{15-12} = 0b0000; 4912 let Inst{11-4} = 0b00000000; 4913 let Inst{3-0} = Rm; 4914 4915 let Unpredictable{15-12} = 0b1111; 4916} 4917 4918def CMNzrsi : AI1<0b1011, (outs), 4919 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4920 "cmn", "\t$Rn, $shift", 4921 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4922 GPR:$Rn, so_reg_imm:$shift)]>, 4923 Sched<[WriteCMPsi, ReadALU]> { 4924 bits<4> Rn; 4925 bits<12> shift; 4926 let Inst{25} = 0; 4927 let Inst{20} = 1; 4928 let Inst{19-16} = Rn; 4929 let Inst{15-12} = 0b0000; 4930 let Inst{11-5} = shift{11-5}; 4931 let Inst{4} = 0; 4932 let Inst{3-0} = shift{3-0}; 4933 4934 let Unpredictable{15-12} = 0b1111; 4935} 4936 4937def CMNzrsr : AI1<0b1011, (outs), 4938 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4939 "cmn", "\t$Rn, $shift", 4940 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4941 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4942 Sched<[WriteCMPsr, ReadALU]> { 4943 bits<4> Rn; 4944 bits<12> shift; 4945 let Inst{25} = 0; 4946 let Inst{20} = 1; 4947 let Inst{19-16} = Rn; 4948 let Inst{15-12} = 0b0000; 4949 let Inst{11-8} = shift{11-8}; 4950 let Inst{7} = 0; 4951 let Inst{6-5} = shift{6-5}; 4952 let Inst{4} = 1; 4953 let Inst{3-0} = shift{3-0}; 4954 4955 let Unpredictable{15-12} = 0b1111; 4956} 4957 4958} 4959 4960def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm), 4961 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4962 4963def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm), 4964 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4965 4966// Note that TST/TEQ don't set all the same flags that CMP does! 4967defm TST : AI1_cmp_irs<0b1000, "tst", 4968 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4969 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1, 4970 "DecodeTSTInstruction">; 4971defm TEQ : AI1_cmp_irs<0b1001, "teq", 4972 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4973 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4974 4975// Pseudo i64 compares for some floating point compares. 4976let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4977 Defs = [CPSR] in { 4978def BCCi64 : PseudoInst<(outs), 4979 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4980 IIC_Br, 4981 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4982 Sched<[WriteBr]>; 4983 4984def BCCZi64 : PseudoInst<(outs), 4985 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4986 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4987 Sched<[WriteBr]>; 4988} // usesCustomInserter 4989 4990 4991// Conditional moves 4992let hasSideEffects = 0 in { 4993 4994let isCommutable = 1, isSelect = 1 in 4995def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4996 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4997 4, IIC_iCMOVr, 4998 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4999 cmovpred:$p))]>, 5000 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 5001 5002def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 5003 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 5004 4, IIC_iCMOVsr, 5005 [(set GPR:$Rd, 5006 (ARMcmov GPR:$false, so_reg_imm:$shift, 5007 cmovpred:$p))]>, 5008 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 5009def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 5010 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 5011 4, IIC_iCMOVsr, 5012 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 5013 cmovpred:$p))]>, 5014 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 5015 5016 5017let isMoveImm = 1 in 5018def MOVCCi16 5019 : ARMPseudoInst<(outs GPR:$Rd), 5020 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 5021 4, IIC_iMOVi, 5022 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 5023 cmovpred:$p))]>, 5024 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 5025 Sched<[WriteALU]>; 5026 5027let isMoveImm = 1 in 5028def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 5029 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 5030 4, IIC_iCMOVi, 5031 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm, 5032 cmovpred:$p))]>, 5033 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 5034 5035// Two instruction predicate mov immediate. 5036let isMoveImm = 1 in 5037def MOVCCi32imm 5038 : ARMPseudoInst<(outs GPR:$Rd), 5039 (ins GPR:$false, i32imm:$src, cmovpred:$p), 5040 8, IIC_iCMOVix2, 5041 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 5042 cmovpred:$p))]>, 5043 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 5044 5045let isMoveImm = 1 in 5046def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 5047 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 5048 4, IIC_iCMOVi, 5049 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm, 5050 cmovpred:$p))]>, 5051 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 5052 5053} // hasSideEffects 5054 5055 5056//===----------------------------------------------------------------------===// 5057// Atomic operations intrinsics 5058// 5059 5060def MemBarrierOptOperand : AsmOperandClass { 5061 let Name = "MemBarrierOpt"; 5062 let ParserMethod = "parseMemBarrierOptOperand"; 5063} 5064def memb_opt : Operand<i32> { 5065 let PrintMethod = "printMemBOption"; 5066 let ParserMatchClass = MemBarrierOptOperand; 5067 let DecoderMethod = "DecodeMemBarrierOption"; 5068} 5069 5070def InstSyncBarrierOptOperand : AsmOperandClass { 5071 let Name = "InstSyncBarrierOpt"; 5072 let ParserMethod = "parseInstSyncBarrierOptOperand"; 5073} 5074def instsyncb_opt : Operand<i32> { 5075 let PrintMethod = "printInstSyncBOption"; 5076 let ParserMatchClass = InstSyncBarrierOptOperand; 5077 let DecoderMethod = "DecodeInstSyncBarrierOption"; 5078} 5079 5080def TraceSyncBarrierOptOperand : AsmOperandClass { 5081 let Name = "TraceSyncBarrierOpt"; 5082 let ParserMethod = "parseTraceSyncBarrierOptOperand"; 5083} 5084def tsb_opt : Operand<i32> { 5085 let PrintMethod = "printTraceSyncBOption"; 5086 let ParserMatchClass = TraceSyncBarrierOptOperand; 5087} 5088 5089// Memory barriers protect the atomic sequences 5090let hasSideEffects = 1 in { 5091def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 5092 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 5093 Requires<[IsARM, HasDB]> { 5094 bits<4> opt; 5095 let Inst{31-4} = 0xf57ff05; 5096 let Inst{3-0} = opt; 5097} 5098 5099def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 5100 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 5101 Requires<[IsARM, HasDB]> { 5102 bits<4> opt; 5103 let Inst{31-4} = 0xf57ff04; 5104 let Inst{3-0} = opt; 5105} 5106 5107// ISB has only full system option 5108def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 5109 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 5110 Requires<[IsARM, HasDB]> { 5111 bits<4> opt; 5112 let Inst{31-4} = 0xf57ff06; 5113 let Inst{3-0} = opt; 5114} 5115 5116let hasNoSchedulingInfo = 1 in 5117def TSB : AInoP<(outs), (ins tsb_opt:$opt), MiscFrm, NoItinerary, 5118 "tsb", "\t$opt", []>, Requires<[IsARM, HasV8_4a]> { 5119 let Inst{31-0} = 0xe320f012; 5120} 5121 5122} 5123 5124// Armv8.5-A speculation barrier 5125def SB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "sb", "", []>, 5126 Requires<[IsARM, HasSB]>, Sched<[]> { 5127 let Inst{31-0} = 0xf57ff070; 5128 let Unpredictable = 0x000fff0f; 5129 let hasSideEffects = 1; 5130} 5131 5132let usesCustomInserter = 1, Defs = [CPSR], hasNoSchedulingInfo = 1 in { 5133 // Pseudo instruction that combines movs + predicated rsbmi 5134 // to implement integer ABS 5135 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 5136} 5137 5138let usesCustomInserter = 1, Defs = [CPSR], hasNoSchedulingInfo = 1 in { 5139 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 5140 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 5141 NoItinerary, 5142 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 5143} 5144 5145let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in { 5146 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs... 5147 // Copies N registers worth of memory from address %src to address %dst 5148 // and returns the incremented addresses. N scratch register will 5149 // be attached for the copy to use. 5150 def MEMCPY : PseudoInst< 5151 (outs GPR:$newdst, GPR:$newsrc), 5152 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops), 5153 NoItinerary, 5154 [(set GPR:$newdst, GPR:$newsrc, 5155 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>; 5156} 5157 5158def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 5159 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 5160}]>; 5161 5162def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 5163 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 5164}]>; 5165 5166def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 5167 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 5168}]>; 5169 5170def strex_1 : PatFrag<(ops node:$val, node:$ptr), 5171 (int_arm_strex node:$val, node:$ptr), [{ 5172 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 5173}]>; 5174 5175def strex_2 : PatFrag<(ops node:$val, node:$ptr), 5176 (int_arm_strex node:$val, node:$ptr), [{ 5177 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 5178}]>; 5179 5180def strex_4 : PatFrag<(ops node:$val, node:$ptr), 5181 (int_arm_strex node:$val, node:$ptr), [{ 5182 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 5183}]>; 5184 5185def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 5186 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 5187}]>; 5188 5189def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 5190 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 5191}]>; 5192 5193def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 5194 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 5195}]>; 5196 5197def stlex_1 : PatFrag<(ops node:$val, node:$ptr), 5198 (int_arm_stlex node:$val, node:$ptr), [{ 5199 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 5200}]>; 5201 5202def stlex_2 : PatFrag<(ops node:$val, node:$ptr), 5203 (int_arm_stlex node:$val, node:$ptr), [{ 5204 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 5205}]>; 5206 5207def stlex_4 : PatFrag<(ops node:$val, node:$ptr), 5208 (int_arm_stlex node:$val, node:$ptr), [{ 5209 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 5210}]>; 5211 5212let mayLoad = 1 in { 5213def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5214 NoItinerary, "ldrexb", "\t$Rt, $addr", 5215 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 5216def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5217 NoItinerary, "ldrexh", "\t$Rt, $addr", 5218 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 5219def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5220 NoItinerary, "ldrex", "\t$Rt, $addr", 5221 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 5222let hasExtraDefRegAllocReq = 1 in 5223def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 5224 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 5225 let DecoderMethod = "DecodeDoubleRegLoad"; 5226} 5227 5228def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5229 NoItinerary, "ldaexb", "\t$Rt, $addr", 5230 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>; 5231def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5232 NoItinerary, "ldaexh", "\t$Rt, $addr", 5233 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>; 5234def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5235 NoItinerary, "ldaex", "\t$Rt, $addr", 5236 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>; 5237let hasExtraDefRegAllocReq = 1 in 5238def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 5239 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 5240 let DecoderMethod = "DecodeDoubleRegLoad"; 5241} 5242} 5243 5244let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 5245def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5246 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 5247 [(set GPR:$Rd, (strex_1 GPR:$Rt, 5248 addr_offset_none:$addr))]>; 5249def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5250 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 5251 [(set GPR:$Rd, (strex_2 GPR:$Rt, 5252 addr_offset_none:$addr))]>; 5253def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5254 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 5255 [(set GPR:$Rd, (strex_4 GPR:$Rt, 5256 addr_offset_none:$addr))]>; 5257let hasExtraSrcRegAllocReq = 1 in 5258def STREXD : AIstrex<0b01, (outs GPR:$Rd), 5259 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5260 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 5261 let DecoderMethod = "DecodeDoubleRegStore"; 5262} 5263def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5264 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 5265 [(set GPR:$Rd, 5266 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>; 5267def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5268 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 5269 [(set GPR:$Rd, 5270 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>; 5271def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5272 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 5273 [(set GPR:$Rd, 5274 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>; 5275let hasExtraSrcRegAllocReq = 1 in 5276def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 5277 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5278 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 5279 let DecoderMethod = "DecodeDoubleRegStore"; 5280} 5281} 5282 5283def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 5284 [(int_arm_clrex)]>, 5285 Requires<[IsARM, HasV6K]> { 5286 let Inst{31-0} = 0b11110101011111111111000000011111; 5287} 5288 5289def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5290 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 5291def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5292 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 5293 5294def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5295 (STLEXB GPR:$Rt, addr_offset_none:$addr)>; 5296def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5297 (STLEXH GPR:$Rt, addr_offset_none:$addr)>; 5298 5299class acquiring_load<PatFrag base> 5300 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 5301 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getSuccessOrdering(); 5302 return isAcquireOrStronger(Ordering); 5303}]>; 5304 5305def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 5306def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 5307def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 5308 5309class releasing_store<PatFrag base> 5310 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 5311 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getSuccessOrdering(); 5312 return isReleaseOrStronger(Ordering); 5313}]>; 5314 5315def atomic_store_release_8 : releasing_store<atomic_store_8>; 5316def atomic_store_release_16 : releasing_store<atomic_store_16>; 5317def atomic_store_release_32 : releasing_store<atomic_store_32>; 5318 5319let AddedComplexity = 8 in { 5320 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 5321 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 5322 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 5323 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 5324 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 5325 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 5326} 5327 5328// SWP/SWPB are deprecated in V6/V7 and optional in v7VE. 5329// FIXME Use InstAlias to generate LDREX/STREX pairs instead. 5330let mayLoad = 1, mayStore = 1 in { 5331def SWP : AIswp<0, (outs GPRnopc:$Rt), 5332 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 5333 Requires<[IsARM,PreV8]>; 5334def SWPB: AIswp<1, (outs GPRnopc:$Rt), 5335 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 5336 Requires<[IsARM,PreV8]>; 5337} 5338 5339//===----------------------------------------------------------------------===// 5340// Coprocessor Instructions. 5341// 5342 5343def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5344 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5345 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5346 [(int_arm_cdp timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn, 5347 timm:$CRm, timm:$opc2)]>, 5348 Requires<[IsARM,PreV8]> { 5349 bits<4> opc1; 5350 bits<4> CRn; 5351 bits<4> CRd; 5352 bits<4> cop; 5353 bits<3> opc2; 5354 bits<4> CRm; 5355 5356 let Inst{3-0} = CRm; 5357 let Inst{4} = 0; 5358 let Inst{7-5} = opc2; 5359 let Inst{11-8} = cop; 5360 let Inst{15-12} = CRd; 5361 let Inst{19-16} = CRn; 5362 let Inst{23-20} = opc1; 5363 5364 let DecoderNamespace = "CoProc"; 5365} 5366 5367def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5368 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5369 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5370 [(int_arm_cdp2 timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn, 5371 timm:$CRm, timm:$opc2)]>, 5372 Requires<[IsARM,PreV8]> { 5373 let Inst{31-28} = 0b1111; 5374 bits<4> opc1; 5375 bits<4> CRn; 5376 bits<4> CRd; 5377 bits<4> cop; 5378 bits<3> opc2; 5379 bits<4> CRm; 5380 5381 let Inst{3-0} = CRm; 5382 let Inst{4} = 0; 5383 let Inst{7-5} = opc2; 5384 let Inst{11-8} = cop; 5385 let Inst{15-12} = CRd; 5386 let Inst{19-16} = CRn; 5387 let Inst{23-20} = opc1; 5388 5389 let DecoderNamespace = "CoProc"; 5390} 5391 5392class ACI<dag oops, dag iops, string opc, string asm, 5393 list<dag> pattern, IndexMode im = IndexModeNone, 5394 AddrMode am = AddrModeNone> 5395 : I<oops, iops, am, 4, im, BrFrm, NoItinerary, 5396 opc, asm, "", pattern> { 5397 let Inst{27-25} = 0b110; 5398} 5399class ACInoP<dag oops, dag iops, string opc, string asm, 5400 list<dag> pattern, IndexMode im = IndexModeNone, 5401 AddrMode am = AddrModeNone> 5402 : InoP<oops, iops, am, 4, im, BrFrm, NoItinerary, 5403 opc, asm, "", pattern> { 5404 let Inst{31-28} = 0b1111; 5405 let Inst{27-25} = 0b110; 5406} 5407 5408let DecoderNamespace = "CoProc" in { 5409multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> { 5410 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5411 asm, "\t$cop, $CRd, $addr", pattern, IndexModeNone, 5412 AddrMode5> { 5413 bits<13> addr; 5414 bits<4> cop; 5415 bits<4> CRd; 5416 let Inst{24} = 1; // P = 1 5417 let Inst{23} = addr{8}; 5418 let Inst{22} = Dbit; 5419 let Inst{21} = 0; // W = 0 5420 let Inst{20} = load; 5421 let Inst{19-16} = addr{12-9}; 5422 let Inst{15-12} = CRd; 5423 let Inst{11-8} = cop; 5424 let Inst{7-0} = addr{7-0}; 5425 let DecoderMethod = "DecodeCopMemInstruction"; 5426 } 5427 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5428 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5429 bits<13> addr; 5430 bits<4> cop; 5431 bits<4> CRd; 5432 let Inst{24} = 1; // P = 1 5433 let Inst{23} = addr{8}; 5434 let Inst{22} = Dbit; 5435 let Inst{21} = 1; // W = 1 5436 let Inst{20} = load; 5437 let Inst{19-16} = addr{12-9}; 5438 let Inst{15-12} = CRd; 5439 let Inst{11-8} = cop; 5440 let Inst{7-0} = addr{7-0}; 5441 let DecoderMethod = "DecodeCopMemInstruction"; 5442 } 5443 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5444 postidx_imm8s4:$offset), 5445 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5446 bits<9> offset; 5447 bits<4> addr; 5448 bits<4> cop; 5449 bits<4> CRd; 5450 let Inst{24} = 0; // P = 0 5451 let Inst{23} = offset{8}; 5452 let Inst{22} = Dbit; 5453 let Inst{21} = 1; // W = 1 5454 let Inst{20} = load; 5455 let Inst{19-16} = addr; 5456 let Inst{15-12} = CRd; 5457 let Inst{11-8} = cop; 5458 let Inst{7-0} = offset{7-0}; 5459 let DecoderMethod = "DecodeCopMemInstruction"; 5460 } 5461 def _OPTION : ACI<(outs), 5462 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5463 coproc_option_imm:$option), 5464 asm, "\t$cop, $CRd, $addr, $option", []> { 5465 bits<8> option; 5466 bits<4> addr; 5467 bits<4> cop; 5468 bits<4> CRd; 5469 let Inst{24} = 0; // P = 0 5470 let Inst{23} = 1; // U = 1 5471 let Inst{22} = Dbit; 5472 let Inst{21} = 0; // W = 0 5473 let Inst{20} = load; 5474 let Inst{19-16} = addr; 5475 let Inst{15-12} = CRd; 5476 let Inst{11-8} = cop; 5477 let Inst{7-0} = option; 5478 let DecoderMethod = "DecodeCopMemInstruction"; 5479 } 5480} 5481multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> { 5482 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5483 asm, "\t$cop, $CRd, $addr", pattern, IndexModeNone, 5484 AddrMode5> { 5485 bits<13> addr; 5486 bits<4> cop; 5487 bits<4> CRd; 5488 let Inst{24} = 1; // P = 1 5489 let Inst{23} = addr{8}; 5490 let Inst{22} = Dbit; 5491 let Inst{21} = 0; // W = 0 5492 let Inst{20} = load; 5493 let Inst{19-16} = addr{12-9}; 5494 let Inst{15-12} = CRd; 5495 let Inst{11-8} = cop; 5496 let Inst{7-0} = addr{7-0}; 5497 let DecoderMethod = "DecodeCopMemInstruction"; 5498 } 5499 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5500 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5501 bits<13> addr; 5502 bits<4> cop; 5503 bits<4> CRd; 5504 let Inst{24} = 1; // P = 1 5505 let Inst{23} = addr{8}; 5506 let Inst{22} = Dbit; 5507 let Inst{21} = 1; // W = 1 5508 let Inst{20} = load; 5509 let Inst{19-16} = addr{12-9}; 5510 let Inst{15-12} = CRd; 5511 let Inst{11-8} = cop; 5512 let Inst{7-0} = addr{7-0}; 5513 let DecoderMethod = "DecodeCopMemInstruction"; 5514 } 5515 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5516 postidx_imm8s4:$offset), 5517 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5518 bits<9> offset; 5519 bits<4> addr; 5520 bits<4> cop; 5521 bits<4> CRd; 5522 let Inst{24} = 0; // P = 0 5523 let Inst{23} = offset{8}; 5524 let Inst{22} = Dbit; 5525 let Inst{21} = 1; // W = 1 5526 let Inst{20} = load; 5527 let Inst{19-16} = addr; 5528 let Inst{15-12} = CRd; 5529 let Inst{11-8} = cop; 5530 let Inst{7-0} = offset{7-0}; 5531 let DecoderMethod = "DecodeCopMemInstruction"; 5532 } 5533 def _OPTION : ACInoP<(outs), 5534 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5535 coproc_option_imm:$option), 5536 asm, "\t$cop, $CRd, $addr, $option", []> { 5537 bits<8> option; 5538 bits<4> addr; 5539 bits<4> cop; 5540 bits<4> CRd; 5541 let Inst{24} = 0; // P = 0 5542 let Inst{23} = 1; // U = 1 5543 let Inst{22} = Dbit; 5544 let Inst{21} = 0; // W = 0 5545 let Inst{20} = load; 5546 let Inst{19-16} = addr; 5547 let Inst{15-12} = CRd; 5548 let Inst{11-8} = cop; 5549 let Inst{7-0} = option; 5550 let DecoderMethod = "DecodeCopMemInstruction"; 5551 } 5552} 5553 5554defm LDC : LdStCop <1, 0, "ldc", [(int_arm_ldc timm:$cop, timm:$CRd, addrmode5:$addr)]>; 5555defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl timm:$cop, timm:$CRd, addrmode5:$addr)]>; 5556defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5557defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5558 5559defm STC : LdStCop <0, 0, "stc", [(int_arm_stc timm:$cop, timm:$CRd, addrmode5:$addr)]>; 5560defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl timm:$cop, timm:$CRd, addrmode5:$addr)]>; 5561defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5562defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5563 5564} // DecoderNamespace = "CoProc" 5565 5566//===----------------------------------------------------------------------===// 5567// Move between coprocessor and ARM core register. 5568// 5569 5570class MovRCopro<string opc, bit direction, dag oops, dag iops, 5571 list<dag> pattern> 5572 : ABI<0b1110, oops, iops, NoItinerary, opc, 5573 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 5574 let Inst{20} = direction; 5575 let Inst{4} = 1; 5576 5577 bits<4> Rt; 5578 bits<4> cop; 5579 bits<3> opc1; 5580 bits<3> opc2; 5581 bits<4> CRm; 5582 bits<4> CRn; 5583 5584 let Inst{15-12} = Rt; 5585 let Inst{11-8} = cop; 5586 let Inst{23-21} = opc1; 5587 let Inst{7-5} = opc2; 5588 let Inst{3-0} = CRm; 5589 let Inst{19-16} = CRn; 5590 5591 let DecoderNamespace = "CoProc"; 5592} 5593 5594def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 5595 (outs), 5596 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5597 c_imm:$CRm, imm0_7:$opc2), 5598 [(int_arm_mcr timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn, 5599 timm:$CRm, timm:$opc2)]>, 5600 ComplexDeprecationPredicate<"MCR">; 5601def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 5602 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5603 c_imm:$CRm, 0, pred:$p)>; 5604def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 5605 (outs GPRwithAPSR:$Rt), 5606 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5607 imm0_7:$opc2), []>, 5608 ComplexDeprecationPredicate<"MRC">; 5609def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 5610 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5611 c_imm:$CRm, 0, pred:$p)>; 5612 5613def : ARMPat<(int_arm_mrc timm:$cop, timm:$opc1, timm:$CRn, timm:$CRm, timm:$opc2), 5614 (MRC p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2)>; 5615 5616class MovRCopro2<string opc, bit direction, dag oops, dag iops, 5617 list<dag> pattern> 5618 : ABXI<0b1110, oops, iops, NoItinerary, 5619 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 5620 let Inst{31-24} = 0b11111110; 5621 let Inst{20} = direction; 5622 let Inst{4} = 1; 5623 5624 bits<4> Rt; 5625 bits<4> cop; 5626 bits<3> opc1; 5627 bits<3> opc2; 5628 bits<4> CRm; 5629 bits<4> CRn; 5630 5631 let Inst{15-12} = Rt; 5632 let Inst{11-8} = cop; 5633 let Inst{23-21} = opc1; 5634 let Inst{7-5} = opc2; 5635 let Inst{3-0} = CRm; 5636 let Inst{19-16} = CRn; 5637 5638 let DecoderNamespace = "CoProc"; 5639} 5640 5641def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 5642 (outs), 5643 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5644 c_imm:$CRm, imm0_7:$opc2), 5645 [(int_arm_mcr2 timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn, 5646 timm:$CRm, timm:$opc2)]>, 5647 Requires<[IsARM,PreV8]>; 5648def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", 5649 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5650 c_imm:$CRm, 0)>; 5651def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 5652 (outs GPRwithAPSR:$Rt), 5653 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5654 imm0_7:$opc2), []>, 5655 Requires<[IsARM,PreV8]>; 5656def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", 5657 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5658 c_imm:$CRm, 0)>; 5659 5660def : ARMV5TPat<(int_arm_mrc2 timm:$cop, timm:$opc1, timm:$CRn, 5661 timm:$CRm, timm:$opc2), 5662 (MRC2 p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2)>; 5663 5664class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag> 5665 pattern = []> 5666 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", 5667 pattern> { 5668 5669 let Inst{23-21} = 0b010; 5670 let Inst{20} = direction; 5671 5672 bits<4> Rt; 5673 bits<4> Rt2; 5674 bits<4> cop; 5675 bits<4> opc1; 5676 bits<4> CRm; 5677 5678 let Inst{15-12} = Rt; 5679 let Inst{19-16} = Rt2; 5680 let Inst{11-8} = cop; 5681 let Inst{7-4} = opc1; 5682 let Inst{3-0} = CRm; 5683} 5684 5685def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 5686 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5687 GPRnopc:$Rt2, c_imm:$CRm), 5688 [(int_arm_mcrr timm:$cop, timm:$opc1, GPRnopc:$Rt, 5689 GPRnopc:$Rt2, timm:$CRm)]>; 5690def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */, 5691 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5692 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5693 5694class MovRRCopro2<string opc, bit direction, dag oops, dag iops, 5695 list<dag> pattern = []> 5696 : ABXI<0b1100, oops, iops, NoItinerary, 5697 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5698 Requires<[IsARM,PreV8]> { 5699 let Inst{31-28} = 0b1111; 5700 let Inst{23-21} = 0b010; 5701 let Inst{20} = direction; 5702 5703 bits<4> Rt; 5704 bits<4> Rt2; 5705 bits<4> cop; 5706 bits<4> opc1; 5707 bits<4> CRm; 5708 5709 let Inst{15-12} = Rt; 5710 let Inst{19-16} = Rt2; 5711 let Inst{11-8} = cop; 5712 let Inst{7-4} = opc1; 5713 let Inst{3-0} = CRm; 5714 5715 let DecoderMethod = "DecoderForMRRC2AndMCRR2"; 5716} 5717 5718def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5719 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5720 GPRnopc:$Rt2, c_imm:$CRm), 5721 [(int_arm_mcrr2 timm:$cop, timm:$opc1, GPRnopc:$Rt, 5722 GPRnopc:$Rt2, timm:$CRm)]>; 5723 5724def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */, 5725 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5726 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5727 5728//===----------------------------------------------------------------------===// 5729// Move between special register and ARM core register 5730// 5731 5732// Move to ARM core register from Special Register 5733def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5734 "mrs", "\t$Rd, apsr", []> { 5735 bits<4> Rd; 5736 let Inst{23-16} = 0b00001111; 5737 let Unpredictable{19-17} = 0b111; 5738 5739 let Inst{15-12} = Rd; 5740 5741 let Inst{11-0} = 0b000000000000; 5742 let Unpredictable{11-0} = 0b110100001111; 5743} 5744 5745def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>, 5746 Requires<[IsARM]>; 5747 5748// The MRSsys instruction is the MRS instruction from the ARM ARM, 5749// section B9.3.9, with the R bit set to 1. 5750def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5751 "mrs", "\t$Rd, spsr", []> { 5752 bits<4> Rd; 5753 let Inst{23-16} = 0b01001111; 5754 let Unpredictable{19-16} = 0b1111; 5755 5756 let Inst{15-12} = Rd; 5757 5758 let Inst{11-0} = 0b000000000000; 5759 let Unpredictable{11-0} = 0b110100001111; 5760} 5761 5762// However, the MRS (banked register) system instruction (ARMv7VE) *does* have a 5763// separate encoding (distinguished by bit 5. 5764def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked), 5765 NoItinerary, "mrs", "\t$Rd, $banked", []>, 5766 Requires<[IsARM, HasVirtualization]> { 5767 bits<6> banked; 5768 bits<4> Rd; 5769 5770 let Inst{23} = 0; 5771 let Inst{22} = banked{5}; // R bit 5772 let Inst{21-20} = 0b00; 5773 let Inst{19-16} = banked{3-0}; 5774 let Inst{15-12} = Rd; 5775 let Inst{11-9} = 0b001; 5776 let Inst{8} = banked{4}; 5777 let Inst{7-0} = 0b00000000; 5778} 5779 5780// Move from ARM core register to Special Register 5781// 5782// No need to have both system and application versions of MSR (immediate) or 5783// MSR (register), the encodings are the same and the assembly parser has no way 5784// to distinguish between them. The mask operand contains the special register 5785// (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be 5786// accessed in the special register. 5787let Defs = [CPSR] in 5788def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5789 "msr", "\t$mask, $Rn", []> { 5790 bits<5> mask; 5791 bits<4> Rn; 5792 5793 let Inst{23} = 0; 5794 let Inst{22} = mask{4}; // R bit 5795 let Inst{21-20} = 0b10; 5796 let Inst{19-16} = mask{3-0}; 5797 let Inst{15-12} = 0b1111; 5798 let Inst{11-4} = 0b00000000; 5799 let Inst{3-0} = Rn; 5800} 5801 5802let Defs = [CPSR] in 5803def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary, 5804 "msr", "\t$mask, $imm", []> { 5805 bits<5> mask; 5806 bits<12> imm; 5807 5808 let Inst{23} = 0; 5809 let Inst{22} = mask{4}; // R bit 5810 let Inst{21-20} = 0b10; 5811 let Inst{19-16} = mask{3-0}; 5812 let Inst{15-12} = 0b1111; 5813 let Inst{11-0} = imm; 5814} 5815 5816// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a 5817// separate encoding (distinguished by bit 5. 5818def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn), 5819 NoItinerary, "msr", "\t$banked, $Rn", []>, 5820 Requires<[IsARM, HasVirtualization]> { 5821 bits<6> banked; 5822 bits<4> Rn; 5823 5824 let Inst{23} = 0; 5825 let Inst{22} = banked{5}; // R bit 5826 let Inst{21-20} = 0b10; 5827 let Inst{19-16} = banked{3-0}; 5828 let Inst{15-12} = 0b1111; 5829 let Inst{11-9} = 0b001; 5830 let Inst{8} = banked{4}; 5831 let Inst{7-4} = 0b0000; 5832 let Inst{3-0} = Rn; 5833} 5834 5835// Dynamic stack allocation yields a _chkstk for Windows targets. These calls 5836// are needed to probe the stack when allocating more than 5837// 4k bytes in one go. Touching the stack at 4K increments is necessary to 5838// ensure that the guard pages used by the OS virtual memory manager are 5839// allocated in correct sequence. 5840// The main point of having separate instruction are extra unmodelled effects 5841// (compared to ordinary calls) like stack pointer change. 5842 5843def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone, 5844 [SDNPHasChain, SDNPSideEffect]>; 5845let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP], hasNoSchedulingInfo = 1 in 5846 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>; 5847 5848def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK, 5849 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 5850let usesCustomInserter = 1, Defs = [CPSR], hasNoSchedulingInfo = 1 in 5851 def WIN__DBZCHK : PseudoInst<(outs), (ins tGPR:$divisor), NoItinerary, 5852 [(win__dbzchk tGPR:$divisor)]>; 5853 5854//===----------------------------------------------------------------------===// 5855// TLS Instructions 5856// 5857 5858// __aeabi_read_tp preserves the registers r1-r3. 5859// This is a pseudo inst so that we can get the encoding right, 5860// complete with fixup for the aeabi_read_tp function. 5861// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern 5862// is defined in "ARMInstrThumb.td". 5863let isCall = 1, 5864 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5865 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br, 5866 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>, 5867 Requires<[IsARM, IsReadTPSoft]>; 5868} 5869 5870// Reading thread pointer from coprocessor register 5871def : ARMPat<(ARMthread_pointer), (MRC 15, 0, 13, 0, 3)>, 5872 Requires<[IsARM, IsReadTPHard]>; 5873 5874//===----------------------------------------------------------------------===// 5875// SJLJ Exception handling intrinsics 5876// eh_sjlj_setjmp() is an instruction sequence to store the return 5877// address and save #0 in R0 for the non-longjmp case. 5878// Since by its nature we may be coming from some other function to get 5879// here, and we're using the stack frame for the containing function to 5880// save/restore registers, we can't keep anything live in regs across 5881// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5882// when we get here from a longjmp(). We force everything out of registers 5883// except for our own input by listing the relevant registers in Defs. By 5884// doing so, we also cause the prologue/epilogue code to actively preserve 5885// all of the callee-saved registers, which is exactly what we want. 5886// A constant value is passed in $val, and we use the location as a scratch. 5887// 5888// These are pseudo-instructions and are lowered to individual MC-insts, so 5889// no encoding information is necessary. 5890let Defs = 5891 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5892 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5893 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5894 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5895 NoItinerary, 5896 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5897 Requires<[IsARM, HasVFP2]>; 5898} 5899 5900let Defs = 5901 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5902 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5903 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5904 NoItinerary, 5905 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5906 Requires<[IsARM, NoVFP]>; 5907} 5908 5909// FIXME: Non-IOS version(s) 5910let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5911 Defs = [ R7, LR, SP ] in { 5912def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5913 NoItinerary, 5914 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5915 Requires<[IsARM]>; 5916} 5917 5918let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in 5919def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary, 5920 [(ARMeh_sjlj_setup_dispatch)]>; 5921 5922// eh.sjlj.dispatchsetup pseudo-instruction. 5923// This pseudo is used for both ARM and Thumb. Any differences are handled when 5924// the pseudo is expanded (which happens before any passes that need the 5925// instruction size). 5926let isBarrier = 1 in 5927def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5928 5929 5930//===----------------------------------------------------------------------===// 5931// Non-Instruction Patterns 5932// 5933 5934// ARMv4 indirect branch using (MOVr PC, dst) 5935let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5936 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5937 4, IIC_Br, [(brind GPR:$dst)], 5938 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5939 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5940 5941let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in 5942 def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst), 5943 4, IIC_Br, [], 5944 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5945 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5946 5947// Large immediate handling. 5948 5949// 32-bit immediate using two piece mod_imms or movw + movt. 5950// This is a single pseudo instruction, the benefit is that it can be remat'd 5951// as a single unit instead of having to handle reg inputs. 5952// FIXME: Remove this when we can do generalized remat. 5953let isReMaterializable = 1, isMoveImm = 1 in 5954def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5955 [(set GPR:$dst, (arm_i32imm:$src))]>, 5956 Requires<[IsARM]>; 5957 5958def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, 5959 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, 5960 Requires<[IsARM, DontUseMovt]>; 5961 5962// Pseudo instruction that combines movw + movt + add pc (if PIC). 5963// It also makes it possible to rematerialize the instructions. 5964// FIXME: Remove this when we can do generalized remat and when machine licm 5965// can properly the instructions. 5966let isReMaterializable = 1 in { 5967def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5968 IIC_iMOVix2addpc, 5969 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5970 Requires<[IsARM, UseMovtInPic]>; 5971 5972def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5973 IIC_iLoadiALU, 5974 [(set GPR:$dst, 5975 (ARMWrapperPIC tglobaladdr:$addr))]>, 5976 Requires<[IsARM, DontUseMovtInPic]>; 5977 5978let AddedComplexity = 10 in 5979def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5980 NoItinerary, 5981 [(set GPR:$dst, 5982 (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5983 Requires<[IsARM, DontUseMovtInPic]>; 5984 5985let AddedComplexity = 10 in 5986def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5987 IIC_iMOVix2ld, 5988 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5989 Requires<[IsARM, UseMovtInPic]>; 5990} // isReMaterializable 5991 5992// The many different faces of TLS access. 5993def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst), 5994 (MOVi32imm tglobaltlsaddr :$dst)>, 5995 Requires<[IsARM, UseMovt]>; 5996 5997def : Pat<(ARMWrapper tglobaltlsaddr:$src), 5998 (LDRLIT_ga_abs tglobaltlsaddr:$src)>, 5999 Requires<[IsARM, DontUseMovt]>; 6000 6001def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 6002 (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovtInPic]>; 6003 6004def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 6005 (LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 6006 Requires<[IsARM, DontUseMovtInPic]>; 6007let AddedComplexity = 10 in 6008def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)), 6009 (MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>, 6010 Requires<[IsARM, UseMovtInPic]>; 6011 6012 6013// ConstantPool, GlobalAddress, and JumpTable 6014def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 6015def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 6016 Requires<[IsARM, UseMovt]>; 6017def : ARMPat<(ARMWrapper texternalsym :$dst), (MOVi32imm texternalsym :$dst)>, 6018 Requires<[IsARM, UseMovt]>; 6019def : ARMPat<(ARMWrapperJT tjumptable:$dst), 6020 (LEApcrelJT tjumptable:$dst)>; 6021 6022// TODO: add,sub,and, 3-instr forms? 6023 6024// Tail calls. These patterns also apply to Thumb mode. 6025def : Pat<(ARMtcret tcGPR:$dst, (i32 timm:$SPDiff)), 6026 (TCRETURNri tcGPR:$dst, timm:$SPDiff)>; 6027def : Pat<(ARMtcret (i32 tglobaladdr:$dst), (i32 timm:$SPDiff)), 6028 (TCRETURNdi texternalsym:$dst, (i32 timm:$SPDiff))>; 6029def : Pat<(ARMtcret (i32 texternalsym:$dst), (i32 timm:$SPDiff)), 6030 (TCRETURNdi texternalsym:$dst, i32imm:$SPDiff)>; 6031 6032// Direct calls 6033def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 6034def : ARMPat<(ARMcall_nolink texternalsym:$func), 6035 (BMOVPCB_CALL texternalsym:$func)>; 6036 6037// zextload i1 -> zextload i8 6038def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 6039def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 6040 6041// extload -> zextload 6042def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 6043def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 6044def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 6045def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 6046 6047def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 6048 6049def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 6050def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 6051 6052// smul* and smla* 6053def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 6054 (SMULBB GPR:$a, GPR:$b)>; 6055def : ARMV5TEPat<(mul sext_16_node:$a, (sext_bottom_16 GPR:$b)), 6056 (SMULBB GPR:$a, GPR:$b)>; 6057def : ARMV5TEPat<(mul sext_16_node:$a, (sext_top_16 GPR:$b)), 6058 (SMULBT GPR:$a, GPR:$b)>; 6059def : ARMV5TEPat<(mul (sext_top_16 GPR:$a), sext_16_node:$b), 6060 (SMULTB GPR:$a, GPR:$b)>; 6061def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, sext_16_node:$b)), 6062 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 6063def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_bottom_16 GPR:$b))), 6064 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 6065def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_top_16 GPR:$b))), 6066 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 6067def : ARMV5MOPat<(add GPR:$acc, (mul (sext_top_16 GPR:$a), sext_16_node:$b)), 6068 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 6069 6070def : ARMV5TEPat<(int_arm_smulbb GPR:$a, GPR:$b), 6071 (SMULBB GPR:$a, GPR:$b)>; 6072def : ARMV5TEPat<(int_arm_smulbt GPR:$a, GPR:$b), 6073 (SMULBT GPR:$a, GPR:$b)>; 6074def : ARMV5TEPat<(int_arm_smultb GPR:$a, GPR:$b), 6075 (SMULTB GPR:$a, GPR:$b)>; 6076def : ARMV5TEPat<(int_arm_smultt GPR:$a, GPR:$b), 6077 (SMULTT GPR:$a, GPR:$b)>; 6078def : ARMV5TEPat<(int_arm_smulwb GPR:$a, GPR:$b), 6079 (SMULWB GPR:$a, GPR:$b)>; 6080def : ARMV5TEPat<(int_arm_smulwt GPR:$a, GPR:$b), 6081 (SMULWT GPR:$a, GPR:$b)>; 6082 6083def : ARMV5TEPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc), 6084 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 6085def : ARMV5TEPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc), 6086 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 6087def : ARMV5TEPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc), 6088 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 6089def : ARMV5TEPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc), 6090 (SMLATT GPR:$a, GPR:$b, GPR:$acc)>; 6091def : ARMV5TEPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc), 6092 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 6093def : ARMV5TEPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc), 6094 (SMLAWT GPR:$a, GPR:$b, GPR:$acc)>; 6095 6096// Pre-v7 uses MCR for synchronization barriers. 6097def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 6098 Requires<[IsARM, HasV6]>; 6099 6100// SXT/UXT with no rotate 6101let AddedComplexity = 16 in { 6102def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 6103def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 6104def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 6105def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 6106 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 6107def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 6108 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 6109} 6110 6111def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 6112def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 6113 6114def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 6115 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 6116def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 6117 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 6118 6119// Atomic load/store patterns 6120def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 6121 (LDRBrs ldst_so_reg:$src)>; 6122def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 6123 (LDRBi12 addrmode_imm12:$src)>; 6124def : ARMPat<(atomic_load_16 addrmode3:$src), 6125 (LDRH addrmode3:$src)>; 6126def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 6127 (LDRrs ldst_so_reg:$src)>; 6128def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 6129 (LDRi12 addrmode_imm12:$src)>; 6130def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 6131 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 6132def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 6133 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 6134def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 6135 (STRH GPR:$val, addrmode3:$ptr)>; 6136def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 6137 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 6138def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 6139 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 6140 6141 6142//===----------------------------------------------------------------------===// 6143// Thumb Support 6144// 6145 6146include "ARMInstrThumb.td" 6147 6148//===----------------------------------------------------------------------===// 6149// Thumb2 Support 6150// 6151 6152include "ARMInstrThumb2.td" 6153 6154//===----------------------------------------------------------------------===// 6155// Floating Point Support 6156// 6157 6158include "ARMInstrVFP.td" 6159 6160//===----------------------------------------------------------------------===// 6161// Advanced SIMD (NEON) Support 6162// 6163 6164include "ARMInstrNEON.td" 6165 6166//===----------------------------------------------------------------------===// 6167// MVE Support 6168// 6169 6170include "ARMInstrMVE.td" 6171 6172//===----------------------------------------------------------------------===// 6173// CDE (Custom Datapath Extension) 6174// 6175 6176include "ARMInstrCDE.td" 6177 6178//===----------------------------------------------------------------------===// 6179// Assembler aliases 6180// 6181 6182// Memory barriers 6183def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>; 6184def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>; 6185def : InstAlias<"ssbb", (DSB 0x0), 1>, Requires<[IsARM, HasDB]>; 6186def : InstAlias<"pssbb", (DSB 0x4), 1>, Requires<[IsARM, HasDB]>; 6187def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>; 6188// Armv8-R 'Data Full Barrier' 6189def : InstAlias<"dfb", (DSB 0xc), 1>, Requires<[IsARM, HasDFB]>; 6190 6191// System instructions 6192def : MnemonicAlias<"swi", "svc">; 6193 6194// Load / Store Multiple 6195def : MnemonicAlias<"ldmfd", "ldm">; 6196def : MnemonicAlias<"ldmia", "ldm">; 6197def : MnemonicAlias<"ldmea", "ldmdb">; 6198def : MnemonicAlias<"stmfd", "stmdb">; 6199def : MnemonicAlias<"stmia", "stm">; 6200def : MnemonicAlias<"stmea", "stm">; 6201 6202// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the 6203// input operands swapped when the shift amount is zero (i.e., unspecified). 6204def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 6205 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>, 6206 Requires<[IsARM, HasV6]>; 6207def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 6208 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>, 6209 Requires<[IsARM, HasV6]>; 6210 6211// PUSH/POP aliases for STM/LDM 6212def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 6213def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 6214 6215// SSAT/USAT optional shift operand. 6216def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 6217 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 6218def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 6219 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 6220 6221 6222// Extend instruction optional rotate operand. 6223def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 6224 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6225def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 6226 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6227def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 6228 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6229def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 6230 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6231def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 6232 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6233def : ARMInstAlias<"sxth${p} $Rd, $Rm", 6234 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6235 6236def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 6237 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6238def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 6239 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6240def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 6241 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 6242def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 6243 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6244def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 6245 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6246def : ARMInstAlias<"uxth${p} $Rd, $Rm", 6247 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6248 6249 6250// RFE aliases 6251def : MnemonicAlias<"rfefa", "rfeda">; 6252def : MnemonicAlias<"rfeea", "rfedb">; 6253def : MnemonicAlias<"rfefd", "rfeia">; 6254def : MnemonicAlias<"rfeed", "rfeib">; 6255def : MnemonicAlias<"rfe", "rfeia">; 6256 6257// SRS aliases 6258def : MnemonicAlias<"srsfa", "srsib">; 6259def : MnemonicAlias<"srsea", "srsia">; 6260def : MnemonicAlias<"srsfd", "srsdb">; 6261def : MnemonicAlias<"srsed", "srsda">; 6262def : MnemonicAlias<"srs", "srsia">; 6263 6264// QSAX == QSUBADDX 6265def : MnemonicAlias<"qsubaddx", "qsax">; 6266// SASX == SADDSUBX 6267def : MnemonicAlias<"saddsubx", "sasx">; 6268// SHASX == SHADDSUBX 6269def : MnemonicAlias<"shaddsubx", "shasx">; 6270// SHSAX == SHSUBADDX 6271def : MnemonicAlias<"shsubaddx", "shsax">; 6272// SSAX == SSUBADDX 6273def : MnemonicAlias<"ssubaddx", "ssax">; 6274// UASX == UADDSUBX 6275def : MnemonicAlias<"uaddsubx", "uasx">; 6276// UHASX == UHADDSUBX 6277def : MnemonicAlias<"uhaddsubx", "uhasx">; 6278// UHSAX == UHSUBADDX 6279def : MnemonicAlias<"uhsubaddx", "uhsax">; 6280// UQASX == UQADDSUBX 6281def : MnemonicAlias<"uqaddsubx", "uqasx">; 6282// UQSAX == UQSUBADDX 6283def : MnemonicAlias<"uqsubaddx", "uqsax">; 6284// USAX == USUBADDX 6285def : MnemonicAlias<"usubaddx", "usax">; 6286 6287// "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like 6288// for isel. 6289def : ARMInstSubst<"mov${s}${p} $Rd, $imm", 6290 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6291def : ARMInstSubst<"mvn${s}${p} $Rd, $imm", 6292 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6293// Same for AND <--> BIC 6294def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm", 6295 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6296 pred:$p, cc_out:$s)>; 6297def : ARMInstSubst<"bic${s}${p} $Rdn, $imm", 6298 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6299 pred:$p, cc_out:$s)>; 6300def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm", 6301 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6302 pred:$p, cc_out:$s)>; 6303def : ARMInstSubst<"and${s}${p} $Rdn, $imm", 6304 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6305 pred:$p, cc_out:$s)>; 6306 6307// Likewise, "add Rd, mod_imm_neg" -> sub 6308def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm", 6309 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6310def : ARMInstSubst<"add${s}${p} $Rd, $imm", 6311 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6312// Likewise, "sub Rd, mod_imm_neg" -> add 6313def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm", 6314 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6315def : ARMInstSubst<"sub${s}${p} $Rd, $imm", 6316 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6317 6318 6319def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm", 6320 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6321def : ARMInstSubst<"adc${s}${p} $Rdn, $imm", 6322 (SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6323def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm", 6324 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6325def : ARMInstSubst<"sbc${s}${p} $Rdn, $imm", 6326 (ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6327 6328// Same for CMP <--> CMN via mod_imm_neg 6329def : ARMInstSubst<"cmp${p} $Rd, $imm", 6330 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6331def : ARMInstSubst<"cmn${p} $Rd, $imm", 6332 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6333 6334// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 6335// LSR, ROR, and RRX instructions. 6336// FIXME: We need C++ parser hooks to map the alias to the MOV 6337// encoding. It seems we should be able to do that sort of thing 6338// in tblgen, but it could get ugly. 6339let TwoOperandAliasConstraint = "$Rm = $Rd" in { 6340def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 6341 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6342 cc_out:$s)>; 6343def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 6344 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6345 cc_out:$s)>; 6346def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 6347 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6348 cc_out:$s)>; 6349def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 6350 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6351 cc_out:$s)>; 6352} 6353def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 6354 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 6355let TwoOperandAliasConstraint = "$Rn = $Rd" in { 6356def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 6357 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6358 cc_out:$s)>; 6359def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 6360 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6361 cc_out:$s)>; 6362def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 6363 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6364 cc_out:$s)>; 6365def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 6366 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6367 cc_out:$s)>; 6368} 6369 6370// "neg" is and alias for "rsb rd, rn, #0" 6371def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 6372 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 6373 6374// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 6375def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 6376 Requires<[IsARM, NoV6]>; 6377 6378// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 6379// the instruction definitions need difference constraints pre-v6. 6380// Use these aliases for the assembly parsing on pre-v6. 6381def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", 6382 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>, 6383 Requires<[IsARM, NoV6]>; 6384def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", 6385 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 6386 pred:$p, cc_out:$s), 0>, 6387 Requires<[IsARM, NoV6]>; 6388def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6389 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6390 Requires<[IsARM, NoV6]>; 6391def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6392 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6393 Requires<[IsARM, NoV6]>; 6394def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6395 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6396 Requires<[IsARM, NoV6]>; 6397def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6398 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6399 Requires<[IsARM, NoV6]>; 6400 6401// 'it' blocks in ARM mode just validate the predicates. The IT itself 6402// is discarded. 6403def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 6404 ComplexDeprecationPredicate<"IT">; 6405 6406let mayLoad = 1, mayStore =1, hasSideEffects = 1, hasNoSchedulingInfo = 1 in 6407def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn), 6408 NoItinerary, 6409 [(set GPR:$Rd, (int_arm_space timm:$size, GPR:$Rn))]>; 6410 6411// SpeculationBarrierEndBB must only be used after an unconditional control 6412// flow, i.e. after a terminator for which isBarrier is True. 6413let hasSideEffects = 1, isCodeGenOnly = 1, isTerminator = 1, isBarrier = 1 in { 6414 def SpeculationBarrierISBDSBEndBB 6415 : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>; 6416 def SpeculationBarrierSBEndBB 6417 : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>; 6418} 6419 6420//===---------------------------------- 6421// Atomic cmpxchg for -O0 6422//===---------------------------------- 6423 6424// The fast register allocator used during -O0 inserts spills to cover any VRegs 6425// live across basic block boundaries. When this happens between an LDXR and an 6426// STXR it can clear the exclusive monitor, causing all cmpxchg attempts to 6427// fail. 6428 6429// Unfortunately, this means we have to have an alternative (expanded 6430// post-regalloc) path for -O0 compilations. Fortunately this path can be 6431// significantly more naive than the standard expansion: we conservatively 6432// assume seq_cst, strong cmpxchg and omit clrex on failure. 6433 6434let Constraints = "@earlyclobber $Rd,@earlyclobber $temp", 6435 mayLoad = 1, mayStore = 1 in { 6436def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6437 (ins GPR:$addr, GPR:$desired, GPR:$new), 6438 NoItinerary, []>, Sched<[]>; 6439 6440def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6441 (ins GPR:$addr, GPR:$desired, GPR:$new), 6442 NoItinerary, []>, Sched<[]>; 6443 6444def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6445 (ins GPR:$addr, GPR:$desired, GPR:$new), 6446 NoItinerary, []>, Sched<[]>; 6447 6448def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp), 6449 (ins GPR:$addr, GPRPair:$desired, GPRPair:$new), 6450 NoItinerary, []>, Sched<[]>; 6451} 6452 6453def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary, 6454 [(atomic_fence timm:$ordering, 0)]> { 6455 let hasSideEffects = 1; 6456 let Size = 0; 6457 let AsmString = "@ COMPILER BARRIER"; 6458 let hasNoSchedulingInfo = 1; 6459} 6460