1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the ARM instructions in TableGen format. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// ARM specific DAG Nodes. 15// 16 17// Type profiles. 18def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 19 SDTCisVT<1, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21def SDT_ARMStructByVal : SDTypeProfile<0, 4, 22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 24 25def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 26 27def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 28 29def SDT_ARMCMov : SDTypeProfile<1, 3, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 31 SDTCisVT<3, i32>]>; 32 33def SDT_ARMBrcond : SDTypeProfile<0, 2, 34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 35 36def SDT_ARMBrJT : SDTypeProfile<0, 2, 37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 38 39def SDT_ARMBr2JT : SDTypeProfile<0, 3, 40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 41 SDTCisVT<2, i32>]>; 42 43def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 44 [SDTCisVT<0, i32>, 45 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 46 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 47 SDTCisVT<5, OtherVT>]>; 48 49def SDT_ARMAnd : SDTypeProfile<1, 2, 50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 51 SDTCisVT<2, i32>]>; 52 53def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 54def SDT_ARMFCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, 55 SDTCisVT<2, i32>]>; 56 57def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 58 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 59 60def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 61def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 62 SDTCisInt<2>]>; 63def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 64def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>; 65 66def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 67 68def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 69 SDTCisInt<1>]>; 70 71def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 72 73def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 74 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 75 76def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 77 78def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 79 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 80 SDTCisVT<4, i32>]>; 81 82def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 83 [SDTCisSameAs<0, 2>, 84 SDTCisSameAs<0, 3>, 85 SDTCisInt<0>, SDTCisVT<1, i32>]>; 86 87// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 88def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 89 [SDTCisSameAs<0, 2>, 90 SDTCisSameAs<0, 3>, 91 SDTCisInt<0>, 92 SDTCisVT<1, i32>, 93 SDTCisVT<4, i32>]>; 94 95def SDT_LongMac : SDTypeProfile<2, 4, [SDTCisVT<0, i32>, 96 SDTCisSameAs<0, 1>, 97 SDTCisSameAs<0, 2>, 98 SDTCisSameAs<0, 3>, 99 SDTCisSameAs<0, 4>, 100 SDTCisSameAs<0, 5>]>; 101 102// ARMlsll, ARMlsrl, ARMasrl 103def SDT_ARMIntShiftParts : SDTypeProfile<2, 3, [SDTCisSameAs<0, 1>, 104 SDTCisSameAs<0, 2>, 105 SDTCisSameAs<0, 3>, 106 SDTCisInt<0>, 107 SDTCisInt<4>]>; 108 109// TODO Add another operand for 'Size' so that we can re-use this node when we 110// start supporting *TP versions. 111def SDT_ARMWhileLoop : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, 112 SDTCisVT<1, OtherVT>]>; 113 114def ARMSmlald : SDNode<"ARMISD::SMLALD", SDT_LongMac>; 115def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>; 116def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>; 117def ARMSmlsldx : SDNode<"ARMISD::SMLSLDX", SDT_LongMac>; 118 119def SDT_MulHSR : SDTypeProfile<1, 3, [SDTCisVT<0,i32>, 120 SDTCisSameAs<0, 1>, 121 SDTCisSameAs<0, 2>, 122 SDTCisSameAs<0, 3>]>; 123 124def ARMsmmlar : SDNode<"ARMISD::SMMLAR", SDT_MulHSR>; 125def ARMsmmlsr : SDNode<"ARMISD::SMMLSR", SDT_MulHSR>; 126 127// Node definitions. 128def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 129def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 130def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>; 131 132def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 133 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 134def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 135 [SDNPHasChain, SDNPSideEffect, 136 SDNPOptInGlue, SDNPOutGlue]>; 137def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 138 SDT_ARMStructByVal, 139 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 140 SDNPMayStore, SDNPMayLoad]>; 141 142def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 143 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 144 SDNPVariadic]>; 145def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 147 SDNPVariadic]>; 148def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 149 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 150 SDNPVariadic]>; 151 152def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 153 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 154def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 156def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 157 [SDNPInGlue]>; 158def ARMsubs : SDNode<"ARMISD::SUBS", SDTIntBinOp, [SDNPOutGlue]>; 159 160def ARMssatnoshift : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>; 161 162def ARMusatnoshift : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>; 163 164def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 165 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 166 167def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 168 [SDNPHasChain]>; 169def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 170 [SDNPHasChain]>; 171 172def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 173 [SDNPHasChain]>; 174 175def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 176 [SDNPOutGlue]>; 177 178def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 179 [SDNPOutGlue]>; 180 181def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 182 [SDNPOutGlue, SDNPCommutative]>; 183 184def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 185 186def ARMasrl : SDNode<"ARMISD::ASRL", SDT_ARMIntShiftParts, []>; 187def ARMlsrl : SDNode<"ARMISD::LSRL", SDT_ARMIntShiftParts, []>; 188def ARMlsll : SDNode<"ARMISD::LSLL", SDT_ARMIntShiftParts, []>; 189 190def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 191def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 192def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 193 194def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 195 [SDNPCommutative]>; 196def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 197def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 198def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 199 200def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 201def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 202 SDT_ARMEH_SJLJ_Setjmp, 203 [SDNPHasChain, SDNPSideEffect]>; 204def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 205 SDT_ARMEH_SJLJ_Longjmp, 206 [SDNPHasChain, SDNPSideEffect]>; 207def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH", 208 SDT_ARMEH_SJLJ_SetupDispatch, 209 [SDNPHasChain, SDNPSideEffect]>; 210 211def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 212 [SDNPHasChain, SDNPSideEffect]>; 213def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 214 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 215 216def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 217 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 218 219def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 220 221def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY, 222 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 223 SDNPMayStore, SDNPMayLoad]>; 224 225def ARMsmulwb : SDNode<"ARMISD::SMULWB", SDTIntBinOp, []>; 226def ARMsmulwt : SDNode<"ARMISD::SMULWT", SDTIntBinOp, []>; 227def ARMsmlalbb : SDNode<"ARMISD::SMLALBB", SDT_LongMac, []>; 228def ARMsmlalbt : SDNode<"ARMISD::SMLALBT", SDT_LongMac, []>; 229def ARMsmlaltb : SDNode<"ARMISD::SMLALTB", SDT_LongMac, []>; 230def ARMsmlaltt : SDNode<"ARMISD::SMLALTT", SDT_LongMac, []>; 231 232// Vector operations shared between NEON and MVE 233 234def ARMvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>; 235 236// VDUPLANE can produce a quad-register result from a double-register source, 237// so the result is not constrained to match the source. 238def ARMvduplane : SDNode<"ARMISD::VDUPLANE", 239 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 240 SDTCisVT<2, i32>]>>; 241 242def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>; 243def ARMvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>; 244def ARMvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>; 245def ARMvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>; 246 247def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>, 248 SDTCisVT<2, i32>]>; 249def ARMvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>; 250def ARMvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>; 251 252def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>; 253def ARMvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>; 254def ARMvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>; 255def ARMvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>; 256 257 258def SDTARMVSHIMM : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 259 SDTCisVT<2, i32>]>; 260def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 261 SDTCisSameAs<0, 2>,]>; 262def ARMvshlImm : SDNode<"ARMISD::VSHLIMM", SDTARMVSHIMM>; 263def ARMvshrsImm : SDNode<"ARMISD::VSHRsIMM", SDTARMVSHIMM>; 264def ARMvshruImm : SDNode<"ARMISD::VSHRuIMM", SDTARMVSHIMM>; 265def ARMvshls : SDNode<"ARMISD::VSHLs", SDTARMVSH>; 266def ARMvshlu : SDNode<"ARMISD::VSHLu", SDTARMVSH>; 267 268def ARMWLS : SDNode<"ARMISD::WLS", SDT_ARMWhileLoop, 269 [SDNPHasChain]>; 270 271//===----------------------------------------------------------------------===// 272// ARM Flag Definitions. 273 274class RegConstraint<string C> { 275 string Constraints = C; 276} 277 278//===----------------------------------------------------------------------===// 279// ARM specific transformation functions and pattern fragments. 280// 281 282// imm_neg_XFORM - Return the negation of an i32 immediate value. 283def imm_neg_XFORM : SDNodeXForm<imm, [{ 284 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32); 285}]>; 286 287// imm_not_XFORM - Return the complement of a i32 immediate value. 288def imm_not_XFORM : SDNodeXForm<imm, [{ 289 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32); 290}]>; 291 292/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 293def imm16_31 : ImmLeaf<i32, [{ 294 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 295}]>; 296 297// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 298def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 299 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 300}]>; 301 302def sext_bottom_16 : PatFrag<(ops node:$a), 303 (sext_inreg node:$a, i16)>; 304def sext_top_16 : PatFrag<(ops node:$a), 305 (i32 (sra node:$a, (i32 16)))>; 306 307def bb_mul : PatFrag<(ops node:$a, node:$b), 308 (mul (sext_bottom_16 node:$a), (sext_bottom_16 node:$b))>; 309def bt_mul : PatFrag<(ops node:$a, node:$b), 310 (mul (sext_bottom_16 node:$a), (sra node:$b, (i32 16)))>; 311def tb_mul : PatFrag<(ops node:$a, node:$b), 312 (mul (sra node:$a, (i32 16)), (sext_bottom_16 node:$b))>; 313def tt_mul : PatFrag<(ops node:$a, node:$b), 314 (mul (sra node:$a, (i32 16)), (sra node:$b, (i32 16)))>; 315 316/// Split a 32-bit immediate into two 16 bit parts. 317def hi16 : SDNodeXForm<imm, [{ 318 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N), 319 MVT::i32); 320}]>; 321 322def lo16AllZero : PatLeaf<(i32 imm), [{ 323 // Returns true if all low 16-bits are 0. 324 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 325}], hi16>; 326 327class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 328class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 329 330// An 'and' node with a single use. 331def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 332 return N->hasOneUse(); 333}]>; 334 335// An 'xor' node with a single use. 336def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 337 return N->hasOneUse(); 338}]>; 339 340// An 'fmul' node with a single use. 341def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 342 return N->hasOneUse(); 343}]>; 344 345// An 'fadd' node which checks for single non-hazardous use. 346def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 347 return hasNoVMLxHazardUse(N); 348}]>; 349 350// An 'fsub' node which checks for single non-hazardous use. 351def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 352 return hasNoVMLxHazardUse(N); 353}]>; 354 355//===----------------------------------------------------------------------===// 356// Operand Definitions. 357// 358 359// Immediate operands with a shared generic asm render method. 360class ImmAsmOperand<int Low, int High> : AsmOperandClass { 361 let RenderMethod = "addImmOperands"; 362 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 363 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 364} 365 366class ImmAsmOperandMinusOne<int Low, int High> : AsmOperandClass { 367 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 368 let DiagnosticType = "ImmRange" # Low # "_" # High; 369 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 370} 371 372// Operands that are part of a memory addressing mode. 373class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; } 374 375// Branch target. 376// FIXME: rename brtarget to t2_brtarget 377def brtarget : Operand<OtherVT> { 378 let EncoderMethod = "getBranchTargetOpValue"; 379 let OperandType = "OPERAND_PCREL"; 380 let DecoderMethod = "DecodeT2BROperand"; 381} 382 383// Branches targeting ARM-mode must be divisible by 4 if they're a raw 384// immediate. 385def ARMBranchTarget : AsmOperandClass { 386 let Name = "ARMBranchTarget"; 387} 388 389// Branches targeting Thumb-mode must be divisible by 2 if they're a raw 390// immediate. 391def ThumbBranchTarget : AsmOperandClass { 392 let Name = "ThumbBranchTarget"; 393} 394 395def arm_br_target : Operand<OtherVT> { 396 let ParserMatchClass = ARMBranchTarget; 397 let EncoderMethod = "getARMBranchTargetOpValue"; 398 let OperandType = "OPERAND_PCREL"; 399} 400 401// Call target for ARM. Handles conditional/unconditional 402// FIXME: rename bl_target to t2_bltarget? 403def arm_bl_target : Operand<i32> { 404 let ParserMatchClass = ARMBranchTarget; 405 let EncoderMethod = "getARMBLTargetOpValue"; 406 let OperandType = "OPERAND_PCREL"; 407} 408 409// Target for BLX *from* ARM mode. 410def arm_blx_target : Operand<i32> { 411 let ParserMatchClass = ThumbBranchTarget; 412 let EncoderMethod = "getARMBLXTargetOpValue"; 413 let OperandType = "OPERAND_PCREL"; 414} 415 416// A list of registers separated by comma. Used by load/store multiple. 417def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 418def reglist : Operand<i32> { 419 let EncoderMethod = "getRegisterListOpValue"; 420 let ParserMatchClass = RegListAsmOperand; 421 let PrintMethod = "printRegisterList"; 422 let DecoderMethod = "DecodeRegListOperand"; 423} 424 425// A list of general purpose registers and APSR separated by comma. 426// Used by CLRM 427def RegListWithAPSRAsmOperand : AsmOperandClass { let Name = "RegListWithAPSR"; } 428def reglist_with_apsr : Operand<i32> { 429 let EncoderMethod = "getRegisterListOpValue"; 430 let ParserMatchClass = RegListWithAPSRAsmOperand; 431 let PrintMethod = "printRegisterList"; 432 let DecoderMethod = "DecodeRegListOperand"; 433} 434 435def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 436 437def DPRRegListAsmOperand : AsmOperandClass { 438 let Name = "DPRRegList"; 439 let DiagnosticType = "DPR_RegList"; 440} 441def dpr_reglist : Operand<i32> { 442 let EncoderMethod = "getRegisterListOpValue"; 443 let ParserMatchClass = DPRRegListAsmOperand; 444 let PrintMethod = "printRegisterList"; 445 let DecoderMethod = "DecodeDPRRegListOperand"; 446} 447 448def SPRRegListAsmOperand : AsmOperandClass { 449 let Name = "SPRRegList"; 450 let DiagnosticString = "operand must be a list of registers in range [s0, s31]"; 451} 452def spr_reglist : Operand<i32> { 453 let EncoderMethod = "getRegisterListOpValue"; 454 let ParserMatchClass = SPRRegListAsmOperand; 455 let PrintMethod = "printRegisterList"; 456 let DecoderMethod = "DecodeSPRRegListOperand"; 457} 458 459def FPSRegListWithVPRAsmOperand : AsmOperandClass { let Name = 460 "FPSRegListWithVPR"; } 461def fp_sreglist_with_vpr : Operand<i32> { 462 let EncoderMethod = "getRegisterListOpValue"; 463 let ParserMatchClass = FPSRegListWithVPRAsmOperand; 464 let PrintMethod = "printRegisterList"; 465} 466def FPDRegListWithVPRAsmOperand : AsmOperandClass { let Name = 467 "FPDRegListWithVPR"; } 468def fp_dreglist_with_vpr : Operand<i32> { 469 let EncoderMethod = "getRegisterListOpValue"; 470 let ParserMatchClass = FPDRegListWithVPRAsmOperand; 471 let PrintMethod = "printRegisterList"; 472} 473 474// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 475def cpinst_operand : Operand<i32> { 476 let PrintMethod = "printCPInstOperand"; 477} 478 479// Local PC labels. 480def pclabel : Operand<i32> { 481 let PrintMethod = "printPCLabel"; 482} 483 484// ADR instruction labels. 485def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 486def adrlabel : Operand<i32> { 487 let EncoderMethod = "getAdrLabelOpValue"; 488 let ParserMatchClass = AdrLabelAsmOperand; 489 let PrintMethod = "printAdrLabelOperand<0>"; 490} 491 492def neon_vcvt_imm32 : Operand<i32> { 493 let EncoderMethod = "getNEONVcvtImm32OpValue"; 494 let DecoderMethod = "DecodeVCVTImmOperand"; 495} 496 497// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 498def rot_imm_XFORM: SDNodeXForm<imm, [{ 499 switch (N->getZExtValue()){ 500 default: llvm_unreachable(nullptr); 501 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); 502 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32); 503 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32); 504 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32); 505 } 506}]>; 507def RotImmAsmOperand : AsmOperandClass { 508 let Name = "RotImm"; 509 let ParserMethod = "parseRotImm"; 510} 511def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 512 int32_t v = N->getZExtValue(); 513 return v == 8 || v == 16 || v == 24; }], 514 rot_imm_XFORM> { 515 let PrintMethod = "printRotImmOperand"; 516 let ParserMatchClass = RotImmAsmOperand; 517} 518 519// Power-of-two operand for MVE VIDUP and friends, which encode 520// {1,2,4,8} as its log to base 2, i.e. as {0,1,2,3} respectively 521def MVE_VIDUP_imm_asmoperand : AsmOperandClass { 522 let Name = "VIDUP_imm"; 523 let PredicateMethod = "isPowerTwoInRange<1,8>"; 524 let RenderMethod = "addPowerTwoOperands"; 525 let DiagnosticString = "vector increment immediate must be 1, 2, 4 or 8"; 526} 527def MVE_VIDUP_imm : Operand<i32> { 528 let EncoderMethod = "getPowerTwoOpValue"; 529 let DecoderMethod = "DecodePowerTwoOperand<0,3>"; 530 let ParserMatchClass = MVE_VIDUP_imm_asmoperand; 531} 532 533// Pair vector indexing 534class MVEPairVectorIndexOperand<string start, string end> : AsmOperandClass { 535 let Name = "MVEPairVectorIndex"#start; 536 let RenderMethod = "addMVEPairVectorIndexOperands"; 537 let PredicateMethod = "isMVEPairVectorIndex<"#start#", "#end#">"; 538} 539 540class MVEPairVectorIndex<string opval> : Operand<i32> { 541 let PrintMethod = "printVectorIndex"; 542 let EncoderMethod = "getMVEPairVectorIndexOpValue<"#opval#">"; 543 let DecoderMethod = "DecodeMVEPairVectorIndexOperand<"#opval#">"; 544 let MIOperandInfo = (ops i32imm); 545} 546 547def MVEPairVectorIndex0 : MVEPairVectorIndex<"0"> { 548 let ParserMatchClass = MVEPairVectorIndexOperand<"0", "1">; 549} 550 551def MVEPairVectorIndex2 : MVEPairVectorIndex<"2"> { 552 let ParserMatchClass = MVEPairVectorIndexOperand<"2", "3">; 553} 554 555// Vector indexing 556class MVEVectorIndexOperand<int NumLanes> : AsmOperandClass { 557 let Name = "MVEVectorIndex"#NumLanes; 558 let RenderMethod = "addMVEVectorIndexOperands"; 559 let PredicateMethod = "isVectorIndexInRange<"#NumLanes#">"; 560} 561 562class MVEVectorIndex<int NumLanes> : Operand<i32> { 563 let PrintMethod = "printVectorIndex"; 564 let ParserMatchClass = MVEVectorIndexOperand<NumLanes>; 565 let MIOperandInfo = (ops i32imm); 566} 567 568// shift_imm: An integer that encodes a shift amount and the type of shift 569// (asr or lsl). The 6-bit immediate encodes as: 570// {5} 0 ==> lsl 571// 1 asr 572// {4-0} imm5 shift amount. 573// asr #32 encoded as imm5 == 0. 574def ShifterImmAsmOperand : AsmOperandClass { 575 let Name = "ShifterImm"; 576 let ParserMethod = "parseShifterImm"; 577} 578def shift_imm : Operand<i32> { 579 let PrintMethod = "printShiftImmOperand"; 580 let ParserMatchClass = ShifterImmAsmOperand; 581} 582 583// shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm. 584def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 585def so_reg_reg : Operand<i32>, // reg reg imm 586 ComplexPattern<i32, 3, "SelectRegShifterOperand", 587 [shl, srl, sra, rotr]> { 588 let EncoderMethod = "getSORegRegOpValue"; 589 let PrintMethod = "printSORegRegOperand"; 590 let DecoderMethod = "DecodeSORegRegOperand"; 591 let ParserMatchClass = ShiftedRegAsmOperand; 592 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 593} 594 595def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 596def so_reg_imm : Operand<i32>, // reg imm 597 ComplexPattern<i32, 2, "SelectImmShifterOperand", 598 [shl, srl, sra, rotr]> { 599 let EncoderMethod = "getSORegImmOpValue"; 600 let PrintMethod = "printSORegImmOperand"; 601 let DecoderMethod = "DecodeSORegImmOperand"; 602 let ParserMatchClass = ShiftedImmAsmOperand; 603 let MIOperandInfo = (ops GPR, i32imm); 604} 605 606// FIXME: Does this need to be distinct from so_reg? 607def shift_so_reg_reg : Operand<i32>, // reg reg imm 608 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 609 [shl,srl,sra,rotr]> { 610 let EncoderMethod = "getSORegRegOpValue"; 611 let PrintMethod = "printSORegRegOperand"; 612 let DecoderMethod = "DecodeSORegRegOperand"; 613 let ParserMatchClass = ShiftedRegAsmOperand; 614 let MIOperandInfo = (ops GPR, GPR, i32imm); 615} 616 617// FIXME: Does this need to be distinct from so_reg? 618def shift_so_reg_imm : Operand<i32>, // reg reg imm 619 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 620 [shl,srl,sra,rotr]> { 621 let EncoderMethod = "getSORegImmOpValue"; 622 let PrintMethod = "printSORegImmOperand"; 623 let DecoderMethod = "DecodeSORegImmOperand"; 624 let ParserMatchClass = ShiftedImmAsmOperand; 625 let MIOperandInfo = (ops GPR, i32imm); 626} 627 628// mod_imm: match a 32-bit immediate operand, which can be encoded into 629// a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM 630// - "Modified Immediate Constants"). Within the MC layer we keep this 631// immediate in its encoded form. 632def ModImmAsmOperand: AsmOperandClass { 633 let Name = "ModImm"; 634 let ParserMethod = "parseModImm"; 635} 636def mod_imm : Operand<i32>, ImmLeaf<i32, [{ 637 return ARM_AM::getSOImmVal(Imm) != -1; 638 }]> { 639 let EncoderMethod = "getModImmOpValue"; 640 let PrintMethod = "printModImmOperand"; 641 let ParserMatchClass = ModImmAsmOperand; 642} 643 644// Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder 645// method and such, as they are only used on aliases (Pat<> and InstAlias<>). 646// The actual parsing, encoding, decoding are handled by the destination 647// instructions, which use mod_imm. 648 649def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; } 650def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{ 651 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 652 }], imm_not_XFORM> { 653 let ParserMatchClass = ModImmNotAsmOperand; 654} 655 656def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; } 657def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 658 unsigned Value = -(unsigned)N->getZExtValue(); 659 return Value && ARM_AM::getSOImmVal(Value) != -1; 660 }], imm_neg_XFORM> { 661 let ParserMatchClass = ModImmNegAsmOperand; 662} 663 664/// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal() 665def arm_i32imm : IntImmLeaf<i32, [{ 666 if (Subtarget->useMovt()) 667 return true; 668 return ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue()); 669}]>; 670 671/// imm0_1 predicate - Immediate in the range [0,1]. 672def Imm0_1AsmOperand: ImmAsmOperand<0,1> { let Name = "Imm0_1"; } 673def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 674 675/// imm0_3 predicate - Immediate in the range [0,3]. 676def Imm0_3AsmOperand: ImmAsmOperand<0,3> { let Name = "Imm0_3"; } 677def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 678 679/// imm0_7 predicate - Immediate in the range [0,7]. 680def Imm0_7AsmOperand: ImmAsmOperand<0,7> { 681 let Name = "Imm0_7"; 682} 683def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 684 return Imm >= 0 && Imm < 8; 685}]> { 686 let ParserMatchClass = Imm0_7AsmOperand; 687} 688 689/// imm8_255 predicate - Immediate in the range [8,255]. 690def Imm8_255AsmOperand: ImmAsmOperand<8,255> { let Name = "Imm8_255"; } 691def imm8_255 : Operand<i32>, ImmLeaf<i32, [{ 692 return Imm >= 8 && Imm < 256; 693}]> { 694 let ParserMatchClass = Imm8_255AsmOperand; 695} 696 697/// imm8 predicate - Immediate is exactly 8. 698def Imm8AsmOperand: ImmAsmOperand<8,8> { let Name = "Imm8"; } 699def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 700 let ParserMatchClass = Imm8AsmOperand; 701} 702 703/// imm16 predicate - Immediate is exactly 16. 704def Imm16AsmOperand: ImmAsmOperand<16,16> { let Name = "Imm16"; } 705def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 706 let ParserMatchClass = Imm16AsmOperand; 707} 708 709/// imm32 predicate - Immediate is exactly 32. 710def Imm32AsmOperand: ImmAsmOperand<32,32> { let Name = "Imm32"; } 711def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 712 let ParserMatchClass = Imm32AsmOperand; 713} 714 715def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>; 716 717/// imm1_7 predicate - Immediate in the range [1,7]. 718def Imm1_7AsmOperand: ImmAsmOperand<1,7> { let Name = "Imm1_7"; } 719def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 720 let ParserMatchClass = Imm1_7AsmOperand; 721} 722 723/// imm1_15 predicate - Immediate in the range [1,15]. 724def Imm1_15AsmOperand: ImmAsmOperand<1,15> { let Name = "Imm1_15"; } 725def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 726 let ParserMatchClass = Imm1_15AsmOperand; 727} 728 729/// imm1_31 predicate - Immediate in the range [1,31]. 730def Imm1_31AsmOperand: ImmAsmOperand<1,31> { let Name = "Imm1_31"; } 731def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 732 let ParserMatchClass = Imm1_31AsmOperand; 733} 734 735/// imm0_15 predicate - Immediate in the range [0,15]. 736def Imm0_15AsmOperand: ImmAsmOperand<0,15> { 737 let Name = "Imm0_15"; 738} 739def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 740 return Imm >= 0 && Imm < 16; 741}]> { 742 let ParserMatchClass = Imm0_15AsmOperand; 743} 744 745/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 746def Imm0_31AsmOperand: ImmAsmOperand<0,31> { let Name = "Imm0_31"; } 747def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 748 return Imm >= 0 && Imm < 32; 749}]> { 750 let ParserMatchClass = Imm0_31AsmOperand; 751} 752 753/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 754def Imm0_32AsmOperand: ImmAsmOperand<0,32> { let Name = "Imm0_32"; } 755def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 756 return Imm >= 0 && Imm < 33; 757}]> { 758 let ParserMatchClass = Imm0_32AsmOperand; 759} 760 761/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 762def Imm0_63AsmOperand: ImmAsmOperand<0,63> { let Name = "Imm0_63"; } 763def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 764 return Imm >= 0 && Imm < 64; 765}]> { 766 let ParserMatchClass = Imm0_63AsmOperand; 767} 768 769/// imm0_239 predicate - Immediate in the range [0,239]. 770def Imm0_239AsmOperand : ImmAsmOperand<0,239> { 771 let Name = "Imm0_239"; 772} 773def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 774 let ParserMatchClass = Imm0_239AsmOperand; 775} 776 777/// imm0_255 predicate - Immediate in the range [0,255]. 778def Imm0_255AsmOperand : ImmAsmOperand<0,255> { let Name = "Imm0_255"; } 779def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 780 let ParserMatchClass = Imm0_255AsmOperand; 781} 782 783/// imm0_65535 - An immediate is in the range [0,65535]. 784def Imm0_65535AsmOperand: ImmAsmOperand<0,65535> { let Name = "Imm0_65535"; } 785def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 786 return Imm >= 0 && Imm < 65536; 787}]> { 788 let ParserMatchClass = Imm0_65535AsmOperand; 789} 790 791// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 792def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 793 return -Imm >= 0 && -Imm < 65536; 794}]>; 795 796// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 797// a relocatable expression. 798// 799// FIXME: This really needs a Thumb version separate from the ARM version. 800// While the range is the same, and can thus use the same match class, 801// the encoding is different so it should have a different encoder method. 802def Imm0_65535ExprAsmOperand: AsmOperandClass { 803 let Name = "Imm0_65535Expr"; 804 let RenderMethod = "addImmOperands"; 805 let DiagnosticString = "operand must be an immediate in the range [0,0xffff] or a relocatable expression"; 806} 807 808def imm0_65535_expr : Operand<i32> { 809 let EncoderMethod = "getHiLo16ImmOpValue"; 810 let ParserMatchClass = Imm0_65535ExprAsmOperand; 811} 812 813def Imm256_65535ExprAsmOperand: ImmAsmOperand<256,65535> { let Name = "Imm256_65535Expr"; } 814def imm256_65535_expr : Operand<i32> { 815 let ParserMatchClass = Imm256_65535ExprAsmOperand; 816} 817 818/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 819def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> { 820 let Name = "Imm24bit"; 821 let DiagnosticString = "operand must be an immediate in the range [0,0xffffff]"; 822} 823def imm24b : Operand<i32>, ImmLeaf<i32, [{ 824 return Imm >= 0 && Imm <= 0xffffff; 825}]> { 826 let ParserMatchClass = Imm24bitAsmOperand; 827} 828 829 830/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 831/// e.g., 0xf000ffff 832def BitfieldAsmOperand : AsmOperandClass { 833 let Name = "Bitfield"; 834 let ParserMethod = "parseBitfield"; 835} 836 837def bf_inv_mask_imm : Operand<i32>, 838 PatLeaf<(imm), [{ 839 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 840}] > { 841 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 842 let PrintMethod = "printBitfieldInvMaskImmOperand"; 843 let DecoderMethod = "DecodeBitfieldMaskOperand"; 844 let ParserMatchClass = BitfieldAsmOperand; 845 let GISelPredicateCode = [{ 846 // There's better methods of implementing this check. IntImmLeaf<> would be 847 // equivalent and have less boilerplate but we need a test for C++ 848 // predicates and this one causes new rules to be imported into GlobalISel 849 // without requiring additional features first. 850 const auto &MO = MI.getOperand(1); 851 if (!MO.isCImm()) 852 return false; 853 return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); 854 }]; 855} 856 857def imm1_32_XFORM: SDNodeXForm<imm, [{ 858 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 859 MVT::i32); 860}]>; 861def Imm1_32AsmOperand: ImmAsmOperandMinusOne<1,32> { 862 let Name = "Imm1_32"; 863} 864def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 865 uint64_t Imm = N->getZExtValue(); 866 return Imm > 0 && Imm <= 32; 867 }], 868 imm1_32_XFORM> { 869 let PrintMethod = "printImmPlusOneOperand"; 870 let ParserMatchClass = Imm1_32AsmOperand; 871} 872 873def imm1_16_XFORM: SDNodeXForm<imm, [{ 874 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 875 MVT::i32); 876}]>; 877def Imm1_16AsmOperand: ImmAsmOperandMinusOne<1,16> { let Name = "Imm1_16"; } 878def imm1_16 : Operand<i32>, ImmLeaf<i32, [{ 879 return Imm > 0 && Imm <= 16; 880 }], 881 imm1_16_XFORM> { 882 let PrintMethod = "printImmPlusOneOperand"; 883 let ParserMatchClass = Imm1_16AsmOperand; 884} 885 886def MVEShiftImm1_7AsmOperand: ImmAsmOperand<1,7> { 887 let Name = "MVEShiftImm1_7"; 888 // Reason we're doing this is because instruction vshll.s8 t1 encoding 889 // accepts 1,7 but the t2 encoding accepts 8. By doing this we can get a 890 // better diagnostic message if someone uses bigger immediate than the t1/t2 891 // encodings allow. 892 let DiagnosticString = "operand must be an immediate in the range [1,8]"; 893} 894def mve_shift_imm1_7 : Operand<i32> { 895 let ParserMatchClass = MVEShiftImm1_7AsmOperand; 896 let EncoderMethod = "getMVEShiftImmOpValue"; 897} 898 899def MVEShiftImm1_15AsmOperand: ImmAsmOperand<1,15> { 900 let Name = "MVEShiftImm1_15"; 901 // Reason we're doing this is because instruction vshll.s16 t1 encoding 902 // accepts 1,15 but the t2 encoding accepts 16. By doing this we can get a 903 // better diagnostic message if someone uses bigger immediate than the t1/t2 904 // encodings allow. 905 let DiagnosticString = "operand must be an immediate in the range [1,16]"; 906} 907def mve_shift_imm1_15 : Operand<i32> { 908 let ParserMatchClass = MVEShiftImm1_15AsmOperand; 909 let EncoderMethod = "getMVEShiftImmOpValue"; 910} 911 912// Define ARM specific addressing modes. 913// addrmode_imm12 := reg +/- imm12 914// 915def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 916class AddrMode_Imm12 : MemOperand, 917 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 918 // 12-bit immediate operand. Note that instructions using this encode 919 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 920 // immediate values are as normal. 921 922 let EncoderMethod = "getAddrModeImm12OpValue"; 923 let DecoderMethod = "DecodeAddrModeImm12Operand"; 924 let ParserMatchClass = MemImm12OffsetAsmOperand; 925 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 926} 927 928def addrmode_imm12 : AddrMode_Imm12 { 929 let PrintMethod = "printAddrModeImm12Operand<false>"; 930} 931 932def addrmode_imm12_pre : AddrMode_Imm12 { 933 let PrintMethod = "printAddrModeImm12Operand<true>"; 934} 935 936// ldst_so_reg := reg +/- reg shop imm 937// 938def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 939def ldst_so_reg : MemOperand, 940 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 941 let EncoderMethod = "getLdStSORegOpValue"; 942 // FIXME: Simplify the printer 943 let PrintMethod = "printAddrMode2Operand"; 944 let DecoderMethod = "DecodeSORegMemOperand"; 945 let ParserMatchClass = MemRegOffsetAsmOperand; 946 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 947} 948 949// postidx_imm8 := +/- [0,255] 950// 951// 9 bit value: 952// {8} 1 is imm8 is non-negative. 0 otherwise. 953// {7-0} [0,255] imm8 value. 954def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 955def postidx_imm8 : MemOperand { 956 let PrintMethod = "printPostIdxImm8Operand"; 957 let ParserMatchClass = PostIdxImm8AsmOperand; 958 let MIOperandInfo = (ops i32imm); 959} 960 961// postidx_imm8s4 := +/- [0,1020] 962// 963// 9 bit value: 964// {8} 1 is imm8 is non-negative. 0 otherwise. 965// {7-0} [0,255] imm8 value, scaled by 4. 966def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 967def postidx_imm8s4 : MemOperand { 968 let PrintMethod = "printPostIdxImm8s4Operand"; 969 let ParserMatchClass = PostIdxImm8s4AsmOperand; 970 let MIOperandInfo = (ops i32imm); 971} 972 973 974// postidx_reg := +/- reg 975// 976def PostIdxRegAsmOperand : AsmOperandClass { 977 let Name = "PostIdxReg"; 978 let ParserMethod = "parsePostIdxReg"; 979} 980def postidx_reg : MemOperand { 981 let EncoderMethod = "getPostIdxRegOpValue"; 982 let DecoderMethod = "DecodePostIdxReg"; 983 let PrintMethod = "printPostIdxRegOperand"; 984 let ParserMatchClass = PostIdxRegAsmOperand; 985 let MIOperandInfo = (ops GPRnopc, i32imm); 986} 987 988def PostIdxRegShiftedAsmOperand : AsmOperandClass { 989 let Name = "PostIdxRegShifted"; 990 let ParserMethod = "parsePostIdxReg"; 991} 992def am2offset_reg : MemOperand, 993 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 994 [], [SDNPWantRoot]> { 995 let EncoderMethod = "getAddrMode2OffsetOpValue"; 996 let PrintMethod = "printAddrMode2OffsetOperand"; 997 // When using this for assembly, it's always as a post-index offset. 998 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 999 let MIOperandInfo = (ops GPRnopc, i32imm); 1000} 1001 1002// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 1003// the GPR is purely vestigal at this point. 1004def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 1005def am2offset_imm : MemOperand, 1006 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 1007 [], [SDNPWantRoot]> { 1008 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1009 let PrintMethod = "printAddrMode2OffsetOperand"; 1010 let ParserMatchClass = AM2OffsetImmAsmOperand; 1011 let MIOperandInfo = (ops GPRnopc, i32imm); 1012} 1013 1014 1015// addrmode3 := reg +/- reg 1016// addrmode3 := reg +/- imm8 1017// 1018// FIXME: split into imm vs. reg versions. 1019def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 1020class AddrMode3 : MemOperand, 1021 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 1022 let EncoderMethod = "getAddrMode3OpValue"; 1023 let ParserMatchClass = AddrMode3AsmOperand; 1024 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 1025} 1026 1027def addrmode3 : AddrMode3 1028{ 1029 let PrintMethod = "printAddrMode3Operand<false>"; 1030} 1031 1032def addrmode3_pre : AddrMode3 1033{ 1034 let PrintMethod = "printAddrMode3Operand<true>"; 1035} 1036 1037// FIXME: split into imm vs. reg versions. 1038// FIXME: parser method to handle +/- register. 1039def AM3OffsetAsmOperand : AsmOperandClass { 1040 let Name = "AM3Offset"; 1041 let ParserMethod = "parseAM3Offset"; 1042} 1043def am3offset : MemOperand, 1044 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 1045 [], [SDNPWantRoot]> { 1046 let EncoderMethod = "getAddrMode3OffsetOpValue"; 1047 let PrintMethod = "printAddrMode3OffsetOperand"; 1048 let ParserMatchClass = AM3OffsetAsmOperand; 1049 let MIOperandInfo = (ops GPR, i32imm); 1050} 1051 1052// ldstm_mode := {ia, ib, da, db} 1053// 1054def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 1055 let EncoderMethod = "getLdStmModeOpValue"; 1056 let PrintMethod = "printLdStmModeOperand"; 1057} 1058 1059// addrmode5 := reg +/- imm8*4 1060// 1061def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 1062class AddrMode5 : MemOperand, 1063 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 1064 let EncoderMethod = "getAddrMode5OpValue"; 1065 let DecoderMethod = "DecodeAddrMode5Operand"; 1066 let ParserMatchClass = AddrMode5AsmOperand; 1067 let MIOperandInfo = (ops GPR:$base, i32imm); 1068} 1069 1070def addrmode5 : AddrMode5 { 1071 let PrintMethod = "printAddrMode5Operand<false>"; 1072} 1073 1074def addrmode5_pre : AddrMode5 { 1075 let PrintMethod = "printAddrMode5Operand<true>"; 1076} 1077 1078// addrmode5fp16 := reg +/- imm8*2 1079// 1080def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; } 1081class AddrMode5FP16 : Operand<i32>, 1082 ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> { 1083 let EncoderMethod = "getAddrMode5FP16OpValue"; 1084 let DecoderMethod = "DecodeAddrMode5FP16Operand"; 1085 let ParserMatchClass = AddrMode5FP16AsmOperand; 1086 let MIOperandInfo = (ops GPR:$base, i32imm); 1087} 1088 1089def addrmode5fp16 : AddrMode5FP16 { 1090 let PrintMethod = "printAddrMode5FP16Operand<false>"; 1091} 1092 1093// addrmode6 := reg with optional alignment 1094// 1095def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 1096def addrmode6 : MemOperand, 1097 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1098 let PrintMethod = "printAddrMode6Operand"; 1099 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1100 let EncoderMethod = "getAddrMode6AddressOpValue"; 1101 let DecoderMethod = "DecodeAddrMode6Operand"; 1102 let ParserMatchClass = AddrMode6AsmOperand; 1103} 1104 1105def am6offset : MemOperand, 1106 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 1107 [], [SDNPWantRoot]> { 1108 let PrintMethod = "printAddrMode6OffsetOperand"; 1109 let MIOperandInfo = (ops GPR); 1110 let EncoderMethod = "getAddrMode6OffsetOpValue"; 1111 let DecoderMethod = "DecodeGPRRegisterClass"; 1112} 1113 1114// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 1115// (single element from one lane) for size 32. 1116def addrmode6oneL32 : MemOperand, 1117 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1118 let PrintMethod = "printAddrMode6Operand"; 1119 let MIOperandInfo = (ops GPR:$addr, i32imm); 1120 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 1121} 1122 1123// Base class for addrmode6 with specific alignment restrictions. 1124class AddrMode6Align : MemOperand, 1125 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1126 let PrintMethod = "printAddrMode6Operand"; 1127 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1128 let EncoderMethod = "getAddrMode6AddressOpValue"; 1129 let DecoderMethod = "DecodeAddrMode6Operand"; 1130} 1131 1132// Special version of addrmode6 to handle no allowed alignment encoding for 1133// VLD/VST instructions and checking the alignment is not specified. 1134def AddrMode6AlignNoneAsmOperand : AsmOperandClass { 1135 let Name = "AlignedMemoryNone"; 1136 let DiagnosticString = "alignment must be omitted"; 1137} 1138def addrmode6alignNone : AddrMode6Align { 1139 // The alignment specifier can only be omitted. 1140 let ParserMatchClass = AddrMode6AlignNoneAsmOperand; 1141} 1142 1143// Special version of addrmode6 to handle 16-bit alignment encoding for 1144// VLD/VST instructions and checking the alignment value. 1145def AddrMode6Align16AsmOperand : AsmOperandClass { 1146 let Name = "AlignedMemory16"; 1147 let DiagnosticString = "alignment must be 16 or omitted"; 1148} 1149def addrmode6align16 : AddrMode6Align { 1150 // The alignment specifier can only be 16 or omitted. 1151 let ParserMatchClass = AddrMode6Align16AsmOperand; 1152} 1153 1154// Special version of addrmode6 to handle 32-bit alignment encoding for 1155// VLD/VST instructions and checking the alignment value. 1156def AddrMode6Align32AsmOperand : AsmOperandClass { 1157 let Name = "AlignedMemory32"; 1158 let DiagnosticString = "alignment must be 32 or omitted"; 1159} 1160def addrmode6align32 : AddrMode6Align { 1161 // The alignment specifier can only be 32 or omitted. 1162 let ParserMatchClass = AddrMode6Align32AsmOperand; 1163} 1164 1165// Special version of addrmode6 to handle 64-bit alignment encoding for 1166// VLD/VST instructions and checking the alignment value. 1167def AddrMode6Align64AsmOperand : AsmOperandClass { 1168 let Name = "AlignedMemory64"; 1169 let DiagnosticString = "alignment must be 64 or omitted"; 1170} 1171def addrmode6align64 : AddrMode6Align { 1172 // The alignment specifier can only be 64 or omitted. 1173 let ParserMatchClass = AddrMode6Align64AsmOperand; 1174} 1175 1176// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1177// for VLD/VST instructions and checking the alignment value. 1178def AddrMode6Align64or128AsmOperand : AsmOperandClass { 1179 let Name = "AlignedMemory64or128"; 1180 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1181} 1182def addrmode6align64or128 : AddrMode6Align { 1183 // The alignment specifier can only be 64, 128 or omitted. 1184 let ParserMatchClass = AddrMode6Align64or128AsmOperand; 1185} 1186 1187// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment 1188// encoding for VLD/VST instructions and checking the alignment value. 1189def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { 1190 let Name = "AlignedMemory64or128or256"; 1191 let DiagnosticString = "alignment must be 64, 128, 256 or omitted"; 1192} 1193def addrmode6align64or128or256 : AddrMode6Align { 1194 // The alignment specifier can only be 64, 128, 256 or omitted. 1195 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand; 1196} 1197 1198// Special version of addrmode6 to handle alignment encoding for VLD-dup 1199// instructions, specifically VLD4-dup. 1200def addrmode6dup : MemOperand, 1201 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1202 let PrintMethod = "printAddrMode6Operand"; 1203 let MIOperandInfo = (ops GPR:$addr, i32imm); 1204 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1205 // FIXME: This is close, but not quite right. The alignment specifier is 1206 // different. 1207 let ParserMatchClass = AddrMode6AsmOperand; 1208} 1209 1210// Base class for addrmode6dup with specific alignment restrictions. 1211class AddrMode6DupAlign : MemOperand, 1212 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1213 let PrintMethod = "printAddrMode6Operand"; 1214 let MIOperandInfo = (ops GPR:$addr, i32imm); 1215 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1216} 1217 1218// Special version of addrmode6 to handle no allowed alignment encoding for 1219// VLD-dup instruction and checking the alignment is not specified. 1220def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { 1221 let Name = "DupAlignedMemoryNone"; 1222 let DiagnosticString = "alignment must be omitted"; 1223} 1224def addrmode6dupalignNone : AddrMode6DupAlign { 1225 // The alignment specifier can only be omitted. 1226 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand; 1227} 1228 1229// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup 1230// instruction and checking the alignment value. 1231def AddrMode6dupAlign16AsmOperand : AsmOperandClass { 1232 let Name = "DupAlignedMemory16"; 1233 let DiagnosticString = "alignment must be 16 or omitted"; 1234} 1235def addrmode6dupalign16 : AddrMode6DupAlign { 1236 // The alignment specifier can only be 16 or omitted. 1237 let ParserMatchClass = AddrMode6dupAlign16AsmOperand; 1238} 1239 1240// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup 1241// instruction and checking the alignment value. 1242def AddrMode6dupAlign32AsmOperand : AsmOperandClass { 1243 let Name = "DupAlignedMemory32"; 1244 let DiagnosticString = "alignment must be 32 or omitted"; 1245} 1246def addrmode6dupalign32 : AddrMode6DupAlign { 1247 // The alignment specifier can only be 32 or omitted. 1248 let ParserMatchClass = AddrMode6dupAlign32AsmOperand; 1249} 1250 1251// Special version of addrmode6 to handle 64-bit alignment encoding for VLD 1252// instructions and checking the alignment value. 1253def AddrMode6dupAlign64AsmOperand : AsmOperandClass { 1254 let Name = "DupAlignedMemory64"; 1255 let DiagnosticString = "alignment must be 64 or omitted"; 1256} 1257def addrmode6dupalign64 : AddrMode6DupAlign { 1258 // The alignment specifier can only be 64 or omitted. 1259 let ParserMatchClass = AddrMode6dupAlign64AsmOperand; 1260} 1261 1262// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1263// for VLD instructions and checking the alignment value. 1264def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { 1265 let Name = "DupAlignedMemory64or128"; 1266 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1267} 1268def addrmode6dupalign64or128 : AddrMode6DupAlign { 1269 // The alignment specifier can only be 64, 128 or omitted. 1270 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand; 1271} 1272 1273// addrmodepc := pc + reg 1274// 1275def addrmodepc : MemOperand, 1276 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1277 let PrintMethod = "printAddrModePCOperand"; 1278 let MIOperandInfo = (ops GPR, i32imm); 1279} 1280 1281// addr_offset_none := reg 1282// 1283def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1284def addr_offset_none : MemOperand, 1285 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1286 let PrintMethod = "printAddrMode7Operand"; 1287 let DecoderMethod = "DecodeAddrMode7Operand"; 1288 let ParserMatchClass = MemNoOffsetAsmOperand; 1289 let MIOperandInfo = (ops GPR:$base); 1290} 1291 1292// t_addr_offset_none := reg [r0-r7] 1293def MemNoOffsetTAsmOperand : AsmOperandClass { let Name = "MemNoOffsetT"; } 1294def t_addr_offset_none : MemOperand { 1295 let PrintMethod = "printAddrMode7Operand"; 1296 let DecoderMethod = "DecodetGPRRegisterClass"; 1297 let ParserMatchClass = MemNoOffsetTAsmOperand; 1298 let MIOperandInfo = (ops tGPR:$base); 1299} 1300 1301def nohash_imm : Operand<i32> { 1302 let PrintMethod = "printNoHashImmediate"; 1303} 1304 1305def CoprocNumAsmOperand : AsmOperandClass { 1306 let Name = "CoprocNum"; 1307 let ParserMethod = "parseCoprocNumOperand"; 1308} 1309def p_imm : Operand<i32> { 1310 let PrintMethod = "printPImmediate"; 1311 let ParserMatchClass = CoprocNumAsmOperand; 1312 let DecoderMethod = "DecodeCoprocessor"; 1313} 1314 1315def CoprocRegAsmOperand : AsmOperandClass { 1316 let Name = "CoprocReg"; 1317 let ParserMethod = "parseCoprocRegOperand"; 1318} 1319def c_imm : Operand<i32> { 1320 let PrintMethod = "printCImmediate"; 1321 let ParserMatchClass = CoprocRegAsmOperand; 1322} 1323def CoprocOptionAsmOperand : AsmOperandClass { 1324 let Name = "CoprocOption"; 1325 let ParserMethod = "parseCoprocOptionOperand"; 1326} 1327def coproc_option_imm : Operand<i32> { 1328 let PrintMethod = "printCoprocOptionImm"; 1329 let ParserMatchClass = CoprocOptionAsmOperand; 1330} 1331 1332//===----------------------------------------------------------------------===// 1333 1334include "ARMInstrFormats.td" 1335 1336//===----------------------------------------------------------------------===// 1337// Multiclass helpers... 1338// 1339 1340/// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a 1341/// binop that produces a value. 1342let TwoOperandAliasConstraint = "$Rn = $Rd" in 1343multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1344 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1345 SDPatternOperator opnode, bit Commutable = 0> { 1346 // The register-immediate version is re-materializable. This is useful 1347 // in particular for taking the address of a local. 1348 let isReMaterializable = 1 in { 1349 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1350 iii, opc, "\t$Rd, $Rn, $imm", 1351 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>, 1352 Sched<[WriteALU, ReadALU]> { 1353 bits<4> Rd; 1354 bits<4> Rn; 1355 bits<12> imm; 1356 let Inst{25} = 1; 1357 let Inst{19-16} = Rn; 1358 let Inst{15-12} = Rd; 1359 let Inst{11-0} = imm; 1360 } 1361 } 1362 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1363 iir, opc, "\t$Rd, $Rn, $Rm", 1364 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1365 Sched<[WriteALU, ReadALU, ReadALU]> { 1366 bits<4> Rd; 1367 bits<4> Rn; 1368 bits<4> Rm; 1369 let Inst{25} = 0; 1370 let isCommutable = Commutable; 1371 let Inst{19-16} = Rn; 1372 let Inst{15-12} = Rd; 1373 let Inst{11-4} = 0b00000000; 1374 let Inst{3-0} = Rm; 1375 } 1376 1377 def rsi : AsI1<opcod, (outs GPR:$Rd), 1378 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1379 iis, opc, "\t$Rd, $Rn, $shift", 1380 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1381 Sched<[WriteALUsi, ReadALU]> { 1382 bits<4> Rd; 1383 bits<4> Rn; 1384 bits<12> shift; 1385 let Inst{25} = 0; 1386 let Inst{19-16} = Rn; 1387 let Inst{15-12} = Rd; 1388 let Inst{11-5} = shift{11-5}; 1389 let Inst{4} = 0; 1390 let Inst{3-0} = shift{3-0}; 1391 } 1392 1393 def rsr : AsI1<opcod, (outs GPR:$Rd), 1394 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1395 iis, opc, "\t$Rd, $Rn, $shift", 1396 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1397 Sched<[WriteALUsr, ReadALUsr]> { 1398 bits<4> Rd; 1399 bits<4> Rn; 1400 bits<12> shift; 1401 let Inst{25} = 0; 1402 let Inst{19-16} = Rn; 1403 let Inst{15-12} = Rd; 1404 let Inst{11-8} = shift{11-8}; 1405 let Inst{7} = 0; 1406 let Inst{6-5} = shift{6-5}; 1407 let Inst{4} = 1; 1408 let Inst{3-0} = shift{3-0}; 1409 } 1410} 1411 1412/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1413/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1414/// it is equivalent to the AsI1_bin_irs counterpart. 1415let TwoOperandAliasConstraint = "$Rn = $Rd" in 1416multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1417 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1418 SDNode opnode, bit Commutable = 0> { 1419 // The register-immediate version is re-materializable. This is useful 1420 // in particular for taking the address of a local. 1421 let isReMaterializable = 1 in { 1422 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1423 iii, opc, "\t$Rd, $Rn, $imm", 1424 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>, 1425 Sched<[WriteALU, ReadALU]> { 1426 bits<4> Rd; 1427 bits<4> Rn; 1428 bits<12> imm; 1429 let Inst{25} = 1; 1430 let Inst{19-16} = Rn; 1431 let Inst{15-12} = Rd; 1432 let Inst{11-0} = imm; 1433 } 1434 } 1435 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1436 iir, opc, "\t$Rd, $Rn, $Rm", 1437 [/* pattern left blank */]>, 1438 Sched<[WriteALU, ReadALU, ReadALU]> { 1439 bits<4> Rd; 1440 bits<4> Rn; 1441 bits<4> Rm; 1442 let Inst{11-4} = 0b00000000; 1443 let Inst{25} = 0; 1444 let Inst{3-0} = Rm; 1445 let Inst{15-12} = Rd; 1446 let Inst{19-16} = Rn; 1447 } 1448 1449 def rsi : AsI1<opcod, (outs GPR:$Rd), 1450 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1451 iis, opc, "\t$Rd, $Rn, $shift", 1452 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1453 Sched<[WriteALUsi, ReadALU]> { 1454 bits<4> Rd; 1455 bits<4> Rn; 1456 bits<12> shift; 1457 let Inst{25} = 0; 1458 let Inst{19-16} = Rn; 1459 let Inst{15-12} = Rd; 1460 let Inst{11-5} = shift{11-5}; 1461 let Inst{4} = 0; 1462 let Inst{3-0} = shift{3-0}; 1463 } 1464 1465 def rsr : AsI1<opcod, (outs GPR:$Rd), 1466 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1467 iis, opc, "\t$Rd, $Rn, $shift", 1468 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1469 Sched<[WriteALUsr, ReadALUsr]> { 1470 bits<4> Rd; 1471 bits<4> Rn; 1472 bits<12> shift; 1473 let Inst{25} = 0; 1474 let Inst{19-16} = Rn; 1475 let Inst{15-12} = Rd; 1476 let Inst{11-8} = shift{11-8}; 1477 let Inst{7} = 0; 1478 let Inst{6-5} = shift{6-5}; 1479 let Inst{4} = 1; 1480 let Inst{3-0} = shift{3-0}; 1481 } 1482} 1483 1484/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1485/// 1486/// These opcodes will be converted to the real non-S opcodes by 1487/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1488let hasPostISelHook = 1, Defs = [CPSR] in { 1489multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1490 InstrItinClass iis, SDNode opnode, 1491 bit Commutable = 0> { 1492 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1493 4, iii, 1494 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>, 1495 Sched<[WriteALU, ReadALU]>; 1496 1497 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1498 4, iir, 1499 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1500 Sched<[WriteALU, ReadALU, ReadALU]> { 1501 let isCommutable = Commutable; 1502 } 1503 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1504 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1505 4, iis, 1506 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1507 so_reg_imm:$shift))]>, 1508 Sched<[WriteALUsi, ReadALU]>; 1509 1510 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1511 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1512 4, iis, 1513 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1514 so_reg_reg:$shift))]>, 1515 Sched<[WriteALUSsr, ReadALUsr]>; 1516} 1517} 1518 1519/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1520/// operands are reversed. 1521let hasPostISelHook = 1, Defs = [CPSR] in { 1522multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1523 InstrItinClass iis, SDNode opnode, 1524 bit Commutable = 0> { 1525 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1526 4, iii, 1527 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>, 1528 Sched<[WriteALU, ReadALU]>; 1529 1530 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1531 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1532 4, iis, 1533 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1534 GPR:$Rn))]>, 1535 Sched<[WriteALUsi, ReadALU]>; 1536 1537 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1538 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1539 4, iis, 1540 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1541 GPR:$Rn))]>, 1542 Sched<[WriteALUSsr, ReadALUsr]>; 1543} 1544} 1545 1546/// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test 1547/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1548/// a explicit result, only implicitly set CPSR. 1549let isCompare = 1, Defs = [CPSR] in { 1550multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1551 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1552 SDPatternOperator opnode, bit Commutable = 0, 1553 string rrDecoderMethod = ""> { 1554 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii, 1555 opc, "\t$Rn, $imm", 1556 [(opnode GPR:$Rn, mod_imm:$imm)]>, 1557 Sched<[WriteCMP, ReadALU]> { 1558 bits<4> Rn; 1559 bits<12> imm; 1560 let Inst{25} = 1; 1561 let Inst{20} = 1; 1562 let Inst{19-16} = Rn; 1563 let Inst{15-12} = 0b0000; 1564 let Inst{11-0} = imm; 1565 1566 let Unpredictable{15-12} = 0b1111; 1567 } 1568 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1569 opc, "\t$Rn, $Rm", 1570 [(opnode GPR:$Rn, GPR:$Rm)]>, 1571 Sched<[WriteCMP, ReadALU, ReadALU]> { 1572 bits<4> Rn; 1573 bits<4> Rm; 1574 let isCommutable = Commutable; 1575 let Inst{25} = 0; 1576 let Inst{20} = 1; 1577 let Inst{19-16} = Rn; 1578 let Inst{15-12} = 0b0000; 1579 let Inst{11-4} = 0b00000000; 1580 let Inst{3-0} = Rm; 1581 let DecoderMethod = rrDecoderMethod; 1582 1583 let Unpredictable{15-12} = 0b1111; 1584 } 1585 def rsi : AI1<opcod, (outs), 1586 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1587 opc, "\t$Rn, $shift", 1588 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1589 Sched<[WriteCMPsi, ReadALU]> { 1590 bits<4> Rn; 1591 bits<12> shift; 1592 let Inst{25} = 0; 1593 let Inst{20} = 1; 1594 let Inst{19-16} = Rn; 1595 let Inst{15-12} = 0b0000; 1596 let Inst{11-5} = shift{11-5}; 1597 let Inst{4} = 0; 1598 let Inst{3-0} = shift{3-0}; 1599 1600 let Unpredictable{15-12} = 0b1111; 1601 } 1602 def rsr : AI1<opcod, (outs), 1603 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1604 opc, "\t$Rn, $shift", 1605 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1606 Sched<[WriteCMPsr, ReadALU]> { 1607 bits<4> Rn; 1608 bits<12> shift; 1609 let Inst{25} = 0; 1610 let Inst{20} = 1; 1611 let Inst{19-16} = Rn; 1612 let Inst{15-12} = 0b0000; 1613 let Inst{11-8} = shift{11-8}; 1614 let Inst{7} = 0; 1615 let Inst{6-5} = shift{6-5}; 1616 let Inst{4} = 1; 1617 let Inst{3-0} = shift{3-0}; 1618 1619 let Unpredictable{15-12} = 0b1111; 1620 } 1621 1622} 1623} 1624 1625/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1626/// register and one whose operand is a register rotated by 8/16/24. 1627/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1628class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1629 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1630 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1631 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1632 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1633 bits<4> Rd; 1634 bits<4> Rm; 1635 bits<2> rot; 1636 let Inst{19-16} = 0b1111; 1637 let Inst{15-12} = Rd; 1638 let Inst{11-10} = rot; 1639 let Inst{3-0} = Rm; 1640} 1641 1642class AI_ext_rrot_np<bits<8> opcod, string opc> 1643 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1644 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1645 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1646 bits<2> rot; 1647 let Inst{19-16} = 0b1111; 1648 let Inst{11-10} = rot; 1649 } 1650 1651/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1652/// register and one whose operand is a register rotated by 8/16/24. 1653class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1654 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1655 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1656 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1657 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1658 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1659 bits<4> Rd; 1660 bits<4> Rm; 1661 bits<4> Rn; 1662 bits<2> rot; 1663 let Inst{19-16} = Rn; 1664 let Inst{15-12} = Rd; 1665 let Inst{11-10} = rot; 1666 let Inst{9-4} = 0b000111; 1667 let Inst{3-0} = Rm; 1668} 1669 1670class AI_exta_rrot_np<bits<8> opcod, string opc> 1671 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1672 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1673 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1674 bits<4> Rn; 1675 bits<2> rot; 1676 let Inst{19-16} = Rn; 1677 let Inst{11-10} = rot; 1678} 1679 1680/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1681let TwoOperandAliasConstraint = "$Rn = $Rd" in 1682multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode, 1683 bit Commutable = 0> { 1684 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1685 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1686 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1687 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>, 1688 Requires<[IsARM]>, 1689 Sched<[WriteALU, ReadALU]> { 1690 bits<4> Rd; 1691 bits<4> Rn; 1692 bits<12> imm; 1693 let Inst{25} = 1; 1694 let Inst{15-12} = Rd; 1695 let Inst{19-16} = Rn; 1696 let Inst{11-0} = imm; 1697 } 1698 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1699 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1700 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1701 Requires<[IsARM]>, 1702 Sched<[WriteALU, ReadALU, ReadALU]> { 1703 bits<4> Rd; 1704 bits<4> Rn; 1705 bits<4> Rm; 1706 let Inst{11-4} = 0b00000000; 1707 let Inst{25} = 0; 1708 let isCommutable = Commutable; 1709 let Inst{3-0} = Rm; 1710 let Inst{15-12} = Rd; 1711 let Inst{19-16} = Rn; 1712 } 1713 def rsi : AsI1<opcod, (outs GPR:$Rd), 1714 (ins GPR:$Rn, so_reg_imm:$shift), 1715 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1716 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1717 Requires<[IsARM]>, 1718 Sched<[WriteALUsi, ReadALU]> { 1719 bits<4> Rd; 1720 bits<4> Rn; 1721 bits<12> shift; 1722 let Inst{25} = 0; 1723 let Inst{19-16} = Rn; 1724 let Inst{15-12} = Rd; 1725 let Inst{11-5} = shift{11-5}; 1726 let Inst{4} = 0; 1727 let Inst{3-0} = shift{3-0}; 1728 } 1729 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1730 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1731 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1732 [(set GPRnopc:$Rd, CPSR, 1733 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1734 Requires<[IsARM]>, 1735 Sched<[WriteALUsr, ReadALUsr]> { 1736 bits<4> Rd; 1737 bits<4> Rn; 1738 bits<12> shift; 1739 let Inst{25} = 0; 1740 let Inst{19-16} = Rn; 1741 let Inst{15-12} = Rd; 1742 let Inst{11-8} = shift{11-8}; 1743 let Inst{7} = 0; 1744 let Inst{6-5} = shift{6-5}; 1745 let Inst{4} = 1; 1746 let Inst{3-0} = shift{3-0}; 1747 } 1748 } 1749} 1750 1751/// AI1_rsc_irs - Define instructions and patterns for rsc 1752let TwoOperandAliasConstraint = "$Rn = $Rd" in 1753multiclass AI1_rsc_irs<bits<4> opcod, string opc, SDNode opnode> { 1754 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1755 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1756 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1757 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>, 1758 Requires<[IsARM]>, 1759 Sched<[WriteALU, ReadALU]> { 1760 bits<4> Rd; 1761 bits<4> Rn; 1762 bits<12> imm; 1763 let Inst{25} = 1; 1764 let Inst{15-12} = Rd; 1765 let Inst{19-16} = Rn; 1766 let Inst{11-0} = imm; 1767 } 1768 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1769 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1770 [/* pattern left blank */]>, 1771 Sched<[WriteALU, ReadALU, ReadALU]> { 1772 bits<4> Rd; 1773 bits<4> Rn; 1774 bits<4> Rm; 1775 let Inst{11-4} = 0b00000000; 1776 let Inst{25} = 0; 1777 let Inst{3-0} = Rm; 1778 let Inst{15-12} = Rd; 1779 let Inst{19-16} = Rn; 1780 } 1781 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1782 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1783 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1784 Requires<[IsARM]>, 1785 Sched<[WriteALUsi, ReadALU]> { 1786 bits<4> Rd; 1787 bits<4> Rn; 1788 bits<12> shift; 1789 let Inst{25} = 0; 1790 let Inst{19-16} = Rn; 1791 let Inst{15-12} = Rd; 1792 let Inst{11-5} = shift{11-5}; 1793 let Inst{4} = 0; 1794 let Inst{3-0} = shift{3-0}; 1795 } 1796 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1797 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1798 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1799 Requires<[IsARM]>, 1800 Sched<[WriteALUsr, ReadALUsr]> { 1801 bits<4> Rd; 1802 bits<4> Rn; 1803 bits<12> shift; 1804 let Inst{25} = 0; 1805 let Inst{19-16} = Rn; 1806 let Inst{15-12} = Rd; 1807 let Inst{11-8} = shift{11-8}; 1808 let Inst{7} = 0; 1809 let Inst{6-5} = shift{6-5}; 1810 let Inst{4} = 1; 1811 let Inst{3-0} = shift{3-0}; 1812 } 1813 } 1814} 1815 1816let canFoldAsLoad = 1, isReMaterializable = 1 in { 1817multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1818 InstrItinClass iir, PatFrag opnode> { 1819 // Note: We use the complex addrmode_imm12 rather than just an input 1820 // GPR and a constrained immediate so that we can use this to match 1821 // frame index references and avoid matching constant pool references. 1822 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1823 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1824 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1825 bits<4> Rt; 1826 bits<17> addr; 1827 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1828 let Inst{19-16} = addr{16-13}; // Rn 1829 let Inst{15-12} = Rt; 1830 let Inst{11-0} = addr{11-0}; // imm12 1831 } 1832 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1833 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1834 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 1835 bits<4> Rt; 1836 bits<17> shift; 1837 let shift{4} = 0; // Inst{4} = 0 1838 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1839 let Inst{19-16} = shift{16-13}; // Rn 1840 let Inst{15-12} = Rt; 1841 let Inst{11-0} = shift{11-0}; 1842 } 1843} 1844} 1845 1846let canFoldAsLoad = 1, isReMaterializable = 1 in { 1847multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 1848 InstrItinClass iir, PatFrag opnode> { 1849 // Note: We use the complex addrmode_imm12 rather than just an input 1850 // GPR and a constrained immediate so that we can use this to match 1851 // frame index references and avoid matching constant pool references. 1852 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 1853 (ins addrmode_imm12:$addr), 1854 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1855 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 1856 bits<4> Rt; 1857 bits<17> addr; 1858 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1859 let Inst{19-16} = addr{16-13}; // Rn 1860 let Inst{15-12} = Rt; 1861 let Inst{11-0} = addr{11-0}; // imm12 1862 } 1863 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 1864 (ins ldst_so_reg:$shift), 1865 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1866 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 1867 bits<4> Rt; 1868 bits<17> shift; 1869 let shift{4} = 0; // Inst{4} = 0 1870 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1871 let Inst{19-16} = shift{16-13}; // Rn 1872 let Inst{15-12} = Rt; 1873 let Inst{11-0} = shift{11-0}; 1874 } 1875} 1876} 1877 1878 1879multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 1880 InstrItinClass iir, PatFrag opnode> { 1881 // Note: We use the complex addrmode_imm12 rather than just an input 1882 // GPR and a constrained immediate so that we can use this to match 1883 // frame index references and avoid matching constant pool references. 1884 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1885 (ins GPR:$Rt, addrmode_imm12:$addr), 1886 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1887 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 1888 bits<4> Rt; 1889 bits<17> addr; 1890 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1891 let Inst{19-16} = addr{16-13}; // Rn 1892 let Inst{15-12} = Rt; 1893 let Inst{11-0} = addr{11-0}; // imm12 1894 } 1895 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 1896 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1897 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 1898 bits<4> Rt; 1899 bits<17> shift; 1900 let shift{4} = 0; // Inst{4} = 0 1901 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1902 let Inst{19-16} = shift{16-13}; // Rn 1903 let Inst{15-12} = Rt; 1904 let Inst{11-0} = shift{11-0}; 1905 } 1906} 1907 1908multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 1909 InstrItinClass iir, PatFrag opnode> { 1910 // Note: We use the complex addrmode_imm12 rather than just an input 1911 // GPR and a constrained immediate so that we can use this to match 1912 // frame index references and avoid matching constant pool references. 1913 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1914 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 1915 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1916 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 1917 bits<4> Rt; 1918 bits<17> addr; 1919 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1920 let Inst{19-16} = addr{16-13}; // Rn 1921 let Inst{15-12} = Rt; 1922 let Inst{11-0} = addr{11-0}; // imm12 1923 } 1924 def rs : AI2ldst<0b011, 0, isByte, (outs), 1925 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 1926 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1927 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 1928 bits<4> Rt; 1929 bits<17> shift; 1930 let shift{4} = 0; // Inst{4} = 0 1931 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1932 let Inst{19-16} = shift{16-13}; // Rn 1933 let Inst{15-12} = Rt; 1934 let Inst{11-0} = shift{11-0}; 1935 } 1936} 1937 1938 1939//===----------------------------------------------------------------------===// 1940// Instructions 1941//===----------------------------------------------------------------------===// 1942 1943//===----------------------------------------------------------------------===// 1944// Miscellaneous Instructions. 1945// 1946 1947/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1948/// the function. The first operand is the ID# for this instruction, the second 1949/// is the index into the MachineConstantPool that this is, the third is the 1950/// size in bytes of this constant pool entry. 1951let hasSideEffects = 0, isNotDuplicable = 1 in 1952def CONSTPOOL_ENTRY : 1953PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1954 i32imm:$size), NoItinerary, []>; 1955 1956/// A jumptable consisting of direct 32-bit addresses of the destination basic 1957/// blocks (either absolute, or relative to the start of the jump-table in PIC 1958/// mode). Used mostly in ARM and Thumb-1 modes. 1959def JUMPTABLE_ADDRS : 1960PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1961 i32imm:$size), NoItinerary, []>; 1962 1963/// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables 1964/// that cannot be optimised to use TBB or TBH. 1965def JUMPTABLE_INSTS : 1966PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1967 i32imm:$size), NoItinerary, []>; 1968 1969/// A jumptable consisting of 8-bit unsigned integers representing offsets from 1970/// a TBB instruction. 1971def JUMPTABLE_TBB : 1972PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1973 i32imm:$size), NoItinerary, []>; 1974 1975/// A jumptable consisting of 16-bit unsigned integers representing offsets from 1976/// a TBH instruction. 1977def JUMPTABLE_TBH : 1978PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1979 i32imm:$size), NoItinerary, []>; 1980 1981 1982// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 1983// from removing one half of the matched pairs. That breaks PEI, which assumes 1984// these will always be in pairs, and asserts if it finds otherwise. Better way? 1985let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 1986def ADJCALLSTACKUP : 1987PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 1988 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 1989 1990def ADJCALLSTACKDOWN : 1991PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2, pred:$p), NoItinerary, 1992 [(ARMcallseq_start timm:$amt, timm:$amt2)]>; 1993} 1994 1995def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 1996 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>, 1997 Requires<[IsARM, HasV6]> { 1998 bits<8> imm; 1999 let Inst{27-8} = 0b00110010000011110000; 2000 let Inst{7-0} = imm; 2001 let DecoderMethod = "DecodeHINTInstruction"; 2002} 2003 2004def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>; 2005def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>; 2006def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>; 2007def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>; 2008def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>; 2009def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 2010def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>; 2011def : InstAlias<"csdb$p", (HINT 20, pred:$p)>, Requires<[IsARM, HasV6K]>; 2012 2013def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 2014 "\t$Rd, $Rn, $Rm", 2015 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>, 2016 Requires<[IsARM, HasV6]> { 2017 bits<4> Rd; 2018 bits<4> Rn; 2019 bits<4> Rm; 2020 let Inst{3-0} = Rm; 2021 let Inst{15-12} = Rd; 2022 let Inst{19-16} = Rn; 2023 let Inst{27-20} = 0b01101000; 2024 let Inst{7-4} = 0b1011; 2025 let Inst{11-8} = 0b1111; 2026 let Unpredictable{11-8} = 0b1111; 2027} 2028 2029// The 16-bit operand $val can be used by a debugger to store more information 2030// about the breakpoint. 2031def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2032 "bkpt", "\t$val", []>, Requires<[IsARM]> { 2033 bits<16> val; 2034 let Inst{3-0} = val{3-0}; 2035 let Inst{19-8} = val{15-4}; 2036 let Inst{27-20} = 0b00010010; 2037 let Inst{31-28} = 0xe; // AL 2038 let Inst{7-4} = 0b0111; 2039} 2040// default immediate for breakpoint mnemonic 2041def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>; 2042 2043def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2044 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 2045 bits<16> val; 2046 let Inst{3-0} = val{3-0}; 2047 let Inst{19-8} = val{15-4}; 2048 let Inst{27-20} = 0b00010000; 2049 let Inst{31-28} = 0xe; // AL 2050 let Inst{7-4} = 0b0111; 2051} 2052 2053// Change Processor State 2054// FIXME: We should use InstAlias to handle the optional operands. 2055class CPS<dag iops, string asm_ops> 2056 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 2057 []>, Requires<[IsARM]> { 2058 bits<2> imod; 2059 bits<3> iflags; 2060 bits<5> mode; 2061 bit M; 2062 2063 let Inst{31-28} = 0b1111; 2064 let Inst{27-20} = 0b00010000; 2065 let Inst{19-18} = imod; 2066 let Inst{17} = M; // Enabled if mode is set; 2067 let Inst{16-9} = 0b00000000; 2068 let Inst{8-6} = iflags; 2069 let Inst{5} = 0; 2070 let Inst{4-0} = mode; 2071} 2072 2073let DecoderMethod = "DecodeCPSInstruction" in { 2074let M = 1 in 2075 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 2076 "$imod\t$iflags, $mode">; 2077let mode = 0, M = 0 in 2078 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 2079 2080let imod = 0, iflags = 0, M = 1 in 2081 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 2082} 2083 2084// Preload signals the memory system of possible future data/instruction access. 2085multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 2086 2087 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, 2088 IIC_Preload, !strconcat(opc, "\t$addr"), 2089 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 2090 Sched<[WritePreLd]> { 2091 bits<4> Rt; 2092 bits<17> addr; 2093 let Inst{31-26} = 0b111101; 2094 let Inst{25} = 0; // 0 for immediate form 2095 let Inst{24} = data; 2096 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2097 let Inst{22} = read; 2098 let Inst{21-20} = 0b01; 2099 let Inst{19-16} = addr{16-13}; // Rn 2100 let Inst{15-12} = 0b1111; 2101 let Inst{11-0} = addr{11-0}; // imm12 2102 } 2103 2104 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 2105 !strconcat(opc, "\t$shift"), 2106 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 2107 Sched<[WritePreLd]> { 2108 bits<17> shift; 2109 let Inst{31-26} = 0b111101; 2110 let Inst{25} = 1; // 1 for register form 2111 let Inst{24} = data; 2112 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2113 let Inst{22} = read; 2114 let Inst{21-20} = 0b01; 2115 let Inst{19-16} = shift{16-13}; // Rn 2116 let Inst{15-12} = 0b1111; 2117 let Inst{11-0} = shift{11-0}; 2118 let Inst{4} = 0; 2119 } 2120} 2121 2122defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 2123defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 2124defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 2125 2126def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 2127 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 2128 bits<1> end; 2129 let Inst{31-10} = 0b1111000100000001000000; 2130 let Inst{9} = end; 2131 let Inst{8-0} = 0; 2132} 2133 2134def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 2135 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> { 2136 bits<4> opt; 2137 let Inst{27-4} = 0b001100100000111100001111; 2138 let Inst{3-0} = opt; 2139} 2140 2141// A8.8.247 UDF - Undefined (Encoding A1) 2142def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, 2143 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { 2144 bits<16> imm16; 2145 let Inst{31-28} = 0b1110; // AL 2146 let Inst{27-25} = 0b011; 2147 let Inst{24-20} = 0b11111; 2148 let Inst{19-8} = imm16{15-4}; 2149 let Inst{7-4} = 0b1111; 2150 let Inst{3-0} = imm16{3-0}; 2151} 2152 2153/* 2154 * A5.4 Permanently UNDEFINED instructions. 2155 * 2156 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 2157 * Other UDF encodings generate SIGILL. 2158 * 2159 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 2160 * Encoding A1: 2161 * 1110 0111 1111 iiii iiii iiii 1111 iiii 2162 * Encoding T1: 2163 * 1101 1110 iiii iiii 2164 * It uses the following encoding: 2165 * 1110 0111 1111 1110 1101 1110 1111 0000 2166 * - In ARM: UDF #60896; 2167 * - In Thumb: UDF #254 followed by a branch-to-self. 2168 */ 2169let isBarrier = 1, isTerminator = 1 in 2170def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 2171 "trap", [(trap)]>, 2172 Requires<[IsARM,UseNaClTrap]> { 2173 let Inst = 0xe7fedef0; 2174} 2175let isBarrier = 1, isTerminator = 1 in 2176def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 2177 "trap", [(trap)]>, 2178 Requires<[IsARM,DontUseNaClTrap]> { 2179 let Inst = 0xe7ffdefe; 2180} 2181 2182def : Pat<(debugtrap), (BKPT 0)>, Requires<[IsARM, HasV5T]>; 2183def : Pat<(debugtrap), (UDF 254)>, Requires<[IsARM, NoV5T]>; 2184 2185// Address computation and loads and stores in PIC mode. 2186let isNotDuplicable = 1 in { 2187def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 2188 4, IIC_iALUr, 2189 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 2190 Sched<[WriteALU, ReadALU]>; 2191 2192let AddedComplexity = 10 in { 2193def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 2194 4, IIC_iLoad_r, 2195 [(set GPR:$dst, (load addrmodepc:$addr))]>; 2196 2197def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2198 4, IIC_iLoad_bh_r, 2199 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 2200 2201def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2202 4, IIC_iLoad_bh_r, 2203 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 2204 2205def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2206 4, IIC_iLoad_bh_r, 2207 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 2208 2209def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2210 4, IIC_iLoad_bh_r, 2211 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 2212} 2213let AddedComplexity = 10 in { 2214def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2215 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 2216 2217def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2218 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 2219 addrmodepc:$addr)]>; 2220 2221def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2222 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 2223} 2224} // isNotDuplicable = 1 2225 2226 2227// LEApcrel - Load a pc-relative address into a register without offending the 2228// assembler. 2229let hasSideEffects = 0, isReMaterializable = 1 in 2230// The 'adr' mnemonic encodes differently if the label is before or after 2231// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 2232// know until then which form of the instruction will be used. 2233def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 2234 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 2235 Sched<[WriteALU, ReadALU]> { 2236 bits<4> Rd; 2237 bits<14> label; 2238 let Inst{27-25} = 0b001; 2239 let Inst{24} = 0; 2240 let Inst{23-22} = label{13-12}; 2241 let Inst{21} = 0; 2242 let Inst{20} = 0; 2243 let Inst{19-16} = 0b1111; 2244 let Inst{15-12} = Rd; 2245 let Inst{11-0} = label{11-0}; 2246} 2247 2248let hasSideEffects = 1 in { 2249def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 2250 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2251 2252def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 2253 (ins i32imm:$label, pred:$p), 2254 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2255} 2256 2257//===----------------------------------------------------------------------===// 2258// Control Flow Instructions. 2259// 2260 2261let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 2262 // ARMV4T and above 2263 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2264 "bx", "\tlr", [(ARMretflag)]>, 2265 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2266 let Inst{27-0} = 0b0001001011111111111100011110; 2267 } 2268 2269 // ARMV4 only 2270 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2271 "mov", "\tpc, lr", [(ARMretflag)]>, 2272 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 2273 let Inst{27-0} = 0b0001101000001111000000001110; 2274 } 2275 2276 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 2277 // the user-space one). 2278 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 2279 4, IIC_Br, 2280 [(ARMintretflag imm:$offset)]>; 2281} 2282 2283// Indirect branches 2284let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 2285 // ARMV4T and above 2286 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 2287 [(brind GPR:$dst)]>, 2288 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2289 bits<4> dst; 2290 let Inst{31-4} = 0b1110000100101111111111110001; 2291 let Inst{3-0} = dst; 2292 } 2293 2294 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 2295 "bx", "\t$dst", [/* pattern left blank */]>, 2296 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2297 bits<4> dst; 2298 let Inst{27-4} = 0b000100101111111111110001; 2299 let Inst{3-0} = dst; 2300 } 2301} 2302 2303// SP is marked as a use to prevent stack-pointer assignments that appear 2304// immediately before calls from potentially appearing dead. 2305let isCall = 1, 2306 // FIXME: Do we really need a non-predicated version? If so, it should 2307 // at least be a pseudo instruction expanding to the predicated version 2308 // at MC lowering time. 2309 Defs = [LR], Uses = [SP] in { 2310 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func), 2311 IIC_Br, "bl\t$func", 2312 [(ARMcall tglobaladdr:$func)]>, 2313 Requires<[IsARM]>, Sched<[WriteBrL]> { 2314 let Inst{31-28} = 0b1110; 2315 bits<24> func; 2316 let Inst{23-0} = func; 2317 let DecoderMethod = "DecodeBranchImmInstruction"; 2318 } 2319 2320 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func), 2321 IIC_Br, "bl", "\t$func", 2322 [(ARMcall_pred tglobaladdr:$func)]>, 2323 Requires<[IsARM]>, Sched<[WriteBrL]> { 2324 bits<24> func; 2325 let Inst{23-0} = func; 2326 let DecoderMethod = "DecodeBranchImmInstruction"; 2327 } 2328 2329 // ARMv5T and above 2330 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, 2331 IIC_Br, "blx\t$func", 2332 [(ARMcall GPR:$func)]>, 2333 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2334 bits<4> func; 2335 let Inst{31-4} = 0b1110000100101111111111110011; 2336 let Inst{3-0} = func; 2337 } 2338 2339 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2340 IIC_Br, "blx", "\t$func", 2341 [(ARMcall_pred GPR:$func)]>, 2342 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2343 bits<4> func; 2344 let Inst{27-4} = 0b000100101111111111110011; 2345 let Inst{3-0} = func; 2346 } 2347 2348 // ARMv4T 2349 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2350 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2351 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2352 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2353 2354 // ARMv4 2355 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2356 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2357 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2358 2359 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2360 // return stack predictor. 2361 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins arm_bl_target:$func), 2362 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2363 Requires<[IsARM]>, Sched<[WriteBr]>; 2364} 2365 2366let isBranch = 1, isTerminator = 1 in { 2367 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2368 // a two-value operand where a dag node expects two operands. :( 2369 def Bcc : ABI<0b1010, (outs), (ins arm_br_target:$target), 2370 IIC_Br, "b", "\t$target", 2371 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2372 Sched<[WriteBr]> { 2373 bits<24> target; 2374 let Inst{23-0} = target; 2375 let DecoderMethod = "DecodeBranchImmInstruction"; 2376 } 2377 2378 let isBarrier = 1 in { 2379 // B is "predicable" since it's just a Bcc with an 'always' condition. 2380 let isPredicable = 1 in 2381 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2382 // should be sufficient. 2383 // FIXME: Is B really a Barrier? That doesn't seem right. 2384 def B : ARMPseudoExpand<(outs), (ins arm_br_target:$target), 4, IIC_Br, 2385 [(br bb:$target)], (Bcc arm_br_target:$target, 2386 (ops 14, zero_reg))>, 2387 Sched<[WriteBr]>; 2388 2389 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in { 2390 def BR_JTr : ARMPseudoInst<(outs), 2391 (ins GPR:$target, i32imm:$jt), 2392 0, IIC_Br, 2393 [(ARMbrjt GPR:$target, tjumptable:$jt)]>, 2394 Sched<[WriteBr]>; 2395 def BR_JTm_i12 : ARMPseudoInst<(outs), 2396 (ins addrmode_imm12:$target, i32imm:$jt), 2397 0, IIC_Br, 2398 [(ARMbrjt (i32 (load addrmode_imm12:$target)), 2399 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2400 def BR_JTm_rs : ARMPseudoInst<(outs), 2401 (ins ldst_so_reg:$target, i32imm:$jt), 2402 0, IIC_Br, 2403 [(ARMbrjt (i32 (load ldst_so_reg:$target)), 2404 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2405 def BR_JTadd : ARMPseudoInst<(outs), 2406 (ins GPR:$target, GPR:$idx, i32imm:$jt), 2407 0, IIC_Br, 2408 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>, 2409 Sched<[WriteBrTbl]>; 2410 } // isNotDuplicable = 1, isIndirectBranch = 1 2411 } // isBarrier = 1 2412 2413} 2414 2415// BLX (immediate) 2416def BLXi : AXI<(outs), (ins arm_blx_target:$target), BrMiscFrm, NoItinerary, 2417 "blx\t$target", []>, 2418 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2419 let Inst{31-25} = 0b1111101; 2420 bits<25> target; 2421 let Inst{23-0} = target{24-1}; 2422 let Inst{24} = target{0}; 2423 let isCall = 1; 2424} 2425 2426// Branch and Exchange Jazelle 2427def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2428 [/* pattern left blank */]>, Sched<[WriteBr]> { 2429 bits<4> func; 2430 let Inst{23-20} = 0b0010; 2431 let Inst{19-8} = 0xfff; 2432 let Inst{7-4} = 0b0010; 2433 let Inst{3-0} = func; 2434 let isBranch = 1; 2435} 2436 2437// Tail calls. 2438 2439let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2440 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, 2441 Sched<[WriteBr]>; 2442 2443 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, 2444 Sched<[WriteBr]>; 2445 2446 def TAILJMPd : ARMPseudoExpand<(outs), (ins arm_br_target:$dst), 2447 4, IIC_Br, [], 2448 (Bcc arm_br_target:$dst, (ops 14, zero_reg))>, 2449 Requires<[IsARM]>, Sched<[WriteBr]>; 2450 2451 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2452 4, IIC_Br, [], 2453 (BX GPR:$dst)>, Sched<[WriteBr]>, 2454 Requires<[IsARM, HasV4T]>; 2455} 2456 2457// Secure Monitor Call is a system instruction. 2458def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2459 []>, Requires<[IsARM, HasTrustZone]> { 2460 bits<4> opt; 2461 let Inst{23-4} = 0b01100000000000000111; 2462 let Inst{3-0} = opt; 2463} 2464def : MnemonicAlias<"smi", "smc">; 2465 2466// Supervisor Call (Software Interrupt) 2467let isCall = 1, Uses = [SP] in { 2468def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2469 Sched<[WriteBr]> { 2470 bits<24> svc; 2471 let Inst{23-0} = svc; 2472} 2473} 2474 2475// Store Return State 2476class SRSI<bit wb, string asm> 2477 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2478 NoItinerary, asm, "", []> { 2479 bits<5> mode; 2480 let Inst{31-28} = 0b1111; 2481 let Inst{27-25} = 0b100; 2482 let Inst{22} = 1; 2483 let Inst{21} = wb; 2484 let Inst{20} = 0; 2485 let Inst{19-16} = 0b1101; // SP 2486 let Inst{15-5} = 0b00000101000; 2487 let Inst{4-0} = mode; 2488} 2489 2490def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2491 let Inst{24-23} = 0; 2492} 2493def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2494 let Inst{24-23} = 0; 2495} 2496def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2497 let Inst{24-23} = 0b10; 2498} 2499def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2500 let Inst{24-23} = 0b10; 2501} 2502def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2503 let Inst{24-23} = 0b01; 2504} 2505def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2506 let Inst{24-23} = 0b01; 2507} 2508def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2509 let Inst{24-23} = 0b11; 2510} 2511def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2512 let Inst{24-23} = 0b11; 2513} 2514 2515def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2516def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2517 2518def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2519def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2520 2521def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2522def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2523 2524def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2525def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2526 2527// Return From Exception 2528class RFEI<bit wb, string asm> 2529 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2530 NoItinerary, asm, "", []> { 2531 bits<4> Rn; 2532 let Inst{31-28} = 0b1111; 2533 let Inst{27-25} = 0b100; 2534 let Inst{22} = 0; 2535 let Inst{21} = wb; 2536 let Inst{20} = 1; 2537 let Inst{19-16} = Rn; 2538 let Inst{15-0} = 0xa00; 2539} 2540 2541def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2542 let Inst{24-23} = 0; 2543} 2544def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2545 let Inst{24-23} = 0; 2546} 2547def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2548 let Inst{24-23} = 0b10; 2549} 2550def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2551 let Inst{24-23} = 0b10; 2552} 2553def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2554 let Inst{24-23} = 0b01; 2555} 2556def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2557 let Inst{24-23} = 0b01; 2558} 2559def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2560 let Inst{24-23} = 0b11; 2561} 2562def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2563 let Inst{24-23} = 0b11; 2564} 2565 2566// Hypervisor Call is a system instruction 2567let isCall = 1 in { 2568def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary, 2569 "hvc", "\t$imm", []>, 2570 Requires<[IsARM, HasVirtualization]> { 2571 bits<16> imm; 2572 2573 // Even though HVC isn't predicable, it's encoding includes a condition field. 2574 // The instruction is undefined if the condition field is 0xf otherwise it is 2575 // unpredictable if it isn't condition AL (0xe). 2576 let Inst{31-28} = 0b1110; 2577 let Unpredictable{31-28} = 0b1111; 2578 let Inst{27-24} = 0b0001; 2579 let Inst{23-20} = 0b0100; 2580 let Inst{19-8} = imm{15-4}; 2581 let Inst{7-4} = 0b0111; 2582 let Inst{3-0} = imm{3-0}; 2583} 2584} 2585 2586// Return from exception in Hypervisor mode. 2587let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 2588def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>, 2589 Requires<[IsARM, HasVirtualization]> { 2590 let Inst{23-0} = 0b011000000000000001101110; 2591} 2592 2593//===----------------------------------------------------------------------===// 2594// Load / Store Instructions. 2595// 2596 2597// Load 2598 2599 2600defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, load>; 2601defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2602 zextloadi8>; 2603defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, store>; 2604defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2605 truncstorei8>; 2606 2607// Special LDR for loads from non-pc-relative constpools. 2608let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0, 2609 isReMaterializable = 1, isCodeGenOnly = 1 in 2610def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2611 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2612 []> { 2613 bits<4> Rt; 2614 bits<17> addr; 2615 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2616 let Inst{19-16} = 0b1111; 2617 let Inst{15-12} = Rt; 2618 let Inst{11-0} = addr{11-0}; // imm12 2619} 2620 2621// Loads with zero extension 2622def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2623 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2624 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2625 2626// Loads with sign extension 2627def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2628 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2629 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2630 2631def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2632 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2633 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2634 2635let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { 2636 // Load doubleword 2637 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), 2638 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, 2639 Requires<[IsARM, HasV5TE]>; 2640} 2641 2642def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2643 NoItinerary, "lda", "\t$Rt, $addr", []>; 2644def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2645 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2646def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2647 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2648 2649// Indexed loads 2650multiclass AI2_ldridx<bit isByte, string opc, 2651 InstrItinClass iii, InstrItinClass iir> { 2652 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2653 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2654 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2655 bits<17> addr; 2656 let Inst{25} = 0; 2657 let Inst{23} = addr{12}; 2658 let Inst{19-16} = addr{16-13}; 2659 let Inst{11-0} = addr{11-0}; 2660 let DecoderMethod = "DecodeLDRPreImm"; 2661 } 2662 2663 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2664 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2665 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2666 bits<17> addr; 2667 let Inst{25} = 1; 2668 let Inst{23} = addr{12}; 2669 let Inst{19-16} = addr{16-13}; 2670 let Inst{11-0} = addr{11-0}; 2671 let Inst{4} = 0; 2672 let DecoderMethod = "DecodeLDRPreReg"; 2673 } 2674 2675 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2676 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2677 IndexModePost, LdFrm, iir, 2678 opc, "\t$Rt, $addr, $offset", 2679 "$addr.base = $Rn_wb", []> { 2680 // {12} isAdd 2681 // {11-0} imm12/Rm 2682 bits<14> offset; 2683 bits<4> addr; 2684 let Inst{25} = 1; 2685 let Inst{23} = offset{12}; 2686 let Inst{19-16} = addr; 2687 let Inst{11-0} = offset{11-0}; 2688 let Inst{4} = 0; 2689 2690 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2691 } 2692 2693 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2694 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2695 IndexModePost, LdFrm, iii, 2696 opc, "\t$Rt, $addr, $offset", 2697 "$addr.base = $Rn_wb", []> { 2698 // {12} isAdd 2699 // {11-0} imm12/Rm 2700 bits<14> offset; 2701 bits<4> addr; 2702 let Inst{25} = 0; 2703 let Inst{23} = offset{12}; 2704 let Inst{19-16} = addr; 2705 let Inst{11-0} = offset{11-0}; 2706 2707 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2708 } 2709 2710} 2711 2712let mayLoad = 1, hasSideEffects = 0 in { 2713// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or 2714// IIC_iLoad_siu depending on whether it the offset register is shifted. 2715defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2716defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2717} 2718 2719multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2720 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2721 (ins addrmode3_pre:$addr), IndexModePre, 2722 LdMiscFrm, itin, 2723 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2724 bits<14> addr; 2725 let Inst{23} = addr{8}; // U bit 2726 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2727 let Inst{19-16} = addr{12-9}; // Rn 2728 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2729 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2730 let DecoderMethod = "DecodeAddrMode3Instruction"; 2731 } 2732 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2733 (ins addr_offset_none:$addr, am3offset:$offset), 2734 IndexModePost, LdMiscFrm, itin, 2735 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2736 []> { 2737 bits<10> offset; 2738 bits<4> addr; 2739 let Inst{23} = offset{8}; // U bit 2740 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2741 let Inst{19-16} = addr; 2742 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2743 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2744 let DecoderMethod = "DecodeAddrMode3Instruction"; 2745 } 2746} 2747 2748let mayLoad = 1, hasSideEffects = 0 in { 2749defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2750defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2751defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2752let hasExtraDefRegAllocReq = 1 in { 2753def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2754 (ins addrmode3_pre:$addr), IndexModePre, 2755 LdMiscFrm, IIC_iLoad_d_ru, 2756 "ldrd", "\t$Rt, $Rt2, $addr!", 2757 "$addr.base = $Rn_wb", []> { 2758 bits<14> addr; 2759 let Inst{23} = addr{8}; // U bit 2760 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2761 let Inst{19-16} = addr{12-9}; // Rn 2762 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2763 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2764 let DecoderMethod = "DecodeAddrMode3Instruction"; 2765} 2766def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2767 (ins addr_offset_none:$addr, am3offset:$offset), 2768 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2769 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2770 "$addr.base = $Rn_wb", []> { 2771 bits<10> offset; 2772 bits<4> addr; 2773 let Inst{23} = offset{8}; // U bit 2774 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2775 let Inst{19-16} = addr; 2776 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2777 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2778 let DecoderMethod = "DecodeAddrMode3Instruction"; 2779} 2780} // hasExtraDefRegAllocReq = 1 2781} // mayLoad = 1, hasSideEffects = 0 2782 2783// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2784let mayLoad = 1, hasSideEffects = 0 in { 2785def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2786 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2787 IndexModePost, LdFrm, IIC_iLoad_ru, 2788 "ldrt", "\t$Rt, $addr, $offset", 2789 "$addr.base = $Rn_wb", []> { 2790 // {12} isAdd 2791 // {11-0} imm12/Rm 2792 bits<14> offset; 2793 bits<4> addr; 2794 let Inst{25} = 1; 2795 let Inst{23} = offset{12}; 2796 let Inst{21} = 1; // overwrite 2797 let Inst{19-16} = addr; 2798 let Inst{11-5} = offset{11-5}; 2799 let Inst{4} = 0; 2800 let Inst{3-0} = offset{3-0}; 2801 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2802} 2803 2804def LDRT_POST_IMM 2805 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2806 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2807 IndexModePost, LdFrm, IIC_iLoad_ru, 2808 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2809 // {12} isAdd 2810 // {11-0} imm12/Rm 2811 bits<14> offset; 2812 bits<4> addr; 2813 let Inst{25} = 0; 2814 let Inst{23} = offset{12}; 2815 let Inst{21} = 1; // overwrite 2816 let Inst{19-16} = addr; 2817 let Inst{11-0} = offset{11-0}; 2818 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2819} 2820 2821def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2822 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2823 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2824 "ldrbt", "\t$Rt, $addr, $offset", 2825 "$addr.base = $Rn_wb", []> { 2826 // {12} isAdd 2827 // {11-0} imm12/Rm 2828 bits<14> offset; 2829 bits<4> addr; 2830 let Inst{25} = 1; 2831 let Inst{23} = offset{12}; 2832 let Inst{21} = 1; // overwrite 2833 let Inst{19-16} = addr; 2834 let Inst{11-5} = offset{11-5}; 2835 let Inst{4} = 0; 2836 let Inst{3-0} = offset{3-0}; 2837 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2838} 2839 2840def LDRBT_POST_IMM 2841 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2842 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2843 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2844 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2845 // {12} isAdd 2846 // {11-0} imm12/Rm 2847 bits<14> offset; 2848 bits<4> addr; 2849 let Inst{25} = 0; 2850 let Inst{23} = offset{12}; 2851 let Inst{21} = 1; // overwrite 2852 let Inst{19-16} = addr; 2853 let Inst{11-0} = offset{11-0}; 2854 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2855} 2856 2857multiclass AI3ldrT<bits<4> op, string opc> { 2858 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 2859 (ins addr_offset_none:$addr, postidx_imm8:$offset), 2860 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2861 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2862 bits<9> offset; 2863 let Inst{23} = offset{8}; 2864 let Inst{22} = 1; 2865 let Inst{11-8} = offset{7-4}; 2866 let Inst{3-0} = offset{3-0}; 2867 } 2868 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 2869 (ins addr_offset_none:$addr, postidx_reg:$Rm), 2870 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2871 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2872 bits<5> Rm; 2873 let Inst{23} = Rm{4}; 2874 let Inst{22} = 0; 2875 let Inst{11-8} = 0; 2876 let Unpredictable{11-8} = 0b1111; 2877 let Inst{3-0} = Rm{3-0}; 2878 let DecoderMethod = "DecodeLDR"; 2879 } 2880} 2881 2882defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 2883defm LDRHT : AI3ldrT<0b1011, "ldrht">; 2884defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 2885} 2886 2887def LDRT_POST 2888 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2889 (outs GPR:$Rt)>; 2890 2891def LDRBT_POST 2892 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2893 (outs GPR:$Rt)>; 2894 2895// Pseudo instruction ldr Rt, =immediate 2896def LDRConstPool 2897 : ARMAsmPseudo<"ldr${q} $Rt, $immediate", 2898 (ins const_pool_asm_imm:$immediate, pred:$q), 2899 (outs GPR:$Rt)>; 2900 2901// Store 2902 2903// Stores with truncate 2904def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 2905 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 2906 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 2907 2908// Store doubleword 2909let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 2910 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 2911 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, 2912 Requires<[IsARM, HasV5TE]> { 2913 let Inst{21} = 0; 2914 } 2915} 2916 2917// Indexed stores 2918multiclass AI2_stridx<bit isByte, string opc, 2919 InstrItinClass iii, InstrItinClass iir> { 2920 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2921 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 2922 StFrm, iii, 2923 opc, "\t$Rt, $addr!", 2924 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2925 bits<17> addr; 2926 let Inst{25} = 0; 2927 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2928 let Inst{19-16} = addr{16-13}; // Rn 2929 let Inst{11-0} = addr{11-0}; // imm12 2930 let DecoderMethod = "DecodeSTRPreImm"; 2931 } 2932 2933 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2934 (ins GPR:$Rt, ldst_so_reg:$addr), 2935 IndexModePre, StFrm, iir, 2936 opc, "\t$Rt, $addr!", 2937 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2938 bits<17> addr; 2939 let Inst{25} = 1; 2940 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2941 let Inst{19-16} = addr{16-13}; // Rn 2942 let Inst{11-0} = addr{11-0}; 2943 let Inst{4} = 0; // Inst{4} = 0 2944 let DecoderMethod = "DecodeSTRPreReg"; 2945 } 2946 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2947 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2948 IndexModePost, StFrm, iir, 2949 opc, "\t$Rt, $addr, $offset", 2950 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2951 // {12} isAdd 2952 // {11-0} imm12/Rm 2953 bits<14> offset; 2954 bits<4> addr; 2955 let Inst{25} = 1; 2956 let Inst{23} = offset{12}; 2957 let Inst{19-16} = addr; 2958 let Inst{11-0} = offset{11-0}; 2959 let Inst{4} = 0; 2960 2961 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2962 } 2963 2964 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2965 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2966 IndexModePost, StFrm, iii, 2967 opc, "\t$Rt, $addr, $offset", 2968 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2969 // {12} isAdd 2970 // {11-0} imm12/Rm 2971 bits<14> offset; 2972 bits<4> addr; 2973 let Inst{25} = 0; 2974 let Inst{23} = offset{12}; 2975 let Inst{19-16} = addr; 2976 let Inst{11-0} = offset{11-0}; 2977 2978 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2979 } 2980} 2981 2982let mayStore = 1, hasSideEffects = 0 in { 2983// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or 2984// IIC_iStore_siu depending on whether it the offset register is shifted. 2985defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 2986defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 2987} 2988 2989def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2990 am2offset_reg:$offset), 2991 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 2992 am2offset_reg:$offset)>; 2993def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2994 am2offset_imm:$offset), 2995 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2996 am2offset_imm:$offset)>; 2997def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2998 am2offset_reg:$offset), 2999 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 3000 am2offset_reg:$offset)>; 3001def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3002 am2offset_imm:$offset), 3003 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3004 am2offset_imm:$offset)>; 3005 3006// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 3007// put the patterns on the instruction definitions directly as ISel wants 3008// the address base and offset to be separate operands, not a single 3009// complex operand like we represent the instructions themselves. The 3010// pseudos map between the two. 3011let usesCustomInserter = 1, 3012 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 3013def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3014 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3015 4, IIC_iStore_ru, 3016 [(set GPR:$Rn_wb, 3017 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3018def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3019 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3020 4, IIC_iStore_ru, 3021 [(set GPR:$Rn_wb, 3022 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3023def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3024 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3025 4, IIC_iStore_ru, 3026 [(set GPR:$Rn_wb, 3027 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3028def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3029 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3030 4, IIC_iStore_ru, 3031 [(set GPR:$Rn_wb, 3032 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3033def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3034 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 3035 4, IIC_iStore_ru, 3036 [(set GPR:$Rn_wb, 3037 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 3038} 3039 3040 3041 3042def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 3043 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 3044 StMiscFrm, IIC_iStore_bh_ru, 3045 "strh", "\t$Rt, $addr!", 3046 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3047 bits<14> addr; 3048 let Inst{23} = addr{8}; // U bit 3049 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3050 let Inst{19-16} = addr{12-9}; // Rn 3051 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3052 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3053 let DecoderMethod = "DecodeAddrMode3Instruction"; 3054} 3055 3056def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 3057 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 3058 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 3059 "strh", "\t$Rt, $addr, $offset", 3060 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", 3061 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 3062 addr_offset_none:$addr, 3063 am3offset:$offset))]> { 3064 bits<10> offset; 3065 bits<4> addr; 3066 let Inst{23} = offset{8}; // U bit 3067 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3068 let Inst{19-16} = addr; 3069 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3070 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3071 let DecoderMethod = "DecodeAddrMode3Instruction"; 3072} 3073 3074let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 3075def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 3076 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 3077 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 3078 "strd", "\t$Rt, $Rt2, $addr!", 3079 "$addr.base = $Rn_wb", []> { 3080 bits<14> addr; 3081 let Inst{23} = addr{8}; // U bit 3082 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3083 let Inst{19-16} = addr{12-9}; // Rn 3084 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3085 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3086 let DecoderMethod = "DecodeAddrMode3Instruction"; 3087} 3088 3089def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 3090 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 3091 am3offset:$offset), 3092 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 3093 "strd", "\t$Rt, $Rt2, $addr, $offset", 3094 "$addr.base = $Rn_wb", []> { 3095 bits<10> offset; 3096 bits<4> addr; 3097 let Inst{23} = offset{8}; // U bit 3098 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3099 let Inst{19-16} = addr; 3100 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3101 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3102 let DecoderMethod = "DecodeAddrMode3Instruction"; 3103} 3104} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 3105 3106// STRT, STRBT, and STRHT 3107 3108def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3109 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3110 IndexModePost, StFrm, IIC_iStore_bh_ru, 3111 "strbt", "\t$Rt, $addr, $offset", 3112 "$addr.base = $Rn_wb", []> { 3113 // {12} isAdd 3114 // {11-0} imm12/Rm 3115 bits<14> offset; 3116 bits<4> addr; 3117 let Inst{25} = 1; 3118 let Inst{23} = offset{12}; 3119 let Inst{21} = 1; // overwrite 3120 let Inst{19-16} = addr; 3121 let Inst{11-5} = offset{11-5}; 3122 let Inst{4} = 0; 3123 let Inst{3-0} = offset{3-0}; 3124 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3125} 3126 3127def STRBT_POST_IMM 3128 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3129 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3130 IndexModePost, StFrm, IIC_iStore_bh_ru, 3131 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3132 // {12} isAdd 3133 // {11-0} imm12/Rm 3134 bits<14> offset; 3135 bits<4> addr; 3136 let Inst{25} = 0; 3137 let Inst{23} = offset{12}; 3138 let Inst{21} = 1; // overwrite 3139 let Inst{19-16} = addr; 3140 let Inst{11-0} = offset{11-0}; 3141 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3142} 3143 3144def STRBT_POST 3145 : ARMAsmPseudo<"strbt${q} $Rt, $addr", 3146 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3147 3148let mayStore = 1, hasSideEffects = 0 in { 3149def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3150 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3151 IndexModePost, StFrm, IIC_iStore_ru, 3152 "strt", "\t$Rt, $addr, $offset", 3153 "$addr.base = $Rn_wb", []> { 3154 // {12} isAdd 3155 // {11-0} imm12/Rm 3156 bits<14> offset; 3157 bits<4> addr; 3158 let Inst{25} = 1; 3159 let Inst{23} = offset{12}; 3160 let Inst{21} = 1; // overwrite 3161 let Inst{19-16} = addr; 3162 let Inst{11-5} = offset{11-5}; 3163 let Inst{4} = 0; 3164 let Inst{3-0} = offset{3-0}; 3165 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3166} 3167 3168def STRT_POST_IMM 3169 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3170 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3171 IndexModePost, StFrm, IIC_iStore_ru, 3172 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3173 // {12} isAdd 3174 // {11-0} imm12/Rm 3175 bits<14> offset; 3176 bits<4> addr; 3177 let Inst{25} = 0; 3178 let Inst{23} = offset{12}; 3179 let Inst{21} = 1; // overwrite 3180 let Inst{19-16} = addr; 3181 let Inst{11-0} = offset{11-0}; 3182 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3183} 3184} 3185 3186def STRT_POST 3187 : ARMAsmPseudo<"strt${q} $Rt, $addr", 3188 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3189 3190multiclass AI3strT<bits<4> op, string opc> { 3191 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3192 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 3193 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3194 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 3195 bits<9> offset; 3196 let Inst{23} = offset{8}; 3197 let Inst{22} = 1; 3198 let Inst{11-8} = offset{7-4}; 3199 let Inst{3-0} = offset{3-0}; 3200 } 3201 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3202 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 3203 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3204 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 3205 bits<5> Rm; 3206 let Inst{23} = Rm{4}; 3207 let Inst{22} = 0; 3208 let Inst{11-8} = 0; 3209 let Inst{3-0} = Rm{3-0}; 3210 } 3211} 3212 3213 3214defm STRHT : AI3strT<0b1011, "strht">; 3215 3216def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3217 NoItinerary, "stl", "\t$Rt, $addr", []>; 3218def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3219 NoItinerary, "stlb", "\t$Rt, $addr", []>; 3220def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3221 NoItinerary, "stlh", "\t$Rt, $addr", []>; 3222 3223//===----------------------------------------------------------------------===// 3224// Load / store multiple Instructions. 3225// 3226 3227multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 3228 InstrItinClass itin, InstrItinClass itin_upd> { 3229 // IA is the default, so no need for an explicit suffix on the 3230 // mnemonic here. Without it is the canonical spelling. 3231 def IA : 3232 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3233 IndexModeNone, f, itin, 3234 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 3235 let Inst{24-23} = 0b01; // Increment After 3236 let Inst{22} = P_bit; 3237 let Inst{21} = 0; // No writeback 3238 let Inst{20} = L_bit; 3239 } 3240 def IA_UPD : 3241 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3242 IndexModeUpd, f, itin_upd, 3243 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3244 let Inst{24-23} = 0b01; // Increment After 3245 let Inst{22} = P_bit; 3246 let Inst{21} = 1; // Writeback 3247 let Inst{20} = L_bit; 3248 3249 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3250 } 3251 def DA : 3252 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3253 IndexModeNone, f, itin, 3254 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 3255 let Inst{24-23} = 0b00; // Decrement After 3256 let Inst{22} = P_bit; 3257 let Inst{21} = 0; // No writeback 3258 let Inst{20} = L_bit; 3259 } 3260 def DA_UPD : 3261 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3262 IndexModeUpd, f, itin_upd, 3263 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3264 let Inst{24-23} = 0b00; // Decrement After 3265 let Inst{22} = P_bit; 3266 let Inst{21} = 1; // Writeback 3267 let Inst{20} = L_bit; 3268 3269 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3270 } 3271 def DB : 3272 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3273 IndexModeNone, f, itin, 3274 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 3275 let Inst{24-23} = 0b10; // Decrement Before 3276 let Inst{22} = P_bit; 3277 let Inst{21} = 0; // No writeback 3278 let Inst{20} = L_bit; 3279 } 3280 def DB_UPD : 3281 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3282 IndexModeUpd, f, itin_upd, 3283 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3284 let Inst{24-23} = 0b10; // Decrement Before 3285 let Inst{22} = P_bit; 3286 let Inst{21} = 1; // Writeback 3287 let Inst{20} = L_bit; 3288 3289 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3290 } 3291 def IB : 3292 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3293 IndexModeNone, f, itin, 3294 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 3295 let Inst{24-23} = 0b11; // Increment Before 3296 let Inst{22} = P_bit; 3297 let Inst{21} = 0; // No writeback 3298 let Inst{20} = L_bit; 3299 } 3300 def IB_UPD : 3301 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3302 IndexModeUpd, f, itin_upd, 3303 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3304 let Inst{24-23} = 0b11; // Increment Before 3305 let Inst{22} = P_bit; 3306 let Inst{21} = 1; // Writeback 3307 let Inst{20} = L_bit; 3308 3309 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3310 } 3311} 3312 3313let hasSideEffects = 0 in { 3314 3315let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in 3316defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 3317 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">; 3318 3319let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3320defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 3321 IIC_iStore_mu>, 3322 ComplexDeprecationPredicate<"ARMStore">; 3323 3324} // hasSideEffects 3325 3326// FIXME: remove when we have a way to marking a MI with these properties. 3327// FIXME: Should pc be an implicit operand like PICADD, etc? 3328let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3329 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3330def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3331 reglist:$regs, variable_ops), 3332 4, IIC_iLoad_mBr, [], 3333 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3334 RegConstraint<"$Rn = $wb">; 3335 3336let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3337defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 3338 IIC_iLoad_mu>; 3339 3340let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3341defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 3342 IIC_iStore_mu>; 3343 3344 3345 3346//===----------------------------------------------------------------------===// 3347// Move Instructions. 3348// 3349 3350let hasSideEffects = 0, isMoveReg = 1 in 3351def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 3352 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3353 bits<4> Rd; 3354 bits<4> Rm; 3355 3356 let Inst{19-16} = 0b0000; 3357 let Inst{11-4} = 0b00000000; 3358 let Inst{25} = 0; 3359 let Inst{3-0} = Rm; 3360 let Inst{15-12} = Rd; 3361} 3362 3363// A version for the smaller set of tail call registers. 3364let hasSideEffects = 0 in 3365def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 3366 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3367 bits<4> Rd; 3368 bits<4> Rm; 3369 3370 let Inst{11-4} = 0b00000000; 3371 let Inst{25} = 0; 3372 let Inst{3-0} = Rm; 3373 let Inst{15-12} = Rd; 3374} 3375 3376def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 3377 DPSoRegRegFrm, IIC_iMOVsr, 3378 "mov", "\t$Rd, $src", 3379 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 3380 Sched<[WriteALU]> { 3381 bits<4> Rd; 3382 bits<12> src; 3383 let Inst{15-12} = Rd; 3384 let Inst{19-16} = 0b0000; 3385 let Inst{11-8} = src{11-8}; 3386 let Inst{7} = 0; 3387 let Inst{6-5} = src{6-5}; 3388 let Inst{4} = 1; 3389 let Inst{3-0} = src{3-0}; 3390 let Inst{25} = 0; 3391} 3392 3393def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3394 DPSoRegImmFrm, IIC_iMOVsr, 3395 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3396 UnaryDP, Sched<[WriteALU]> { 3397 bits<4> Rd; 3398 bits<12> src; 3399 let Inst{15-12} = Rd; 3400 let Inst{19-16} = 0b0000; 3401 let Inst{11-5} = src{11-5}; 3402 let Inst{4} = 0; 3403 let Inst{3-0} = src{3-0}; 3404 let Inst{25} = 0; 3405} 3406 3407let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3408def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi, 3409 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP, 3410 Sched<[WriteALU]> { 3411 bits<4> Rd; 3412 bits<12> imm; 3413 let Inst{25} = 1; 3414 let Inst{15-12} = Rd; 3415 let Inst{19-16} = 0b0000; 3416 let Inst{11-0} = imm; 3417} 3418 3419let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3420def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3421 DPFrm, IIC_iMOVi, 3422 "movw", "\t$Rd, $imm", 3423 [(set GPR:$Rd, imm0_65535:$imm)]>, 3424 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3425 bits<4> Rd; 3426 bits<16> imm; 3427 let Inst{15-12} = Rd; 3428 let Inst{11-0} = imm{11-0}; 3429 let Inst{19-16} = imm{15-12}; 3430 let Inst{20} = 0; 3431 let Inst{25} = 1; 3432 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3433} 3434 3435def : InstAlias<"mov${p} $Rd, $imm", 3436 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>, 3437 Requires<[IsARM, HasV6T2]>; 3438 3439def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3440 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3441 Sched<[WriteALU]>; 3442 3443let Constraints = "$src = $Rd" in { 3444def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3445 (ins GPR:$src, imm0_65535_expr:$imm), 3446 DPFrm, IIC_iMOVi, 3447 "movt", "\t$Rd, $imm", 3448 [(set GPRnopc:$Rd, 3449 (or (and GPR:$src, 0xffff), 3450 lo16AllZero:$imm))]>, UnaryDP, 3451 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3452 bits<4> Rd; 3453 bits<16> imm; 3454 let Inst{15-12} = Rd; 3455 let Inst{11-0} = imm{11-0}; 3456 let Inst{19-16} = imm{15-12}; 3457 let Inst{20} = 0; 3458 let Inst{25} = 1; 3459 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3460} 3461 3462def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3463 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3464 Sched<[WriteALU]>; 3465 3466} // Constraints 3467 3468def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3469 Requires<[IsARM, HasV6T2]>; 3470 3471let Uses = [CPSR] in 3472def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3473 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3474 Requires<[IsARM]>, Sched<[WriteALU]>; 3475 3476// These aren't really mov instructions, but we have to define them this way 3477// due to flag operands. 3478 3479let Defs = [CPSR] in { 3480def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3481 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3482 Sched<[WriteALU]>, Requires<[IsARM]>; 3483def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3484 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3485 Sched<[WriteALU]>, Requires<[IsARM]>; 3486} 3487 3488//===----------------------------------------------------------------------===// 3489// Extend Instructions. 3490// 3491 3492// Sign extenders 3493 3494def SXTB : AI_ext_rrot<0b01101010, 3495 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3496def SXTH : AI_ext_rrot<0b01101011, 3497 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3498 3499def SXTAB : AI_exta_rrot<0b01101010, 3500 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3501def SXTAH : AI_exta_rrot<0b01101011, 3502 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3503 3504def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)), 3505 (SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3506def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), 3507 i16)), 3508 (SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3509 3510def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3511def : ARMV6Pat<(int_arm_sxtb16 GPR:$Src), 3512 (SXTB16 GPR:$Src, 0)>; 3513def : ARMV6Pat<(int_arm_sxtb16 (rotr GPR:$Src, rot_imm:$rot)), 3514 (SXTB16 GPR:$Src, rot_imm:$rot)>; 3515 3516def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3517def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, GPR:$RHS), 3518 (SXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3519def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)), 3520 (SXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>; 3521 3522// Zero extenders 3523 3524let AddedComplexity = 16 in { 3525def UXTB : AI_ext_rrot<0b01101110, 3526 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3527def UXTH : AI_ext_rrot<0b01101111, 3528 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3529def UXTB16 : AI_ext_rrot<0b01101100, 3530 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3531 3532// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3533// The transformation should probably be done as a combiner action 3534// instead so we can include a check for masking back in the upper 3535// eight bits of the source into the lower eight bits of the result. 3536//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3537// (UXTB16r_rot GPR:$Src, 3)>; 3538def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3539 (UXTB16 GPR:$Src, 1)>; 3540def : ARMV6Pat<(int_arm_uxtb16 GPR:$Src), 3541 (UXTB16 GPR:$Src, 0)>; 3542def : ARMV6Pat<(int_arm_uxtb16 (rotr GPR:$Src, rot_imm:$rot)), 3543 (UXTB16 GPR:$Src, rot_imm:$rot)>; 3544 3545def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3546 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3547def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3548 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3549 3550def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)), 3551 (UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3552def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)), 3553 (UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3554} 3555 3556// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3557def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3558def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, GPR:$RHS), 3559 (UXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3560def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)), 3561 (UXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>; 3562 3563 3564def SBFX : I<(outs GPRnopc:$Rd), 3565 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3566 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3567 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3568 Requires<[IsARM, HasV6T2]> { 3569 bits<4> Rd; 3570 bits<4> Rn; 3571 bits<5> lsb; 3572 bits<5> width; 3573 let Inst{27-21} = 0b0111101; 3574 let Inst{6-4} = 0b101; 3575 let Inst{20-16} = width; 3576 let Inst{15-12} = Rd; 3577 let Inst{11-7} = lsb; 3578 let Inst{3-0} = Rn; 3579} 3580 3581def UBFX : I<(outs GPRnopc:$Rd), 3582 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3583 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3584 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3585 Requires<[IsARM, HasV6T2]> { 3586 bits<4> Rd; 3587 bits<4> Rn; 3588 bits<5> lsb; 3589 bits<5> width; 3590 let Inst{27-21} = 0b0111111; 3591 let Inst{6-4} = 0b101; 3592 let Inst{20-16} = width; 3593 let Inst{15-12} = Rd; 3594 let Inst{11-7} = lsb; 3595 let Inst{3-0} = Rn; 3596} 3597 3598//===----------------------------------------------------------------------===// 3599// Arithmetic Instructions. 3600// 3601 3602let isAdd = 1 in 3603defm ADD : AsI1_bin_irs<0b0100, "add", 3604 IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>; 3605defm SUB : AsI1_bin_irs<0b0010, "sub", 3606 IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>; 3607 3608// ADD and SUB with 's' bit set. 3609// 3610// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3611// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3612// AdjustInstrPostInstrSelection where we determine whether or not to 3613// set the "s" bit based on CPSR liveness. 3614// 3615// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3616// support for an optional CPSR definition that corresponds to the DAG 3617// node's second value. We can then eliminate the implicit def of CPSR. 3618let isAdd = 1 in 3619defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>; 3620defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3621 3622def : ARMPat<(ARMsubs GPR:$Rn, mod_imm:$imm), (SUBSri $Rn, mod_imm:$imm)>; 3623def : ARMPat<(ARMsubs GPR:$Rn, GPR:$Rm), (SUBSrr $Rn, $Rm)>; 3624def : ARMPat<(ARMsubs GPR:$Rn, so_reg_imm:$shift), 3625 (SUBSrsi $Rn, so_reg_imm:$shift)>; 3626def : ARMPat<(ARMsubs GPR:$Rn, so_reg_reg:$shift), 3627 (SUBSrsr $Rn, so_reg_reg:$shift)>; 3628 3629 3630let isAdd = 1 in 3631defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>; 3632defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>; 3633 3634defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3635 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3636 sub>; 3637 3638// FIXME: Eliminate them if we can write def : Pat patterns which defines 3639// CPSR and the implicit def of CPSR is not needed. 3640defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3641 3642defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>; 3643 3644// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3645// The assume-no-carry-in form uses the negation of the input since add/sub 3646// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3647// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3648// details. 3649def : ARMPat<(add GPR:$src, mod_imm_neg:$imm), 3650 (SUBri GPR:$src, mod_imm_neg:$imm)>; 3651def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm), 3652 (SUBSri GPR:$src, mod_imm_neg:$imm)>; 3653 3654def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3655 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3656 Requires<[IsARM, HasV6T2]>; 3657def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3658 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3659 Requires<[IsARM, HasV6T2]>; 3660 3661// The with-carry-in form matches bitwise not instead of the negation. 3662// Effectively, the inverse interpretation of the carry flag already accounts 3663// for part of the negation. 3664def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR), 3665 (SBCri GPR:$src, mod_imm_not:$imm)>; 3666def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3667 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>, 3668 Requires<[IsARM, HasV6T2]>; 3669 3670// Note: These are implemented in C++ code, because they have to generate 3671// ADD/SUBrs instructions, which use a complex pattern that a xform function 3672// cannot produce. 3673// (mul X, 2^n+1) -> (add (X << n), X) 3674// (mul X, 2^n-1) -> (rsb X, (X << n)) 3675 3676// ARM Arithmetic Instruction 3677// GPR:$dst = GPR:$a op GPR:$b 3678class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3679 list<dag> pattern = [], 3680 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3681 string asm = "\t$Rd, $Rn, $Rm"> 3682 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3683 Sched<[WriteALU, ReadALU, ReadALU]> { 3684 bits<4> Rn; 3685 bits<4> Rd; 3686 bits<4> Rm; 3687 let Inst{27-20} = op27_20; 3688 let Inst{11-4} = op11_4; 3689 let Inst{19-16} = Rn; 3690 let Inst{15-12} = Rd; 3691 let Inst{3-0} = Rm; 3692 3693 let Unpredictable{11-8} = 0b1111; 3694} 3695 3696// Wrappers around the AAI class 3697class AAIRevOpr<bits<8> op27_20, bits<8> op11_4, string opc, 3698 list<dag> pattern = []> 3699 : AAI<op27_20, op11_4, opc, 3700 pattern, 3701 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3702 "\t$Rd, $Rm, $Rn">; 3703 3704class AAIIntrinsic<bits<8> op27_20, bits<8> op11_4, string opc, 3705 Intrinsic intrinsic> 3706 : AAI<op27_20, op11_4, opc, 3707 [(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>; 3708 3709// Saturating add/subtract 3710let hasSideEffects = 1 in { 3711def QADD8 : AAIIntrinsic<0b01100010, 0b11111001, "qadd8", int_arm_qadd8>; 3712def QADD16 : AAIIntrinsic<0b01100010, 0b11110001, "qadd16", int_arm_qadd16>; 3713def QSUB16 : AAIIntrinsic<0b01100010, 0b11110111, "qsub16", int_arm_qsub16>; 3714def QSUB8 : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>; 3715 3716def QDADD : AAIRevOpr<0b00010100, 0b00000101, "qdadd", 3717 [(set GPRnopc:$Rd, (int_arm_qadd (int_arm_qadd GPRnopc:$Rm, 3718 GPRnopc:$Rm), 3719 GPRnopc:$Rn))]>; 3720def QDSUB : AAIRevOpr<0b00010110, 0b00000101, "qdsub", 3721 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, 3722 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>; 3723def QSUB : AAIRevOpr<0b00010010, 0b00000101, "qsub", 3724 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>; 3725let DecoderMethod = "DecodeQADDInstruction" in 3726 def QADD : AAIRevOpr<0b00010000, 0b00000101, "qadd", 3727 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>; 3728} 3729 3730def UQADD16 : AAIIntrinsic<0b01100110, 0b11110001, "uqadd16", int_arm_uqadd16>; 3731def UQADD8 : AAIIntrinsic<0b01100110, 0b11111001, "uqadd8", int_arm_uqadd8>; 3732def UQSUB16 : AAIIntrinsic<0b01100110, 0b11110111, "uqsub16", int_arm_uqsub16>; 3733def UQSUB8 : AAIIntrinsic<0b01100110, 0b11111111, "uqsub8", int_arm_uqsub8>; 3734def QASX : AAIIntrinsic<0b01100010, 0b11110011, "qasx", int_arm_qasx>; 3735def QSAX : AAIIntrinsic<0b01100010, 0b11110101, "qsax", int_arm_qsax>; 3736def UQASX : AAIIntrinsic<0b01100110, 0b11110011, "uqasx", int_arm_uqasx>; 3737def UQSAX : AAIIntrinsic<0b01100110, 0b11110101, "uqsax", int_arm_uqsax>; 3738 3739// Signed/Unsigned add/subtract 3740 3741def SASX : AAIIntrinsic<0b01100001, 0b11110011, "sasx", int_arm_sasx>; 3742def SADD16 : AAIIntrinsic<0b01100001, 0b11110001, "sadd16", int_arm_sadd16>; 3743def SADD8 : AAIIntrinsic<0b01100001, 0b11111001, "sadd8", int_arm_sadd8>; 3744def SSAX : AAIIntrinsic<0b01100001, 0b11110101, "ssax", int_arm_ssax>; 3745def SSUB16 : AAIIntrinsic<0b01100001, 0b11110111, "ssub16", int_arm_ssub16>; 3746def SSUB8 : AAIIntrinsic<0b01100001, 0b11111111, "ssub8", int_arm_ssub8>; 3747def UASX : AAIIntrinsic<0b01100101, 0b11110011, "uasx", int_arm_uasx>; 3748def UADD16 : AAIIntrinsic<0b01100101, 0b11110001, "uadd16", int_arm_uadd16>; 3749def UADD8 : AAIIntrinsic<0b01100101, 0b11111001, "uadd8", int_arm_uadd8>; 3750def USAX : AAIIntrinsic<0b01100101, 0b11110101, "usax", int_arm_usax>; 3751def USUB16 : AAIIntrinsic<0b01100101, 0b11110111, "usub16", int_arm_usub16>; 3752def USUB8 : AAIIntrinsic<0b01100101, 0b11111111, "usub8", int_arm_usub8>; 3753 3754// Signed/Unsigned halving add/subtract 3755 3756def SHASX : AAIIntrinsic<0b01100011, 0b11110011, "shasx", int_arm_shasx>; 3757def SHADD16 : AAIIntrinsic<0b01100011, 0b11110001, "shadd16", int_arm_shadd16>; 3758def SHADD8 : AAIIntrinsic<0b01100011, 0b11111001, "shadd8", int_arm_shadd8>; 3759def SHSAX : AAIIntrinsic<0b01100011, 0b11110101, "shsax", int_arm_shsax>; 3760def SHSUB16 : AAIIntrinsic<0b01100011, 0b11110111, "shsub16", int_arm_shsub16>; 3761def SHSUB8 : AAIIntrinsic<0b01100011, 0b11111111, "shsub8", int_arm_shsub8>; 3762def UHASX : AAIIntrinsic<0b01100111, 0b11110011, "uhasx", int_arm_uhasx>; 3763def UHADD16 : AAIIntrinsic<0b01100111, 0b11110001, "uhadd16", int_arm_uhadd16>; 3764def UHADD8 : AAIIntrinsic<0b01100111, 0b11111001, "uhadd8", int_arm_uhadd8>; 3765def UHSAX : AAIIntrinsic<0b01100111, 0b11110101, "uhsax", int_arm_uhsax>; 3766def UHSUB16 : AAIIntrinsic<0b01100111, 0b11110111, "uhsub16", int_arm_uhsub16>; 3767def UHSUB8 : AAIIntrinsic<0b01100111, 0b11111111, "uhsub8", int_arm_uhsub8>; 3768 3769// Unsigned Sum of Absolute Differences [and Accumulate]. 3770 3771def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3772 MulFrm /* for convenience */, NoItinerary, "usad8", 3773 "\t$Rd, $Rn, $Rm", 3774 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>, 3775 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 3776 bits<4> Rd; 3777 bits<4> Rn; 3778 bits<4> Rm; 3779 let Inst{27-20} = 0b01111000; 3780 let Inst{15-12} = 0b1111; 3781 let Inst{7-4} = 0b0001; 3782 let Inst{19-16} = Rd; 3783 let Inst{11-8} = Rm; 3784 let Inst{3-0} = Rn; 3785} 3786def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3787 MulFrm /* for convenience */, NoItinerary, "usada8", 3788 "\t$Rd, $Rn, $Rm, $Ra", 3789 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 3790 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 3791 bits<4> Rd; 3792 bits<4> Rn; 3793 bits<4> Rm; 3794 bits<4> Ra; 3795 let Inst{27-20} = 0b01111000; 3796 let Inst{7-4} = 0b0001; 3797 let Inst{19-16} = Rd; 3798 let Inst{15-12} = Ra; 3799 let Inst{11-8} = Rm; 3800 let Inst{3-0} = Rn; 3801} 3802 3803// Signed/Unsigned saturate 3804def SSAT : AI<(outs GPRnopc:$Rd), 3805 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3806 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>, 3807 Requires<[IsARM,HasV6]>{ 3808 bits<4> Rd; 3809 bits<5> sat_imm; 3810 bits<4> Rn; 3811 bits<8> sh; 3812 let Inst{27-21} = 0b0110101; 3813 let Inst{5-4} = 0b01; 3814 let Inst{20-16} = sat_imm; 3815 let Inst{15-12} = Rd; 3816 let Inst{11-7} = sh{4-0}; 3817 let Inst{6} = sh{5}; 3818 let Inst{3-0} = Rn; 3819} 3820 3821def SSAT16 : AI<(outs GPRnopc:$Rd), 3822 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 3823 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>, 3824 Requires<[IsARM,HasV6]>{ 3825 bits<4> Rd; 3826 bits<4> sat_imm; 3827 bits<4> Rn; 3828 let Inst{27-20} = 0b01101010; 3829 let Inst{11-4} = 0b11110011; 3830 let Inst{15-12} = Rd; 3831 let Inst{19-16} = sat_imm; 3832 let Inst{3-0} = Rn; 3833} 3834 3835def USAT : AI<(outs GPRnopc:$Rd), 3836 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3837 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>, 3838 Requires<[IsARM,HasV6]> { 3839 bits<4> Rd; 3840 bits<5> sat_imm; 3841 bits<4> Rn; 3842 bits<8> sh; 3843 let Inst{27-21} = 0b0110111; 3844 let Inst{5-4} = 0b01; 3845 let Inst{15-12} = Rd; 3846 let Inst{11-7} = sh{4-0}; 3847 let Inst{6} = sh{5}; 3848 let Inst{20-16} = sat_imm; 3849 let Inst{3-0} = Rn; 3850} 3851 3852def USAT16 : AI<(outs GPRnopc:$Rd), 3853 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 3854 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>, 3855 Requires<[IsARM,HasV6]>{ 3856 bits<4> Rd; 3857 bits<4> sat_imm; 3858 bits<4> Rn; 3859 let Inst{27-20} = 0b01101110; 3860 let Inst{11-4} = 0b11110011; 3861 let Inst{15-12} = Rd; 3862 let Inst{19-16} = sat_imm; 3863 let Inst{3-0} = Rn; 3864} 3865 3866def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos), 3867 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>; 3868def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos), 3869 (USAT imm0_31:$pos, GPRnopc:$a, 0)>; 3870def : ARMPat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm), 3871 (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 3872def : ARMPat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm), 3873 (USAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 3874def : ARMV6Pat<(int_arm_ssat16 GPRnopc:$a, imm1_16:$pos), 3875 (SSAT16 imm1_16:$pos, GPRnopc:$a)>; 3876def : ARMV6Pat<(int_arm_usat16 GPRnopc:$a, imm0_15:$pos), 3877 (USAT16 imm0_15:$pos, GPRnopc:$a)>; 3878 3879//===----------------------------------------------------------------------===// 3880// Bitwise Instructions. 3881// 3882 3883defm AND : AsI1_bin_irs<0b0000, "and", 3884 IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>; 3885defm ORR : AsI1_bin_irs<0b1100, "orr", 3886 IIC_iBITi, IIC_iBITr, IIC_iBITsr, or, 1>; 3887defm EOR : AsI1_bin_irs<0b0001, "eor", 3888 IIC_iBITi, IIC_iBITr, IIC_iBITsr, xor, 1>; 3889defm BIC : AsI1_bin_irs<0b1110, "bic", 3890 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3891 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 3892 3893// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 3894// like in the actual instruction encoding. The complexity of mapping the mask 3895// to the lsb/msb pair should be handled by ISel, not encapsulated in the 3896// instruction description. 3897def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 3898 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3899 "bfc", "\t$Rd, $imm", "$src = $Rd", 3900 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 3901 Requires<[IsARM, HasV6T2]> { 3902 bits<4> Rd; 3903 bits<10> imm; 3904 let Inst{27-21} = 0b0111110; 3905 let Inst{6-0} = 0b0011111; 3906 let Inst{15-12} = Rd; 3907 let Inst{11-7} = imm{4-0}; // lsb 3908 let Inst{20-16} = imm{9-5}; // msb 3909} 3910 3911// A8.6.18 BFI - Bitfield insert (Encoding A1) 3912def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 3913 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3914 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 3915 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 3916 bf_inv_mask_imm:$imm))]>, 3917 Requires<[IsARM, HasV6T2]> { 3918 bits<4> Rd; 3919 bits<4> Rn; 3920 bits<10> imm; 3921 let Inst{27-21} = 0b0111110; 3922 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 3923 let Inst{15-12} = Rd; 3924 let Inst{11-7} = imm{4-0}; // lsb 3925 let Inst{20-16} = imm{9-5}; // width 3926 let Inst{3-0} = Rn; 3927} 3928 3929def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 3930 "mvn", "\t$Rd, $Rm", 3931 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 3932 bits<4> Rd; 3933 bits<4> Rm; 3934 let Inst{25} = 0; 3935 let Inst{19-16} = 0b0000; 3936 let Inst{11-4} = 0b00000000; 3937 let Inst{15-12} = Rd; 3938 let Inst{3-0} = Rm; 3939 3940 let Unpredictable{19-16} = 0b1111; 3941} 3942def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 3943 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3944 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 3945 Sched<[WriteALU]> { 3946 bits<4> Rd; 3947 bits<12> shift; 3948 let Inst{25} = 0; 3949 let Inst{19-16} = 0b0000; 3950 let Inst{15-12} = Rd; 3951 let Inst{11-5} = shift{11-5}; 3952 let Inst{4} = 0; 3953 let Inst{3-0} = shift{3-0}; 3954 3955 let Unpredictable{19-16} = 0b1111; 3956} 3957def MVNsr : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift), 3958 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3959 [(set GPRnopc:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 3960 Sched<[WriteALU]> { 3961 bits<4> Rd; 3962 bits<12> shift; 3963 let Inst{25} = 0; 3964 let Inst{19-16} = 0b0000; 3965 let Inst{15-12} = Rd; 3966 let Inst{11-8} = shift{11-8}; 3967 let Inst{7} = 0; 3968 let Inst{6-5} = shift{6-5}; 3969 let Inst{4} = 1; 3970 let Inst{3-0} = shift{3-0}; 3971 3972 let Unpredictable{19-16} = 0b1111; 3973} 3974let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3975def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, 3976 IIC_iMVNi, "mvn", "\t$Rd, $imm", 3977 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 3978 bits<4> Rd; 3979 bits<12> imm; 3980 let Inst{25} = 1; 3981 let Inst{19-16} = 0b0000; 3982 let Inst{15-12} = Rd; 3983 let Inst{11-0} = imm; 3984} 3985 3986let AddedComplexity = 1 in 3987def : ARMPat<(and GPR:$src, mod_imm_not:$imm), 3988 (BICri GPR:$src, mod_imm_not:$imm)>; 3989 3990//===----------------------------------------------------------------------===// 3991// Multiply Instructions. 3992// 3993class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3994 string opc, string asm, list<dag> pattern> 3995 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3996 bits<4> Rd; 3997 bits<4> Rm; 3998 bits<4> Rn; 3999 let Inst{19-16} = Rd; 4000 let Inst{11-8} = Rm; 4001 let Inst{3-0} = Rn; 4002} 4003class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4004 string opc, string asm, list<dag> pattern> 4005 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4006 bits<4> RdLo; 4007 bits<4> RdHi; 4008 bits<4> Rm; 4009 bits<4> Rn; 4010 let Inst{19-16} = RdHi; 4011 let Inst{15-12} = RdLo; 4012 let Inst{11-8} = Rm; 4013 let Inst{3-0} = Rn; 4014} 4015class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4016 string opc, string asm, list<dag> pattern> 4017 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4018 bits<4> RdLo; 4019 bits<4> RdHi; 4020 bits<4> Rm; 4021 bits<4> Rn; 4022 let Inst{19-16} = RdHi; 4023 let Inst{15-12} = RdLo; 4024 let Inst{11-8} = Rm; 4025 let Inst{3-0} = Rn; 4026} 4027 4028// FIXME: The v5 pseudos are only necessary for the additional Constraint 4029// property. Remove them when it's possible to add those properties 4030// on an individual MachineInstr, not just an instruction description. 4031let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 4032def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 4033 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4034 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 4035 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 4036 Requires<[IsARM, HasV6]>, 4037 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4038 let Inst{15-12} = 0b0000; 4039 let Unpredictable{15-12} = 0b1111; 4040} 4041 4042let Constraints = "@earlyclobber $Rd" in 4043def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 4044 pred:$p, cc_out:$s), 4045 4, IIC_iMUL32, 4046 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 4047 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 4048 Requires<[IsARM, NoV6, UseMulOps]>, 4049 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4050} 4051 4052def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), 4053 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), 4054 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 4055 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, 4056 Requires<[IsARM, HasV6, UseMulOps]>, 4057 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4058 bits<4> Ra; 4059 let Inst{15-12} = Ra; 4060} 4061 4062let Constraints = "@earlyclobber $Rd" in 4063def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), 4064 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 4065 pred:$p, cc_out:$s), 4, IIC_iMAC32, 4066 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], 4067 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, 4068 Requires<[IsARM, NoV6]>, 4069 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4070 4071def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4072 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 4073 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 4074 Requires<[IsARM, HasV6T2, UseMulOps]>, 4075 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4076 bits<4> Rd; 4077 bits<4> Rm; 4078 bits<4> Rn; 4079 bits<4> Ra; 4080 let Inst{19-16} = Rd; 4081 let Inst{15-12} = Ra; 4082 let Inst{11-8} = Rm; 4083 let Inst{3-0} = Rn; 4084} 4085 4086// Extra precision multiplies with low / high results 4087let hasSideEffects = 0 in { 4088let isCommutable = 1 in { 4089def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 4090 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4091 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", 4092 [(set GPR:$RdLo, GPR:$RdHi, 4093 (smullohi GPR:$Rn, GPR:$Rm))]>, 4094 Requires<[IsARM, HasV6]>, 4095 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4096 4097def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 4098 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4099 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", 4100 [(set GPR:$RdLo, GPR:$RdHi, 4101 (umullohi GPR:$Rn, GPR:$Rm))]>, 4102 Requires<[IsARM, HasV6]>, 4103 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL]>; 4104 4105let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 4106def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4107 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4108 4, IIC_iMUL64, 4109 [(set GPR:$RdLo, GPR:$RdHi, 4110 (smullohi GPR:$Rn, GPR:$Rm))], 4111 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4112 Requires<[IsARM, NoV6]>, 4113 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4114 4115def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4116 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4117 4, IIC_iMUL64, 4118 [(set GPR:$RdLo, GPR:$RdHi, 4119 (umullohi GPR:$Rn, GPR:$Rm))], 4120 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4121 Requires<[IsARM, NoV6]>, 4122 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4123} 4124} 4125 4126// Multiply + accumulate 4127def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 4128 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4129 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4130 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4131 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4132def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 4133 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4134 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4135 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4136 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4137 4138def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 4139 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4140 IIC_iMAC64, 4141 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4142 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4143 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> { 4144 bits<4> RdLo; 4145 bits<4> RdHi; 4146 bits<4> Rm; 4147 bits<4> Rn; 4148 let Inst{19-16} = RdHi; 4149 let Inst{15-12} = RdLo; 4150 let Inst{11-8} = Rm; 4151 let Inst{3-0} = Rn; 4152} 4153 4154let Constraints = 4155 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 4156def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4157 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4158 4, IIC_iMAC64, [], 4159 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4160 pred:$p, cc_out:$s)>, 4161 Requires<[IsARM, NoV6]>, 4162 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4163def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4164 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4165 4, IIC_iMAC64, [], 4166 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4167 pred:$p, cc_out:$s)>, 4168 Requires<[IsARM, NoV6]>, 4169 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4170} 4171 4172} // hasSideEffects 4173 4174// Most significant word multiply 4175def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4176 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 4177 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 4178 Requires<[IsARM, HasV6]>, 4179 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4180 let Inst{15-12} = 0b1111; 4181} 4182 4183def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4184 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", 4185 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>, 4186 Requires<[IsARM, HasV6]>, 4187 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4188 let Inst{15-12} = 0b1111; 4189} 4190 4191def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 4192 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4193 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 4194 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 4195 Requires<[IsARM, HasV6, UseMulOps]>, 4196 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4197 4198def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 4199 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4200 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", 4201 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4202 Requires<[IsARM, HasV6]>, 4203 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4204 4205def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 4206 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4207 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 4208 Requires<[IsARM, HasV6, UseMulOps]>, 4209 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4210 4211def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 4212 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4213 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", 4214 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4215 Requires<[IsARM, HasV6]>, 4216 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4217 4218multiclass AI_smul<string opc> { 4219 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4220 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 4221 [(set GPR:$Rd, (bb_mul GPR:$Rn, GPR:$Rm))]>, 4222 Requires<[IsARM, HasV5TE]>, 4223 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4224 4225 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4226 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 4227 [(set GPR:$Rd, (bt_mul GPR:$Rn, GPR:$Rm))]>, 4228 Requires<[IsARM, HasV5TE]>, 4229 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4230 4231 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4232 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 4233 [(set GPR:$Rd, (tb_mul GPR:$Rn, GPR:$Rm))]>, 4234 Requires<[IsARM, HasV5TE]>, 4235 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4236 4237 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4238 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 4239 [(set GPR:$Rd, (tt_mul GPR:$Rn, GPR:$Rm))]>, 4240 Requires<[IsARM, HasV5TE]>, 4241 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4242 4243 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4244 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 4245 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>, 4246 Requires<[IsARM, HasV5TE]>, 4247 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4248 4249 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4250 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 4251 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>, 4252 Requires<[IsARM, HasV5TE]>, 4253 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4254} 4255 4256 4257multiclass AI_smla<string opc> { 4258 let DecoderMethod = "DecodeSMLAInstruction" in { 4259 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 4260 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4261 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 4262 [(set GPRnopc:$Rd, (add GPR:$Ra, 4263 (bb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4264 Requires<[IsARM, HasV5TE, UseMulOps]>, 4265 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4266 4267 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 4268 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4269 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 4270 [(set GPRnopc:$Rd, (add GPR:$Ra, 4271 (bt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4272 Requires<[IsARM, HasV5TE, UseMulOps]>, 4273 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4274 4275 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 4276 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4277 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 4278 [(set GPRnopc:$Rd, (add GPR:$Ra, 4279 (tb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4280 Requires<[IsARM, HasV5TE, UseMulOps]>, 4281 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4282 4283 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 4284 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4285 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 4286 [(set GPRnopc:$Rd, (add GPR:$Ra, 4287 (tt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4288 Requires<[IsARM, HasV5TE, UseMulOps]>, 4289 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4290 4291 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 4292 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4293 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 4294 [(set GPRnopc:$Rd, 4295 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4296 Requires<[IsARM, HasV5TE, UseMulOps]>, 4297 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4298 4299 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 4300 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4301 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 4302 [(set GPRnopc:$Rd, 4303 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4304 Requires<[IsARM, HasV5TE, UseMulOps]>, 4305 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4306 } 4307} 4308 4309defm SMUL : AI_smul<"smul">; 4310defm SMLA : AI_smla<"smla">; 4311 4312// Halfword multiply accumulate long: SMLAL<x><y>. 4313class SMLAL<bits<2> opc1, string asm> 4314 : AMulxyI64<0b0001010, opc1, 4315 (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4316 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4317 IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4318 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4319 Requires<[IsARM, HasV5TE]>, 4320 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4321 4322def SMLALBB : SMLAL<0b00, "smlalbb">; 4323def SMLALBT : SMLAL<0b10, "smlalbt">; 4324def SMLALTB : SMLAL<0b01, "smlaltb">; 4325def SMLALTT : SMLAL<0b11, "smlaltt">; 4326 4327def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4328 (SMLALBB $Rn, $Rm, $RLo, $RHi)>; 4329def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4330 (SMLALBT $Rn, $Rm, $RLo, $RHi)>; 4331def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4332 (SMLALTB $Rn, $Rm, $RLo, $RHi)>; 4333def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4334 (SMLALTT $Rn, $Rm, $RLo, $RHi)>; 4335 4336// Helper class for AI_smld. 4337class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 4338 InstrItinClass itin, string opc, string asm> 4339 : AI<oops, iops, MulFrm, itin, opc, asm, []>, 4340 Requires<[IsARM, HasV6]> { 4341 bits<4> Rn; 4342 bits<4> Rm; 4343 let Inst{27-23} = 0b01110; 4344 let Inst{22} = long; 4345 let Inst{21-20} = 0b00; 4346 let Inst{11-8} = Rm; 4347 let Inst{7} = 0; 4348 let Inst{6} = sub; 4349 let Inst{5} = swap; 4350 let Inst{4} = 1; 4351 let Inst{3-0} = Rn; 4352} 4353class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 4354 InstrItinClass itin, string opc, string asm> 4355 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4356 bits<4> Rd; 4357 let Inst{15-12} = 0b1111; 4358 let Inst{19-16} = Rd; 4359} 4360class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 4361 InstrItinClass itin, string opc, string asm> 4362 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4363 bits<4> Ra; 4364 bits<4> Rd; 4365 let Inst{19-16} = Rd; 4366 let Inst{15-12} = Ra; 4367} 4368class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 4369 InstrItinClass itin, string opc, string asm> 4370 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4371 bits<4> RdLo; 4372 bits<4> RdHi; 4373 let Inst{19-16} = RdHi; 4374 let Inst{15-12} = RdLo; 4375} 4376 4377multiclass AI_smld<bit sub, string opc> { 4378 4379 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 4380 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4381 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">, 4382 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4383 4384 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 4385 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4386 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">, 4387 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4388 4389 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4390 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4391 NoItinerary, 4392 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">, 4393 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4394 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4395 4396 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4397 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4398 NoItinerary, 4399 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">, 4400 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4401 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4402} 4403 4404defm SMLA : AI_smld<0, "smla">; 4405defm SMLS : AI_smld<1, "smls">; 4406 4407def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4408 (SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4409def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4410 (SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4411def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4412 (SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4413def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4414 (SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4415def : ARMV6Pat<(ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4416 (SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4417def : ARMV6Pat<(ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4418 (SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4419def : ARMV6Pat<(ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4420 (SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4421def : ARMV6Pat<(ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4422 (SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4423 4424multiclass AI_sdml<bit sub, string opc> { 4425 4426 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 4427 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">, 4428 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4429 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 4430 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">, 4431 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4432} 4433 4434defm SMUA : AI_sdml<0, "smua">; 4435defm SMUS : AI_sdml<1, "smus">; 4436 4437def : ARMV6Pat<(int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm), 4438 (SMUAD GPRnopc:$Rn, GPRnopc:$Rm)>; 4439def : ARMV6Pat<(int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm), 4440 (SMUADX GPRnopc:$Rn, GPRnopc:$Rm)>; 4441def : ARMV6Pat<(int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm), 4442 (SMUSD GPRnopc:$Rn, GPRnopc:$Rm)>; 4443def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm), 4444 (SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)>; 4445 4446//===----------------------------------------------------------------------===// 4447// Division Instructions (ARMv7-A with virtualization extension) 4448// 4449def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4450 "sdiv", "\t$Rd, $Rn, $Rm", 4451 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 4452 Requires<[IsARM, HasDivideInARM]>, 4453 Sched<[WriteDIV]>; 4454 4455def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4456 "udiv", "\t$Rd, $Rn, $Rm", 4457 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 4458 Requires<[IsARM, HasDivideInARM]>, 4459 Sched<[WriteDIV]>; 4460 4461//===----------------------------------------------------------------------===// 4462// Misc. Arithmetic Instructions. 4463// 4464 4465def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 4466 IIC_iUNAr, "clz", "\t$Rd, $Rm", 4467 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 4468 Sched<[WriteALU]>; 4469 4470def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4471 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 4472 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>, 4473 Requires<[IsARM, HasV6T2]>, 4474 Sched<[WriteALU]>; 4475 4476def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4477 IIC_iUNAr, "rev", "\t$Rd, $Rm", 4478 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 4479 Sched<[WriteALU]>; 4480 4481let AddedComplexity = 5 in 4482def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4483 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 4484 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 4485 Requires<[IsARM, HasV6]>, 4486 Sched<[WriteALU]>; 4487 4488def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), 4489 (REV16 (LDRH addrmode3:$addr))>; 4490def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), 4491 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; 4492 4493let AddedComplexity = 5 in 4494def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4495 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 4496 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 4497 Requires<[IsARM, HasV6]>, 4498 Sched<[WriteALU]>; 4499 4500def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 4501 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 4502 (REVSH GPR:$Rm)>; 4503 4504def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 4505 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 4506 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 4507 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 4508 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4509 0xFFFF0000)))]>, 4510 Requires<[IsARM, HasV6]>, 4511 Sched<[WriteALUsi, ReadALU]>; 4512 4513// Alternate cases for PKHBT where identities eliminate some nodes. 4514def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 4515 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 4516def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 4517 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 4518 4519// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4520// will match the pattern below. 4521def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4522 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4523 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4524 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4525 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4526 0xFFFF)))]>, 4527 Requires<[IsARM, HasV6]>, 4528 Sched<[WriteALUsi, ReadALU]>; 4529 4530// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4531// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4532// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4533// pkhtb src1, src2, asr (17..31). 4534def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4535 (srl GPRnopc:$src2, imm16:$sh)), 4536 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4537def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4538 (sra GPRnopc:$src2, imm16_31:$sh)), 4539 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4540def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4541 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4542 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4543 4544//===----------------------------------------------------------------------===// 4545// CRC Instructions 4546// 4547// Polynomials: 4548// + CRC32{B,H,W} 0x04C11DB7 4549// + CRC32C{B,H,W} 0x1EDC6F41 4550// 4551 4552class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4553 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4554 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4555 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4556 Requires<[IsARM, HasV8, HasCRC]> { 4557 bits<4> Rd; 4558 bits<4> Rn; 4559 bits<4> Rm; 4560 4561 let Inst{31-28} = 0b1110; 4562 let Inst{27-23} = 0b00010; 4563 let Inst{22-21} = sz; 4564 let Inst{20} = 0; 4565 let Inst{19-16} = Rn; 4566 let Inst{15-12} = Rd; 4567 let Inst{11-10} = 0b00; 4568 let Inst{9} = C; 4569 let Inst{8} = 0; 4570 let Inst{7-4} = 0b0100; 4571 let Inst{3-0} = Rm; 4572 4573 let Unpredictable{11-8} = 0b1101; 4574} 4575 4576def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4577def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4578def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4579def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4580def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4581def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4582 4583//===----------------------------------------------------------------------===// 4584// ARMv8.1a Privilege Access Never extension 4585// 4586// SETPAN #imm1 4587 4588def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan", 4589 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> { 4590 bits<1> imm; 4591 4592 let Inst{31-28} = 0b1111; 4593 let Inst{27-20} = 0b00010001; 4594 let Inst{19-16} = 0b0000; 4595 let Inst{15-10} = 0b000000; 4596 let Inst{9} = imm; 4597 let Inst{8} = 0b0; 4598 let Inst{7-4} = 0b0000; 4599 let Inst{3-0} = 0b0000; 4600 4601 let Unpredictable{19-16} = 0b1111; 4602 let Unpredictable{15-10} = 0b111111; 4603 let Unpredictable{8} = 0b1; 4604 let Unpredictable{3-0} = 0b1111; 4605} 4606 4607//===----------------------------------------------------------------------===// 4608// Comparison Instructions... 4609// 4610 4611defm CMP : AI1_cmp_irs<0b1010, "cmp", 4612 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, ARMcmp>; 4613 4614// ARMcmpZ can re-use the above instruction definitions. 4615def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm), 4616 (CMPri GPR:$src, mod_imm:$imm)>; 4617def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4618 (CMPrr GPR:$src, GPR:$rhs)>; 4619def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4620 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4621def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4622 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4623 4624// CMN register-integer 4625let isCompare = 1, Defs = [CPSR] in { 4626def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi, 4627 "cmn", "\t$Rn, $imm", 4628 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>, 4629 Sched<[WriteCMP, ReadALU]> { 4630 bits<4> Rn; 4631 bits<12> imm; 4632 let Inst{25} = 1; 4633 let Inst{20} = 1; 4634 let Inst{19-16} = Rn; 4635 let Inst{15-12} = 0b0000; 4636 let Inst{11-0} = imm; 4637 4638 let Unpredictable{15-12} = 0b1111; 4639} 4640 4641// CMN register-register/shift 4642def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4643 "cmn", "\t$Rn, $Rm", 4644 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4645 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4646 bits<4> Rn; 4647 bits<4> Rm; 4648 let isCommutable = 1; 4649 let Inst{25} = 0; 4650 let Inst{20} = 1; 4651 let Inst{19-16} = Rn; 4652 let Inst{15-12} = 0b0000; 4653 let Inst{11-4} = 0b00000000; 4654 let Inst{3-0} = Rm; 4655 4656 let Unpredictable{15-12} = 0b1111; 4657} 4658 4659def CMNzrsi : AI1<0b1011, (outs), 4660 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4661 "cmn", "\t$Rn, $shift", 4662 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4663 GPR:$Rn, so_reg_imm:$shift)]>, 4664 Sched<[WriteCMPsi, ReadALU]> { 4665 bits<4> Rn; 4666 bits<12> shift; 4667 let Inst{25} = 0; 4668 let Inst{20} = 1; 4669 let Inst{19-16} = Rn; 4670 let Inst{15-12} = 0b0000; 4671 let Inst{11-5} = shift{11-5}; 4672 let Inst{4} = 0; 4673 let Inst{3-0} = shift{3-0}; 4674 4675 let Unpredictable{15-12} = 0b1111; 4676} 4677 4678def CMNzrsr : AI1<0b1011, (outs), 4679 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4680 "cmn", "\t$Rn, $shift", 4681 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4682 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4683 Sched<[WriteCMPsr, ReadALU]> { 4684 bits<4> Rn; 4685 bits<12> shift; 4686 let Inst{25} = 0; 4687 let Inst{20} = 1; 4688 let Inst{19-16} = Rn; 4689 let Inst{15-12} = 0b0000; 4690 let Inst{11-8} = shift{11-8}; 4691 let Inst{7} = 0; 4692 let Inst{6-5} = shift{6-5}; 4693 let Inst{4} = 1; 4694 let Inst{3-0} = shift{3-0}; 4695 4696 let Unpredictable{15-12} = 0b1111; 4697} 4698 4699} 4700 4701def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm), 4702 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4703 4704def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm), 4705 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4706 4707// Note that TST/TEQ don't set all the same flags that CMP does! 4708defm TST : AI1_cmp_irs<0b1000, "tst", 4709 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4710 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1, 4711 "DecodeTSTInstruction">; 4712defm TEQ : AI1_cmp_irs<0b1001, "teq", 4713 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4714 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4715 4716// Pseudo i64 compares for some floating point compares. 4717let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4718 Defs = [CPSR] in { 4719def BCCi64 : PseudoInst<(outs), 4720 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4721 IIC_Br, 4722 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4723 Sched<[WriteBr]>; 4724 4725def BCCZi64 : PseudoInst<(outs), 4726 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4727 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4728 Sched<[WriteBr]>; 4729} // usesCustomInserter 4730 4731 4732// Conditional moves 4733let hasSideEffects = 0 in { 4734 4735let isCommutable = 1, isSelect = 1 in 4736def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4737 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4738 4, IIC_iCMOVr, 4739 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4740 cmovpred:$p))]>, 4741 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4742 4743def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4744 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4745 4, IIC_iCMOVsr, 4746 [(set GPR:$Rd, 4747 (ARMcmov GPR:$false, so_reg_imm:$shift, 4748 cmovpred:$p))]>, 4749 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4750def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4751 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4752 4, IIC_iCMOVsr, 4753 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4754 cmovpred:$p))]>, 4755 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4756 4757 4758let isMoveImm = 1 in 4759def MOVCCi16 4760 : ARMPseudoInst<(outs GPR:$Rd), 4761 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 4762 4, IIC_iMOVi, 4763 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 4764 cmovpred:$p))]>, 4765 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 4766 Sched<[WriteALU]>; 4767 4768let isMoveImm = 1 in 4769def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4770 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4771 4, IIC_iCMOVi, 4772 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm, 4773 cmovpred:$p))]>, 4774 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4775 4776// Two instruction predicate mov immediate. 4777let isMoveImm = 1 in 4778def MOVCCi32imm 4779 : ARMPseudoInst<(outs GPR:$Rd), 4780 (ins GPR:$false, i32imm:$src, cmovpred:$p), 4781 8, IIC_iCMOVix2, 4782 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 4783 cmovpred:$p))]>, 4784 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 4785 4786let isMoveImm = 1 in 4787def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 4788 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4789 4, IIC_iCMOVi, 4790 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm, 4791 cmovpred:$p))]>, 4792 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4793 4794} // hasSideEffects 4795 4796 4797//===----------------------------------------------------------------------===// 4798// Atomic operations intrinsics 4799// 4800 4801def MemBarrierOptOperand : AsmOperandClass { 4802 let Name = "MemBarrierOpt"; 4803 let ParserMethod = "parseMemBarrierOptOperand"; 4804} 4805def memb_opt : Operand<i32> { 4806 let PrintMethod = "printMemBOption"; 4807 let ParserMatchClass = MemBarrierOptOperand; 4808 let DecoderMethod = "DecodeMemBarrierOption"; 4809} 4810 4811def InstSyncBarrierOptOperand : AsmOperandClass { 4812 let Name = "InstSyncBarrierOpt"; 4813 let ParserMethod = "parseInstSyncBarrierOptOperand"; 4814} 4815def instsyncb_opt : Operand<i32> { 4816 let PrintMethod = "printInstSyncBOption"; 4817 let ParserMatchClass = InstSyncBarrierOptOperand; 4818 let DecoderMethod = "DecodeInstSyncBarrierOption"; 4819} 4820 4821def TraceSyncBarrierOptOperand : AsmOperandClass { 4822 let Name = "TraceSyncBarrierOpt"; 4823 let ParserMethod = "parseTraceSyncBarrierOptOperand"; 4824} 4825def tsb_opt : Operand<i32> { 4826 let PrintMethod = "printTraceSyncBOption"; 4827 let ParserMatchClass = TraceSyncBarrierOptOperand; 4828} 4829 4830// Memory barriers protect the atomic sequences 4831let hasSideEffects = 1 in { 4832def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4833 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 4834 Requires<[IsARM, HasDB]> { 4835 bits<4> opt; 4836 let Inst{31-4} = 0xf57ff05; 4837 let Inst{3-0} = opt; 4838} 4839 4840def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4841 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 4842 Requires<[IsARM, HasDB]> { 4843 bits<4> opt; 4844 let Inst{31-4} = 0xf57ff04; 4845 let Inst{3-0} = opt; 4846} 4847 4848// ISB has only full system option 4849def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 4850 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 4851 Requires<[IsARM, HasDB]> { 4852 bits<4> opt; 4853 let Inst{31-4} = 0xf57ff06; 4854 let Inst{3-0} = opt; 4855} 4856 4857let hasNoSchedulingInfo = 1 in 4858def TSB : AInoP<(outs), (ins tsb_opt:$opt), MiscFrm, NoItinerary, 4859 "tsb", "\t$opt", []>, Requires<[IsARM, HasV8_4a]> { 4860 let Inst{31-0} = 0xe320f012; 4861} 4862 4863} 4864 4865// Armv8.5-A speculation barrier 4866def SB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "sb", "", []>, 4867 Requires<[IsARM, HasSB]>, Sched<[]> { 4868 let Inst{31-0} = 0xf57ff070; 4869 let Unpredictable = 0x000fff0f; 4870 let hasSideEffects = 1; 4871} 4872 4873let usesCustomInserter = 1, Defs = [CPSR] in { 4874 4875// Pseudo instruction that combines movs + predicated rsbmi 4876// to implement integer ABS 4877 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 4878} 4879 4880let usesCustomInserter = 1, Defs = [CPSR] in { 4881 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 4882 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 4883 NoItinerary, 4884 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 4885} 4886 4887let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in { 4888 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs... 4889 // Copies N registers worth of memory from address %src to address %dst 4890 // and returns the incremented addresses. N scratch register will 4891 // be attached for the copy to use. 4892 def MEMCPY : PseudoInst< 4893 (outs GPR:$newdst, GPR:$newsrc), 4894 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops), 4895 NoItinerary, 4896 [(set GPR:$newdst, GPR:$newsrc, 4897 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>; 4898} 4899 4900def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4901 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4902}]>; 4903 4904def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4905 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4906}]>; 4907 4908def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4909 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4910}]>; 4911 4912def strex_1 : PatFrag<(ops node:$val, node:$ptr), 4913 (int_arm_strex node:$val, node:$ptr), [{ 4914 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4915}]>; 4916 4917def strex_2 : PatFrag<(ops node:$val, node:$ptr), 4918 (int_arm_strex node:$val, node:$ptr), [{ 4919 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4920}]>; 4921 4922def strex_4 : PatFrag<(ops node:$val, node:$ptr), 4923 (int_arm_strex node:$val, node:$ptr), [{ 4924 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4925}]>; 4926 4927def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4928 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4929}]>; 4930 4931def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4932 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4933}]>; 4934 4935def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4936 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4937}]>; 4938 4939def stlex_1 : PatFrag<(ops node:$val, node:$ptr), 4940 (int_arm_stlex node:$val, node:$ptr), [{ 4941 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4942}]>; 4943 4944def stlex_2 : PatFrag<(ops node:$val, node:$ptr), 4945 (int_arm_stlex node:$val, node:$ptr), [{ 4946 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4947}]>; 4948 4949def stlex_4 : PatFrag<(ops node:$val, node:$ptr), 4950 (int_arm_stlex node:$val, node:$ptr), [{ 4951 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4952}]>; 4953 4954let mayLoad = 1 in { 4955def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4956 NoItinerary, "ldrexb", "\t$Rt, $addr", 4957 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 4958def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4959 NoItinerary, "ldrexh", "\t$Rt, $addr", 4960 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 4961def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4962 NoItinerary, "ldrex", "\t$Rt, $addr", 4963 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 4964let hasExtraDefRegAllocReq = 1 in 4965def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4966 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 4967 let DecoderMethod = "DecodeDoubleRegLoad"; 4968} 4969 4970def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4971 NoItinerary, "ldaexb", "\t$Rt, $addr", 4972 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>; 4973def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4974 NoItinerary, "ldaexh", "\t$Rt, $addr", 4975 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>; 4976def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4977 NoItinerary, "ldaex", "\t$Rt, $addr", 4978 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>; 4979let hasExtraDefRegAllocReq = 1 in 4980def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4981 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 4982 let DecoderMethod = "DecodeDoubleRegLoad"; 4983} 4984} 4985 4986let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 4987def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4988 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 4989 [(set GPR:$Rd, (strex_1 GPR:$Rt, 4990 addr_offset_none:$addr))]>; 4991def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4992 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 4993 [(set GPR:$Rd, (strex_2 GPR:$Rt, 4994 addr_offset_none:$addr))]>; 4995def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4996 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 4997 [(set GPR:$Rd, (strex_4 GPR:$Rt, 4998 addr_offset_none:$addr))]>; 4999let hasExtraSrcRegAllocReq = 1 in 5000def STREXD : AIstrex<0b01, (outs GPR:$Rd), 5001 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5002 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 5003 let DecoderMethod = "DecodeDoubleRegStore"; 5004} 5005def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5006 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 5007 [(set GPR:$Rd, 5008 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>; 5009def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5010 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 5011 [(set GPR:$Rd, 5012 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>; 5013def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5014 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 5015 [(set GPR:$Rd, 5016 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>; 5017let hasExtraSrcRegAllocReq = 1 in 5018def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 5019 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5020 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 5021 let DecoderMethod = "DecodeDoubleRegStore"; 5022} 5023} 5024 5025def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 5026 [(int_arm_clrex)]>, 5027 Requires<[IsARM, HasV6K]> { 5028 let Inst{31-0} = 0b11110101011111111111000000011111; 5029} 5030 5031def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5032 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 5033def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5034 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 5035 5036def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5037 (STLEXB GPR:$Rt, addr_offset_none:$addr)>; 5038def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5039 (STLEXH GPR:$Rt, addr_offset_none:$addr)>; 5040 5041class acquiring_load<PatFrag base> 5042 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 5043 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 5044 return isAcquireOrStronger(Ordering); 5045}]>; 5046 5047def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 5048def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 5049def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 5050 5051class releasing_store<PatFrag base> 5052 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 5053 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 5054 return isReleaseOrStronger(Ordering); 5055}]>; 5056 5057def atomic_store_release_8 : releasing_store<atomic_store_8>; 5058def atomic_store_release_16 : releasing_store<atomic_store_16>; 5059def atomic_store_release_32 : releasing_store<atomic_store_32>; 5060 5061let AddedComplexity = 8 in { 5062 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 5063 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 5064 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 5065 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 5066 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 5067 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 5068} 5069 5070// SWP/SWPB are deprecated in V6/V7 and optional in v7VE. 5071// FIXME Use InstAlias to generate LDREX/STREX pairs instead. 5072let mayLoad = 1, mayStore = 1 in { 5073def SWP : AIswp<0, (outs GPRnopc:$Rt), 5074 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 5075 Requires<[IsARM,PreV8]>; 5076def SWPB: AIswp<1, (outs GPRnopc:$Rt), 5077 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 5078 Requires<[IsARM,PreV8]>; 5079} 5080 5081//===----------------------------------------------------------------------===// 5082// Coprocessor Instructions. 5083// 5084 5085def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5086 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5087 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5088 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 5089 imm:$CRm, imm:$opc2)]>, 5090 Requires<[IsARM,PreV8]> { 5091 bits<4> opc1; 5092 bits<4> CRn; 5093 bits<4> CRd; 5094 bits<4> cop; 5095 bits<3> opc2; 5096 bits<4> CRm; 5097 5098 let Inst{3-0} = CRm; 5099 let Inst{4} = 0; 5100 let Inst{7-5} = opc2; 5101 let Inst{11-8} = cop; 5102 let Inst{15-12} = CRd; 5103 let Inst{19-16} = CRn; 5104 let Inst{23-20} = opc1; 5105 5106 let DecoderNamespace = "CoProc"; 5107} 5108 5109def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5110 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5111 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5112 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 5113 imm:$CRm, imm:$opc2)]>, 5114 Requires<[IsARM,PreV8]> { 5115 let Inst{31-28} = 0b1111; 5116 bits<4> opc1; 5117 bits<4> CRn; 5118 bits<4> CRd; 5119 bits<4> cop; 5120 bits<3> opc2; 5121 bits<4> CRm; 5122 5123 let Inst{3-0} = CRm; 5124 let Inst{4} = 0; 5125 let Inst{7-5} = opc2; 5126 let Inst{11-8} = cop; 5127 let Inst{15-12} = CRd; 5128 let Inst{19-16} = CRn; 5129 let Inst{23-20} = opc1; 5130 5131 let DecoderNamespace = "CoProc"; 5132} 5133 5134class ACI<dag oops, dag iops, string opc, string asm, 5135 list<dag> pattern, IndexMode im = IndexModeNone> 5136 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5137 opc, asm, "", pattern> { 5138 let Inst{27-25} = 0b110; 5139} 5140class ACInoP<dag oops, dag iops, string opc, string asm, 5141 list<dag> pattern, IndexMode im = IndexModeNone> 5142 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5143 opc, asm, "", pattern> { 5144 let Inst{31-28} = 0b1111; 5145 let Inst{27-25} = 0b110; 5146} 5147 5148let DecoderNamespace = "CoProc" in { 5149multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> { 5150 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5151 asm, "\t$cop, $CRd, $addr", pattern> { 5152 bits<13> addr; 5153 bits<4> cop; 5154 bits<4> CRd; 5155 let Inst{24} = 1; // P = 1 5156 let Inst{23} = addr{8}; 5157 let Inst{22} = Dbit; 5158 let Inst{21} = 0; // W = 0 5159 let Inst{20} = load; 5160 let Inst{19-16} = addr{12-9}; 5161 let Inst{15-12} = CRd; 5162 let Inst{11-8} = cop; 5163 let Inst{7-0} = addr{7-0}; 5164 let DecoderMethod = "DecodeCopMemInstruction"; 5165 } 5166 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5167 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5168 bits<13> addr; 5169 bits<4> cop; 5170 bits<4> CRd; 5171 let Inst{24} = 1; // P = 1 5172 let Inst{23} = addr{8}; 5173 let Inst{22} = Dbit; 5174 let Inst{21} = 1; // W = 1 5175 let Inst{20} = load; 5176 let Inst{19-16} = addr{12-9}; 5177 let Inst{15-12} = CRd; 5178 let Inst{11-8} = cop; 5179 let Inst{7-0} = addr{7-0}; 5180 let DecoderMethod = "DecodeCopMemInstruction"; 5181 } 5182 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5183 postidx_imm8s4:$offset), 5184 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5185 bits<9> offset; 5186 bits<4> addr; 5187 bits<4> cop; 5188 bits<4> CRd; 5189 let Inst{24} = 0; // P = 0 5190 let Inst{23} = offset{8}; 5191 let Inst{22} = Dbit; 5192 let Inst{21} = 1; // W = 1 5193 let Inst{20} = load; 5194 let Inst{19-16} = addr; 5195 let Inst{15-12} = CRd; 5196 let Inst{11-8} = cop; 5197 let Inst{7-0} = offset{7-0}; 5198 let DecoderMethod = "DecodeCopMemInstruction"; 5199 } 5200 def _OPTION : ACI<(outs), 5201 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5202 coproc_option_imm:$option), 5203 asm, "\t$cop, $CRd, $addr, $option", []> { 5204 bits<8> option; 5205 bits<4> addr; 5206 bits<4> cop; 5207 bits<4> CRd; 5208 let Inst{24} = 0; // P = 0 5209 let Inst{23} = 1; // U = 1 5210 let Inst{22} = Dbit; 5211 let Inst{21} = 0; // W = 0 5212 let Inst{20} = load; 5213 let Inst{19-16} = addr; 5214 let Inst{15-12} = CRd; 5215 let Inst{11-8} = cop; 5216 let Inst{7-0} = option; 5217 let DecoderMethod = "DecodeCopMemInstruction"; 5218 } 5219} 5220multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> { 5221 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5222 asm, "\t$cop, $CRd, $addr", pattern> { 5223 bits<13> addr; 5224 bits<4> cop; 5225 bits<4> CRd; 5226 let Inst{24} = 1; // P = 1 5227 let Inst{23} = addr{8}; 5228 let Inst{22} = Dbit; 5229 let Inst{21} = 0; // W = 0 5230 let Inst{20} = load; 5231 let Inst{19-16} = addr{12-9}; 5232 let Inst{15-12} = CRd; 5233 let Inst{11-8} = cop; 5234 let Inst{7-0} = addr{7-0}; 5235 let DecoderMethod = "DecodeCopMemInstruction"; 5236 } 5237 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5238 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5239 bits<13> addr; 5240 bits<4> cop; 5241 bits<4> CRd; 5242 let Inst{24} = 1; // P = 1 5243 let Inst{23} = addr{8}; 5244 let Inst{22} = Dbit; 5245 let Inst{21} = 1; // W = 1 5246 let Inst{20} = load; 5247 let Inst{19-16} = addr{12-9}; 5248 let Inst{15-12} = CRd; 5249 let Inst{11-8} = cop; 5250 let Inst{7-0} = addr{7-0}; 5251 let DecoderMethod = "DecodeCopMemInstruction"; 5252 } 5253 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5254 postidx_imm8s4:$offset), 5255 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5256 bits<9> offset; 5257 bits<4> addr; 5258 bits<4> cop; 5259 bits<4> CRd; 5260 let Inst{24} = 0; // P = 0 5261 let Inst{23} = offset{8}; 5262 let Inst{22} = Dbit; 5263 let Inst{21} = 1; // W = 1 5264 let Inst{20} = load; 5265 let Inst{19-16} = addr; 5266 let Inst{15-12} = CRd; 5267 let Inst{11-8} = cop; 5268 let Inst{7-0} = offset{7-0}; 5269 let DecoderMethod = "DecodeCopMemInstruction"; 5270 } 5271 def _OPTION : ACInoP<(outs), 5272 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5273 coproc_option_imm:$option), 5274 asm, "\t$cop, $CRd, $addr, $option", []> { 5275 bits<8> option; 5276 bits<4> addr; 5277 bits<4> cop; 5278 bits<4> CRd; 5279 let Inst{24} = 0; // P = 0 5280 let Inst{23} = 1; // U = 1 5281 let Inst{22} = Dbit; 5282 let Inst{21} = 0; // W = 0 5283 let Inst{20} = load; 5284 let Inst{19-16} = addr; 5285 let Inst{15-12} = CRd; 5286 let Inst{11-8} = cop; 5287 let Inst{7-0} = option; 5288 let DecoderMethod = "DecodeCopMemInstruction"; 5289 } 5290} 5291 5292defm LDC : LdStCop <1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5293defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5294defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5295defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5296 5297defm STC : LdStCop <0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5298defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5299defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5300defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5301 5302} // DecoderNamespace = "CoProc" 5303 5304//===----------------------------------------------------------------------===// 5305// Move between coprocessor and ARM core register. 5306// 5307 5308class MovRCopro<string opc, bit direction, dag oops, dag iops, 5309 list<dag> pattern> 5310 : ABI<0b1110, oops, iops, NoItinerary, opc, 5311 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 5312 let Inst{20} = direction; 5313 let Inst{4} = 1; 5314 5315 bits<4> Rt; 5316 bits<4> cop; 5317 bits<3> opc1; 5318 bits<3> opc2; 5319 bits<4> CRm; 5320 bits<4> CRn; 5321 5322 let Inst{15-12} = Rt; 5323 let Inst{11-8} = cop; 5324 let Inst{23-21} = opc1; 5325 let Inst{7-5} = opc2; 5326 let Inst{3-0} = CRm; 5327 let Inst{19-16} = CRn; 5328 5329 let DecoderNamespace = "CoProc"; 5330} 5331 5332def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 5333 (outs), 5334 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5335 c_imm:$CRm, imm0_7:$opc2), 5336 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5337 imm:$CRm, imm:$opc2)]>, 5338 ComplexDeprecationPredicate<"MCR">; 5339def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 5340 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5341 c_imm:$CRm, 0, pred:$p)>; 5342def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 5343 (outs GPRwithAPSR:$Rt), 5344 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5345 imm0_7:$opc2), []>; 5346def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 5347 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5348 c_imm:$CRm, 0, pred:$p)>; 5349 5350def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 5351 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5352 5353class MovRCopro2<string opc, bit direction, dag oops, dag iops, 5354 list<dag> pattern> 5355 : ABXI<0b1110, oops, iops, NoItinerary, 5356 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 5357 let Inst{31-24} = 0b11111110; 5358 let Inst{20} = direction; 5359 let Inst{4} = 1; 5360 5361 bits<4> Rt; 5362 bits<4> cop; 5363 bits<3> opc1; 5364 bits<3> opc2; 5365 bits<4> CRm; 5366 bits<4> CRn; 5367 5368 let Inst{15-12} = Rt; 5369 let Inst{11-8} = cop; 5370 let Inst{23-21} = opc1; 5371 let Inst{7-5} = opc2; 5372 let Inst{3-0} = CRm; 5373 let Inst{19-16} = CRn; 5374 5375 let DecoderNamespace = "CoProc"; 5376} 5377 5378def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 5379 (outs), 5380 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5381 c_imm:$CRm, imm0_7:$opc2), 5382 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5383 imm:$CRm, imm:$opc2)]>, 5384 Requires<[IsARM,PreV8]>; 5385def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", 5386 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5387 c_imm:$CRm, 0)>; 5388def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 5389 (outs GPRwithAPSR:$Rt), 5390 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5391 imm0_7:$opc2), []>, 5392 Requires<[IsARM,PreV8]>; 5393def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", 5394 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5395 c_imm:$CRm, 0)>; 5396 5397def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, 5398 imm:$CRm, imm:$opc2), 5399 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5400 5401class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag> 5402 pattern = []> 5403 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", 5404 pattern> { 5405 5406 let Inst{23-21} = 0b010; 5407 let Inst{20} = direction; 5408 5409 bits<4> Rt; 5410 bits<4> Rt2; 5411 bits<4> cop; 5412 bits<4> opc1; 5413 bits<4> CRm; 5414 5415 let Inst{15-12} = Rt; 5416 let Inst{19-16} = Rt2; 5417 let Inst{11-8} = cop; 5418 let Inst{7-4} = opc1; 5419 let Inst{3-0} = CRm; 5420} 5421 5422def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 5423 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5424 GPRnopc:$Rt2, c_imm:$CRm), 5425 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, 5426 GPRnopc:$Rt2, imm:$CRm)]>; 5427def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */, 5428 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5429 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5430 5431class MovRRCopro2<string opc, bit direction, dag oops, dag iops, 5432 list<dag> pattern = []> 5433 : ABXI<0b1100, oops, iops, NoItinerary, 5434 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5435 Requires<[IsARM,PreV8]> { 5436 let Inst{31-28} = 0b1111; 5437 let Inst{23-21} = 0b010; 5438 let Inst{20} = direction; 5439 5440 bits<4> Rt; 5441 bits<4> Rt2; 5442 bits<4> cop; 5443 bits<4> opc1; 5444 bits<4> CRm; 5445 5446 let Inst{15-12} = Rt; 5447 let Inst{19-16} = Rt2; 5448 let Inst{11-8} = cop; 5449 let Inst{7-4} = opc1; 5450 let Inst{3-0} = CRm; 5451 5452 let DecoderMethod = "DecoderForMRRC2AndMCRR2"; 5453} 5454 5455def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5456 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5457 GPRnopc:$Rt2, c_imm:$CRm), 5458 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, 5459 GPRnopc:$Rt2, imm:$CRm)]>; 5460 5461def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */, 5462 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5463 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5464 5465//===----------------------------------------------------------------------===// 5466// Move between special register and ARM core register 5467// 5468 5469// Move to ARM core register from Special Register 5470def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5471 "mrs", "\t$Rd, apsr", []> { 5472 bits<4> Rd; 5473 let Inst{23-16} = 0b00001111; 5474 let Unpredictable{19-17} = 0b111; 5475 5476 let Inst{15-12} = Rd; 5477 5478 let Inst{11-0} = 0b000000000000; 5479 let Unpredictable{11-0} = 0b110100001111; 5480} 5481 5482def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>, 5483 Requires<[IsARM]>; 5484 5485// The MRSsys instruction is the MRS instruction from the ARM ARM, 5486// section B9.3.9, with the R bit set to 1. 5487def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5488 "mrs", "\t$Rd, spsr", []> { 5489 bits<4> Rd; 5490 let Inst{23-16} = 0b01001111; 5491 let Unpredictable{19-16} = 0b1111; 5492 5493 let Inst{15-12} = Rd; 5494 5495 let Inst{11-0} = 0b000000000000; 5496 let Unpredictable{11-0} = 0b110100001111; 5497} 5498 5499// However, the MRS (banked register) system instruction (ARMv7VE) *does* have a 5500// separate encoding (distinguished by bit 5. 5501def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked), 5502 NoItinerary, "mrs", "\t$Rd, $banked", []>, 5503 Requires<[IsARM, HasVirtualization]> { 5504 bits<6> banked; 5505 bits<4> Rd; 5506 5507 let Inst{23} = 0; 5508 let Inst{22} = banked{5}; // R bit 5509 let Inst{21-20} = 0b00; 5510 let Inst{19-16} = banked{3-0}; 5511 let Inst{15-12} = Rd; 5512 let Inst{11-9} = 0b001; 5513 let Inst{8} = banked{4}; 5514 let Inst{7-0} = 0b00000000; 5515} 5516 5517// Move from ARM core register to Special Register 5518// 5519// No need to have both system and application versions of MSR (immediate) or 5520// MSR (register), the encodings are the same and the assembly parser has no way 5521// to distinguish between them. The mask operand contains the special register 5522// (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be 5523// accessed in the special register. 5524let Defs = [CPSR] in 5525def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5526 "msr", "\t$mask, $Rn", []> { 5527 bits<5> mask; 5528 bits<4> Rn; 5529 5530 let Inst{23} = 0; 5531 let Inst{22} = mask{4}; // R bit 5532 let Inst{21-20} = 0b10; 5533 let Inst{19-16} = mask{3-0}; 5534 let Inst{15-12} = 0b1111; 5535 let Inst{11-4} = 0b00000000; 5536 let Inst{3-0} = Rn; 5537} 5538 5539let Defs = [CPSR] in 5540def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary, 5541 "msr", "\t$mask, $imm", []> { 5542 bits<5> mask; 5543 bits<12> imm; 5544 5545 let Inst{23} = 0; 5546 let Inst{22} = mask{4}; // R bit 5547 let Inst{21-20} = 0b10; 5548 let Inst{19-16} = mask{3-0}; 5549 let Inst{15-12} = 0b1111; 5550 let Inst{11-0} = imm; 5551} 5552 5553// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a 5554// separate encoding (distinguished by bit 5. 5555def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn), 5556 NoItinerary, "msr", "\t$banked, $Rn", []>, 5557 Requires<[IsARM, HasVirtualization]> { 5558 bits<6> banked; 5559 bits<4> Rn; 5560 5561 let Inst{23} = 0; 5562 let Inst{22} = banked{5}; // R bit 5563 let Inst{21-20} = 0b10; 5564 let Inst{19-16} = banked{3-0}; 5565 let Inst{15-12} = 0b1111; 5566 let Inst{11-9} = 0b001; 5567 let Inst{8} = banked{4}; 5568 let Inst{7-4} = 0b0000; 5569 let Inst{3-0} = Rn; 5570} 5571 5572// Dynamic stack allocation yields a _chkstk for Windows targets. These calls 5573// are needed to probe the stack when allocating more than 5574// 4k bytes in one go. Touching the stack at 4K increments is necessary to 5575// ensure that the guard pages used by the OS virtual memory manager are 5576// allocated in correct sequence. 5577// The main point of having separate instruction are extra unmodelled effects 5578// (compared to ordinary calls) like stack pointer change. 5579 5580def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone, 5581 [SDNPHasChain, SDNPSideEffect]>; 5582let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in 5583 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>; 5584 5585def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK, 5586 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 5587let usesCustomInserter = 1, Defs = [CPSR] in 5588 def WIN__DBZCHK : PseudoInst<(outs), (ins tGPR:$divisor), NoItinerary, 5589 [(win__dbzchk tGPR:$divisor)]>; 5590 5591//===----------------------------------------------------------------------===// 5592// TLS Instructions 5593// 5594 5595// __aeabi_read_tp preserves the registers r1-r3. 5596// This is a pseudo inst so that we can get the encoding right, 5597// complete with fixup for the aeabi_read_tp function. 5598// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern 5599// is defined in "ARMInstrThumb.td". 5600let isCall = 1, 5601 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5602 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br, 5603 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>, 5604 Requires<[IsARM, IsReadTPSoft]>; 5605} 5606 5607// Reading thread pointer from coprocessor register 5608def : ARMPat<(ARMthread_pointer), (MRC 15, 0, 13, 0, 3)>, 5609 Requires<[IsARM, IsReadTPHard]>; 5610 5611//===----------------------------------------------------------------------===// 5612// SJLJ Exception handling intrinsics 5613// eh_sjlj_setjmp() is an instruction sequence to store the return 5614// address and save #0 in R0 for the non-longjmp case. 5615// Since by its nature we may be coming from some other function to get 5616// here, and we're using the stack frame for the containing function to 5617// save/restore registers, we can't keep anything live in regs across 5618// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5619// when we get here from a longjmp(). We force everything out of registers 5620// except for our own input by listing the relevant registers in Defs. By 5621// doing so, we also cause the prologue/epilogue code to actively preserve 5622// all of the callee-saved resgisters, which is exactly what we want. 5623// A constant value is passed in $val, and we use the location as a scratch. 5624// 5625// These are pseudo-instructions and are lowered to individual MC-insts, so 5626// no encoding information is necessary. 5627let Defs = 5628 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5629 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5630 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5631 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5632 NoItinerary, 5633 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5634 Requires<[IsARM, HasVFP2]>; 5635} 5636 5637let Defs = 5638 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5639 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5640 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5641 NoItinerary, 5642 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5643 Requires<[IsARM, NoVFP]>; 5644} 5645 5646// FIXME: Non-IOS version(s) 5647let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5648 Defs = [ R7, LR, SP ] in { 5649def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5650 NoItinerary, 5651 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5652 Requires<[IsARM]>; 5653} 5654 5655let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in 5656def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary, 5657 [(ARMeh_sjlj_setup_dispatch)]>; 5658 5659// eh.sjlj.dispatchsetup pseudo-instruction. 5660// This pseudo is used for both ARM and Thumb. Any differences are handled when 5661// the pseudo is expanded (which happens before any passes that need the 5662// instruction size). 5663let isBarrier = 1 in 5664def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5665 5666 5667//===----------------------------------------------------------------------===// 5668// Non-Instruction Patterns 5669// 5670 5671// ARMv4 indirect branch using (MOVr PC, dst) 5672let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5673 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5674 4, IIC_Br, [(brind GPR:$dst)], 5675 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5676 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5677 5678let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in 5679 def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst), 5680 4, IIC_Br, [], 5681 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5682 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5683 5684// Large immediate handling. 5685 5686// 32-bit immediate using two piece mod_imms or movw + movt. 5687// This is a single pseudo instruction, the benefit is that it can be remat'd 5688// as a single unit instead of having to handle reg inputs. 5689// FIXME: Remove this when we can do generalized remat. 5690let isReMaterializable = 1, isMoveImm = 1 in 5691def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5692 [(set GPR:$dst, (arm_i32imm:$src))]>, 5693 Requires<[IsARM]>; 5694 5695def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, 5696 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, 5697 Requires<[IsARM, DontUseMovt]>; 5698 5699// Pseudo instruction that combines movw + movt + add pc (if PIC). 5700// It also makes it possible to rematerialize the instructions. 5701// FIXME: Remove this when we can do generalized remat and when machine licm 5702// can properly the instructions. 5703let isReMaterializable = 1 in { 5704def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5705 IIC_iMOVix2addpc, 5706 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5707 Requires<[IsARM, UseMovtInPic]>; 5708 5709def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5710 IIC_iLoadiALU, 5711 [(set GPR:$dst, 5712 (ARMWrapperPIC tglobaladdr:$addr))]>, 5713 Requires<[IsARM, DontUseMovtInPic]>; 5714 5715let AddedComplexity = 10 in 5716def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5717 NoItinerary, 5718 [(set GPR:$dst, 5719 (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5720 Requires<[IsARM, DontUseMovtInPic]>; 5721 5722let AddedComplexity = 10 in 5723def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5724 IIC_iMOVix2ld, 5725 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5726 Requires<[IsARM, UseMovtInPic]>; 5727} // isReMaterializable 5728 5729// The many different faces of TLS access. 5730def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst), 5731 (MOVi32imm tglobaltlsaddr :$dst)>, 5732 Requires<[IsARM, UseMovt]>; 5733 5734def : Pat<(ARMWrapper tglobaltlsaddr:$src), 5735 (LDRLIT_ga_abs tglobaltlsaddr:$src)>, 5736 Requires<[IsARM, DontUseMovt]>; 5737 5738def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5739 (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovtInPic]>; 5740 5741def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5742 (LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 5743 Requires<[IsARM, DontUseMovtInPic]>; 5744let AddedComplexity = 10 in 5745def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)), 5746 (MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>, 5747 Requires<[IsARM, UseMovtInPic]>; 5748 5749 5750// ConstantPool, GlobalAddress, and JumpTable 5751def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 5752def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 5753 Requires<[IsARM, UseMovt]>; 5754def : ARMPat<(ARMWrapper texternalsym :$dst), (MOVi32imm texternalsym :$dst)>, 5755 Requires<[IsARM, UseMovt]>; 5756def : ARMPat<(ARMWrapperJT tjumptable:$dst), 5757 (LEApcrelJT tjumptable:$dst)>; 5758 5759// TODO: add,sub,and, 3-instr forms? 5760 5761// Tail calls. These patterns also apply to Thumb mode. 5762def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 5763def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 5764def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 5765 5766// Direct calls 5767def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 5768def : ARMPat<(ARMcall_nolink texternalsym:$func), 5769 (BMOVPCB_CALL texternalsym:$func)>; 5770 5771// zextload i1 -> zextload i8 5772def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5773def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5774 5775// extload -> zextload 5776def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5777def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5778def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5779def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5780 5781def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 5782 5783def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 5784def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 5785 5786// smul* and smla* 5787def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 5788 (SMULBB GPR:$a, GPR:$b)>; 5789def : ARMV5TEPat<(mul sext_16_node:$a, (sext_bottom_16 GPR:$b)), 5790 (SMULBB GPR:$a, GPR:$b)>; 5791def : ARMV5TEPat<(mul sext_16_node:$a, (sext_top_16 GPR:$b)), 5792 (SMULBT GPR:$a, GPR:$b)>; 5793def : ARMV5TEPat<(mul (sext_top_16 GPR:$a), sext_16_node:$b), 5794 (SMULTB GPR:$a, GPR:$b)>; 5795def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, sext_16_node:$b)), 5796 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5797def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_bottom_16 GPR:$b))), 5798 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5799def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_top_16 GPR:$b))), 5800 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5801def : ARMV5MOPat<(add GPR:$acc, (mul (sext_top_16 GPR:$a), sext_16_node:$b)), 5802 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5803 5804def : ARMV5TEPat<(int_arm_smulbb GPR:$a, GPR:$b), 5805 (SMULBB GPR:$a, GPR:$b)>; 5806def : ARMV5TEPat<(int_arm_smulbt GPR:$a, GPR:$b), 5807 (SMULBT GPR:$a, GPR:$b)>; 5808def : ARMV5TEPat<(int_arm_smultb GPR:$a, GPR:$b), 5809 (SMULTB GPR:$a, GPR:$b)>; 5810def : ARMV5TEPat<(int_arm_smultt GPR:$a, GPR:$b), 5811 (SMULTT GPR:$a, GPR:$b)>; 5812def : ARMV5TEPat<(int_arm_smulwb GPR:$a, GPR:$b), 5813 (SMULWB GPR:$a, GPR:$b)>; 5814def : ARMV5TEPat<(int_arm_smulwt GPR:$a, GPR:$b), 5815 (SMULWT GPR:$a, GPR:$b)>; 5816 5817def : ARMV5TEPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc), 5818 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5819def : ARMV5TEPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc), 5820 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5821def : ARMV5TEPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc), 5822 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5823def : ARMV5TEPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc), 5824 (SMLATT GPR:$a, GPR:$b, GPR:$acc)>; 5825def : ARMV5TEPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc), 5826 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 5827def : ARMV5TEPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc), 5828 (SMLAWT GPR:$a, GPR:$b, GPR:$acc)>; 5829 5830// Pre-v7 uses MCR for synchronization barriers. 5831def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 5832 Requires<[IsARM, HasV6]>; 5833 5834// SXT/UXT with no rotate 5835let AddedComplexity = 16 in { 5836def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 5837def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 5838def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 5839def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 5840 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 5841def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 5842 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 5843} 5844 5845def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 5846def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 5847 5848def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 5849 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 5850def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 5851 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 5852 5853// Atomic load/store patterns 5854def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 5855 (LDRBrs ldst_so_reg:$src)>; 5856def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 5857 (LDRBi12 addrmode_imm12:$src)>; 5858def : ARMPat<(atomic_load_16 addrmode3:$src), 5859 (LDRH addrmode3:$src)>; 5860def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 5861 (LDRrs ldst_so_reg:$src)>; 5862def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 5863 (LDRi12 addrmode_imm12:$src)>; 5864def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 5865 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 5866def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 5867 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 5868def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 5869 (STRH GPR:$val, addrmode3:$ptr)>; 5870def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 5871 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 5872def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 5873 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 5874 5875 5876//===----------------------------------------------------------------------===// 5877// Thumb Support 5878// 5879 5880include "ARMInstrThumb.td" 5881 5882//===----------------------------------------------------------------------===// 5883// Thumb2 Support 5884// 5885 5886include "ARMInstrThumb2.td" 5887 5888//===----------------------------------------------------------------------===// 5889// Floating Point Support 5890// 5891 5892include "ARMInstrVFP.td" 5893 5894//===----------------------------------------------------------------------===// 5895// Advanced SIMD (NEON) Support 5896// 5897 5898include "ARMInstrNEON.td" 5899 5900//===----------------------------------------------------------------------===// 5901// MVE Support 5902// 5903 5904include "ARMInstrMVE.td" 5905 5906//===----------------------------------------------------------------------===// 5907// Assembler aliases 5908// 5909 5910// Memory barriers 5911def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>; 5912def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>; 5913def : InstAlias<"ssbb", (DSB 0x0), 1>, Requires<[IsARM, HasDB]>; 5914def : InstAlias<"pssbb", (DSB 0x4), 1>, Requires<[IsARM, HasDB]>; 5915def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>; 5916// Armv8-R 'Data Full Barrier' 5917def : InstAlias<"dfb", (DSB 0xc), 1>, Requires<[IsARM, HasDFB]>; 5918 5919// System instructions 5920def : MnemonicAlias<"swi", "svc">; 5921 5922// Load / Store Multiple 5923def : MnemonicAlias<"ldmfd", "ldm">; 5924def : MnemonicAlias<"ldmia", "ldm">; 5925def : MnemonicAlias<"ldmea", "ldmdb">; 5926def : MnemonicAlias<"stmfd", "stmdb">; 5927def : MnemonicAlias<"stmia", "stm">; 5928def : MnemonicAlias<"stmea", "stm">; 5929 5930// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the 5931// input operands swapped when the shift amount is zero (i.e., unspecified). 5932def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 5933 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>, 5934 Requires<[IsARM, HasV6]>; 5935def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 5936 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>, 5937 Requires<[IsARM, HasV6]>; 5938 5939// PUSH/POP aliases for STM/LDM 5940def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 5941def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 5942 5943// SSAT/USAT optional shift operand. 5944def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 5945 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5946def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 5947 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5948 5949 5950// Extend instruction optional rotate operand. 5951def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 5952 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5953def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 5954 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5955def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 5956 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5957def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 5958 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5959def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 5960 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5961def : ARMInstAlias<"sxth${p} $Rd, $Rm", 5962 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5963 5964def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 5965 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5966def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 5967 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5968def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 5969 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5970def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 5971 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5972def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 5973 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5974def : ARMInstAlias<"uxth${p} $Rd, $Rm", 5975 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5976 5977 5978// RFE aliases 5979def : MnemonicAlias<"rfefa", "rfeda">; 5980def : MnemonicAlias<"rfeea", "rfedb">; 5981def : MnemonicAlias<"rfefd", "rfeia">; 5982def : MnemonicAlias<"rfeed", "rfeib">; 5983def : MnemonicAlias<"rfe", "rfeia">; 5984 5985// SRS aliases 5986def : MnemonicAlias<"srsfa", "srsib">; 5987def : MnemonicAlias<"srsea", "srsia">; 5988def : MnemonicAlias<"srsfd", "srsdb">; 5989def : MnemonicAlias<"srsed", "srsda">; 5990def : MnemonicAlias<"srs", "srsia">; 5991 5992// QSAX == QSUBADDX 5993def : MnemonicAlias<"qsubaddx", "qsax">; 5994// SASX == SADDSUBX 5995def : MnemonicAlias<"saddsubx", "sasx">; 5996// SHASX == SHADDSUBX 5997def : MnemonicAlias<"shaddsubx", "shasx">; 5998// SHSAX == SHSUBADDX 5999def : MnemonicAlias<"shsubaddx", "shsax">; 6000// SSAX == SSUBADDX 6001def : MnemonicAlias<"ssubaddx", "ssax">; 6002// UASX == UADDSUBX 6003def : MnemonicAlias<"uaddsubx", "uasx">; 6004// UHASX == UHADDSUBX 6005def : MnemonicAlias<"uhaddsubx", "uhasx">; 6006// UHSAX == UHSUBADDX 6007def : MnemonicAlias<"uhsubaddx", "uhsax">; 6008// UQASX == UQADDSUBX 6009def : MnemonicAlias<"uqaddsubx", "uqasx">; 6010// UQSAX == UQSUBADDX 6011def : MnemonicAlias<"uqsubaddx", "uqsax">; 6012// USAX == USUBADDX 6013def : MnemonicAlias<"usubaddx", "usax">; 6014 6015// "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like 6016// for isel. 6017def : ARMInstSubst<"mov${s}${p} $Rd, $imm", 6018 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6019def : ARMInstSubst<"mvn${s}${p} $Rd, $imm", 6020 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6021// Same for AND <--> BIC 6022def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm", 6023 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6024 pred:$p, cc_out:$s)>; 6025def : ARMInstSubst<"bic${s}${p} $Rdn, $imm", 6026 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6027 pred:$p, cc_out:$s)>; 6028def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm", 6029 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6030 pred:$p, cc_out:$s)>; 6031def : ARMInstSubst<"and${s}${p} $Rdn, $imm", 6032 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6033 pred:$p, cc_out:$s)>; 6034 6035// Likewise, "add Rd, mod_imm_neg" -> sub 6036def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm", 6037 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6038def : ARMInstSubst<"add${s}${p} $Rd, $imm", 6039 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6040// Likewise, "sub Rd, mod_imm_neg" -> add 6041def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm", 6042 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6043def : ARMInstSubst<"sub${s}${p} $Rd, $imm", 6044 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6045 6046 6047def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm", 6048 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6049def : ARMInstSubst<"adc${s}${p} $Rdn, $imm", 6050 (SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6051def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm", 6052 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6053def : ARMInstSubst<"sbc${s}${p} $Rdn, $imm", 6054 (ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6055 6056// Same for CMP <--> CMN via mod_imm_neg 6057def : ARMInstSubst<"cmp${p} $Rd, $imm", 6058 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6059def : ARMInstSubst<"cmn${p} $Rd, $imm", 6060 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6061 6062// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 6063// LSR, ROR, and RRX instructions. 6064// FIXME: We need C++ parser hooks to map the alias to the MOV 6065// encoding. It seems we should be able to do that sort of thing 6066// in tblgen, but it could get ugly. 6067let TwoOperandAliasConstraint = "$Rm = $Rd" in { 6068def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 6069 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6070 cc_out:$s)>; 6071def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 6072 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6073 cc_out:$s)>; 6074def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 6075 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6076 cc_out:$s)>; 6077def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 6078 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6079 cc_out:$s)>; 6080} 6081def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 6082 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 6083let TwoOperandAliasConstraint = "$Rn = $Rd" in { 6084def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 6085 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6086 cc_out:$s)>; 6087def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 6088 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6089 cc_out:$s)>; 6090def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 6091 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6092 cc_out:$s)>; 6093def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 6094 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6095 cc_out:$s)>; 6096} 6097 6098// "neg" is and alias for "rsb rd, rn, #0" 6099def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 6100 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 6101 6102// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 6103def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 6104 Requires<[IsARM, NoV6]>; 6105 6106// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 6107// the instruction definitions need difference constraints pre-v6. 6108// Use these aliases for the assembly parsing on pre-v6. 6109def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", 6110 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>, 6111 Requires<[IsARM, NoV6]>; 6112def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", 6113 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 6114 pred:$p, cc_out:$s), 0>, 6115 Requires<[IsARM, NoV6]>; 6116def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6117 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6118 Requires<[IsARM, NoV6]>; 6119def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6120 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6121 Requires<[IsARM, NoV6]>; 6122def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6123 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6124 Requires<[IsARM, NoV6]>; 6125def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6126 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6127 Requires<[IsARM, NoV6]>; 6128 6129// 'it' blocks in ARM mode just validate the predicates. The IT itself 6130// is discarded. 6131def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 6132 ComplexDeprecationPredicate<"IT">; 6133 6134let mayLoad = 1, mayStore =1, hasSideEffects = 1 in 6135def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn), 6136 NoItinerary, 6137 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>; 6138 6139//===---------------------------------- 6140// Atomic cmpxchg for -O0 6141//===---------------------------------- 6142 6143// The fast register allocator used during -O0 inserts spills to cover any VRegs 6144// live across basic block boundaries. When this happens between an LDXR and an 6145// STXR it can clear the exclusive monitor, causing all cmpxchg attempts to 6146// fail. 6147 6148// Unfortunately, this means we have to have an alternative (expanded 6149// post-regalloc) path for -O0 compilations. Fortunately this path can be 6150// significantly more naive than the standard expansion: we conservatively 6151// assume seq_cst, strong cmpxchg and omit clrex on failure. 6152 6153let Constraints = "@earlyclobber $Rd,@earlyclobber $temp", 6154 mayLoad = 1, mayStore = 1 in { 6155def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6156 (ins GPR:$addr, GPR:$desired, GPR:$new), 6157 NoItinerary, []>, Sched<[]>; 6158 6159def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6160 (ins GPR:$addr, GPR:$desired, GPR:$new), 6161 NoItinerary, []>, Sched<[]>; 6162 6163def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6164 (ins GPR:$addr, GPR:$desired, GPR:$new), 6165 NoItinerary, []>, Sched<[]>; 6166 6167def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp), 6168 (ins GPR:$addr, GPRPair:$desired, GPRPair:$new), 6169 NoItinerary, []>, Sched<[]>; 6170} 6171 6172def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary, 6173 [(atomic_fence imm:$ordering, 0)]> { 6174 let hasSideEffects = 1; 6175 let Size = 0; 6176 let AsmString = "@ COMPILER BARRIER"; 6177} 6178