1*0b57cec5SDimitry Andric //===-- ARMInstrInfo.h - ARM Instruction Information ------------*- C++ -*-===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric // 9*0b57cec5SDimitry Andric // This file contains the ARM implementation of the TargetInstrInfo class. 10*0b57cec5SDimitry Andric // 11*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_ARM_ARMINSTRINFO_H 14*0b57cec5SDimitry Andric #define LLVM_LIB_TARGET_ARM_ARMINSTRINFO_H 15*0b57cec5SDimitry Andric 16*0b57cec5SDimitry Andric #include "ARMBaseInstrInfo.h" 17*0b57cec5SDimitry Andric #include "ARMRegisterInfo.h" 18*0b57cec5SDimitry Andric 19*0b57cec5SDimitry Andric namespace llvm { 20*0b57cec5SDimitry Andric class ARMSubtarget; 21*0b57cec5SDimitry Andric 22*0b57cec5SDimitry Andric class ARMInstrInfo : public ARMBaseInstrInfo { 23*0b57cec5SDimitry Andric ARMRegisterInfo RI; 24*0b57cec5SDimitry Andric public: 25*0b57cec5SDimitry Andric explicit ARMInstrInfo(const ARMSubtarget &STI); 26*0b57cec5SDimitry Andric 27*0b57cec5SDimitry Andric /// Return the noop instruction to use for a noop. 28*0b57cec5SDimitry Andric void getNoop(MCInst &NopInst) const override; 29*0b57cec5SDimitry Andric 30*0b57cec5SDimitry Andric // Return the non-pre/post incrementing version of 'Opc'. Return 0 31*0b57cec5SDimitry Andric // if there is not such an opcode. 32*0b57cec5SDimitry Andric unsigned getUnindexedOpcode(unsigned Opc) const override; 33*0b57cec5SDimitry Andric 34*0b57cec5SDimitry Andric /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 35*0b57cec5SDimitry Andric /// such, whenever a client has an instance of instruction info, it should 36*0b57cec5SDimitry Andric /// always be able to get register info as well (through this method). 37*0b57cec5SDimitry Andric /// 38*0b57cec5SDimitry Andric const ARMRegisterInfo &getRegisterInfo() const override { return RI; } 39*0b57cec5SDimitry Andric 40*0b57cec5SDimitry Andric private: 41*0b57cec5SDimitry Andric void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override; 42*0b57cec5SDimitry Andric }; 43*0b57cec5SDimitry Andric 44*0b57cec5SDimitry Andric } 45*0b57cec5SDimitry Andric 46*0b57cec5SDimitry Andric #endif 47