1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that ARM uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 15 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 16 17 #include "MCTargetDesc/ARMBaseInfo.h" 18 #include "llvm/ADT/SmallVector.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/CodeGen/CallingConvLower.h" 21 #include "llvm/CodeGen/ISDOpcodes.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/SelectionDAGNodes.h" 24 #include "llvm/CodeGen/TargetLowering.h" 25 #include "llvm/CodeGen/ValueTypes.h" 26 #include "llvm/IR/Attributes.h" 27 #include "llvm/IR/CallingConv.h" 28 #include "llvm/IR/Function.h" 29 #include "llvm/IR/IRBuilder.h" 30 #include "llvm/IR/InlineAsm.h" 31 #include "llvm/Support/CodeGen.h" 32 #include "llvm/Support/MachineValueType.h" 33 #include <utility> 34 35 namespace llvm { 36 37 class ARMSubtarget; 38 class DataLayout; 39 class FastISel; 40 class FunctionLoweringInfo; 41 class GlobalValue; 42 class InstrItineraryData; 43 class Instruction; 44 class MachineBasicBlock; 45 class MachineInstr; 46 class SelectionDAG; 47 class TargetLibraryInfo; 48 class TargetMachine; 49 class TargetRegisterInfo; 50 class VectorType; 51 52 namespace ARMISD { 53 54 // ARM Specific DAG Nodes 55 enum NodeType : unsigned { 56 // Start the numbering where the builtin ops and target ops leave off. 57 FIRST_NUMBER = ISD::BUILTIN_OP_END, 58 59 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 60 // TargetExternalSymbol, and TargetGlobalAddress. 61 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 62 // PIC mode. 63 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 64 65 // Add pseudo op to model memcpy for struct byval. 66 COPY_STRUCT_BYVAL, 67 68 CALL, // Function call. 69 CALL_PRED, // Function call that's predicable. 70 CALL_NOLINK, // Function call with branch not branch-and-link. 71 tSECALL, // CMSE non-secure function call. 72 BRCOND, // Conditional branch. 73 BR_JT, // Jumptable branch. 74 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 75 RET_FLAG, // Return with a flag operand. 76 SERET_FLAG, // CMSE Entry function return with a flag operand. 77 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand. 78 79 PIC_ADD, // Add with a PC operand and a PIC label. 80 81 ASRL, // MVE long arithmetic shift right. 82 LSRL, // MVE long shift right. 83 LSLL, // MVE long shift left. 84 85 CMP, // ARM compare instructions. 86 CMN, // ARM CMN instructions. 87 CMPZ, // ARM compare that sets only Z flag. 88 CMPFP, // ARM VFP compare instruction, sets FPSCR. 89 CMPFPE, // ARM VFP signalling compare instruction, sets FPSCR. 90 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 91 CMPFPEw0, // ARM VFP signalling compare against zero instruction, sets 92 // FPSCR. 93 FMSTAT, // ARM fmstat instruction. 94 95 CMOV, // ARM conditional move instructions. 96 SUBS, // Flag-setting subtraction. 97 98 SSAT, // Signed saturation 99 USAT, // Unsigned saturation 100 101 BCC_i64, 102 103 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 104 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 105 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 106 107 ADDC, // Add with carry 108 ADDE, // Add using carry 109 SUBC, // Sub with carry 110 SUBE, // Sub using carry 111 LSLS, // Shift left producing carry 112 113 VMOVRRD, // double to two gprs. 114 VMOVDRR, // Two gprs to double. 115 VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr 116 117 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 118 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 119 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch. 120 121 TC_RETURN, // Tail call return pseudo. 122 123 THREAD_POINTER, 124 125 DYN_ALLOC, // Dynamic allocation on the stack. 126 127 MEMBARRIER_MCR, // Memory barrier (MCR) 128 129 PRELOAD, // Preload 130 131 WIN__CHKSTK, // Windows' __chkstk call to do stack probing. 132 WIN__DBZCHK, // Windows' divide by zero check 133 134 WLS, // Low-overhead loops, While Loop Start branch. See t2WhileLoopStart 135 WLSSETUP, // Setup for the iteration count of a WLS. See t2WhileLoopSetup. 136 LOOP_DEC, // Really a part of LE, performs the sub 137 LE, // Low-overhead loops, Loop End 138 139 PREDICATE_CAST, // Predicate cast for MVE i1 types 140 VECTOR_REG_CAST, // Reinterpret the current contents of a vector register 141 142 MVESEXT, // Legalization aids for extending a vector into two/four vectors. 143 MVEZEXT, // or truncating two/four vectors into one. Eventually becomes 144 MVETRUNC, // stack store/load sequence, if not optimized to anything else. 145 146 VCMP, // Vector compare. 147 VCMPZ, // Vector compare to zero. 148 VTST, // Vector test bits. 149 150 // Vector shift by vector 151 VSHLs, // ...left/right by signed 152 VSHLu, // ...left/right by unsigned 153 154 // Vector shift by immediate: 155 VSHLIMM, // ...left 156 VSHRsIMM, // ...right (signed) 157 VSHRuIMM, // ...right (unsigned) 158 159 // Vector rounding shift by immediate: 160 VRSHRsIMM, // ...right (signed) 161 VRSHRuIMM, // ...right (unsigned) 162 VRSHRNIMM, // ...right narrow 163 164 // Vector saturating shift by immediate: 165 VQSHLsIMM, // ...left (signed) 166 VQSHLuIMM, // ...left (unsigned) 167 VQSHLsuIMM, // ...left (signed to unsigned) 168 VQSHRNsIMM, // ...right narrow (signed) 169 VQSHRNuIMM, // ...right narrow (unsigned) 170 VQSHRNsuIMM, // ...right narrow (signed to unsigned) 171 172 // Vector saturating rounding shift by immediate: 173 VQRSHRNsIMM, // ...right narrow (signed) 174 VQRSHRNuIMM, // ...right narrow (unsigned) 175 VQRSHRNsuIMM, // ...right narrow (signed to unsigned) 176 177 // Vector shift and insert: 178 VSLIIMM, // ...left 179 VSRIIMM, // ...right 180 181 // Vector get lane (VMOV scalar to ARM core register) 182 // (These are used for 8- and 16-bit element types only.) 183 VGETLANEu, // zero-extend vector extract element 184 VGETLANEs, // sign-extend vector extract element 185 186 // Vector move immediate and move negated immediate: 187 VMOVIMM, 188 VMVNIMM, 189 190 // Vector move f32 immediate: 191 VMOVFPIMM, 192 193 // Move H <-> R, clearing top 16 bits 194 VMOVrh, 195 VMOVhr, 196 197 // Vector duplicate: 198 VDUP, 199 VDUPLANE, 200 201 // Vector shuffles: 202 VEXT, // extract 203 VREV64, // reverse elements within 64-bit doublewords 204 VREV32, // reverse elements within 32-bit words 205 VREV16, // reverse elements within 16-bit halfwords 206 VZIP, // zip (interleave) 207 VUZP, // unzip (deinterleave) 208 VTRN, // transpose 209 VTBL1, // 1-register shuffle with mask 210 VTBL2, // 2-register shuffle with mask 211 VMOVN, // MVE vmovn 212 213 // MVE Saturating truncates 214 VQMOVNs, // Vector (V) Saturating (Q) Move and Narrow (N), signed (s) 215 VQMOVNu, // Vector (V) Saturating (Q) Move and Narrow (N), unsigned (u) 216 217 // MVE float <> half converts 218 VCVTN, // MVE vcvt f32 -> f16, truncating into either the bottom or top 219 // lanes 220 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes 221 222 // MVE VIDUP instruction, taking a start value and increment. 223 VIDUP, 224 225 // Vector multiply long: 226 VMULLs, // ...signed 227 VMULLu, // ...unsigned 228 229 VQDMULH, // MVE vqdmulh instruction 230 231 // MVE reductions 232 VADDVs, // sign- or zero-extend the elements of a vector to i32, 233 VADDVu, // add them all together, and return an i32 of their sum 234 VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask 235 VADDVpu, 236 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning 237 VADDLVu, // the low and high 32-bit halves of the sum 238 VADDLVAs, // Same as VADDLV[su] but also add an input accumulator 239 VADDLVAu, // provided as low and high halves 240 VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask 241 VADDLVpu, 242 VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask 243 VADDLVApu, 244 VMLAVs, // sign- or zero-extend the elements of two vectors to i32, multiply 245 // them 246 VMLAVu, // and add the results together, returning an i32 of their sum 247 VMLAVps, // Same as VMLAV[su] with a v4i1 predicate mask 248 VMLAVpu, 249 VMLALVs, // Same as VMLAV but with i64, returning the low and 250 VMLALVu, // high 32-bit halves of the sum 251 VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask 252 VMLALVpu, 253 VMLALVAs, // Same as VMLALV but also add an input accumulator 254 VMLALVAu, // provided as low and high halves 255 VMLALVAps, // Same as VMLALVA[su] with a v4i1 predicate mask 256 VMLALVApu, 257 VMINVu, // Find minimum unsigned value of a vector and register 258 VMINVs, // Find minimum signed value of a vector and register 259 VMAXVu, // Find maximum unsigned value of a vector and register 260 VMAXVs, // Find maximum signed value of a vector and register 261 262 SMULWB, // Signed multiply word by half word, bottom 263 SMULWT, // Signed multiply word by half word, top 264 UMLAL, // 64bit Unsigned Accumulate Multiply 265 SMLAL, // 64bit Signed Accumulate Multiply 266 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply 267 SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16 268 SMLALBT, // 64-bit signed accumulate multiply bottom, top 16 269 SMLALTB, // 64-bit signed accumulate multiply top, bottom 16 270 SMLALTT, // 64-bit signed accumulate multiply top, top 16 271 SMLALD, // Signed multiply accumulate long dual 272 SMLALDX, // Signed multiply accumulate long dual exchange 273 SMLSLD, // Signed multiply subtract long dual 274 SMLSLDX, // Signed multiply subtract long dual exchange 275 SMMLAR, // Signed multiply long, round and add 276 SMMLSR, // Signed multiply long, subtract and round 277 278 // Single Lane QADD8 and QADD16. Only the bottom lane. That's what the b 279 // stands for. 280 QADD8b, 281 QSUB8b, 282 QADD16b, 283 QSUB16b, 284 UQADD8b, 285 UQSUB8b, 286 UQADD16b, 287 UQSUB16b, 288 289 // Operands of the standard BUILD_VECTOR node are not legalized, which 290 // is fine if BUILD_VECTORs are always lowered to shuffles or other 291 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 292 // operands need to be legalized. Define an ARM-specific version of 293 // BUILD_VECTOR for this purpose. 294 BUILD_VECTOR, 295 296 // Bit-field insert 297 BFI, 298 299 // Vector OR with immediate 300 VORRIMM, 301 // Vector AND with NOT of immediate 302 VBICIMM, 303 304 // Pseudo vector bitwise select 305 VBSP, 306 307 // Pseudo-instruction representing a memory copy using ldm/stm 308 // instructions. 309 MEMCPY, 310 311 // Pseudo-instruction representing a memory copy using a tail predicated 312 // loop 313 MEMCPYLOOP, 314 // Pseudo-instruction representing a memset using a tail predicated 315 // loop 316 MEMSETLOOP, 317 318 // V8.1MMainline condition select 319 CSINV, // Conditional select invert. 320 CSNEG, // Conditional select negate. 321 CSINC, // Conditional select increment. 322 323 // Vector load N-element structure to all lanes: 324 VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, 325 VLD2DUP, 326 VLD3DUP, 327 VLD4DUP, 328 329 // NEON loads with post-increment base updates: 330 VLD1_UPD, 331 VLD2_UPD, 332 VLD3_UPD, 333 VLD4_UPD, 334 VLD2LN_UPD, 335 VLD3LN_UPD, 336 VLD4LN_UPD, 337 VLD1DUP_UPD, 338 VLD2DUP_UPD, 339 VLD3DUP_UPD, 340 VLD4DUP_UPD, 341 VLD1x2_UPD, 342 VLD1x3_UPD, 343 VLD1x4_UPD, 344 345 // NEON stores with post-increment base updates: 346 VST1_UPD, 347 VST2_UPD, 348 VST3_UPD, 349 VST4_UPD, 350 VST2LN_UPD, 351 VST3LN_UPD, 352 VST4LN_UPD, 353 VST1x2_UPD, 354 VST1x3_UPD, 355 VST1x4_UPD, 356 357 // Load/Store of dual registers 358 LDRD, 359 STRD 360 }; 361 362 } // end namespace ARMISD 363 364 namespace ARM { 365 /// Possible values of current rounding mode, which is specified in bits 366 /// 23:22 of FPSCR. 367 enum Rounding { 368 RN = 0, // Round to Nearest 369 RP = 1, // Round towards Plus infinity 370 RM = 2, // Round towards Minus infinity 371 RZ = 3, // Round towards Zero 372 rmMask = 3 // Bit mask selecting rounding mode 373 }; 374 375 // Bit position of rounding mode bits in FPSCR. 376 const unsigned RoundingBitsPos = 22; 377 } // namespace ARM 378 379 /// Define some predicates that are used for node matching. 380 namespace ARM { 381 382 bool isBitFieldInvertedMask(unsigned v); 383 384 } // end namespace ARM 385 386 //===--------------------------------------------------------------------===// 387 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 388 389 class ARMTargetLowering : public TargetLowering { 390 public: 391 explicit ARMTargetLowering(const TargetMachine &TM, 392 const ARMSubtarget &STI); 393 394 unsigned getJumpTableEncoding() const override; 395 bool useSoftFloat() const override; 396 397 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 398 399 /// ReplaceNodeResults - Replace the results of node with an illegal result 400 /// type with new values built out of custom code. 401 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 402 SelectionDAG &DAG) const override; 403 404 const char *getTargetNodeName(unsigned Opcode) const override; 405 406 bool isSelectSupported(SelectSupportKind Kind) const override { 407 // ARM does not support scalar condition selects on vectors. 408 return (Kind != ScalarCondVectorVal); 409 } 410 411 bool isReadOnly(const GlobalValue *GV) const; 412 413 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 414 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 415 EVT VT) const override; 416 417 MachineBasicBlock * 418 EmitInstrWithCustomInserter(MachineInstr &MI, 419 MachineBasicBlock *MBB) const override; 420 421 void AdjustInstrPostInstrSelection(MachineInstr &MI, 422 SDNode *Node) const override; 423 424 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 425 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const; 426 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const; 427 SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const; 428 SDValue PerformMVEExtCombine(SDNode *N, DAGCombinerInfo &DCI) const; 429 SDValue PerformMVETruncCombine(SDNode *N, DAGCombinerInfo &DCI) const; 430 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 431 432 bool SimplifyDemandedBitsForTargetNode(SDValue Op, 433 const APInt &OriginalDemandedBits, 434 const APInt &OriginalDemandedElts, 435 KnownBits &Known, 436 TargetLoweringOpt &TLO, 437 unsigned Depth) const override; 438 439 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override; 440 441 /// allowsMisalignedMemoryAccesses - Returns true if the target allows 442 /// unaligned memory accesses of the specified type. Returns whether it 443 /// is "fast" by reference in the second argument. 444 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, 445 Align Alignment, 446 MachineMemOperand::Flags Flags, 447 bool *Fast) const override; 448 449 EVT getOptimalMemOpType(const MemOp &Op, 450 const AttributeList &FuncAttributes) const override; 451 452 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 453 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 454 bool isZExtFree(SDValue Val, EVT VT2) const override; 455 bool shouldSinkOperands(Instruction *I, 456 SmallVectorImpl<Use *> &Ops) const override; 457 Type* shouldConvertSplatType(ShuffleVectorInst* SVI) const override; 458 459 bool isFNegFree(EVT VT) const override; 460 461 bool isVectorLoadExtDesirable(SDValue ExtVal) const override; 462 463 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override; 464 465 466 /// isLegalAddressingMode - Return true if the addressing mode represented 467 /// by AM is legal for this target, for a load/store of the specified type. 468 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 469 Type *Ty, unsigned AS, 470 Instruction *I = nullptr) const override; 471 472 /// getScalingFactorCost - Return the cost of the scaling used in 473 /// addressing mode represented by AM. 474 /// If the AM is supported, the return value must be >= 0. 475 /// If the AM is not supported, the return value must be negative. 476 InstructionCost getScalingFactorCost(const DataLayout &DL, 477 const AddrMode &AM, Type *Ty, 478 unsigned AS) const override; 479 480 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 481 482 /// Returns true if the addressing mode representing by AM is legal 483 /// for the Thumb1 target, for a load/store of the specified type. 484 bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 485 486 /// isLegalICmpImmediate - Return true if the specified immediate is legal 487 /// icmp immediate, that is the target has icmp instructions which can 488 /// compare a register against the immediate without having to materialize 489 /// the immediate into a register. 490 bool isLegalICmpImmediate(int64_t Imm) const override; 491 492 /// isLegalAddImmediate - Return true if the specified immediate is legal 493 /// add immediate, that is the target has add instructions which can 494 /// add a register and the immediate without having to materialize 495 /// the immediate into a register. 496 bool isLegalAddImmediate(int64_t Imm) const override; 497 498 /// getPreIndexedAddressParts - returns true by value, base pointer and 499 /// offset pointer and addressing mode by reference if the node's address 500 /// can be legally represented as pre-indexed load / store address. 501 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 502 ISD::MemIndexedMode &AM, 503 SelectionDAG &DAG) const override; 504 505 /// getPostIndexedAddressParts - returns true by value, base pointer and 506 /// offset pointer and addressing mode by reference if this node can be 507 /// combined with a load / store to form a post-indexed load / store. 508 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 509 SDValue &Offset, ISD::MemIndexedMode &AM, 510 SelectionDAG &DAG) const override; 511 512 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 513 const APInt &DemandedElts, 514 const SelectionDAG &DAG, 515 unsigned Depth) const override; 516 517 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 518 const APInt &DemandedElts, 519 TargetLoweringOpt &TLO) const override; 520 521 bool ExpandInlineAsm(CallInst *CI) const override; 522 523 ConstraintType getConstraintType(StringRef Constraint) const override; 524 525 /// Examine constraint string and operand type and determine a weight value. 526 /// The operand object must already have been set up with the operand type. 527 ConstraintWeight getSingleConstraintMatchWeight( 528 AsmOperandInfo &info, const char *constraint) const override; 529 530 std::pair<unsigned, const TargetRegisterClass *> 531 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 532 StringRef Constraint, MVT VT) const override; 533 534 const char *LowerXConstraint(EVT ConstraintVT) const override; 535 536 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 537 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 538 /// true it means one of the asm constraint of the inline asm instruction 539 /// being processed is 'm'. 540 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 541 std::vector<SDValue> &Ops, 542 SelectionDAG &DAG) const override; 543 544 unsigned 545 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 546 if (ConstraintCode == "Q") 547 return InlineAsm::Constraint_Q; 548 else if (ConstraintCode.size() == 2) { 549 if (ConstraintCode[0] == 'U') { 550 switch(ConstraintCode[1]) { 551 default: 552 break; 553 case 'm': 554 return InlineAsm::Constraint_Um; 555 case 'n': 556 return InlineAsm::Constraint_Un; 557 case 'q': 558 return InlineAsm::Constraint_Uq; 559 case 's': 560 return InlineAsm::Constraint_Us; 561 case 't': 562 return InlineAsm::Constraint_Ut; 563 case 'v': 564 return InlineAsm::Constraint_Uv; 565 case 'y': 566 return InlineAsm::Constraint_Uy; 567 } 568 } 569 } 570 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 571 } 572 573 const ARMSubtarget* getSubtarget() const { 574 return Subtarget; 575 } 576 577 /// getRegClassFor - Return the register class that should be used for the 578 /// specified value type. 579 const TargetRegisterClass * 580 getRegClassFor(MVT VT, bool isDivergent = false) const override; 581 582 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, 583 unsigned &PrefAlign) const override; 584 585 /// createFastISel - This method returns a target specific FastISel object, 586 /// or null if the target does not support "fast" ISel. 587 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 588 const TargetLibraryInfo *libInfo) const override; 589 590 Sched::Preference getSchedulingPreference(SDNode *N) const override; 591 592 bool preferZeroCompareBranch() const override { return true; } 593 594 bool 595 isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 596 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 597 598 /// isFPImmLegal - Returns true if the target can instruction select the 599 /// specified FP immediate natively. If false, the legalizer will 600 /// materialize the FP immediate as a load from a constant pool. 601 bool isFPImmLegal(const APFloat &Imm, EVT VT, 602 bool ForCodeSize = false) const override; 603 604 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 605 const CallInst &I, 606 MachineFunction &MF, 607 unsigned Intrinsic) const override; 608 609 /// Returns true if it is beneficial to convert a load of a constant 610 /// to just the constant itself. 611 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 612 Type *Ty) const override; 613 614 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type 615 /// with this index. 616 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 617 unsigned Index) const override; 618 619 bool shouldFormOverflowOp(unsigned Opcode, EVT VT, 620 bool MathUsed) const override { 621 // Using overflow ops for overflow checks only should beneficial on ARM. 622 return TargetLowering::shouldFormOverflowOp(Opcode, VT, true); 623 } 624 625 /// Returns true if an argument of type Ty needs to be passed in a 626 /// contiguous block of registers in calling convention CallConv. 627 bool functionArgumentNeedsConsecutiveRegisters( 628 Type *Ty, CallingConv::ID CallConv, bool isVarArg, 629 const DataLayout &DL) const override; 630 631 /// If a physical register, this returns the register that receives the 632 /// exception address on entry to an EH pad. 633 Register 634 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 635 636 /// If a physical register, this returns the register that receives the 637 /// exception typeid on entry to a landing pad. 638 Register 639 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 640 641 Instruction *makeDMB(IRBuilderBase &Builder, ARM_MB::MemBOpt Domain) const; 642 Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, 643 AtomicOrdering Ord) const override; 644 Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, 645 AtomicOrdering Ord) const override; 646 647 void 648 emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override; 649 650 Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, 651 AtomicOrdering Ord) const override; 652 Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, 653 AtomicOrdering Ord) const override; 654 655 unsigned getMaxSupportedInterleaveFactor() const override; 656 657 bool lowerInterleavedLoad(LoadInst *LI, 658 ArrayRef<ShuffleVectorInst *> Shuffles, 659 ArrayRef<unsigned> Indices, 660 unsigned Factor) const override; 661 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, 662 unsigned Factor) const override; 663 664 bool shouldInsertFencesForAtomic(const Instruction *I) const override; 665 TargetLoweringBase::AtomicExpansionKind 666 shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 667 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 668 TargetLoweringBase::AtomicExpansionKind 669 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 670 TargetLoweringBase::AtomicExpansionKind 671 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 672 673 bool useLoadStackGuardNode() const override; 674 675 void insertSSPDeclarations(Module &M) const override; 676 Value *getSDagStackGuard(const Module &M) const override; 677 Function *getSSPStackGuardCheck(const Module &M) const override; 678 679 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, 680 unsigned &Cost) const override; 681 682 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, 683 const SelectionDAG &DAG) const override { 684 // Do not merge to larger than i32. 685 return (MemVT.getSizeInBits() <= 32); 686 } 687 688 bool isCheapToSpeculateCttz() const override; 689 bool isCheapToSpeculateCtlz() const override; 690 691 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 692 return VT.isScalarInteger(); 693 } 694 695 bool supportSwiftError() const override { 696 return true; 697 } 698 699 bool hasStandaloneRem(EVT VT) const override { 700 return HasStandaloneRem; 701 } 702 703 bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override; 704 705 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const; 706 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const; 707 708 /// Returns true if \p VecTy is a legal interleaved access type. This 709 /// function checks the vector element type and the overall width of the 710 /// vector. 711 bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy, 712 Align Alignment, 713 const DataLayout &DL) const; 714 715 bool alignLoopsWithOptSize() const override; 716 717 /// Returns the number of interleaved accesses that will be generated when 718 /// lowering accesses of the given type. 719 unsigned getNumInterleavedAccesses(VectorType *VecTy, 720 const DataLayout &DL) const; 721 722 void finalizeLowering(MachineFunction &MF) const override; 723 724 /// Return the correct alignment for the current calling convention. 725 Align getABIAlignmentForCallingConv(Type *ArgTy, 726 const DataLayout &DL) const override; 727 728 bool isDesirableToCommuteWithShift(const SDNode *N, 729 CombineLevel Level) const override; 730 731 bool shouldFoldConstantShiftPairToMask(const SDNode *N, 732 CombineLevel Level) const override; 733 734 bool preferIncOfAddToSubOfNot(EVT VT) const override; 735 736 protected: 737 std::pair<const TargetRegisterClass *, uint8_t> 738 findRepresentativeClass(const TargetRegisterInfo *TRI, 739 MVT VT) const override; 740 741 private: 742 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 743 /// make the right decision when generating code for different targets. 744 const ARMSubtarget *Subtarget; 745 746 const TargetRegisterInfo *RegInfo; 747 748 const InstrItineraryData *Itins; 749 750 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 751 unsigned ARMPCLabelIndex; 752 753 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper 754 // check. 755 bool InsertFencesForAtomic; 756 757 bool HasStandaloneRem = true; 758 759 void addTypeForNEON(MVT VT, MVT PromotedLdStVT); 760 void addDRTypeForNEON(MVT VT); 761 void addQRTypeForNEON(MVT VT); 762 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const; 763 764 using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>; 765 766 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, 767 SDValue &Arg, RegsToPassVector &RegsToPass, 768 CCValAssign &VA, CCValAssign &NextVA, 769 SDValue &StackPtr, 770 SmallVectorImpl<SDValue> &MemOpChains, 771 bool IsTailCall, 772 int SPDiff) const; 773 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 774 SDValue &Root, SelectionDAG &DAG, 775 const SDLoc &dl) const; 776 777 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC, 778 bool isVarArg) const; 779 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 780 bool isVarArg) const; 781 std::pair<SDValue, MachinePointerInfo> 782 computeAddrForCallArg(const SDLoc &dl, SelectionDAG &DAG, 783 const CCValAssign &VA, SDValue StackPtr, 784 bool IsTailCall, int SPDiff) const; 785 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 786 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 787 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const; 788 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG, 789 const ARMSubtarget *Subtarget) const; 790 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 791 const ARMSubtarget *Subtarget) const; 792 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 793 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 794 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 795 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 796 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 797 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const; 798 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 799 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 800 SelectionDAG &DAG) const; 801 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 802 SelectionDAG &DAG, 803 TLSModel::Model model) const; 804 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 805 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const; 806 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 807 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 808 SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const; 809 SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const; 810 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 811 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 812 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 813 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 814 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 815 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 816 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 817 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 818 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 819 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 820 SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 821 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, 822 const ARMSubtarget *ST) const; 823 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 824 const ARMSubtarget *ST) const; 825 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 826 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 827 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; 828 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const; 829 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed, 830 SmallVectorImpl<SDValue> &Results) const; 831 SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG, 832 const ARMSubtarget *Subtarget) const; 833 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed, 834 SDValue &Chain) const; 835 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const; 836 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 837 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 838 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 839 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 840 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 841 SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const; 842 void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results, 843 SelectionDAG &DAG) const; 844 void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results, 845 SelectionDAG &DAG) const; 846 847 Register getRegisterByName(const char* RegName, LLT VT, 848 const MachineFunction &MF) const override; 849 850 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 851 SmallVectorImpl<SDNode *> &Created) const override; 852 853 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 854 EVT VT) const override; 855 856 SDValue MoveToHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, MVT ValVT, 857 SDValue Val) const; 858 SDValue MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, 859 MVT ValVT, SDValue Val) const; 860 861 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 862 863 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 864 CallingConv::ID CallConv, bool isVarArg, 865 const SmallVectorImpl<ISD::InputArg> &Ins, 866 const SDLoc &dl, SelectionDAG &DAG, 867 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 868 SDValue ThisVal) const; 869 870 bool supportSplitCSR(MachineFunction *MF) const override { 871 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 872 MF->getFunction().hasFnAttribute(Attribute::NoUnwind); 873 } 874 875 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 876 void insertCopiesSplitCSR( 877 MachineBasicBlock *Entry, 878 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 879 880 bool 881 splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, 882 SDValue *Parts, unsigned NumParts, MVT PartVT, 883 Optional<CallingConv::ID> CC) const override; 884 885 SDValue 886 joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, 887 const SDValue *Parts, unsigned NumParts, 888 MVT PartVT, EVT ValueVT, 889 Optional<CallingConv::ID> CC) const override; 890 891 SDValue 892 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 893 const SmallVectorImpl<ISD::InputArg> &Ins, 894 const SDLoc &dl, SelectionDAG &DAG, 895 SmallVectorImpl<SDValue> &InVals) const override; 896 897 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl, 898 SDValue &Chain, const Value *OrigArg, 899 unsigned InRegsParamRecordIdx, int ArgOffset, 900 unsigned ArgSize) const; 901 902 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 903 const SDLoc &dl, SDValue &Chain, 904 unsigned ArgOffset, unsigned TotalArgRegsSaveSize, 905 bool ForceMutable = false) const; 906 907 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 908 SmallVectorImpl<SDValue> &InVals) const override; 909 910 /// HandleByVal - Target-specific cleanup for ByVal support. 911 void HandleByVal(CCState *, unsigned &, Align) const override; 912 913 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 914 /// for tail call optimization. Targets which want to do tail call 915 /// optimization should implement this function. 916 bool IsEligibleForTailCallOptimization( 917 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 918 bool isCalleeStructRet, bool isCallerStructRet, 919 const SmallVectorImpl<ISD::OutputArg> &Outs, 920 const SmallVectorImpl<SDValue> &OutVals, 921 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG, 922 const bool isIndirect) const; 923 924 bool CanLowerReturn(CallingConv::ID CallConv, 925 MachineFunction &MF, bool isVarArg, 926 const SmallVectorImpl<ISD::OutputArg> &Outs, 927 LLVMContext &Context) const override; 928 929 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 930 const SmallVectorImpl<ISD::OutputArg> &Outs, 931 const SmallVectorImpl<SDValue> &OutVals, 932 const SDLoc &dl, SelectionDAG &DAG) const override; 933 934 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 935 936 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 937 938 bool shouldConsiderGEPOffsetSplit() const override { return true; } 939 940 bool isUnsupportedFloatingType(EVT VT) const; 941 942 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal, 943 SDValue ARMcc, SDValue CCR, SDValue Cmp, 944 SelectionDAG &DAG) const; 945 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 946 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const; 947 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 948 const SDLoc &dl, bool Signaling = false) const; 949 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const; 950 951 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 952 953 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, 954 MachineBasicBlock *DispatchBB, int FI) const; 955 956 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const; 957 958 bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const; 959 960 MachineBasicBlock *EmitStructByval(MachineInstr &MI, 961 MachineBasicBlock *MBB) const; 962 963 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI, 964 MachineBasicBlock *MBB) const; 965 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI, 966 MachineBasicBlock *MBB) const; 967 void addMVEVectorTypes(bool HasMVEFP); 968 void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action); 969 void setAllExpand(MVT VT); 970 }; 971 972 enum VMOVModImmType { 973 VMOVModImm, 974 VMVNModImm, 975 MVEVMVNModImm, 976 OtherModImm 977 }; 978 979 namespace ARM { 980 981 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 982 const TargetLibraryInfo *libInfo); 983 984 } // end namespace ARM 985 986 } // end namespace llvm 987 988 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 989