1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that ARM uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 15 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 16 17 #include "MCTargetDesc/ARMBaseInfo.h" 18 #include "llvm/ADT/SmallVector.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/CodeGen/CallingConvLower.h" 21 #include "llvm/CodeGen/ISDOpcodes.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/MachineValueType.h" 24 #include "llvm/CodeGen/SelectionDAGNodes.h" 25 #include "llvm/CodeGen/TargetLowering.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/IR/Attributes.h" 28 #include "llvm/IR/CallingConv.h" 29 #include "llvm/IR/Function.h" 30 #include "llvm/IR/IRBuilder.h" 31 #include "llvm/IR/InlineAsm.h" 32 #include "llvm/Support/CodeGen.h" 33 #include <optional> 34 #include <utility> 35 36 namespace llvm { 37 38 class ARMSubtarget; 39 class DataLayout; 40 class FastISel; 41 class FunctionLoweringInfo; 42 class GlobalValue; 43 class InstrItineraryData; 44 class Instruction; 45 class MachineBasicBlock; 46 class MachineInstr; 47 class SelectionDAG; 48 class TargetLibraryInfo; 49 class TargetMachine; 50 class TargetRegisterInfo; 51 class VectorType; 52 53 namespace ARMISD { 54 55 // ARM Specific DAG Nodes 56 enum NodeType : unsigned { 57 // Start the numbering where the builtin ops and target ops leave off. 58 FIRST_NUMBER = ISD::BUILTIN_OP_END, 59 60 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 61 // TargetExternalSymbol, and TargetGlobalAddress. 62 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 63 // PIC mode. 64 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 65 66 // Add pseudo op to model memcpy for struct byval. 67 COPY_STRUCT_BYVAL, 68 69 CALL, // Function call. 70 CALL_PRED, // Function call that's predicable. 71 CALL_NOLINK, // Function call with branch not branch-and-link. 72 tSECALL, // CMSE non-secure function call. 73 t2CALL_BTI, // Thumb function call followed by BTI instruction. 74 BRCOND, // Conditional branch. 75 BR_JT, // Jumptable branch. 76 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 77 RET_GLUE, // Return with a flag operand. 78 SERET_GLUE, // CMSE Entry function return with a flag operand. 79 INTRET_GLUE, // Interrupt return with an LR-offset and a flag operand. 80 81 PIC_ADD, // Add with a PC operand and a PIC label. 82 83 ASRL, // MVE long arithmetic shift right. 84 LSRL, // MVE long shift right. 85 LSLL, // MVE long shift left. 86 87 CMP, // ARM compare instructions. 88 CMN, // ARM CMN instructions. 89 CMPZ, // ARM compare that sets only Z flag. 90 CMPFP, // ARM VFP compare instruction, sets FPSCR. 91 CMPFPE, // ARM VFP signalling compare instruction, sets FPSCR. 92 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 93 CMPFPEw0, // ARM VFP signalling compare against zero instruction, sets 94 // FPSCR. 95 FMSTAT, // ARM fmstat instruction. 96 97 CMOV, // ARM conditional move instructions. 98 SUBS, // Flag-setting subtraction. 99 100 SSAT, // Signed saturation 101 USAT, // Unsigned saturation 102 103 BCC_i64, 104 105 SRL_GLUE, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 106 SRA_GLUE, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 107 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 108 109 ADDC, // Add with carry 110 ADDE, // Add using carry 111 SUBC, // Sub with carry 112 SUBE, // Sub using carry 113 LSLS, // Shift left producing carry 114 115 VMOVRRD, // double to two gprs. 116 VMOVDRR, // Two gprs to double. 117 VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr 118 119 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 120 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 121 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch. 122 123 TC_RETURN, // Tail call return pseudo. 124 125 THREAD_POINTER, 126 127 DYN_ALLOC, // Dynamic allocation on the stack. 128 129 MEMBARRIER_MCR, // Memory barrier (MCR) 130 131 PRELOAD, // Preload 132 133 WIN__CHKSTK, // Windows' __chkstk call to do stack probing. 134 WIN__DBZCHK, // Windows' divide by zero check 135 136 WLS, // Low-overhead loops, While Loop Start branch. See t2WhileLoopStart 137 WLSSETUP, // Setup for the iteration count of a WLS. See t2WhileLoopSetup. 138 LOOP_DEC, // Really a part of LE, performs the sub 139 LE, // Low-overhead loops, Loop End 140 141 PREDICATE_CAST, // Predicate cast for MVE i1 types 142 VECTOR_REG_CAST, // Reinterpret the current contents of a vector register 143 144 MVESEXT, // Legalization aids for extending a vector into two/four vectors. 145 MVEZEXT, // or truncating two/four vectors into one. Eventually becomes 146 MVETRUNC, // stack store/load sequence, if not optimized to anything else. 147 148 VCMP, // Vector compare. 149 VCMPZ, // Vector compare to zero. 150 VTST, // Vector test bits. 151 152 // Vector shift by vector 153 VSHLs, // ...left/right by signed 154 VSHLu, // ...left/right by unsigned 155 156 // Vector shift by immediate: 157 VSHLIMM, // ...left 158 VSHRsIMM, // ...right (signed) 159 VSHRuIMM, // ...right (unsigned) 160 161 // Vector rounding shift by immediate: 162 VRSHRsIMM, // ...right (signed) 163 VRSHRuIMM, // ...right (unsigned) 164 VRSHRNIMM, // ...right narrow 165 166 // Vector saturating shift by immediate: 167 VQSHLsIMM, // ...left (signed) 168 VQSHLuIMM, // ...left (unsigned) 169 VQSHLsuIMM, // ...left (signed to unsigned) 170 VQSHRNsIMM, // ...right narrow (signed) 171 VQSHRNuIMM, // ...right narrow (unsigned) 172 VQSHRNsuIMM, // ...right narrow (signed to unsigned) 173 174 // Vector saturating rounding shift by immediate: 175 VQRSHRNsIMM, // ...right narrow (signed) 176 VQRSHRNuIMM, // ...right narrow (unsigned) 177 VQRSHRNsuIMM, // ...right narrow (signed to unsigned) 178 179 // Vector shift and insert: 180 VSLIIMM, // ...left 181 VSRIIMM, // ...right 182 183 // Vector get lane (VMOV scalar to ARM core register) 184 // (These are used for 8- and 16-bit element types only.) 185 VGETLANEu, // zero-extend vector extract element 186 VGETLANEs, // sign-extend vector extract element 187 188 // Vector move immediate and move negated immediate: 189 VMOVIMM, 190 VMVNIMM, 191 192 // Vector move f32 immediate: 193 VMOVFPIMM, 194 195 // Move H <-> R, clearing top 16 bits 196 VMOVrh, 197 VMOVhr, 198 199 // Vector duplicate: 200 VDUP, 201 VDUPLANE, 202 203 // Vector shuffles: 204 VEXT, // extract 205 VREV64, // reverse elements within 64-bit doublewords 206 VREV32, // reverse elements within 32-bit words 207 VREV16, // reverse elements within 16-bit halfwords 208 VZIP, // zip (interleave) 209 VUZP, // unzip (deinterleave) 210 VTRN, // transpose 211 VTBL1, // 1-register shuffle with mask 212 VTBL2, // 2-register shuffle with mask 213 VMOVN, // MVE vmovn 214 215 // MVE Saturating truncates 216 VQMOVNs, // Vector (V) Saturating (Q) Move and Narrow (N), signed (s) 217 VQMOVNu, // Vector (V) Saturating (Q) Move and Narrow (N), unsigned (u) 218 219 // MVE float <> half converts 220 VCVTN, // MVE vcvt f32 -> f16, truncating into either the bottom or top 221 // lanes 222 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes 223 224 // MVE VIDUP instruction, taking a start value and increment. 225 VIDUP, 226 227 // Vector multiply long: 228 VMULLs, // ...signed 229 VMULLu, // ...unsigned 230 231 VQDMULH, // MVE vqdmulh instruction 232 233 // MVE reductions 234 VADDVs, // sign- or zero-extend the elements of a vector to i32, 235 VADDVu, // add them all together, and return an i32 of their sum 236 VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask 237 VADDVpu, 238 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning 239 VADDLVu, // the low and high 32-bit halves of the sum 240 VADDLVAs, // Same as VADDLV[su] but also add an input accumulator 241 VADDLVAu, // provided as low and high halves 242 VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask 243 VADDLVpu, 244 VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask 245 VADDLVApu, 246 VMLAVs, // sign- or zero-extend the elements of two vectors to i32, multiply 247 VMLAVu, // them and add the results together, returning an i32 of their sum 248 VMLAVps, // Same as VMLAV[su] with a v4i1 predicate mask 249 VMLAVpu, 250 VMLALVs, // Same as VMLAV but with i64, returning the low and 251 VMLALVu, // high 32-bit halves of the sum 252 VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask 253 VMLALVpu, 254 VMLALVAs, // Same as VMLALV but also add an input accumulator 255 VMLALVAu, // provided as low and high halves 256 VMLALVAps, // Same as VMLALVA[su] with a v4i1 predicate mask 257 VMLALVApu, 258 VMINVu, // Find minimum unsigned value of a vector and register 259 VMINVs, // Find minimum signed value of a vector and register 260 VMAXVu, // Find maximum unsigned value of a vector and register 261 VMAXVs, // Find maximum signed value of a vector and register 262 263 SMULWB, // Signed multiply word by half word, bottom 264 SMULWT, // Signed multiply word by half word, top 265 UMLAL, // 64bit Unsigned Accumulate Multiply 266 SMLAL, // 64bit Signed Accumulate Multiply 267 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply 268 SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16 269 SMLALBT, // 64-bit signed accumulate multiply bottom, top 16 270 SMLALTB, // 64-bit signed accumulate multiply top, bottom 16 271 SMLALTT, // 64-bit signed accumulate multiply top, top 16 272 SMLALD, // Signed multiply accumulate long dual 273 SMLALDX, // Signed multiply accumulate long dual exchange 274 SMLSLD, // Signed multiply subtract long dual 275 SMLSLDX, // Signed multiply subtract long dual exchange 276 SMMLAR, // Signed multiply long, round and add 277 SMMLSR, // Signed multiply long, subtract and round 278 279 // Single Lane QADD8 and QADD16. Only the bottom lane. That's what the b 280 // stands for. 281 QADD8b, 282 QSUB8b, 283 QADD16b, 284 QSUB16b, 285 UQADD8b, 286 UQSUB8b, 287 UQADD16b, 288 UQSUB16b, 289 290 // Operands of the standard BUILD_VECTOR node are not legalized, which 291 // is fine if BUILD_VECTORs are always lowered to shuffles or other 292 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 293 // operands need to be legalized. Define an ARM-specific version of 294 // BUILD_VECTOR for this purpose. 295 BUILD_VECTOR, 296 297 // Bit-field insert 298 BFI, 299 300 // Vector OR with immediate 301 VORRIMM, 302 // Vector AND with NOT of immediate 303 VBICIMM, 304 305 // Pseudo vector bitwise select 306 VBSP, 307 308 // Pseudo-instruction representing a memory copy using ldm/stm 309 // instructions. 310 MEMCPY, 311 312 // Pseudo-instruction representing a memory copy using a tail predicated 313 // loop 314 MEMCPYLOOP, 315 // Pseudo-instruction representing a memset using a tail predicated 316 // loop 317 MEMSETLOOP, 318 319 // V8.1MMainline condition select 320 CSINV, // Conditional select invert. 321 CSNEG, // Conditional select negate. 322 CSINC, // Conditional select increment. 323 324 // Vector load N-element structure to all lanes: 325 VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, 326 VLD2DUP, 327 VLD3DUP, 328 VLD4DUP, 329 330 // NEON loads with post-increment base updates: 331 VLD1_UPD, 332 VLD2_UPD, 333 VLD3_UPD, 334 VLD4_UPD, 335 VLD2LN_UPD, 336 VLD3LN_UPD, 337 VLD4LN_UPD, 338 VLD1DUP_UPD, 339 VLD2DUP_UPD, 340 VLD3DUP_UPD, 341 VLD4DUP_UPD, 342 VLD1x2_UPD, 343 VLD1x3_UPD, 344 VLD1x4_UPD, 345 346 // NEON stores with post-increment base updates: 347 VST1_UPD, 348 VST2_UPD, 349 VST3_UPD, 350 VST4_UPD, 351 VST2LN_UPD, 352 VST3LN_UPD, 353 VST4LN_UPD, 354 VST1x2_UPD, 355 VST1x3_UPD, 356 VST1x4_UPD, 357 358 // Load/Store of dual registers 359 LDRD, 360 STRD 361 }; 362 363 } // end namespace ARMISD 364 365 namespace ARM { 366 /// Possible values of current rounding mode, which is specified in bits 367 /// 23:22 of FPSCR. 368 enum Rounding { 369 RN = 0, // Round to Nearest 370 RP = 1, // Round towards Plus infinity 371 RM = 2, // Round towards Minus infinity 372 RZ = 3, // Round towards Zero 373 rmMask = 3 // Bit mask selecting rounding mode 374 }; 375 376 // Bit position of rounding mode bits in FPSCR. 377 const unsigned RoundingBitsPos = 22; 378 } // namespace ARM 379 380 /// Define some predicates that are used for node matching. 381 namespace ARM { 382 383 bool isBitFieldInvertedMask(unsigned v); 384 385 } // end namespace ARM 386 387 //===--------------------------------------------------------------------===// 388 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 389 390 class ARMTargetLowering : public TargetLowering { 391 public: 392 explicit ARMTargetLowering(const TargetMachine &TM, 393 const ARMSubtarget &STI); 394 395 unsigned getJumpTableEncoding() const override; 396 bool useSoftFloat() const override; 397 398 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 399 400 /// ReplaceNodeResults - Replace the results of node with an illegal result 401 /// type with new values built out of custom code. 402 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 403 SelectionDAG &DAG) const override; 404 405 const char *getTargetNodeName(unsigned Opcode) const override; 406 407 bool isSelectSupported(SelectSupportKind Kind) const override { 408 // ARM does not support scalar condition selects on vectors. 409 return (Kind != ScalarCondVectorVal); 410 } 411 412 bool isReadOnly(const GlobalValue *GV) const; 413 414 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 415 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 416 EVT VT) const override; 417 418 MachineBasicBlock * 419 EmitInstrWithCustomInserter(MachineInstr &MI, 420 MachineBasicBlock *MBB) const override; 421 422 void AdjustInstrPostInstrSelection(MachineInstr &MI, 423 SDNode *Node) const override; 424 425 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 426 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const; 427 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const; 428 SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const; 429 SDValue PerformMVEExtCombine(SDNode *N, DAGCombinerInfo &DCI) const; 430 SDValue PerformMVETruncCombine(SDNode *N, DAGCombinerInfo &DCI) const; 431 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 432 433 bool SimplifyDemandedBitsForTargetNode(SDValue Op, 434 const APInt &OriginalDemandedBits, 435 const APInt &OriginalDemandedElts, 436 KnownBits &Known, 437 TargetLoweringOpt &TLO, 438 unsigned Depth) const override; 439 440 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override; 441 442 /// allowsMisalignedMemoryAccesses - Returns true if the target allows 443 /// unaligned memory accesses of the specified type. Returns whether it 444 /// is "fast" by reference in the second argument. 445 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, 446 Align Alignment, 447 MachineMemOperand::Flags Flags, 448 unsigned *Fast) const override; 449 450 EVT getOptimalMemOpType(const MemOp &Op, 451 const AttributeList &FuncAttributes) const override; 452 453 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 454 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 455 bool isZExtFree(SDValue Val, EVT VT2) const override; 456 bool shouldSinkOperands(Instruction *I, 457 SmallVectorImpl<Use *> &Ops) const override; 458 Type* shouldConvertSplatType(ShuffleVectorInst* SVI) const override; 459 460 bool isFNegFree(EVT VT) const override; 461 462 bool isVectorLoadExtDesirable(SDValue ExtVal) const override; 463 464 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override; 465 466 467 /// isLegalAddressingMode - Return true if the addressing mode represented 468 /// by AM is legal for this target, for a load/store of the specified type. 469 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 470 Type *Ty, unsigned AS, 471 Instruction *I = nullptr) const override; 472 473 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 474 475 /// Returns true if the addressing mode representing by AM is legal 476 /// for the Thumb1 target, for a load/store of the specified type. 477 bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 478 479 /// isLegalICmpImmediate - Return true if the specified immediate is legal 480 /// icmp immediate, that is the target has icmp instructions which can 481 /// compare a register against the immediate without having to materialize 482 /// the immediate into a register. 483 bool isLegalICmpImmediate(int64_t Imm) const override; 484 485 /// isLegalAddImmediate - Return true if the specified immediate is legal 486 /// add immediate, that is the target has add instructions which can 487 /// add a register and the immediate without having to materialize 488 /// the immediate into a register. 489 bool isLegalAddImmediate(int64_t Imm) const override; 490 491 /// getPreIndexedAddressParts - returns true by value, base pointer and 492 /// offset pointer and addressing mode by reference if the node's address 493 /// can be legally represented as pre-indexed load / store address. 494 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 495 ISD::MemIndexedMode &AM, 496 SelectionDAG &DAG) const override; 497 498 /// getPostIndexedAddressParts - returns true by value, base pointer and 499 /// offset pointer and addressing mode by reference if this node can be 500 /// combined with a load / store to form a post-indexed load / store. 501 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 502 SDValue &Offset, ISD::MemIndexedMode &AM, 503 SelectionDAG &DAG) const override; 504 505 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 506 const APInt &DemandedElts, 507 const SelectionDAG &DAG, 508 unsigned Depth) const override; 509 510 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 511 const APInt &DemandedElts, 512 TargetLoweringOpt &TLO) const override; 513 514 bool ExpandInlineAsm(CallInst *CI) const override; 515 516 ConstraintType getConstraintType(StringRef Constraint) const override; 517 518 /// Examine constraint string and operand type and determine a weight value. 519 /// The operand object must already have been set up with the operand type. 520 ConstraintWeight getSingleConstraintMatchWeight( 521 AsmOperandInfo &info, const char *constraint) const override; 522 523 std::pair<unsigned, const TargetRegisterClass *> 524 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 525 StringRef Constraint, MVT VT) const override; 526 527 const char *LowerXConstraint(EVT ConstraintVT) const override; 528 529 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 530 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 531 /// true it means one of the asm constraint of the inline asm instruction 532 /// being processed is 'm'. 533 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 534 std::vector<SDValue> &Ops, 535 SelectionDAG &DAG) const override; 536 537 unsigned 538 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 539 if (ConstraintCode == "Q") 540 return InlineAsm::Constraint_Q; 541 else if (ConstraintCode.size() == 2) { 542 if (ConstraintCode[0] == 'U') { 543 switch(ConstraintCode[1]) { 544 default: 545 break; 546 case 'm': 547 return InlineAsm::Constraint_Um; 548 case 'n': 549 return InlineAsm::Constraint_Un; 550 case 'q': 551 return InlineAsm::Constraint_Uq; 552 case 's': 553 return InlineAsm::Constraint_Us; 554 case 't': 555 return InlineAsm::Constraint_Ut; 556 case 'v': 557 return InlineAsm::Constraint_Uv; 558 case 'y': 559 return InlineAsm::Constraint_Uy; 560 } 561 } 562 } 563 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 564 } 565 566 const ARMSubtarget* getSubtarget() const { 567 return Subtarget; 568 } 569 570 /// getRegClassFor - Return the register class that should be used for the 571 /// specified value type. 572 const TargetRegisterClass * 573 getRegClassFor(MVT VT, bool isDivergent = false) const override; 574 575 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, 576 Align &PrefAlign) const override; 577 578 /// createFastISel - This method returns a target specific FastISel object, 579 /// or null if the target does not support "fast" ISel. 580 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 581 const TargetLibraryInfo *libInfo) const override; 582 583 Sched::Preference getSchedulingPreference(SDNode *N) const override; 584 585 bool preferZeroCompareBranch() const override { return true; } 586 587 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override; 588 589 bool 590 isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 591 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 592 593 /// isFPImmLegal - Returns true if the target can instruction select the 594 /// specified FP immediate natively. If false, the legalizer will 595 /// materialize the FP immediate as a load from a constant pool. 596 bool isFPImmLegal(const APFloat &Imm, EVT VT, 597 bool ForCodeSize = false) const override; 598 599 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 600 const CallInst &I, 601 MachineFunction &MF, 602 unsigned Intrinsic) const override; 603 604 /// Returns true if it is beneficial to convert a load of a constant 605 /// to just the constant itself. 606 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 607 Type *Ty) const override; 608 609 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type 610 /// with this index. 611 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 612 unsigned Index) const override; 613 614 bool shouldFormOverflowOp(unsigned Opcode, EVT VT, 615 bool MathUsed) const override { 616 // Using overflow ops for overflow checks only should beneficial on ARM. 617 return TargetLowering::shouldFormOverflowOp(Opcode, VT, true); 618 } 619 620 bool shouldReassociateReduction(unsigned Opc, EVT VT) const override { 621 return Opc != ISD::VECREDUCE_ADD; 622 } 623 624 /// Returns true if an argument of type Ty needs to be passed in a 625 /// contiguous block of registers in calling convention CallConv. 626 bool functionArgumentNeedsConsecutiveRegisters( 627 Type *Ty, CallingConv::ID CallConv, bool isVarArg, 628 const DataLayout &DL) const override; 629 630 /// If a physical register, this returns the register that receives the 631 /// exception address on entry to an EH pad. 632 Register 633 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 634 635 /// If a physical register, this returns the register that receives the 636 /// exception typeid on entry to a landing pad. 637 Register 638 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 639 640 Instruction *makeDMB(IRBuilderBase &Builder, ARM_MB::MemBOpt Domain) const; 641 Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, 642 AtomicOrdering Ord) const override; 643 Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, 644 AtomicOrdering Ord) const override; 645 646 void 647 emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override; 648 649 Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, 650 AtomicOrdering Ord) const override; 651 Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, 652 AtomicOrdering Ord) const override; 653 654 unsigned getMaxSupportedInterleaveFactor() const override; 655 656 bool lowerInterleavedLoad(LoadInst *LI, 657 ArrayRef<ShuffleVectorInst *> Shuffles, 658 ArrayRef<unsigned> Indices, 659 unsigned Factor) const override; 660 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, 661 unsigned Factor) const override; 662 663 bool shouldInsertFencesForAtomic(const Instruction *I) const override; 664 TargetLoweringBase::AtomicExpansionKind 665 shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 666 TargetLoweringBase::AtomicExpansionKind 667 shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 668 TargetLoweringBase::AtomicExpansionKind 669 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 670 TargetLoweringBase::AtomicExpansionKind 671 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 672 673 bool useLoadStackGuardNode() const override; 674 675 void insertSSPDeclarations(Module &M) const override; 676 Value *getSDagStackGuard(const Module &M) const override; 677 Function *getSSPStackGuardCheck(const Module &M) const override; 678 679 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, 680 unsigned &Cost) const override; 681 682 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, 683 const MachineFunction &MF) const override { 684 // Do not merge to larger than i32. 685 return (MemVT.getSizeInBits() <= 32); 686 } 687 688 bool isCheapToSpeculateCttz(Type *Ty) const override; 689 bool isCheapToSpeculateCtlz(Type *Ty) const override; 690 691 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 692 return VT.isScalarInteger(); 693 } 694 695 bool supportSwiftError() const override { 696 return true; 697 } 698 699 bool hasStandaloneRem(EVT VT) const override { 700 return HasStandaloneRem; 701 } 702 703 ShiftLegalizationStrategy 704 preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, 705 unsigned ExpansionFactor) const override; 706 707 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const; 708 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const; 709 710 /// Returns true if \p VecTy is a legal interleaved access type. This 711 /// function checks the vector element type and the overall width of the 712 /// vector. 713 bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy, 714 Align Alignment, 715 const DataLayout &DL) const; 716 717 bool isMulAddWithConstProfitable(SDValue AddNode, 718 SDValue ConstNode) const override; 719 720 bool alignLoopsWithOptSize() const override; 721 722 /// Returns the number of interleaved accesses that will be generated when 723 /// lowering accesses of the given type. 724 unsigned getNumInterleavedAccesses(VectorType *VecTy, 725 const DataLayout &DL) const; 726 727 void finalizeLowering(MachineFunction &MF) const override; 728 729 /// Return the correct alignment for the current calling convention. 730 Align getABIAlignmentForCallingConv(Type *ArgTy, 731 const DataLayout &DL) const override; 732 733 bool isDesirableToCommuteWithShift(const SDNode *N, 734 CombineLevel Level) const override; 735 736 bool isDesirableToCommuteXorWithShift(const SDNode *N) const override; 737 738 bool shouldFoldConstantShiftPairToMask(const SDNode *N, 739 CombineLevel Level) const override; 740 741 bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, 742 EVT VT) const override; 743 744 bool preferIncOfAddToSubOfNot(EVT VT) const override; 745 746 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override; 747 748 bool isComplexDeinterleavingSupported() const override; 749 bool isComplexDeinterleavingOperationSupported( 750 ComplexDeinterleavingOperation Operation, Type *Ty) const override; 751 752 Value *createComplexDeinterleavingIR( 753 IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, 754 ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, 755 Value *Accumulator = nullptr) const override; 756 757 protected: 758 std::pair<const TargetRegisterClass *, uint8_t> 759 findRepresentativeClass(const TargetRegisterInfo *TRI, 760 MVT VT) const override; 761 762 private: 763 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 764 /// make the right decision when generating code for different targets. 765 const ARMSubtarget *Subtarget; 766 767 const TargetRegisterInfo *RegInfo; 768 769 const InstrItineraryData *Itins; 770 771 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper 772 // check. 773 bool InsertFencesForAtomic; 774 775 bool HasStandaloneRem = true; 776 777 void addTypeForNEON(MVT VT, MVT PromotedLdStVT); 778 void addDRTypeForNEON(MVT VT); 779 void addQRTypeForNEON(MVT VT); 780 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const; 781 782 using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>; 783 784 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, 785 SDValue &Arg, RegsToPassVector &RegsToPass, 786 CCValAssign &VA, CCValAssign &NextVA, 787 SDValue &StackPtr, 788 SmallVectorImpl<SDValue> &MemOpChains, 789 bool IsTailCall, 790 int SPDiff) const; 791 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 792 SDValue &Root, SelectionDAG &DAG, 793 const SDLoc &dl) const; 794 795 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC, 796 bool isVarArg) const; 797 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 798 bool isVarArg) const; 799 std::pair<SDValue, MachinePointerInfo> 800 computeAddrForCallArg(const SDLoc &dl, SelectionDAG &DAG, 801 const CCValAssign &VA, SDValue StackPtr, 802 bool IsTailCall, int SPDiff) const; 803 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 804 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 805 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const; 806 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG, 807 const ARMSubtarget *Subtarget) const; 808 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 809 const ARMSubtarget *Subtarget) const; 810 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 811 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 812 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 813 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 814 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 815 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const; 816 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 817 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 818 SelectionDAG &DAG) const; 819 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 820 SelectionDAG &DAG, 821 TLSModel::Model model) const; 822 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 823 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const; 824 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 825 SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const; 826 SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const; 827 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 828 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 829 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 830 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 831 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 832 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 833 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 834 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 835 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 836 SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 837 SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 838 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, 839 const ARMSubtarget *ST) const; 840 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 841 const ARMSubtarget *ST) const; 842 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 843 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 844 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; 845 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const; 846 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed, 847 SmallVectorImpl<SDValue> &Results) const; 848 SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG, 849 const ARMSubtarget *Subtarget) const; 850 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed, 851 SDValue &Chain) const; 852 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const; 853 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 854 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 855 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 856 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 857 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 858 SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const; 859 SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const; 860 void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results, 861 SelectionDAG &DAG) const; 862 863 Register getRegisterByName(const char* RegName, LLT VT, 864 const MachineFunction &MF) const override; 865 866 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 867 SmallVectorImpl<SDNode *> &Created) const override; 868 869 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 870 EVT VT) const override; 871 872 SDValue MoveToHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, MVT ValVT, 873 SDValue Val) const; 874 SDValue MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, 875 MVT ValVT, SDValue Val) const; 876 877 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 878 879 SDValue LowerCallResult(SDValue Chain, SDValue InGlue, 880 CallingConv::ID CallConv, bool isVarArg, 881 const SmallVectorImpl<ISD::InputArg> &Ins, 882 const SDLoc &dl, SelectionDAG &DAG, 883 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 884 SDValue ThisVal) const; 885 886 bool supportSplitCSR(MachineFunction *MF) const override { 887 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 888 MF->getFunction().hasFnAttribute(Attribute::NoUnwind); 889 } 890 891 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 892 void insertCopiesSplitCSR( 893 MachineBasicBlock *Entry, 894 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 895 896 bool splitValueIntoRegisterParts( 897 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, 898 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) 899 const override; 900 901 SDValue joinRegisterPartsIntoValue( 902 SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts, 903 unsigned NumParts, MVT PartVT, EVT ValueVT, 904 std::optional<CallingConv::ID> CC) const override; 905 906 SDValue 907 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 908 const SmallVectorImpl<ISD::InputArg> &Ins, 909 const SDLoc &dl, SelectionDAG &DAG, 910 SmallVectorImpl<SDValue> &InVals) const override; 911 912 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl, 913 SDValue &Chain, const Value *OrigArg, 914 unsigned InRegsParamRecordIdx, int ArgOffset, 915 unsigned ArgSize) const; 916 917 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 918 const SDLoc &dl, SDValue &Chain, 919 unsigned ArgOffset, unsigned TotalArgRegsSaveSize, 920 bool ForceMutable = false) const; 921 922 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 923 SmallVectorImpl<SDValue> &InVals) const override; 924 925 /// HandleByVal - Target-specific cleanup for ByVal support. 926 void HandleByVal(CCState *, unsigned &, Align) const override; 927 928 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 929 /// for tail call optimization. Targets which want to do tail call 930 /// optimization should implement this function. 931 bool IsEligibleForTailCallOptimization( 932 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 933 bool isCalleeStructRet, bool isCallerStructRet, 934 const SmallVectorImpl<ISD::OutputArg> &Outs, 935 const SmallVectorImpl<SDValue> &OutVals, 936 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG, 937 const bool isIndirect) const; 938 939 bool CanLowerReturn(CallingConv::ID CallConv, 940 MachineFunction &MF, bool isVarArg, 941 const SmallVectorImpl<ISD::OutputArg> &Outs, 942 LLVMContext &Context) const override; 943 944 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 945 const SmallVectorImpl<ISD::OutputArg> &Outs, 946 const SmallVectorImpl<SDValue> &OutVals, 947 const SDLoc &dl, SelectionDAG &DAG) const override; 948 949 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 950 951 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 952 953 bool shouldConsiderGEPOffsetSplit() const override { return true; } 954 955 bool isUnsupportedFloatingType(EVT VT) const; 956 957 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal, 958 SDValue ARMcc, SDValue CCR, SDValue Cmp, 959 SelectionDAG &DAG) const; 960 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 961 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const; 962 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 963 const SDLoc &dl, bool Signaling = false) const; 964 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const; 965 966 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 967 968 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, 969 MachineBasicBlock *DispatchBB, int FI) const; 970 971 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const; 972 973 MachineBasicBlock *EmitStructByval(MachineInstr &MI, 974 MachineBasicBlock *MBB) const; 975 976 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI, 977 MachineBasicBlock *MBB) const; 978 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI, 979 MachineBasicBlock *MBB) const; 980 void addMVEVectorTypes(bool HasMVEFP); 981 void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action); 982 void setAllExpand(MVT VT); 983 }; 984 985 enum VMOVModImmType { 986 VMOVModImm, 987 VMVNModImm, 988 MVEVMVNModImm, 989 OtherModImm 990 }; 991 992 namespace ARM { 993 994 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 995 const TargetLibraryInfo *libInfo); 996 997 } // end namespace ARM 998 999 } // end namespace llvm 1000 1001 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 1002