1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that ARM uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 15 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 16 17 #include "MCTargetDesc/ARMBaseInfo.h" 18 #include "llvm/ADT/SmallVector.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/CodeGen/CallingConvLower.h" 21 #include "llvm/CodeGen/ISDOpcodes.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/SelectionDAGNodes.h" 24 #include "llvm/CodeGen/TargetLowering.h" 25 #include "llvm/CodeGen/ValueTypes.h" 26 #include "llvm/IR/Attributes.h" 27 #include "llvm/IR/CallingConv.h" 28 #include "llvm/IR/Function.h" 29 #include "llvm/IR/IRBuilder.h" 30 #include "llvm/IR/InlineAsm.h" 31 #include "llvm/Support/CodeGen.h" 32 #include "llvm/Support/MachineValueType.h" 33 #include <utility> 34 35 namespace llvm { 36 37 class ARMSubtarget; 38 class DataLayout; 39 class FastISel; 40 class FunctionLoweringInfo; 41 class GlobalValue; 42 class InstrItineraryData; 43 class Instruction; 44 class MachineBasicBlock; 45 class MachineInstr; 46 class SelectionDAG; 47 class TargetLibraryInfo; 48 class TargetMachine; 49 class TargetRegisterInfo; 50 class VectorType; 51 52 namespace ARMISD { 53 54 // ARM Specific DAG Nodes 55 enum NodeType : unsigned { 56 // Start the numbering where the builtin ops and target ops leave off. 57 FIRST_NUMBER = ISD::BUILTIN_OP_END, 58 59 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 60 // TargetExternalSymbol, and TargetGlobalAddress. 61 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 62 // PIC mode. 63 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 64 65 // Add pseudo op to model memcpy for struct byval. 66 COPY_STRUCT_BYVAL, 67 68 CALL, // Function call. 69 CALL_PRED, // Function call that's predicable. 70 CALL_NOLINK, // Function call with branch not branch-and-link. 71 tSECALL, // CMSE non-secure function call. 72 t2CALL_BTI, // Thumb function call followed by BTI instruction. 73 BRCOND, // Conditional branch. 74 BR_JT, // Jumptable branch. 75 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 76 RET_FLAG, // Return with a flag operand. 77 SERET_FLAG, // CMSE Entry function return with a flag operand. 78 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand. 79 80 PIC_ADD, // Add with a PC operand and a PIC label. 81 82 ASRL, // MVE long arithmetic shift right. 83 LSRL, // MVE long shift right. 84 LSLL, // MVE long shift left. 85 86 CMP, // ARM compare instructions. 87 CMN, // ARM CMN instructions. 88 CMPZ, // ARM compare that sets only Z flag. 89 CMPFP, // ARM VFP compare instruction, sets FPSCR. 90 CMPFPE, // ARM VFP signalling compare instruction, sets FPSCR. 91 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 92 CMPFPEw0, // ARM VFP signalling compare against zero instruction, sets 93 // FPSCR. 94 FMSTAT, // ARM fmstat instruction. 95 96 CMOV, // ARM conditional move instructions. 97 SUBS, // Flag-setting subtraction. 98 99 SSAT, // Signed saturation 100 USAT, // Unsigned saturation 101 102 BCC_i64, 103 104 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 105 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 106 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 107 108 ADDC, // Add with carry 109 ADDE, // Add using carry 110 SUBC, // Sub with carry 111 SUBE, // Sub using carry 112 LSLS, // Shift left producing carry 113 114 VMOVRRD, // double to two gprs. 115 VMOVDRR, // Two gprs to double. 116 VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr 117 118 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 119 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 120 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch. 121 122 TC_RETURN, // Tail call return pseudo. 123 124 THREAD_POINTER, 125 126 DYN_ALLOC, // Dynamic allocation on the stack. 127 128 MEMBARRIER_MCR, // Memory barrier (MCR) 129 130 PRELOAD, // Preload 131 132 WIN__CHKSTK, // Windows' __chkstk call to do stack probing. 133 WIN__DBZCHK, // Windows' divide by zero check 134 135 WLS, // Low-overhead loops, While Loop Start branch. See t2WhileLoopStart 136 WLSSETUP, // Setup for the iteration count of a WLS. See t2WhileLoopSetup. 137 LOOP_DEC, // Really a part of LE, performs the sub 138 LE, // Low-overhead loops, Loop End 139 140 PREDICATE_CAST, // Predicate cast for MVE i1 types 141 VECTOR_REG_CAST, // Reinterpret the current contents of a vector register 142 143 MVESEXT, // Legalization aids for extending a vector into two/four vectors. 144 MVEZEXT, // or truncating two/four vectors into one. Eventually becomes 145 MVETRUNC, // stack store/load sequence, if not optimized to anything else. 146 147 VCMP, // Vector compare. 148 VCMPZ, // Vector compare to zero. 149 VTST, // Vector test bits. 150 151 // Vector shift by vector 152 VSHLs, // ...left/right by signed 153 VSHLu, // ...left/right by unsigned 154 155 // Vector shift by immediate: 156 VSHLIMM, // ...left 157 VSHRsIMM, // ...right (signed) 158 VSHRuIMM, // ...right (unsigned) 159 160 // Vector rounding shift by immediate: 161 VRSHRsIMM, // ...right (signed) 162 VRSHRuIMM, // ...right (unsigned) 163 VRSHRNIMM, // ...right narrow 164 165 // Vector saturating shift by immediate: 166 VQSHLsIMM, // ...left (signed) 167 VQSHLuIMM, // ...left (unsigned) 168 VQSHLsuIMM, // ...left (signed to unsigned) 169 VQSHRNsIMM, // ...right narrow (signed) 170 VQSHRNuIMM, // ...right narrow (unsigned) 171 VQSHRNsuIMM, // ...right narrow (signed to unsigned) 172 173 // Vector saturating rounding shift by immediate: 174 VQRSHRNsIMM, // ...right narrow (signed) 175 VQRSHRNuIMM, // ...right narrow (unsigned) 176 VQRSHRNsuIMM, // ...right narrow (signed to unsigned) 177 178 // Vector shift and insert: 179 VSLIIMM, // ...left 180 VSRIIMM, // ...right 181 182 // Vector get lane (VMOV scalar to ARM core register) 183 // (These are used for 8- and 16-bit element types only.) 184 VGETLANEu, // zero-extend vector extract element 185 VGETLANEs, // sign-extend vector extract element 186 187 // Vector move immediate and move negated immediate: 188 VMOVIMM, 189 VMVNIMM, 190 191 // Vector move f32 immediate: 192 VMOVFPIMM, 193 194 // Move H <-> R, clearing top 16 bits 195 VMOVrh, 196 VMOVhr, 197 198 // Vector duplicate: 199 VDUP, 200 VDUPLANE, 201 202 // Vector shuffles: 203 VEXT, // extract 204 VREV64, // reverse elements within 64-bit doublewords 205 VREV32, // reverse elements within 32-bit words 206 VREV16, // reverse elements within 16-bit halfwords 207 VZIP, // zip (interleave) 208 VUZP, // unzip (deinterleave) 209 VTRN, // transpose 210 VTBL1, // 1-register shuffle with mask 211 VTBL2, // 2-register shuffle with mask 212 VMOVN, // MVE vmovn 213 214 // MVE Saturating truncates 215 VQMOVNs, // Vector (V) Saturating (Q) Move and Narrow (N), signed (s) 216 VQMOVNu, // Vector (V) Saturating (Q) Move and Narrow (N), unsigned (u) 217 218 // MVE float <> half converts 219 VCVTN, // MVE vcvt f32 -> f16, truncating into either the bottom or top 220 // lanes 221 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes 222 223 // MVE VIDUP instruction, taking a start value and increment. 224 VIDUP, 225 226 // Vector multiply long: 227 VMULLs, // ...signed 228 VMULLu, // ...unsigned 229 230 VQDMULH, // MVE vqdmulh instruction 231 232 // MVE reductions 233 VADDVs, // sign- or zero-extend the elements of a vector to i32, 234 VADDVu, // add them all together, and return an i32 of their sum 235 VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask 236 VADDVpu, 237 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning 238 VADDLVu, // the low and high 32-bit halves of the sum 239 VADDLVAs, // Same as VADDLV[su] but also add an input accumulator 240 VADDLVAu, // provided as low and high halves 241 VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask 242 VADDLVpu, 243 VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask 244 VADDLVApu, 245 VMLAVs, // sign- or zero-extend the elements of two vectors to i32, multiply 246 // them 247 VMLAVu, // and add the results together, returning an i32 of their sum 248 VMLAVps, // Same as VMLAV[su] with a v4i1 predicate mask 249 VMLAVpu, 250 VMLALVs, // Same as VMLAV but with i64, returning the low and 251 VMLALVu, // high 32-bit halves of the sum 252 VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask 253 VMLALVpu, 254 VMLALVAs, // Same as VMLALV but also add an input accumulator 255 VMLALVAu, // provided as low and high halves 256 VMLALVAps, // Same as VMLALVA[su] with a v4i1 predicate mask 257 VMLALVApu, 258 VMINVu, // Find minimum unsigned value of a vector and register 259 VMINVs, // Find minimum signed value of a vector and register 260 VMAXVu, // Find maximum unsigned value of a vector and register 261 VMAXVs, // Find maximum signed value of a vector and register 262 263 SMULWB, // Signed multiply word by half word, bottom 264 SMULWT, // Signed multiply word by half word, top 265 UMLAL, // 64bit Unsigned Accumulate Multiply 266 SMLAL, // 64bit Signed Accumulate Multiply 267 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply 268 SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16 269 SMLALBT, // 64-bit signed accumulate multiply bottom, top 16 270 SMLALTB, // 64-bit signed accumulate multiply top, bottom 16 271 SMLALTT, // 64-bit signed accumulate multiply top, top 16 272 SMLALD, // Signed multiply accumulate long dual 273 SMLALDX, // Signed multiply accumulate long dual exchange 274 SMLSLD, // Signed multiply subtract long dual 275 SMLSLDX, // Signed multiply subtract long dual exchange 276 SMMLAR, // Signed multiply long, round and add 277 SMMLSR, // Signed multiply long, subtract and round 278 279 // Single Lane QADD8 and QADD16. Only the bottom lane. That's what the b 280 // stands for. 281 QADD8b, 282 QSUB8b, 283 QADD16b, 284 QSUB16b, 285 UQADD8b, 286 UQSUB8b, 287 UQADD16b, 288 UQSUB16b, 289 290 // Operands of the standard BUILD_VECTOR node are not legalized, which 291 // is fine if BUILD_VECTORs are always lowered to shuffles or other 292 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 293 // operands need to be legalized. Define an ARM-specific version of 294 // BUILD_VECTOR for this purpose. 295 BUILD_VECTOR, 296 297 // Bit-field insert 298 BFI, 299 300 // Vector OR with immediate 301 VORRIMM, 302 // Vector AND with NOT of immediate 303 VBICIMM, 304 305 // Pseudo vector bitwise select 306 VBSP, 307 308 // Pseudo-instruction representing a memory copy using ldm/stm 309 // instructions. 310 MEMCPY, 311 312 // Pseudo-instruction representing a memory copy using a tail predicated 313 // loop 314 MEMCPYLOOP, 315 // Pseudo-instruction representing a memset using a tail predicated 316 // loop 317 MEMSETLOOP, 318 319 // V8.1MMainline condition select 320 CSINV, // Conditional select invert. 321 CSNEG, // Conditional select negate. 322 CSINC, // Conditional select increment. 323 324 // Vector load N-element structure to all lanes: 325 VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, 326 VLD2DUP, 327 VLD3DUP, 328 VLD4DUP, 329 330 // NEON loads with post-increment base updates: 331 VLD1_UPD, 332 VLD2_UPD, 333 VLD3_UPD, 334 VLD4_UPD, 335 VLD2LN_UPD, 336 VLD3LN_UPD, 337 VLD4LN_UPD, 338 VLD1DUP_UPD, 339 VLD2DUP_UPD, 340 VLD3DUP_UPD, 341 VLD4DUP_UPD, 342 VLD1x2_UPD, 343 VLD1x3_UPD, 344 VLD1x4_UPD, 345 346 // NEON stores with post-increment base updates: 347 VST1_UPD, 348 VST2_UPD, 349 VST3_UPD, 350 VST4_UPD, 351 VST2LN_UPD, 352 VST3LN_UPD, 353 VST4LN_UPD, 354 VST1x2_UPD, 355 VST1x3_UPD, 356 VST1x4_UPD, 357 358 // Load/Store of dual registers 359 LDRD, 360 STRD 361 }; 362 363 } // end namespace ARMISD 364 365 namespace ARM { 366 /// Possible values of current rounding mode, which is specified in bits 367 /// 23:22 of FPSCR. 368 enum Rounding { 369 RN = 0, // Round to Nearest 370 RP = 1, // Round towards Plus infinity 371 RM = 2, // Round towards Minus infinity 372 RZ = 3, // Round towards Zero 373 rmMask = 3 // Bit mask selecting rounding mode 374 }; 375 376 // Bit position of rounding mode bits in FPSCR. 377 const unsigned RoundingBitsPos = 22; 378 } // namespace ARM 379 380 /// Define some predicates that are used for node matching. 381 namespace ARM { 382 383 bool isBitFieldInvertedMask(unsigned v); 384 385 } // end namespace ARM 386 387 //===--------------------------------------------------------------------===// 388 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 389 390 class ARMTargetLowering : public TargetLowering { 391 public: 392 explicit ARMTargetLowering(const TargetMachine &TM, 393 const ARMSubtarget &STI); 394 395 unsigned getJumpTableEncoding() const override; 396 bool useSoftFloat() const override; 397 398 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 399 400 /// ReplaceNodeResults - Replace the results of node with an illegal result 401 /// type with new values built out of custom code. 402 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 403 SelectionDAG &DAG) const override; 404 405 const char *getTargetNodeName(unsigned Opcode) const override; 406 407 bool isSelectSupported(SelectSupportKind Kind) const override { 408 // ARM does not support scalar condition selects on vectors. 409 return (Kind != ScalarCondVectorVal); 410 } 411 412 bool isReadOnly(const GlobalValue *GV) const; 413 414 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 415 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 416 EVT VT) const override; 417 418 MachineBasicBlock * 419 EmitInstrWithCustomInserter(MachineInstr &MI, 420 MachineBasicBlock *MBB) const override; 421 422 void AdjustInstrPostInstrSelection(MachineInstr &MI, 423 SDNode *Node) const override; 424 425 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 426 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const; 427 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const; 428 SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const; 429 SDValue PerformMVEExtCombine(SDNode *N, DAGCombinerInfo &DCI) const; 430 SDValue PerformMVETruncCombine(SDNode *N, DAGCombinerInfo &DCI) const; 431 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 432 433 bool SimplifyDemandedBitsForTargetNode(SDValue Op, 434 const APInt &OriginalDemandedBits, 435 const APInt &OriginalDemandedElts, 436 KnownBits &Known, 437 TargetLoweringOpt &TLO, 438 unsigned Depth) const override; 439 440 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override; 441 442 /// allowsMisalignedMemoryAccesses - Returns true if the target allows 443 /// unaligned memory accesses of the specified type. Returns whether it 444 /// is "fast" by reference in the second argument. 445 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, 446 Align Alignment, 447 MachineMemOperand::Flags Flags, 448 bool *Fast) const override; 449 450 EVT getOptimalMemOpType(const MemOp &Op, 451 const AttributeList &FuncAttributes) const override; 452 453 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 454 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 455 bool isZExtFree(SDValue Val, EVT VT2) const override; 456 bool shouldSinkOperands(Instruction *I, 457 SmallVectorImpl<Use *> &Ops) const override; 458 Type* shouldConvertSplatType(ShuffleVectorInst* SVI) const override; 459 460 bool isFNegFree(EVT VT) const override; 461 462 bool isVectorLoadExtDesirable(SDValue ExtVal) const override; 463 464 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override; 465 466 467 /// isLegalAddressingMode - Return true if the addressing mode represented 468 /// by AM is legal for this target, for a load/store of the specified type. 469 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 470 Type *Ty, unsigned AS, 471 Instruction *I = nullptr) const override; 472 473 /// getScalingFactorCost - Return the cost of the scaling used in 474 /// addressing mode represented by AM. 475 /// If the AM is supported, the return value must be >= 0. 476 /// If the AM is not supported, the return value must be negative. 477 InstructionCost getScalingFactorCost(const DataLayout &DL, 478 const AddrMode &AM, Type *Ty, 479 unsigned AS) const override; 480 481 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 482 483 /// Returns true if the addressing mode representing by AM is legal 484 /// for the Thumb1 target, for a load/store of the specified type. 485 bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 486 487 /// isLegalICmpImmediate - Return true if the specified immediate is legal 488 /// icmp immediate, that is the target has icmp instructions which can 489 /// compare a register against the immediate without having to materialize 490 /// the immediate into a register. 491 bool isLegalICmpImmediate(int64_t Imm) const override; 492 493 /// isLegalAddImmediate - Return true if the specified immediate is legal 494 /// add immediate, that is the target has add instructions which can 495 /// add a register and the immediate without having to materialize 496 /// the immediate into a register. 497 bool isLegalAddImmediate(int64_t Imm) const override; 498 499 /// getPreIndexedAddressParts - returns true by value, base pointer and 500 /// offset pointer and addressing mode by reference if the node's address 501 /// can be legally represented as pre-indexed load / store address. 502 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 503 ISD::MemIndexedMode &AM, 504 SelectionDAG &DAG) const override; 505 506 /// getPostIndexedAddressParts - returns true by value, base pointer and 507 /// offset pointer and addressing mode by reference if this node can be 508 /// combined with a load / store to form a post-indexed load / store. 509 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 510 SDValue &Offset, ISD::MemIndexedMode &AM, 511 SelectionDAG &DAG) const override; 512 513 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 514 const APInt &DemandedElts, 515 const SelectionDAG &DAG, 516 unsigned Depth) const override; 517 518 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 519 const APInt &DemandedElts, 520 TargetLoweringOpt &TLO) const override; 521 522 bool ExpandInlineAsm(CallInst *CI) const override; 523 524 ConstraintType getConstraintType(StringRef Constraint) const override; 525 526 /// Examine constraint string and operand type and determine a weight value. 527 /// The operand object must already have been set up with the operand type. 528 ConstraintWeight getSingleConstraintMatchWeight( 529 AsmOperandInfo &info, const char *constraint) const override; 530 531 std::pair<unsigned, const TargetRegisterClass *> 532 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 533 StringRef Constraint, MVT VT) const override; 534 535 const char *LowerXConstraint(EVT ConstraintVT) const override; 536 537 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 538 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 539 /// true it means one of the asm constraint of the inline asm instruction 540 /// being processed is 'm'. 541 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 542 std::vector<SDValue> &Ops, 543 SelectionDAG &DAG) const override; 544 545 unsigned 546 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 547 if (ConstraintCode == "Q") 548 return InlineAsm::Constraint_Q; 549 else if (ConstraintCode.size() == 2) { 550 if (ConstraintCode[0] == 'U') { 551 switch(ConstraintCode[1]) { 552 default: 553 break; 554 case 'm': 555 return InlineAsm::Constraint_Um; 556 case 'n': 557 return InlineAsm::Constraint_Un; 558 case 'q': 559 return InlineAsm::Constraint_Uq; 560 case 's': 561 return InlineAsm::Constraint_Us; 562 case 't': 563 return InlineAsm::Constraint_Ut; 564 case 'v': 565 return InlineAsm::Constraint_Uv; 566 case 'y': 567 return InlineAsm::Constraint_Uy; 568 } 569 } 570 } 571 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 572 } 573 574 const ARMSubtarget* getSubtarget() const { 575 return Subtarget; 576 } 577 578 /// getRegClassFor - Return the register class that should be used for the 579 /// specified value type. 580 const TargetRegisterClass * 581 getRegClassFor(MVT VT, bool isDivergent = false) const override; 582 583 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, 584 unsigned &PrefAlign) const override; 585 586 /// createFastISel - This method returns a target specific FastISel object, 587 /// or null if the target does not support "fast" ISel. 588 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 589 const TargetLibraryInfo *libInfo) const override; 590 591 Sched::Preference getSchedulingPreference(SDNode *N) const override; 592 593 bool preferZeroCompareBranch() const override { return true; } 594 595 bool 596 isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 597 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 598 599 /// isFPImmLegal - Returns true if the target can instruction select the 600 /// specified FP immediate natively. If false, the legalizer will 601 /// materialize the FP immediate as a load from a constant pool. 602 bool isFPImmLegal(const APFloat &Imm, EVT VT, 603 bool ForCodeSize = false) const override; 604 605 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 606 const CallInst &I, 607 MachineFunction &MF, 608 unsigned Intrinsic) const override; 609 610 /// Returns true if it is beneficial to convert a load of a constant 611 /// to just the constant itself. 612 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 613 Type *Ty) const override; 614 615 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type 616 /// with this index. 617 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 618 unsigned Index) const override; 619 620 bool shouldFormOverflowOp(unsigned Opcode, EVT VT, 621 bool MathUsed) const override { 622 // Using overflow ops for overflow checks only should beneficial on ARM. 623 return TargetLowering::shouldFormOverflowOp(Opcode, VT, true); 624 } 625 626 /// Returns true if an argument of type Ty needs to be passed in a 627 /// contiguous block of registers in calling convention CallConv. 628 bool functionArgumentNeedsConsecutiveRegisters( 629 Type *Ty, CallingConv::ID CallConv, bool isVarArg, 630 const DataLayout &DL) const override; 631 632 /// If a physical register, this returns the register that receives the 633 /// exception address on entry to an EH pad. 634 Register 635 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 636 637 /// If a physical register, this returns the register that receives the 638 /// exception typeid on entry to a landing pad. 639 Register 640 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 641 642 Instruction *makeDMB(IRBuilderBase &Builder, ARM_MB::MemBOpt Domain) const; 643 Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, 644 AtomicOrdering Ord) const override; 645 Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, 646 AtomicOrdering Ord) const override; 647 648 void 649 emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override; 650 651 Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, 652 AtomicOrdering Ord) const override; 653 Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, 654 AtomicOrdering Ord) const override; 655 656 unsigned getMaxSupportedInterleaveFactor() const override; 657 658 bool lowerInterleavedLoad(LoadInst *LI, 659 ArrayRef<ShuffleVectorInst *> Shuffles, 660 ArrayRef<unsigned> Indices, 661 unsigned Factor) const override; 662 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, 663 unsigned Factor) const override; 664 665 bool shouldInsertFencesForAtomic(const Instruction *I) const override; 666 TargetLoweringBase::AtomicExpansionKind 667 shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 668 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 669 TargetLoweringBase::AtomicExpansionKind 670 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 671 TargetLoweringBase::AtomicExpansionKind 672 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 673 674 bool useLoadStackGuardNode() const override; 675 676 void insertSSPDeclarations(Module &M) const override; 677 Value *getSDagStackGuard(const Module &M) const override; 678 Function *getSSPStackGuardCheck(const Module &M) const override; 679 680 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, 681 unsigned &Cost) const override; 682 683 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, 684 const MachineFunction &MF) const override { 685 // Do not merge to larger than i32. 686 return (MemVT.getSizeInBits() <= 32); 687 } 688 689 bool isCheapToSpeculateCttz() const override; 690 bool isCheapToSpeculateCtlz() const override; 691 692 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 693 return VT.isScalarInteger(); 694 } 695 696 bool supportSwiftError() const override { 697 return true; 698 } 699 700 bool hasStandaloneRem(EVT VT) const override { 701 return HasStandaloneRem; 702 } 703 704 bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override; 705 706 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const; 707 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const; 708 709 /// Returns true if \p VecTy is a legal interleaved access type. This 710 /// function checks the vector element type and the overall width of the 711 /// vector. 712 bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy, 713 Align Alignment, 714 const DataLayout &DL) const; 715 716 bool isMulAddWithConstProfitable(const SDValue &AddNode, 717 const SDValue &ConstNode) const override; 718 719 bool alignLoopsWithOptSize() const override; 720 721 /// Returns the number of interleaved accesses that will be generated when 722 /// lowering accesses of the given type. 723 unsigned getNumInterleavedAccesses(VectorType *VecTy, 724 const DataLayout &DL) const; 725 726 void finalizeLowering(MachineFunction &MF) const override; 727 728 /// Return the correct alignment for the current calling convention. 729 Align getABIAlignmentForCallingConv(Type *ArgTy, 730 const DataLayout &DL) const override; 731 732 bool isDesirableToCommuteWithShift(const SDNode *N, 733 CombineLevel Level) const override; 734 735 bool shouldFoldConstantShiftPairToMask(const SDNode *N, 736 CombineLevel Level) const override; 737 738 bool preferIncOfAddToSubOfNot(EVT VT) const override; 739 740 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override; 741 742 protected: 743 std::pair<const TargetRegisterClass *, uint8_t> 744 findRepresentativeClass(const TargetRegisterInfo *TRI, 745 MVT VT) const override; 746 747 private: 748 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 749 /// make the right decision when generating code for different targets. 750 const ARMSubtarget *Subtarget; 751 752 const TargetRegisterInfo *RegInfo; 753 754 const InstrItineraryData *Itins; 755 756 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 757 unsigned ARMPCLabelIndex; 758 759 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper 760 // check. 761 bool InsertFencesForAtomic; 762 763 bool HasStandaloneRem = true; 764 765 void addTypeForNEON(MVT VT, MVT PromotedLdStVT); 766 void addDRTypeForNEON(MVT VT); 767 void addQRTypeForNEON(MVT VT); 768 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const; 769 770 using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>; 771 772 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, 773 SDValue &Arg, RegsToPassVector &RegsToPass, 774 CCValAssign &VA, CCValAssign &NextVA, 775 SDValue &StackPtr, 776 SmallVectorImpl<SDValue> &MemOpChains, 777 bool IsTailCall, 778 int SPDiff) const; 779 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 780 SDValue &Root, SelectionDAG &DAG, 781 const SDLoc &dl) const; 782 783 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC, 784 bool isVarArg) const; 785 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 786 bool isVarArg) const; 787 std::pair<SDValue, MachinePointerInfo> 788 computeAddrForCallArg(const SDLoc &dl, SelectionDAG &DAG, 789 const CCValAssign &VA, SDValue StackPtr, 790 bool IsTailCall, int SPDiff) const; 791 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 792 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 793 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const; 794 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG, 795 const ARMSubtarget *Subtarget) const; 796 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 797 const ARMSubtarget *Subtarget) const; 798 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 799 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 800 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 801 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 802 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 803 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const; 804 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 805 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 806 SelectionDAG &DAG) const; 807 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 808 SelectionDAG &DAG, 809 TLSModel::Model model) const; 810 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 811 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const; 812 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 813 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 814 SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const; 815 SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const; 816 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 817 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 818 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 819 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 820 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 821 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 822 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 823 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 824 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 825 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 826 SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 827 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, 828 const ARMSubtarget *ST) const; 829 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 830 const ARMSubtarget *ST) const; 831 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 832 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 833 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; 834 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const; 835 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed, 836 SmallVectorImpl<SDValue> &Results) const; 837 SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG, 838 const ARMSubtarget *Subtarget) const; 839 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed, 840 SDValue &Chain) const; 841 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const; 842 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 843 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 844 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 845 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 846 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 847 SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const; 848 void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results, 849 SelectionDAG &DAG) const; 850 void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results, 851 SelectionDAG &DAG) const; 852 853 Register getRegisterByName(const char* RegName, LLT VT, 854 const MachineFunction &MF) const override; 855 856 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 857 SmallVectorImpl<SDNode *> &Created) const override; 858 859 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 860 EVT VT) const override; 861 862 SDValue MoveToHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, MVT ValVT, 863 SDValue Val) const; 864 SDValue MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, 865 MVT ValVT, SDValue Val) const; 866 867 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 868 869 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 870 CallingConv::ID CallConv, bool isVarArg, 871 const SmallVectorImpl<ISD::InputArg> &Ins, 872 const SDLoc &dl, SelectionDAG &DAG, 873 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 874 SDValue ThisVal) const; 875 876 bool supportSplitCSR(MachineFunction *MF) const override { 877 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 878 MF->getFunction().hasFnAttribute(Attribute::NoUnwind); 879 } 880 881 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 882 void insertCopiesSplitCSR( 883 MachineBasicBlock *Entry, 884 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 885 886 bool 887 splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, 888 SDValue *Parts, unsigned NumParts, MVT PartVT, 889 Optional<CallingConv::ID> CC) const override; 890 891 SDValue 892 joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, 893 const SDValue *Parts, unsigned NumParts, 894 MVT PartVT, EVT ValueVT, 895 Optional<CallingConv::ID> CC) const override; 896 897 SDValue 898 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 899 const SmallVectorImpl<ISD::InputArg> &Ins, 900 const SDLoc &dl, SelectionDAG &DAG, 901 SmallVectorImpl<SDValue> &InVals) const override; 902 903 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl, 904 SDValue &Chain, const Value *OrigArg, 905 unsigned InRegsParamRecordIdx, int ArgOffset, 906 unsigned ArgSize) const; 907 908 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 909 const SDLoc &dl, SDValue &Chain, 910 unsigned ArgOffset, unsigned TotalArgRegsSaveSize, 911 bool ForceMutable = false) const; 912 913 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 914 SmallVectorImpl<SDValue> &InVals) const override; 915 916 /// HandleByVal - Target-specific cleanup for ByVal support. 917 void HandleByVal(CCState *, unsigned &, Align) const override; 918 919 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 920 /// for tail call optimization. Targets which want to do tail call 921 /// optimization should implement this function. 922 bool IsEligibleForTailCallOptimization( 923 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 924 bool isCalleeStructRet, bool isCallerStructRet, 925 const SmallVectorImpl<ISD::OutputArg> &Outs, 926 const SmallVectorImpl<SDValue> &OutVals, 927 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG, 928 const bool isIndirect) const; 929 930 bool CanLowerReturn(CallingConv::ID CallConv, 931 MachineFunction &MF, bool isVarArg, 932 const SmallVectorImpl<ISD::OutputArg> &Outs, 933 LLVMContext &Context) const override; 934 935 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 936 const SmallVectorImpl<ISD::OutputArg> &Outs, 937 const SmallVectorImpl<SDValue> &OutVals, 938 const SDLoc &dl, SelectionDAG &DAG) const override; 939 940 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 941 942 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 943 944 bool shouldConsiderGEPOffsetSplit() const override { return true; } 945 946 bool isUnsupportedFloatingType(EVT VT) const; 947 948 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal, 949 SDValue ARMcc, SDValue CCR, SDValue Cmp, 950 SelectionDAG &DAG) const; 951 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 952 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const; 953 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 954 const SDLoc &dl, bool Signaling = false) const; 955 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const; 956 957 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 958 959 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, 960 MachineBasicBlock *DispatchBB, int FI) const; 961 962 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const; 963 964 bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const; 965 966 MachineBasicBlock *EmitStructByval(MachineInstr &MI, 967 MachineBasicBlock *MBB) const; 968 969 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI, 970 MachineBasicBlock *MBB) const; 971 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI, 972 MachineBasicBlock *MBB) const; 973 void addMVEVectorTypes(bool HasMVEFP); 974 void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action); 975 void setAllExpand(MVT VT); 976 }; 977 978 enum VMOVModImmType { 979 VMOVModImm, 980 VMVNModImm, 981 MVEVMVNModImm, 982 OtherModImm 983 }; 984 985 namespace ARM { 986 987 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 988 const TargetLibraryInfo *libInfo); 989 990 } // end namespace ARM 991 992 } // end namespace llvm 993 994 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 995