1 //===- ARMFrameLowering.cpp - ARM Frame Information -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the ARM implementation of TargetFrameLowering class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMFrameLowering.h" 14 #include "ARMBaseInstrInfo.h" 15 #include "ARMBaseRegisterInfo.h" 16 #include "ARMConstantPoolValue.h" 17 #include "ARMMachineFunctionInfo.h" 18 #include "ARMSubtarget.h" 19 #include "MCTargetDesc/ARMAddressingModes.h" 20 #include "MCTargetDesc/ARMBaseInfo.h" 21 #include "Utils/ARMBaseInfo.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/SmallPtrSet.h" 25 #include "llvm/ADT/SmallVector.h" 26 #include "llvm/CodeGen/MachineBasicBlock.h" 27 #include "llvm/CodeGen/MachineConstantPool.h" 28 #include "llvm/CodeGen/MachineFrameInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineInstr.h" 31 #include "llvm/CodeGen/MachineInstrBuilder.h" 32 #include "llvm/CodeGen/MachineJumpTableInfo.h" 33 #include "llvm/CodeGen/MachineModuleInfo.h" 34 #include "llvm/CodeGen/MachineOperand.h" 35 #include "llvm/CodeGen/MachineRegisterInfo.h" 36 #include "llvm/CodeGen/RegisterScavenging.h" 37 #include "llvm/CodeGen/TargetInstrInfo.h" 38 #include "llvm/CodeGen/TargetOpcodes.h" 39 #include "llvm/CodeGen/TargetRegisterInfo.h" 40 #include "llvm/CodeGen/TargetSubtargetInfo.h" 41 #include "llvm/IR/Attributes.h" 42 #include "llvm/IR/CallingConv.h" 43 #include "llvm/IR/DebugLoc.h" 44 #include "llvm/IR/Function.h" 45 #include "llvm/MC/MCContext.h" 46 #include "llvm/MC/MCDwarf.h" 47 #include "llvm/MC/MCInstrDesc.h" 48 #include "llvm/MC/MCRegisterInfo.h" 49 #include "llvm/Support/CodeGen.h" 50 #include "llvm/Support/CommandLine.h" 51 #include "llvm/Support/Compiler.h" 52 #include "llvm/Support/Debug.h" 53 #include "llvm/Support/ErrorHandling.h" 54 #include "llvm/Support/MathExtras.h" 55 #include "llvm/Support/raw_ostream.h" 56 #include "llvm/Target/TargetMachine.h" 57 #include "llvm/Target/TargetOptions.h" 58 #include <algorithm> 59 #include <cassert> 60 #include <cstddef> 61 #include <cstdint> 62 #include <iterator> 63 #include <utility> 64 #include <vector> 65 66 #define DEBUG_TYPE "arm-frame-lowering" 67 68 using namespace llvm; 69 70 static cl::opt<bool> 71 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true), 72 cl::desc("Align ARM NEON spills in prolog and epilog")); 73 74 static MachineBasicBlock::iterator 75 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI, 76 unsigned NumAlignedDPRCS2Regs); 77 78 ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti) 79 : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, Align(4)), 80 STI(sti) {} 81 82 bool ARMFrameLowering::keepFramePointer(const MachineFunction &MF) const { 83 // iOS always has a FP for backtracking, force other targets to keep their FP 84 // when doing FastISel. The emitted code is currently superior, and in cases 85 // like test-suite's lencod FastISel isn't quite correct when FP is eliminated. 86 return MF.getSubtarget<ARMSubtarget>().useFastISel(); 87 } 88 89 /// Returns true if the target can safely skip saving callee-saved registers 90 /// for noreturn nounwind functions. 91 bool ARMFrameLowering::enableCalleeSaveSkip(const MachineFunction &MF) const { 92 assert(MF.getFunction().hasFnAttribute(Attribute::NoReturn) && 93 MF.getFunction().hasFnAttribute(Attribute::NoUnwind) && 94 !MF.getFunction().hasFnAttribute(Attribute::UWTable)); 95 96 // Frame pointer and link register are not treated as normal CSR, thus we 97 // can always skip CSR saves for nonreturning functions. 98 return true; 99 } 100 101 /// hasFP - Return true if the specified function should have a dedicated frame 102 /// pointer register. This is true if the function has variable sized allocas 103 /// or if frame pointer elimination is disabled. 104 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const { 105 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); 106 const MachineFrameInfo &MFI = MF.getFrameInfo(); 107 108 // ABI-required frame pointer. 109 if (MF.getTarget().Options.DisableFramePointerElim(MF)) 110 return true; 111 112 // Frame pointer required for use within this function. 113 return (RegInfo->needsStackRealignment(MF) || 114 MFI.hasVarSizedObjects() || 115 MFI.isFrameAddressTaken()); 116 } 117 118 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 119 /// not required, we reserve argument space for call sites in the function 120 /// immediately on entry to the current function. This eliminates the need for 121 /// add/sub sp brackets around call sites. Returns true if the call frame is 122 /// included as part of the stack frame. 123 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { 124 const MachineFrameInfo &MFI = MF.getFrameInfo(); 125 unsigned CFSize = MFI.getMaxCallFrameSize(); 126 // It's not always a good idea to include the call frame as part of the 127 // stack frame. ARM (especially Thumb) has small immediate offset to 128 // address the stack frame. So a large call frame can cause poor codegen 129 // and may even makes it impossible to scavenge a register. 130 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 131 return false; 132 133 return !MFI.hasVarSizedObjects(); 134 } 135 136 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the 137 /// call frame pseudos can be simplified. Unlike most targets, having a FP 138 /// is not sufficient here since we still may reference some objects via SP 139 /// even when FP is available in Thumb2 mode. 140 bool 141 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const { 142 return hasReservedCallFrame(MF) || MF.getFrameInfo().hasVarSizedObjects(); 143 } 144 145 static void emitRegPlusImmediate( 146 bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 147 const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg, 148 unsigned SrcReg, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags, 149 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 150 if (isARM) 151 emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes, 152 Pred, PredReg, TII, MIFlags); 153 else 154 emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes, 155 Pred, PredReg, TII, MIFlags); 156 } 157 158 static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB, 159 MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, 160 const ARMBaseInstrInfo &TII, int NumBytes, 161 unsigned MIFlags = MachineInstr::NoFlags, 162 ARMCC::CondCodes Pred = ARMCC::AL, 163 unsigned PredReg = 0) { 164 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, 165 MIFlags, Pred, PredReg); 166 } 167 168 static int sizeOfSPAdjustment(const MachineInstr &MI) { 169 int RegSize; 170 switch (MI.getOpcode()) { 171 case ARM::VSTMDDB_UPD: 172 RegSize = 8; 173 break; 174 case ARM::STMDB_UPD: 175 case ARM::t2STMDB_UPD: 176 RegSize = 4; 177 break; 178 case ARM::t2STR_PRE: 179 case ARM::STR_PRE_IMM: 180 return 4; 181 default: 182 llvm_unreachable("Unknown push or pop like instruction"); 183 } 184 185 int count = 0; 186 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+ 187 // pred) so the list starts at 4. 188 for (int i = MI.getNumOperands() - 1; i >= 4; --i) 189 count += RegSize; 190 return count; 191 } 192 193 static bool WindowsRequiresStackProbe(const MachineFunction &MF, 194 size_t StackSizeInBytes) { 195 const MachineFrameInfo &MFI = MF.getFrameInfo(); 196 const Function &F = MF.getFunction(); 197 unsigned StackProbeSize = (MFI.getStackProtectorIndex() > 0) ? 4080 : 4096; 198 if (F.hasFnAttribute("stack-probe-size")) 199 F.getFnAttribute("stack-probe-size") 200 .getValueAsString() 201 .getAsInteger(0, StackProbeSize); 202 return (StackSizeInBytes >= StackProbeSize) && 203 !F.hasFnAttribute("no-stack-arg-probe"); 204 } 205 206 namespace { 207 208 struct StackAdjustingInsts { 209 struct InstInfo { 210 MachineBasicBlock::iterator I; 211 unsigned SPAdjust; 212 bool BeforeFPSet; 213 }; 214 215 SmallVector<InstInfo, 4> Insts; 216 217 void addInst(MachineBasicBlock::iterator I, unsigned SPAdjust, 218 bool BeforeFPSet = false) { 219 InstInfo Info = {I, SPAdjust, BeforeFPSet}; 220 Insts.push_back(Info); 221 } 222 223 void addExtraBytes(const MachineBasicBlock::iterator I, unsigned ExtraBytes) { 224 auto Info = 225 llvm::find_if(Insts, [&](InstInfo &Info) { return Info.I == I; }); 226 assert(Info != Insts.end() && "invalid sp adjusting instruction"); 227 Info->SPAdjust += ExtraBytes; 228 } 229 230 void emitDefCFAOffsets(MachineBasicBlock &MBB, const DebugLoc &dl, 231 const ARMBaseInstrInfo &TII, bool HasFP) { 232 MachineFunction &MF = *MBB.getParent(); 233 unsigned CFAOffset = 0; 234 for (auto &Info : Insts) { 235 if (HasFP && !Info.BeforeFPSet) 236 return; 237 238 CFAOffset += Info.SPAdjust; 239 unsigned CFIIndex = MF.addFrameInst( 240 MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset)); 241 BuildMI(MBB, std::next(Info.I), dl, 242 TII.get(TargetOpcode::CFI_INSTRUCTION)) 243 .addCFIIndex(CFIIndex) 244 .setMIFlags(MachineInstr::FrameSetup); 245 } 246 } 247 }; 248 249 } // end anonymous namespace 250 251 /// Emit an instruction sequence that will align the address in 252 /// register Reg by zero-ing out the lower bits. For versions of the 253 /// architecture that support Neon, this must be done in a single 254 /// instruction, since skipAlignedDPRCS2Spills assumes it is done in a 255 /// single instruction. That function only gets called when optimizing 256 /// spilling of D registers on a core with the Neon instruction set 257 /// present. 258 static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI, 259 const TargetInstrInfo &TII, 260 MachineBasicBlock &MBB, 261 MachineBasicBlock::iterator MBBI, 262 const DebugLoc &DL, const unsigned Reg, 263 const Align Alignment, 264 const bool MustBeSingleInstruction) { 265 const ARMSubtarget &AST = 266 static_cast<const ARMSubtarget &>(MF.getSubtarget()); 267 const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops(); 268 const unsigned AlignMask = Alignment.value() - 1U; 269 const unsigned NrBitsToZero = Log2(Alignment); 270 assert(!AFI->isThumb1OnlyFunction() && "Thumb1 not supported"); 271 if (!AFI->isThumbFunction()) { 272 // if the BFC instruction is available, use that to zero the lower 273 // bits: 274 // bfc Reg, #0, log2(Alignment) 275 // otherwise use BIC, if the mask to zero the required number of bits 276 // can be encoded in the bic immediate field 277 // bic Reg, Reg, Alignment-1 278 // otherwise, emit 279 // lsr Reg, Reg, log2(Alignment) 280 // lsl Reg, Reg, log2(Alignment) 281 if (CanUseBFC) { 282 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) 283 .addReg(Reg, RegState::Kill) 284 .addImm(~AlignMask) 285 .add(predOps(ARMCC::AL)); 286 } else if (AlignMask <= 255) { 287 BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) 288 .addReg(Reg, RegState::Kill) 289 .addImm(AlignMask) 290 .add(predOps(ARMCC::AL)) 291 .add(condCodeOp()); 292 } else { 293 assert(!MustBeSingleInstruction && 294 "Shouldn't call emitAligningInstructions demanding a single " 295 "instruction to be emitted for large stack alignment for a target " 296 "without BFC."); 297 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) 298 .addReg(Reg, RegState::Kill) 299 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero)) 300 .add(predOps(ARMCC::AL)) 301 .add(condCodeOp()); 302 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) 303 .addReg(Reg, RegState::Kill) 304 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero)) 305 .add(predOps(ARMCC::AL)) 306 .add(condCodeOp()); 307 } 308 } else { 309 // Since this is only reached for Thumb-2 targets, the BFC instruction 310 // should always be available. 311 assert(CanUseBFC); 312 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg) 313 .addReg(Reg, RegState::Kill) 314 .addImm(~AlignMask) 315 .add(predOps(ARMCC::AL)); 316 } 317 } 318 319 /// We need the offset of the frame pointer relative to other MachineFrameInfo 320 /// offsets which are encoded relative to SP at function begin. 321 /// See also emitPrologue() for how the FP is set up. 322 /// Unfortunately we cannot determine this value in determineCalleeSaves() yet 323 /// as assignCalleeSavedSpillSlots() hasn't run at this point. Instead we use 324 /// this to produce a conservative estimate that we check in an assert() later. 325 static int getMaxFPOffset(const ARMSubtarget &STI, const ARMFunctionInfo &AFI) { 326 // For Thumb1, push.w isn't available, so the first push will always push 327 // r7 and lr onto the stack first. 328 if (AFI.isThumb1OnlyFunction()) 329 return -AFI.getArgRegsSaveSize() - (2 * 4); 330 // This is a conservative estimation: Assume the frame pointer being r7 and 331 // pc("r15") up to r8 getting spilled before (= 8 registers). 332 int FPCXTSaveSize = (STI.hasV8_1MMainlineOps() && AFI.isCmseNSEntryFunction()) ? 4 : 0; 333 return - FPCXTSaveSize - AFI.getArgRegsSaveSize() - (8 * 4); 334 } 335 336 void ARMFrameLowering::emitPrologue(MachineFunction &MF, 337 MachineBasicBlock &MBB) const { 338 MachineBasicBlock::iterator MBBI = MBB.begin(); 339 MachineFrameInfo &MFI = MF.getFrameInfo(); 340 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 341 MachineModuleInfo &MMI = MF.getMMI(); 342 MCContext &Context = MMI.getContext(); 343 const TargetMachine &TM = MF.getTarget(); 344 const MCRegisterInfo *MRI = Context.getRegisterInfo(); 345 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo(); 346 const ARMBaseInstrInfo &TII = *STI.getInstrInfo(); 347 assert(!AFI->isThumb1OnlyFunction() && 348 "This emitPrologue does not support Thumb1!"); 349 bool isARM = !AFI->isThumbFunction(); 350 Align Alignment = STI.getFrameLowering()->getStackAlign(); 351 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(); 352 unsigned NumBytes = MFI.getStackSize(); 353 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); 354 int FPCXTSaveSize = 0; 355 356 // Debug location must be unknown since the first debug location is used 357 // to determine the end of the prologue. 358 DebugLoc dl; 359 360 Register FramePtr = RegInfo->getFrameRegister(MF); 361 362 // Determine the sizes of each callee-save spill areas and record which frame 363 // belongs to which callee-save spill areas. 364 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 365 int FramePtrSpillFI = 0; 366 int D8SpillFI = 0; 367 368 // All calls are tail calls in GHC calling conv, and functions have no 369 // prologue/epilogue. 370 if (MF.getFunction().getCallingConv() == CallingConv::GHC) 371 return; 372 373 StackAdjustingInsts DefCFAOffsetCandidates; 374 bool HasFP = hasFP(MF); 375 376 // Allocate the vararg register save area. 377 if (ArgRegsSaveSize) { 378 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize, 379 MachineInstr::FrameSetup); 380 DefCFAOffsetCandidates.addInst(std::prev(MBBI), ArgRegsSaveSize, true); 381 } 382 383 if (!AFI->hasStackFrame() && 384 (!STI.isTargetWindows() || !WindowsRequiresStackProbe(MF, NumBytes))) { 385 if (NumBytes - ArgRegsSaveSize != 0) { 386 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize), 387 MachineInstr::FrameSetup); 388 DefCFAOffsetCandidates.addInst(std::prev(MBBI), 389 NumBytes - ArgRegsSaveSize, true); 390 } 391 DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP); 392 return; 393 } 394 395 // Determine spill area sizes. 396 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 397 unsigned Reg = CSI[i].getReg(); 398 int FI = CSI[i].getFrameIdx(); 399 switch (Reg) { 400 case ARM::R8: 401 case ARM::R9: 402 case ARM::R10: 403 case ARM::R11: 404 case ARM::R12: 405 if (STI.splitFramePushPop(MF)) { 406 GPRCS2Size += 4; 407 break; 408 } 409 LLVM_FALLTHROUGH; 410 case ARM::R0: 411 case ARM::R1: 412 case ARM::R2: 413 case ARM::R3: 414 case ARM::R4: 415 case ARM::R5: 416 case ARM::R6: 417 case ARM::R7: 418 case ARM::LR: 419 if (Reg == FramePtr) 420 FramePtrSpillFI = FI; 421 GPRCS1Size += 4; 422 break; 423 case ARM::FPCXTNS: 424 FPCXTSaveSize = 4; 425 break; 426 default: 427 // This is a DPR. Exclude the aligned DPRCS2 spills. 428 if (Reg == ARM::D8) 429 D8SpillFI = FI; 430 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) 431 DPRCSSize += 8; 432 } 433 } 434 435 // Move past FPCXT area. 436 MachineBasicBlock::iterator LastPush = MBB.end(), GPRCS1Push, GPRCS2Push; 437 if (FPCXTSaveSize > 0) { 438 LastPush = MBBI++; 439 DefCFAOffsetCandidates.addInst(LastPush, FPCXTSaveSize, true); 440 } 441 442 // Move past area 1. 443 if (GPRCS1Size > 0) { 444 GPRCS1Push = LastPush = MBBI++; 445 DefCFAOffsetCandidates.addInst(LastPush, GPRCS1Size, true); 446 } 447 448 // Determine starting offsets of spill areas. 449 unsigned FPCXTOffset = NumBytes - ArgRegsSaveSize - FPCXTSaveSize; 450 unsigned GPRCS1Offset = FPCXTOffset - GPRCS1Size; 451 unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size; 452 Align DPRAlign = DPRCSSize ? std::min(Align(8), Alignment) : Align(4); 453 unsigned DPRGapSize = 454 (GPRCS1Size + GPRCS2Size + FPCXTSaveSize + ArgRegsSaveSize) % 455 DPRAlign.value(); 456 457 unsigned DPRCSOffset = GPRCS2Offset - DPRGapSize - DPRCSSize; 458 int FramePtrOffsetInPush = 0; 459 if (HasFP) { 460 int FPOffset = MFI.getObjectOffset(FramePtrSpillFI); 461 assert(getMaxFPOffset(STI, *AFI) <= FPOffset && 462 "Max FP estimation is wrong"); 463 FramePtrOffsetInPush = FPOffset + ArgRegsSaveSize + FPCXTSaveSize; 464 AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) + 465 NumBytes); 466 } 467 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 468 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 469 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 470 471 // Move past area 2. 472 if (GPRCS2Size > 0) { 473 GPRCS2Push = LastPush = MBBI++; 474 DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size); 475 } 476 477 // Prolog/epilog inserter assumes we correctly align DPRs on the stack, so our 478 // .cfi_offset operations will reflect that. 479 if (DPRGapSize) { 480 assert(DPRGapSize == 4 && "unexpected alignment requirements for DPRs"); 481 if (LastPush != MBB.end() && 482 tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, DPRGapSize)) 483 DefCFAOffsetCandidates.addExtraBytes(LastPush, DPRGapSize); 484 else { 485 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize, 486 MachineInstr::FrameSetup); 487 DefCFAOffsetCandidates.addInst(std::prev(MBBI), DPRGapSize); 488 } 489 } 490 491 // Move past area 3. 492 if (DPRCSSize > 0) { 493 // Since vpush register list cannot have gaps, there may be multiple vpush 494 // instructions in the prologue. 495 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VSTMDDB_UPD) { 496 DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(*MBBI)); 497 LastPush = MBBI++; 498 } 499 } 500 501 // Move past the aligned DPRCS2 area. 502 if (AFI->getNumAlignedDPRCS2Regs() > 0) { 503 MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs()); 504 // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and 505 // leaves the stack pointer pointing to the DPRCS2 area. 506 // 507 // Adjust NumBytes to represent the stack slots below the DPRCS2 area. 508 NumBytes += MFI.getObjectOffset(D8SpillFI); 509 } else 510 NumBytes = DPRCSOffset; 511 512 if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) { 513 uint32_t NumWords = NumBytes >> 2; 514 515 if (NumWords < 65536) 516 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) 517 .addImm(NumWords) 518 .setMIFlags(MachineInstr::FrameSetup) 519 .add(predOps(ARMCC::AL)); 520 else 521 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4) 522 .addImm(NumWords) 523 .setMIFlags(MachineInstr::FrameSetup); 524 525 switch (TM.getCodeModel()) { 526 case CodeModel::Tiny: 527 llvm_unreachable("Tiny code model not available on ARM."); 528 case CodeModel::Small: 529 case CodeModel::Medium: 530 case CodeModel::Kernel: 531 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) 532 .add(predOps(ARMCC::AL)) 533 .addExternalSymbol("__chkstk") 534 .addReg(ARM::R4, RegState::Implicit) 535 .setMIFlags(MachineInstr::FrameSetup); 536 break; 537 case CodeModel::Large: 538 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) 539 .addExternalSymbol("__chkstk") 540 .setMIFlags(MachineInstr::FrameSetup); 541 542 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr)) 543 .add(predOps(ARMCC::AL)) 544 .addReg(ARM::R12, RegState::Kill) 545 .addReg(ARM::R4, RegState::Implicit) 546 .setMIFlags(MachineInstr::FrameSetup); 547 break; 548 } 549 550 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP) 551 .addReg(ARM::SP, RegState::Kill) 552 .addReg(ARM::R4, RegState::Kill) 553 .setMIFlags(MachineInstr::FrameSetup) 554 .add(predOps(ARMCC::AL)) 555 .add(condCodeOp()); 556 NumBytes = 0; 557 } 558 559 if (NumBytes) { 560 // Adjust SP after all the callee-save spills. 561 if (AFI->getNumAlignedDPRCS2Regs() == 0 && 562 tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, NumBytes)) 563 DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes); 564 else { 565 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, 566 MachineInstr::FrameSetup); 567 DefCFAOffsetCandidates.addInst(std::prev(MBBI), NumBytes); 568 } 569 570 if (HasFP && isARM) 571 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24 572 // Note it's not safe to do this in Thumb2 mode because it would have 573 // taken two instructions: 574 // mov sp, r7 575 // sub sp, #24 576 // If an interrupt is taken between the two instructions, then sp is in 577 // an inconsistent state (pointing to the middle of callee-saved area). 578 // The interrupt handler can end up clobbering the registers. 579 AFI->setShouldRestoreSPFromFP(true); 580 } 581 582 // Set FP to point to the stack slot that contains the previous FP. 583 // For iOS, FP is R7, which has now been stored in spill area 1. 584 // Otherwise, if this is not iOS, all the callee-saved registers go 585 // into spill area 1, including the FP in R11. In either case, it 586 // is in area one and the adjustment needs to take place just after 587 // that push. 588 if (HasFP) { 589 MachineBasicBlock::iterator AfterPush = std::next(GPRCS1Push); 590 unsigned PushSize = sizeOfSPAdjustment(*GPRCS1Push); 591 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush, 592 dl, TII, FramePtr, ARM::SP, 593 PushSize + FramePtrOffsetInPush, 594 MachineInstr::FrameSetup); 595 if (FramePtrOffsetInPush + PushSize != 0) { 596 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa( 597 nullptr, MRI->getDwarfRegNum(FramePtr, true), 598 FPCXTSaveSize + ArgRegsSaveSize - FramePtrOffsetInPush)); 599 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 600 .addCFIIndex(CFIIndex) 601 .setMIFlags(MachineInstr::FrameSetup); 602 } else { 603 unsigned CFIIndex = 604 MF.addFrameInst(MCCFIInstruction::createDefCfaRegister( 605 nullptr, MRI->getDwarfRegNum(FramePtr, true))); 606 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 607 .addCFIIndex(CFIIndex) 608 .setMIFlags(MachineInstr::FrameSetup); 609 } 610 } 611 612 // Now that the prologue's actual instructions are finalised, we can insert 613 // the necessary DWARF cf instructions to describe the situation. Start by 614 // recording where each register ended up: 615 if (GPRCS1Size > 0) { 616 MachineBasicBlock::iterator Pos = std::next(GPRCS1Push); 617 int CFIIndex; 618 for (const auto &Entry : CSI) { 619 unsigned Reg = Entry.getReg(); 620 int FI = Entry.getFrameIdx(); 621 switch (Reg) { 622 case ARM::R8: 623 case ARM::R9: 624 case ARM::R10: 625 case ARM::R11: 626 case ARM::R12: 627 if (STI.splitFramePushPop(MF)) 628 break; 629 LLVM_FALLTHROUGH; 630 case ARM::R0: 631 case ARM::R1: 632 case ARM::R2: 633 case ARM::R3: 634 case ARM::R4: 635 case ARM::R5: 636 case ARM::R6: 637 case ARM::R7: 638 case ARM::LR: 639 CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( 640 nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI))); 641 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 642 .addCFIIndex(CFIIndex) 643 .setMIFlags(MachineInstr::FrameSetup); 644 break; 645 } 646 } 647 } 648 649 if (GPRCS2Size > 0) { 650 MachineBasicBlock::iterator Pos = std::next(GPRCS2Push); 651 for (const auto &Entry : CSI) { 652 unsigned Reg = Entry.getReg(); 653 int FI = Entry.getFrameIdx(); 654 switch (Reg) { 655 case ARM::R8: 656 case ARM::R9: 657 case ARM::R10: 658 case ARM::R11: 659 case ARM::R12: 660 if (STI.splitFramePushPop(MF)) { 661 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); 662 unsigned Offset = MFI.getObjectOffset(FI); 663 unsigned CFIIndex = MF.addFrameInst( 664 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset)); 665 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 666 .addCFIIndex(CFIIndex) 667 .setMIFlags(MachineInstr::FrameSetup); 668 } 669 break; 670 } 671 } 672 } 673 674 if (DPRCSSize > 0) { 675 // Since vpush register list cannot have gaps, there may be multiple vpush 676 // instructions in the prologue. 677 MachineBasicBlock::iterator Pos = std::next(LastPush); 678 for (const auto &Entry : CSI) { 679 unsigned Reg = Entry.getReg(); 680 int FI = Entry.getFrameIdx(); 681 if ((Reg >= ARM::D0 && Reg <= ARM::D31) && 682 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) { 683 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); 684 unsigned Offset = MFI.getObjectOffset(FI); 685 unsigned CFIIndex = MF.addFrameInst( 686 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset)); 687 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 688 .addCFIIndex(CFIIndex) 689 .setMIFlags(MachineInstr::FrameSetup); 690 } 691 } 692 } 693 694 // Now we can emit descriptions of where the canonical frame address was 695 // throughout the process. If we have a frame pointer, it takes over the job 696 // half-way through, so only the first few .cfi_def_cfa_offset instructions 697 // actually get emitted. 698 DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP); 699 700 if (STI.isTargetELF() && hasFP(MF)) 701 MFI.setOffsetAdjustment(MFI.getOffsetAdjustment() - 702 AFI->getFramePtrSpillOffset()); 703 704 AFI->setFPCXTSaveAreaSize(FPCXTSaveSize); 705 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 706 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 707 AFI->setDPRCalleeSavedGapSize(DPRGapSize); 708 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 709 710 // If we need dynamic stack realignment, do it here. Be paranoid and make 711 // sure if we also have VLAs, we have a base pointer for frame access. 712 // If aligned NEON registers were spilled, the stack has already been 713 // realigned. 714 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) { 715 Align MaxAlign = MFI.getMaxAlign(); 716 assert(!AFI->isThumb1OnlyFunction()); 717 if (!AFI->isThumbFunction()) { 718 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign, 719 false); 720 } else { 721 // We cannot use sp as source/dest register here, thus we're using r4 to 722 // perform the calculations. We're emitting the following sequence: 723 // mov r4, sp 724 // -- use emitAligningInstructions to produce best sequence to zero 725 // -- out lower bits in r4 726 // mov sp, r4 727 // FIXME: It will be better just to find spare register here. 728 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) 729 .addReg(ARM::SP, RegState::Kill) 730 .add(predOps(ARMCC::AL)); 731 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign, 732 false); 733 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) 734 .addReg(ARM::R4, RegState::Kill) 735 .add(predOps(ARMCC::AL)); 736 } 737 738 AFI->setShouldRestoreSPFromFP(true); 739 } 740 741 // If we need a base pointer, set it up here. It's whatever the value 742 // of the stack pointer is at this point. Any variable size objects 743 // will be allocated after this, so we can still use the base pointer 744 // to reference locals. 745 // FIXME: Clarify FrameSetup flags here. 746 if (RegInfo->hasBasePointer(MF)) { 747 if (isARM) 748 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister()) 749 .addReg(ARM::SP) 750 .add(predOps(ARMCC::AL)) 751 .add(condCodeOp()); 752 else 753 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister()) 754 .addReg(ARM::SP) 755 .add(predOps(ARMCC::AL)); 756 } 757 758 // If the frame has variable sized objects then the epilogue must restore 759 // the sp from fp. We can assume there's an FP here since hasFP already 760 // checks for hasVarSizedObjects. 761 if (MFI.hasVarSizedObjects()) 762 AFI->setShouldRestoreSPFromFP(true); 763 } 764 765 void ARMFrameLowering::emitEpilogue(MachineFunction &MF, 766 MachineBasicBlock &MBB) const { 767 MachineFrameInfo &MFI = MF.getFrameInfo(); 768 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 769 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); 770 const ARMBaseInstrInfo &TII = 771 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 772 assert(!AFI->isThumb1OnlyFunction() && 773 "This emitEpilogue does not support Thumb1!"); 774 bool isARM = !AFI->isThumbFunction(); 775 776 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(); 777 int NumBytes = (int)MFI.getStackSize(); 778 Register FramePtr = RegInfo->getFrameRegister(MF); 779 780 // All calls are tail calls in GHC calling conv, and functions have no 781 // prologue/epilogue. 782 if (MF.getFunction().getCallingConv() == CallingConv::GHC) 783 return; 784 785 // First put ourselves on the first (from top) terminator instructions. 786 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); 787 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 788 789 if (!AFI->hasStackFrame()) { 790 if (NumBytes - ArgRegsSaveSize != 0) 791 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize, 792 MachineInstr::FrameDestroy); 793 } else { 794 // Unwind MBBI to point to first LDR / VLDRD. 795 if (MBBI != MBB.begin()) { 796 do { 797 --MBBI; 798 } while (MBBI != MBB.begin() && 799 MBBI->getFlag(MachineInstr::FrameDestroy)); 800 if (!MBBI->getFlag(MachineInstr::FrameDestroy)) 801 ++MBBI; 802 } 803 804 // Move SP to start of FP callee save spill area. 805 NumBytes -= (ArgRegsSaveSize + 806 AFI->getFPCXTSaveAreaSize() + 807 AFI->getGPRCalleeSavedArea1Size() + 808 AFI->getGPRCalleeSavedArea2Size() + 809 AFI->getDPRCalleeSavedGapSize() + 810 AFI->getDPRCalleeSavedAreaSize()); 811 812 // Reset SP based on frame pointer only if the stack frame extends beyond 813 // frame pointer stack slot or target is ELF and the function has FP. 814 if (AFI->shouldRestoreSPFromFP()) { 815 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 816 if (NumBytes) { 817 if (isARM) 818 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 819 ARMCC::AL, 0, TII, 820 MachineInstr::FrameDestroy); 821 else { 822 // It's not possible to restore SP from FP in a single instruction. 823 // For iOS, this looks like: 824 // mov sp, r7 825 // sub sp, #24 826 // This is bad, if an interrupt is taken after the mov, sp is in an 827 // inconsistent state. 828 // Use the first callee-saved register as a scratch register. 829 assert(!MFI.getPristineRegs(MF).test(ARM::R4) && 830 "No scratch register to restore SP from FP!"); 831 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, 832 ARMCC::AL, 0, TII, MachineInstr::FrameDestroy); 833 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) 834 .addReg(ARM::R4) 835 .add(predOps(ARMCC::AL)) 836 .setMIFlag(MachineInstr::FrameDestroy); 837 } 838 } else { 839 // Thumb2 or ARM. 840 if (isARM) 841 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 842 .addReg(FramePtr) 843 .add(predOps(ARMCC::AL)) 844 .add(condCodeOp()) 845 .setMIFlag(MachineInstr::FrameDestroy); 846 else 847 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) 848 .addReg(FramePtr) 849 .add(predOps(ARMCC::AL)) 850 .setMIFlag(MachineInstr::FrameDestroy); 851 } 852 } else if (NumBytes && 853 !tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes)) 854 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes, 855 MachineInstr::FrameDestroy); 856 857 // Increment past our save areas. 858 if (MBBI != MBB.end() && AFI->getDPRCalleeSavedAreaSize()) { 859 MBBI++; 860 // Since vpop register list cannot have gaps, there may be multiple vpop 861 // instructions in the epilogue. 862 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VLDMDIA_UPD) 863 MBBI++; 864 } 865 if (AFI->getDPRCalleeSavedGapSize()) { 866 assert(AFI->getDPRCalleeSavedGapSize() == 4 && 867 "unexpected DPR alignment gap"); 868 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize(), 869 MachineInstr::FrameDestroy); 870 } 871 872 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++; 873 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++; 874 if (AFI->getFPCXTSaveAreaSize()) MBBI++; 875 } 876 877 if (ArgRegsSaveSize) 878 emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize, 879 MachineInstr::FrameDestroy); 880 } 881 882 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for 883 /// debug info. It's the same as what we use for resolving the code-gen 884 /// references for now. FIXME: This can go wrong when references are 885 /// SP-relative and simple call frames aren't used. 886 StackOffset ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, 887 int FI, 888 Register &FrameReg) const { 889 return StackOffset::getFixed(ResolveFrameIndexReference(MF, FI, FrameReg, 0)); 890 } 891 892 int ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF, 893 int FI, Register &FrameReg, 894 int SPAdj) const { 895 const MachineFrameInfo &MFI = MF.getFrameInfo(); 896 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>( 897 MF.getSubtarget().getRegisterInfo()); 898 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 899 int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize(); 900 int FPOffset = Offset - AFI->getFramePtrSpillOffset(); 901 bool isFixed = MFI.isFixedObjectIndex(FI); 902 903 FrameReg = ARM::SP; 904 Offset += SPAdj; 905 906 // SP can move around if there are allocas. We may also lose track of SP 907 // when emergency spilling inside a non-reserved call frame setup. 908 bool hasMovingSP = !hasReservedCallFrame(MF); 909 910 // When dynamically realigning the stack, use the frame pointer for 911 // parameters, and the stack/base pointer for locals. 912 if (RegInfo->needsStackRealignment(MF)) { 913 assert(hasFP(MF) && "dynamic stack realignment without a FP!"); 914 if (isFixed) { 915 FrameReg = RegInfo->getFrameRegister(MF); 916 Offset = FPOffset; 917 } else if (hasMovingSP) { 918 assert(RegInfo->hasBasePointer(MF) && 919 "VLAs and dynamic stack alignment, but missing base pointer!"); 920 FrameReg = RegInfo->getBaseRegister(); 921 Offset -= SPAdj; 922 } 923 return Offset; 924 } 925 926 // If there is a frame pointer, use it when we can. 927 if (hasFP(MF) && AFI->hasStackFrame()) { 928 // Use frame pointer to reference fixed objects. Use it for locals if 929 // there are VLAs (and thus the SP isn't reliable as a base). 930 if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) { 931 FrameReg = RegInfo->getFrameRegister(MF); 932 return FPOffset; 933 } else if (hasMovingSP) { 934 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!"); 935 if (AFI->isThumb2Function()) { 936 // Try to use the frame pointer if we can, else use the base pointer 937 // since it's available. This is handy for the emergency spill slot, in 938 // particular. 939 if (FPOffset >= -255 && FPOffset < 0) { 940 FrameReg = RegInfo->getFrameRegister(MF); 941 return FPOffset; 942 } 943 } 944 } else if (AFI->isThumbFunction()) { 945 // Prefer SP to base pointer, if the offset is suitably aligned and in 946 // range as the effective range of the immediate offset is bigger when 947 // basing off SP. 948 // Use add <rd>, sp, #<imm8> 949 // ldr <rd>, [sp, #<imm8>] 950 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020) 951 return Offset; 952 // In Thumb2 mode, the negative offset is very limited. Try to avoid 953 // out of range references. ldr <rt>,[<rn>, #-<imm8>] 954 if (AFI->isThumb2Function() && FPOffset >= -255 && FPOffset < 0) { 955 FrameReg = RegInfo->getFrameRegister(MF); 956 return FPOffset; 957 } 958 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) { 959 // Otherwise, use SP or FP, whichever is closer to the stack slot. 960 FrameReg = RegInfo->getFrameRegister(MF); 961 return FPOffset; 962 } 963 } 964 // Use the base pointer if we have one. 965 // FIXME: Maybe prefer sp on Thumb1 if it's legal and the offset is cheaper? 966 // That can happen if we forced a base pointer for a large call frame. 967 if (RegInfo->hasBasePointer(MF)) { 968 FrameReg = RegInfo->getBaseRegister(); 969 Offset -= SPAdj; 970 } 971 return Offset; 972 } 973 974 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB, 975 MachineBasicBlock::iterator MI, 976 ArrayRef<CalleeSavedInfo> CSI, 977 unsigned StmOpc, unsigned StrOpc, 978 bool NoGap, bool (*Func)(unsigned, bool), 979 unsigned NumAlignedDPRCS2Regs, 980 unsigned MIFlags) const { 981 MachineFunction &MF = *MBB.getParent(); 982 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 983 const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); 984 985 DebugLoc DL; 986 987 using RegAndKill = std::pair<unsigned, bool>; 988 989 SmallVector<RegAndKill, 4> Regs; 990 unsigned i = CSI.size(); 991 while (i != 0) { 992 unsigned LastReg = 0; 993 for (; i != 0; --i) { 994 unsigned Reg = CSI[i-1].getReg(); 995 if (!(Func)(Reg, STI.splitFramePushPop(MF))) continue; 996 997 // D-registers in the aligned area DPRCS2 are NOT spilled here. 998 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) 999 continue; 1000 1001 const MachineRegisterInfo &MRI = MF.getRegInfo(); 1002 bool isLiveIn = MRI.isLiveIn(Reg); 1003 if (!isLiveIn && !MRI.isReserved(Reg)) 1004 MBB.addLiveIn(Reg); 1005 // If NoGap is true, push consecutive registers and then leave the rest 1006 // for other instructions. e.g. 1007 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11} 1008 if (NoGap && LastReg && LastReg != Reg-1) 1009 break; 1010 LastReg = Reg; 1011 // Do not set a kill flag on values that are also marked as live-in. This 1012 // happens with the @llvm-returnaddress intrinsic and with arguments 1013 // passed in callee saved registers. 1014 // Omitting the kill flags is conservatively correct even if the live-in 1015 // is not used after all. 1016 Regs.push_back(std::make_pair(Reg, /*isKill=*/!isLiveIn)); 1017 } 1018 1019 if (Regs.empty()) 1020 continue; 1021 1022 llvm::sort(Regs, [&](const RegAndKill &LHS, const RegAndKill &RHS) { 1023 return TRI.getEncodingValue(LHS.first) < TRI.getEncodingValue(RHS.first); 1024 }); 1025 1026 if (Regs.size() > 1 || StrOpc== 0) { 1027 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP) 1028 .addReg(ARM::SP) 1029 .setMIFlags(MIFlags) 1030 .add(predOps(ARMCC::AL)); 1031 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 1032 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); 1033 } else if (Regs.size() == 1) { 1034 BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP) 1035 .addReg(Regs[0].first, getKillRegState(Regs[0].second)) 1036 .addReg(ARM::SP) 1037 .setMIFlags(MIFlags) 1038 .addImm(-4) 1039 .add(predOps(ARMCC::AL)); 1040 } 1041 Regs.clear(); 1042 1043 // Put any subsequent vpush instructions before this one: they will refer to 1044 // higher register numbers so need to be pushed first in order to preserve 1045 // monotonicity. 1046 if (MI != MBB.begin()) 1047 --MI; 1048 } 1049 } 1050 1051 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB, 1052 MachineBasicBlock::iterator MI, 1053 MutableArrayRef<CalleeSavedInfo> CSI, 1054 unsigned LdmOpc, unsigned LdrOpc, 1055 bool isVarArg, bool NoGap, 1056 bool (*Func)(unsigned, bool), 1057 unsigned NumAlignedDPRCS2Regs) const { 1058 MachineFunction &MF = *MBB.getParent(); 1059 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 1060 const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); 1061 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1062 DebugLoc DL; 1063 bool isTailCall = false; 1064 bool isInterrupt = false; 1065 bool isTrap = false; 1066 bool isCmseEntry = false; 1067 if (MBB.end() != MI) { 1068 DL = MI->getDebugLoc(); 1069 unsigned RetOpcode = MI->getOpcode(); 1070 isTailCall = (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri); 1071 isInterrupt = 1072 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR; 1073 isTrap = 1074 RetOpcode == ARM::TRAP || RetOpcode == ARM::TRAPNaCl || 1075 RetOpcode == ARM::tTRAP; 1076 isCmseEntry = (RetOpcode == ARM::tBXNS || RetOpcode == ARM::tBXNS_RET); 1077 } 1078 1079 SmallVector<unsigned, 4> Regs; 1080 unsigned i = CSI.size(); 1081 while (i != 0) { 1082 unsigned LastReg = 0; 1083 bool DeleteRet = false; 1084 for (; i != 0; --i) { 1085 CalleeSavedInfo &Info = CSI[i-1]; 1086 unsigned Reg = Info.getReg(); 1087 if (!(Func)(Reg, STI.splitFramePushPop(MF))) continue; 1088 1089 // The aligned reloads from area DPRCS2 are not inserted here. 1090 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) 1091 continue; 1092 1093 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt && 1094 !isCmseEntry && !isTrap && STI.hasV5TOps()) { 1095 if (MBB.succ_empty()) { 1096 Reg = ARM::PC; 1097 // Fold the return instruction into the LDM. 1098 DeleteRet = true; 1099 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET; 1100 // We 'restore' LR into PC so it is not live out of the return block: 1101 // Clear Restored bit. 1102 Info.setRestored(false); 1103 } else 1104 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; 1105 } 1106 1107 // If NoGap is true, pop consecutive registers and then leave the rest 1108 // for other instructions. e.g. 1109 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11} 1110 if (NoGap && LastReg && LastReg != Reg-1) 1111 break; 1112 1113 LastReg = Reg; 1114 Regs.push_back(Reg); 1115 } 1116 1117 if (Regs.empty()) 1118 continue; 1119 1120 llvm::sort(Regs, [&](unsigned LHS, unsigned RHS) { 1121 return TRI.getEncodingValue(LHS) < TRI.getEncodingValue(RHS); 1122 }); 1123 1124 if (Regs.size() > 1 || LdrOpc == 0) { 1125 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP) 1126 .addReg(ARM::SP) 1127 .add(predOps(ARMCC::AL)) 1128 .setMIFlags(MachineInstr::FrameDestroy); 1129 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 1130 MIB.addReg(Regs[i], getDefRegState(true)); 1131 if (DeleteRet) { 1132 if (MI != MBB.end()) { 1133 MIB.copyImplicitOps(*MI); 1134 MI->eraseFromParent(); 1135 } 1136 } 1137 MI = MIB; 1138 } else if (Regs.size() == 1) { 1139 // If we adjusted the reg to PC from LR above, switch it back here. We 1140 // only do that for LDM. 1141 if (Regs[0] == ARM::PC) 1142 Regs[0] = ARM::LR; 1143 MachineInstrBuilder MIB = 1144 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0]) 1145 .addReg(ARM::SP, RegState::Define) 1146 .addReg(ARM::SP) 1147 .setMIFlags(MachineInstr::FrameDestroy); 1148 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once 1149 // that refactoring is complete (eventually). 1150 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) { 1151 MIB.addReg(0); 1152 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift)); 1153 } else 1154 MIB.addImm(4); 1155 MIB.add(predOps(ARMCC::AL)); 1156 } 1157 Regs.clear(); 1158 1159 // Put any subsequent vpop instructions after this one: they will refer to 1160 // higher register numbers so need to be popped afterwards. 1161 if (MI != MBB.end()) 1162 ++MI; 1163 } 1164 } 1165 1166 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers 1167 /// starting from d8. Also insert stack realignment code and leave the stack 1168 /// pointer pointing to the d8 spill slot. 1169 static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB, 1170 MachineBasicBlock::iterator MI, 1171 unsigned NumAlignedDPRCS2Regs, 1172 ArrayRef<CalleeSavedInfo> CSI, 1173 const TargetRegisterInfo *TRI) { 1174 MachineFunction &MF = *MBB.getParent(); 1175 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1176 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc(); 1177 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 1178 MachineFrameInfo &MFI = MF.getFrameInfo(); 1179 1180 // Mark the D-register spill slots as properly aligned. Since MFI computes 1181 // stack slot layout backwards, this can actually mean that the d-reg stack 1182 // slot offsets can be wrong. The offset for d8 will always be correct. 1183 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1184 unsigned DNum = CSI[i].getReg() - ARM::D8; 1185 if (DNum > NumAlignedDPRCS2Regs - 1) 1186 continue; 1187 int FI = CSI[i].getFrameIdx(); 1188 // The even-numbered registers will be 16-byte aligned, the odd-numbered 1189 // registers will be 8-byte aligned. 1190 MFI.setObjectAlignment(FI, DNum % 2 ? Align(8) : Align(16)); 1191 1192 // The stack slot for D8 needs to be maximally aligned because this is 1193 // actually the point where we align the stack pointer. MachineFrameInfo 1194 // computes all offsets relative to the incoming stack pointer which is a 1195 // bit weird when realigning the stack. Any extra padding for this 1196 // over-alignment is not realized because the code inserted below adjusts 1197 // the stack pointer by numregs * 8 before aligning the stack pointer. 1198 if (DNum == 0) 1199 MFI.setObjectAlignment(FI, MFI.getMaxAlign()); 1200 } 1201 1202 // Move the stack pointer to the d8 spill slot, and align it at the same 1203 // time. Leave the stack slot address in the scratch register r4. 1204 // 1205 // sub r4, sp, #numregs * 8 1206 // bic r4, r4, #align - 1 1207 // mov sp, r4 1208 // 1209 bool isThumb = AFI->isThumbFunction(); 1210 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1"); 1211 AFI->setShouldRestoreSPFromFP(true); 1212 1213 // sub r4, sp, #numregs * 8 1214 // The immediate is <= 64, so it doesn't need any special encoding. 1215 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri; 1216 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) 1217 .addReg(ARM::SP) 1218 .addImm(8 * NumAlignedDPRCS2Regs) 1219 .add(predOps(ARMCC::AL)) 1220 .add(condCodeOp()); 1221 1222 Align MaxAlign = MF.getFrameInfo().getMaxAlign(); 1223 // We must set parameter MustBeSingleInstruction to true, since 1224 // skipAlignedDPRCS2Spills expects exactly 3 instructions to perform 1225 // stack alignment. Luckily, this can always be done since all ARM 1226 // architecture versions that support Neon also support the BFC 1227 // instruction. 1228 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true); 1229 1230 // mov sp, r4 1231 // The stack pointer must be adjusted before spilling anything, otherwise 1232 // the stack slots could be clobbered by an interrupt handler. 1233 // Leave r4 live, it is used below. 1234 Opc = isThumb ? ARM::tMOVr : ARM::MOVr; 1235 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) 1236 .addReg(ARM::R4) 1237 .add(predOps(ARMCC::AL)); 1238 if (!isThumb) 1239 MIB.add(condCodeOp()); 1240 1241 // Now spill NumAlignedDPRCS2Regs registers starting from d8. 1242 // r4 holds the stack slot address. 1243 unsigned NextReg = ARM::D8; 1244 1245 // 16-byte aligned vst1.64 with 4 d-regs and address writeback. 1246 // The writeback is only needed when emitting two vst1.64 instructions. 1247 if (NumAlignedDPRCS2Regs >= 6) { 1248 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1249 &ARM::QQPRRegClass); 1250 MBB.addLiveIn(SupReg); 1251 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4) 1252 .addReg(ARM::R4, RegState::Kill) 1253 .addImm(16) 1254 .addReg(NextReg) 1255 .addReg(SupReg, RegState::ImplicitKill) 1256 .add(predOps(ARMCC::AL)); 1257 NextReg += 4; 1258 NumAlignedDPRCS2Regs -= 4; 1259 } 1260 1261 // We won't modify r4 beyond this point. It currently points to the next 1262 // register to be spilled. 1263 unsigned R4BaseReg = NextReg; 1264 1265 // 16-byte aligned vst1.64 with 4 d-regs, no writeback. 1266 if (NumAlignedDPRCS2Regs >= 4) { 1267 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1268 &ARM::QQPRRegClass); 1269 MBB.addLiveIn(SupReg); 1270 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q)) 1271 .addReg(ARM::R4) 1272 .addImm(16) 1273 .addReg(NextReg) 1274 .addReg(SupReg, RegState::ImplicitKill) 1275 .add(predOps(ARMCC::AL)); 1276 NextReg += 4; 1277 NumAlignedDPRCS2Regs -= 4; 1278 } 1279 1280 // 16-byte aligned vst1.64 with 2 d-regs. 1281 if (NumAlignedDPRCS2Regs >= 2) { 1282 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1283 &ARM::QPRRegClass); 1284 MBB.addLiveIn(SupReg); 1285 BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64)) 1286 .addReg(ARM::R4) 1287 .addImm(16) 1288 .addReg(SupReg) 1289 .add(predOps(ARMCC::AL)); 1290 NextReg += 2; 1291 NumAlignedDPRCS2Regs -= 2; 1292 } 1293 1294 // Finally, use a vanilla vstr.64 for the odd last register. 1295 if (NumAlignedDPRCS2Regs) { 1296 MBB.addLiveIn(NextReg); 1297 // vstr.64 uses addrmode5 which has an offset scale of 4. 1298 BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD)) 1299 .addReg(NextReg) 1300 .addReg(ARM::R4) 1301 .addImm((NextReg - R4BaseReg) * 2) 1302 .add(predOps(ARMCC::AL)); 1303 } 1304 1305 // The last spill instruction inserted should kill the scratch register r4. 1306 std::prev(MI)->addRegisterKilled(ARM::R4, TRI); 1307 } 1308 1309 /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an 1310 /// iterator to the following instruction. 1311 static MachineBasicBlock::iterator 1312 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI, 1313 unsigned NumAlignedDPRCS2Regs) { 1314 // sub r4, sp, #numregs * 8 1315 // bic r4, r4, #align - 1 1316 // mov sp, r4 1317 ++MI; ++MI; ++MI; 1318 assert(MI->mayStore() && "Expecting spill instruction"); 1319 1320 // These switches all fall through. 1321 switch(NumAlignedDPRCS2Regs) { 1322 case 7: 1323 ++MI; 1324 assert(MI->mayStore() && "Expecting spill instruction"); 1325 LLVM_FALLTHROUGH; 1326 default: 1327 ++MI; 1328 assert(MI->mayStore() && "Expecting spill instruction"); 1329 LLVM_FALLTHROUGH; 1330 case 1: 1331 case 2: 1332 case 4: 1333 assert(MI->killsRegister(ARM::R4) && "Missed kill flag"); 1334 ++MI; 1335 } 1336 return MI; 1337 } 1338 1339 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers 1340 /// starting from d8. These instructions are assumed to execute while the 1341 /// stack is still aligned, unlike the code inserted by emitPopInst. 1342 static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB, 1343 MachineBasicBlock::iterator MI, 1344 unsigned NumAlignedDPRCS2Regs, 1345 ArrayRef<CalleeSavedInfo> CSI, 1346 const TargetRegisterInfo *TRI) { 1347 MachineFunction &MF = *MBB.getParent(); 1348 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1349 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc(); 1350 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 1351 1352 // Find the frame index assigned to d8. 1353 int D8SpillFI = 0; 1354 for (unsigned i = 0, e = CSI.size(); i != e; ++i) 1355 if (CSI[i].getReg() == ARM::D8) { 1356 D8SpillFI = CSI[i].getFrameIdx(); 1357 break; 1358 } 1359 1360 // Materialize the address of the d8 spill slot into the scratch register r4. 1361 // This can be fairly complicated if the stack frame is large, so just use 1362 // the normal frame index elimination mechanism to do it. This code runs as 1363 // the initial part of the epilog where the stack and base pointers haven't 1364 // been changed yet. 1365 bool isThumb = AFI->isThumbFunction(); 1366 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1"); 1367 1368 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; 1369 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) 1370 .addFrameIndex(D8SpillFI) 1371 .addImm(0) 1372 .add(predOps(ARMCC::AL)) 1373 .add(condCodeOp()); 1374 1375 // Now restore NumAlignedDPRCS2Regs registers starting from d8. 1376 unsigned NextReg = ARM::D8; 1377 1378 // 16-byte aligned vld1.64 with 4 d-regs and writeback. 1379 if (NumAlignedDPRCS2Regs >= 6) { 1380 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1381 &ARM::QQPRRegClass); 1382 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg) 1383 .addReg(ARM::R4, RegState::Define) 1384 .addReg(ARM::R4, RegState::Kill) 1385 .addImm(16) 1386 .addReg(SupReg, RegState::ImplicitDefine) 1387 .add(predOps(ARMCC::AL)); 1388 NextReg += 4; 1389 NumAlignedDPRCS2Regs -= 4; 1390 } 1391 1392 // We won't modify r4 beyond this point. It currently points to the next 1393 // register to be spilled. 1394 unsigned R4BaseReg = NextReg; 1395 1396 // 16-byte aligned vld1.64 with 4 d-regs, no writeback. 1397 if (NumAlignedDPRCS2Regs >= 4) { 1398 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1399 &ARM::QQPRRegClass); 1400 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg) 1401 .addReg(ARM::R4) 1402 .addImm(16) 1403 .addReg(SupReg, RegState::ImplicitDefine) 1404 .add(predOps(ARMCC::AL)); 1405 NextReg += 4; 1406 NumAlignedDPRCS2Regs -= 4; 1407 } 1408 1409 // 16-byte aligned vld1.64 with 2 d-regs. 1410 if (NumAlignedDPRCS2Regs >= 2) { 1411 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 1412 &ARM::QPRRegClass); 1413 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg) 1414 .addReg(ARM::R4) 1415 .addImm(16) 1416 .add(predOps(ARMCC::AL)); 1417 NextReg += 2; 1418 NumAlignedDPRCS2Regs -= 2; 1419 } 1420 1421 // Finally, use a vanilla vldr.64 for the remaining odd register. 1422 if (NumAlignedDPRCS2Regs) 1423 BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg) 1424 .addReg(ARM::R4) 1425 .addImm(2 * (NextReg - R4BaseReg)) 1426 .add(predOps(ARMCC::AL)); 1427 1428 // Last store kills r4. 1429 std::prev(MI)->addRegisterKilled(ARM::R4, TRI); 1430 } 1431 1432 bool ARMFrameLowering::spillCalleeSavedRegisters( 1433 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1434 ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const { 1435 if (CSI.empty()) 1436 return false; 1437 1438 MachineFunction &MF = *MBB.getParent(); 1439 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1440 1441 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD; 1442 unsigned PushOneOpc = AFI->isThumbFunction() ? 1443 ARM::t2STR_PRE : ARM::STR_PRE_IMM; 1444 unsigned FltOpc = ARM::VSTMDDB_UPD; 1445 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs(); 1446 // Save the non-secure floating point context. 1447 if (llvm::any_of(CSI, [](const CalleeSavedInfo &C) { 1448 return C.getReg() == ARM::FPCXTNS; 1449 })) { 1450 BuildMI(MBB, MI, DebugLoc(), STI.getInstrInfo()->get(ARM::VSTR_FPCXTNS_pre), 1451 ARM::SP) 1452 .addReg(ARM::SP) 1453 .addImm(-4) 1454 .add(predOps(ARMCC::AL)); 1455 } 1456 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0, 1457 MachineInstr::FrameSetup); 1458 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0, 1459 MachineInstr::FrameSetup); 1460 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register, 1461 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup); 1462 1463 // The code above does not insert spill code for the aligned DPRCS2 registers. 1464 // The stack realignment code will be inserted between the push instructions 1465 // and these spills. 1466 if (NumAlignedDPRCS2Regs) 1467 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI); 1468 1469 return true; 1470 } 1471 1472 bool ARMFrameLowering::restoreCalleeSavedRegisters( 1473 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1474 MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const { 1475 if (CSI.empty()) 1476 return false; 1477 1478 MachineFunction &MF = *MBB.getParent(); 1479 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1480 bool isVarArg = AFI->getArgRegsSaveSize() > 0; 1481 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs(); 1482 1483 // The emitPopInst calls below do not insert reloads for the aligned DPRCS2 1484 // registers. Do that here instead. 1485 if (NumAlignedDPRCS2Regs) 1486 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI); 1487 1488 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; 1489 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM; 1490 unsigned FltOpc = ARM::VLDMDIA_UPD; 1491 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register, 1492 NumAlignedDPRCS2Regs); 1493 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, 1494 &isARMArea2Register, 0); 1495 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, 1496 &isARMArea1Register, 0); 1497 1498 return true; 1499 } 1500 1501 // FIXME: Make generic? 1502 static unsigned EstimateFunctionSizeInBytes(const MachineFunction &MF, 1503 const ARMBaseInstrInfo &TII) { 1504 unsigned FnSize = 0; 1505 for (auto &MBB : MF) { 1506 for (auto &MI : MBB) 1507 FnSize += TII.getInstSizeInBytes(MI); 1508 } 1509 if (MF.getJumpTableInfo()) 1510 for (auto &Table: MF.getJumpTableInfo()->getJumpTables()) 1511 FnSize += Table.MBBs.size() * 4; 1512 FnSize += MF.getConstantPool()->getConstants().size() * 4; 1513 return FnSize; 1514 } 1515 1516 /// estimateRSStackSizeLimit - Look at each instruction that references stack 1517 /// frames and return the stack size limit beyond which some of these 1518 /// instructions will require a scratch register during their expansion later. 1519 // FIXME: Move to TII? 1520 static unsigned estimateRSStackSizeLimit(MachineFunction &MF, 1521 const TargetFrameLowering *TFI, 1522 bool &HasNonSPFrameIndex) { 1523 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1524 const ARMBaseInstrInfo &TII = 1525 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 1526 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); 1527 unsigned Limit = (1 << 12) - 1; 1528 for (auto &MBB : MF) { 1529 for (auto &MI : MBB) { 1530 if (MI.isDebugInstr()) 1531 continue; 1532 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1533 if (!MI.getOperand(i).isFI()) 1534 continue; 1535 1536 // When using ADDri to get the address of a stack object, 255 is the 1537 // largest offset guaranteed to fit in the immediate offset. 1538 if (MI.getOpcode() == ARM::ADDri) { 1539 Limit = std::min(Limit, (1U << 8) - 1); 1540 break; 1541 } 1542 // t2ADDri will not require an extra register, it can reuse the 1543 // destination. 1544 if (MI.getOpcode() == ARM::t2ADDri || MI.getOpcode() == ARM::t2ADDri12) 1545 break; 1546 1547 const MCInstrDesc &MCID = MI.getDesc(); 1548 const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF); 1549 if (RegClass && !RegClass->contains(ARM::SP)) 1550 HasNonSPFrameIndex = true; 1551 1552 // Otherwise check the addressing mode. 1553 switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) { 1554 case ARMII::AddrMode_i12: 1555 case ARMII::AddrMode2: 1556 // Default 12 bit limit. 1557 break; 1558 case ARMII::AddrMode3: 1559 case ARMII::AddrModeT2_i8: 1560 Limit = std::min(Limit, (1U << 8) - 1); 1561 break; 1562 case ARMII::AddrMode5FP16: 1563 Limit = std::min(Limit, ((1U << 8) - 1) * 2); 1564 break; 1565 case ARMII::AddrMode5: 1566 case ARMII::AddrModeT2_i8s4: 1567 case ARMII::AddrModeT2_ldrex: 1568 Limit = std::min(Limit, ((1U << 8) - 1) * 4); 1569 break; 1570 case ARMII::AddrModeT2_i12: 1571 // i12 supports only positive offset so these will be converted to 1572 // i8 opcodes. See llvm::rewriteT2FrameIndex. 1573 if (TFI->hasFP(MF) && AFI->hasStackFrame()) 1574 Limit = std::min(Limit, (1U << 8) - 1); 1575 break; 1576 case ARMII::AddrMode4: 1577 case ARMII::AddrMode6: 1578 // Addressing modes 4 & 6 (load/store) instructions can't encode an 1579 // immediate offset for stack references. 1580 return 0; 1581 case ARMII::AddrModeT2_i7: 1582 Limit = std::min(Limit, ((1U << 7) - 1) * 1); 1583 break; 1584 case ARMII::AddrModeT2_i7s2: 1585 Limit = std::min(Limit, ((1U << 7) - 1) * 2); 1586 break; 1587 case ARMII::AddrModeT2_i7s4: 1588 Limit = std::min(Limit, ((1U << 7) - 1) * 4); 1589 break; 1590 default: 1591 llvm_unreachable("Unhandled addressing mode in stack size limit calculation"); 1592 } 1593 break; // At most one FI per instruction 1594 } 1595 } 1596 } 1597 1598 return Limit; 1599 } 1600 1601 // In functions that realign the stack, it can be an advantage to spill the 1602 // callee-saved vector registers after realigning the stack. The vst1 and vld1 1603 // instructions take alignment hints that can improve performance. 1604 static void 1605 checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) { 1606 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0); 1607 if (!SpillAlignedNEONRegs) 1608 return; 1609 1610 // Naked functions don't spill callee-saved registers. 1611 if (MF.getFunction().hasFnAttribute(Attribute::Naked)) 1612 return; 1613 1614 // We are planning to use NEON instructions vst1 / vld1. 1615 if (!static_cast<const ARMSubtarget &>(MF.getSubtarget()).hasNEON()) 1616 return; 1617 1618 // Don't bother if the default stack alignment is sufficiently high. 1619 if (MF.getSubtarget().getFrameLowering()->getStackAlign() >= Align(8)) 1620 return; 1621 1622 // Aligned spills require stack realignment. 1623 if (!static_cast<const ARMBaseRegisterInfo *>( 1624 MF.getSubtarget().getRegisterInfo())->canRealignStack(MF)) 1625 return; 1626 1627 // We always spill contiguous d-registers starting from d8. Count how many 1628 // needs spilling. The register allocator will almost always use the 1629 // callee-saved registers in order, but it can happen that there are holes in 1630 // the range. Registers above the hole will be spilled to the standard DPRCS 1631 // area. 1632 unsigned NumSpills = 0; 1633 for (; NumSpills < 8; ++NumSpills) 1634 if (!SavedRegs.test(ARM::D8 + NumSpills)) 1635 break; 1636 1637 // Don't do this for just one d-register. It's not worth it. 1638 if (NumSpills < 2) 1639 return; 1640 1641 // Spill the first NumSpills D-registers after realigning the stack. 1642 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills); 1643 1644 // A scratch register is required for the vst1 / vld1 instructions. 1645 SavedRegs.set(ARM::R4); 1646 } 1647 1648 bool ARMFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const { 1649 // For CMSE entry functions, we want to save the FPCXT_NS immediately 1650 // upon function entry (resp. restore it immmediately before return) 1651 if (STI.hasV8_1MMainlineOps() && 1652 MF.getInfo<ARMFunctionInfo>()->isCmseNSEntryFunction()) 1653 return false; 1654 1655 return true; 1656 } 1657 1658 void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, 1659 BitVector &SavedRegs, 1660 RegScavenger *RS) const { 1661 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); 1662 // This tells PEI to spill the FP as if it is any other callee-save register 1663 // to take advantage the eliminateFrameIndex machinery. This also ensures it 1664 // is spilled in the order specified by getCalleeSavedRegs() to make it easier 1665 // to combine multiple loads / stores. 1666 bool CanEliminateFrame = true; 1667 bool CS1Spilled = false; 1668 bool LRSpilled = false; 1669 unsigned NumGPRSpills = 0; 1670 unsigned NumFPRSpills = 0; 1671 SmallVector<unsigned, 4> UnspilledCS1GPRs; 1672 SmallVector<unsigned, 4> UnspilledCS2GPRs; 1673 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>( 1674 MF.getSubtarget().getRegisterInfo()); 1675 const ARMBaseInstrInfo &TII = 1676 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 1677 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1678 MachineFrameInfo &MFI = MF.getFrameInfo(); 1679 MachineRegisterInfo &MRI = MF.getRegInfo(); 1680 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); 1681 (void)TRI; // Silence unused warning in non-assert builds. 1682 Register FramePtr = RegInfo->getFrameRegister(MF); 1683 1684 // Spill R4 if Thumb2 function requires stack realignment - it will be used as 1685 // scratch register. Also spill R4 if Thumb2 function has varsized objects, 1686 // since it's not always possible to restore sp from fp in a single 1687 // instruction. 1688 // FIXME: It will be better just to find spare register here. 1689 if (AFI->isThumb2Function() && 1690 (MFI.hasVarSizedObjects() || RegInfo->needsStackRealignment(MF))) 1691 SavedRegs.set(ARM::R4); 1692 1693 // If a stack probe will be emitted, spill R4 and LR, since they are 1694 // clobbered by the stack probe call. 1695 // This estimate should be a safe, conservative estimate. The actual 1696 // stack probe is enabled based on the size of the local objects; 1697 // this estimate also includes the varargs store size. 1698 if (STI.isTargetWindows() && 1699 WindowsRequiresStackProbe(MF, MFI.estimateStackSize(MF))) { 1700 SavedRegs.set(ARM::R4); 1701 SavedRegs.set(ARM::LR); 1702 } 1703 1704 if (AFI->isThumb1OnlyFunction()) { 1705 // Spill LR if Thumb1 function uses variable length argument lists. 1706 if (AFI->getArgRegsSaveSize() > 0) 1707 SavedRegs.set(ARM::LR); 1708 1709 // Spill R4 if Thumb1 epilogue has to restore SP from FP or the function 1710 // requires stack alignment. We don't know for sure what the stack size 1711 // will be, but for this, an estimate is good enough. If there anything 1712 // changes it, it'll be a spill, which implies we've used all the registers 1713 // and so R4 is already used, so not marking it here will be OK. 1714 // FIXME: It will be better just to find spare register here. 1715 if (MFI.hasVarSizedObjects() || RegInfo->needsStackRealignment(MF) || 1716 MFI.estimateStackSize(MF) > 508) 1717 SavedRegs.set(ARM::R4); 1718 } 1719 1720 // See if we can spill vector registers to aligned stack. 1721 checkNumAlignedDPRCS2Regs(MF, SavedRegs); 1722 1723 // Spill the BasePtr if it's used. 1724 if (RegInfo->hasBasePointer(MF)) 1725 SavedRegs.set(RegInfo->getBaseRegister()); 1726 1727 // On v8.1-M.Main CMSE entry functions save/restore FPCXT. 1728 if (STI.hasV8_1MMainlineOps() && AFI->isCmseNSEntryFunction()) 1729 CanEliminateFrame = false; 1730 1731 // Don't spill FP if the frame can be eliminated. This is determined 1732 // by scanning the callee-save registers to see if any is modified. 1733 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF); 1734 for (unsigned i = 0; CSRegs[i]; ++i) { 1735 unsigned Reg = CSRegs[i]; 1736 bool Spilled = false; 1737 if (SavedRegs.test(Reg)) { 1738 Spilled = true; 1739 CanEliminateFrame = false; 1740 } 1741 1742 if (!ARM::GPRRegClass.contains(Reg)) { 1743 if (Spilled) { 1744 if (ARM::SPRRegClass.contains(Reg)) 1745 NumFPRSpills++; 1746 else if (ARM::DPRRegClass.contains(Reg)) 1747 NumFPRSpills += 2; 1748 else if (ARM::QPRRegClass.contains(Reg)) 1749 NumFPRSpills += 4; 1750 } 1751 continue; 1752 } 1753 1754 if (Spilled) { 1755 NumGPRSpills++; 1756 1757 if (!STI.splitFramePushPop(MF)) { 1758 if (Reg == ARM::LR) 1759 LRSpilled = true; 1760 CS1Spilled = true; 1761 continue; 1762 } 1763 1764 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 1765 switch (Reg) { 1766 case ARM::LR: 1767 LRSpilled = true; 1768 LLVM_FALLTHROUGH; 1769 case ARM::R0: case ARM::R1: 1770 case ARM::R2: case ARM::R3: 1771 case ARM::R4: case ARM::R5: 1772 case ARM::R6: case ARM::R7: 1773 CS1Spilled = true; 1774 break; 1775 default: 1776 break; 1777 } 1778 } else { 1779 if (!STI.splitFramePushPop(MF)) { 1780 UnspilledCS1GPRs.push_back(Reg); 1781 continue; 1782 } 1783 1784 switch (Reg) { 1785 case ARM::R0: case ARM::R1: 1786 case ARM::R2: case ARM::R3: 1787 case ARM::R4: case ARM::R5: 1788 case ARM::R6: case ARM::R7: 1789 case ARM::LR: 1790 UnspilledCS1GPRs.push_back(Reg); 1791 break; 1792 default: 1793 UnspilledCS2GPRs.push_back(Reg); 1794 break; 1795 } 1796 } 1797 } 1798 1799 bool ForceLRSpill = false; 1800 if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 1801 unsigned FnSize = EstimateFunctionSizeInBytes(MF, TII); 1802 // Force LR to be spilled if the Thumb function size is > 2048. This enables 1803 // use of BL to implement far jump. 1804 if (FnSize >= (1 << 11)) { 1805 CanEliminateFrame = false; 1806 ForceLRSpill = true; 1807 } 1808 } 1809 1810 // If any of the stack slot references may be out of range of an immediate 1811 // offset, make sure a register (or a spill slot) is available for the 1812 // register scavenger. Note that if we're indexing off the frame pointer, the 1813 // effective stack size is 4 bytes larger since the FP points to the stack 1814 // slot of the previous FP. Also, if we have variable sized objects in the 1815 // function, stack slot references will often be negative, and some of 1816 // our instructions are positive-offset only, so conservatively consider 1817 // that case to want a spill slot (or register) as well. Similarly, if 1818 // the function adjusts the stack pointer during execution and the 1819 // adjustments aren't already part of our stack size estimate, our offset 1820 // calculations may be off, so be conservative. 1821 // FIXME: We could add logic to be more precise about negative offsets 1822 // and which instructions will need a scratch register for them. Is it 1823 // worth the effort and added fragility? 1824 unsigned EstimatedStackSize = 1825 MFI.estimateStackSize(MF) + 4 * (NumGPRSpills + NumFPRSpills); 1826 1827 // Determine biggest (positive) SP offset in MachineFrameInfo. 1828 int MaxFixedOffset = 0; 1829 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) { 1830 int MaxObjectOffset = MFI.getObjectOffset(I) + MFI.getObjectSize(I); 1831 MaxFixedOffset = std::max(MaxFixedOffset, MaxObjectOffset); 1832 } 1833 1834 bool HasFP = hasFP(MF); 1835 if (HasFP) { 1836 if (AFI->hasStackFrame()) 1837 EstimatedStackSize += 4; 1838 } else { 1839 // If FP is not used, SP will be used to access arguments, so count the 1840 // size of arguments into the estimation. 1841 EstimatedStackSize += MaxFixedOffset; 1842 } 1843 EstimatedStackSize += 16; // For possible paddings. 1844 1845 unsigned EstimatedRSStackSizeLimit, EstimatedRSFixedSizeLimit; 1846 bool HasNonSPFrameIndex = false; 1847 if (AFI->isThumb1OnlyFunction()) { 1848 // For Thumb1, don't bother to iterate over the function. The only 1849 // instruction that requires an emergency spill slot is a store to a 1850 // frame index. 1851 // 1852 // tSTRspi, which is used for sp-relative accesses, has an 8-bit unsigned 1853 // immediate. tSTRi, which is used for bp- and fp-relative accesses, has 1854 // a 5-bit unsigned immediate. 1855 // 1856 // We could try to check if the function actually contains a tSTRspi 1857 // that might need the spill slot, but it's not really important. 1858 // Functions with VLAs or extremely large call frames are rare, and 1859 // if a function is allocating more than 1KB of stack, an extra 4-byte 1860 // slot probably isn't relevant. 1861 if (RegInfo->hasBasePointer(MF)) 1862 EstimatedRSStackSizeLimit = (1U << 5) * 4; 1863 else 1864 EstimatedRSStackSizeLimit = (1U << 8) * 4; 1865 EstimatedRSFixedSizeLimit = (1U << 5) * 4; 1866 } else { 1867 EstimatedRSStackSizeLimit = 1868 estimateRSStackSizeLimit(MF, this, HasNonSPFrameIndex); 1869 EstimatedRSFixedSizeLimit = EstimatedRSStackSizeLimit; 1870 } 1871 // Final estimate of whether sp or bp-relative accesses might require 1872 // scavenging. 1873 bool HasLargeStack = EstimatedStackSize > EstimatedRSStackSizeLimit; 1874 1875 // If the stack pointer moves and we don't have a base pointer, the 1876 // estimate logic doesn't work. The actual offsets might be larger when 1877 // we're constructing a call frame, or we might need to use negative 1878 // offsets from fp. 1879 bool HasMovingSP = MFI.hasVarSizedObjects() || 1880 (MFI.adjustsStack() && !canSimplifyCallFramePseudos(MF)); 1881 bool HasBPOrFixedSP = RegInfo->hasBasePointer(MF) || !HasMovingSP; 1882 1883 // If we have a frame pointer, we assume arguments will be accessed 1884 // relative to the frame pointer. Check whether fp-relative accesses to 1885 // arguments require scavenging. 1886 // 1887 // We could do slightly better on Thumb1; in some cases, an sp-relative 1888 // offset would be legal even though an fp-relative offset is not. 1889 int MaxFPOffset = getMaxFPOffset(STI, *AFI); 1890 bool HasLargeArgumentList = 1891 HasFP && (MaxFixedOffset - MaxFPOffset) > (int)EstimatedRSFixedSizeLimit; 1892 1893 bool BigFrameOffsets = HasLargeStack || !HasBPOrFixedSP || 1894 HasLargeArgumentList || HasNonSPFrameIndex; 1895 LLVM_DEBUG(dbgs() << "EstimatedLimit: " << EstimatedRSStackSizeLimit 1896 << "; EstimatedStack: " << EstimatedStackSize 1897 << "; EstimatedFPStack: " << MaxFixedOffset - MaxFPOffset 1898 << "; BigFrameOffsets: " << BigFrameOffsets << "\n"); 1899 if (BigFrameOffsets || 1900 !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) { 1901 AFI->setHasStackFrame(true); 1902 1903 if (HasFP) { 1904 SavedRegs.set(FramePtr); 1905 // If the frame pointer is required by the ABI, also spill LR so that we 1906 // emit a complete frame record. 1907 if (MF.getTarget().Options.DisableFramePointerElim(MF) && !LRSpilled) { 1908 SavedRegs.set(ARM::LR); 1909 LRSpilled = true; 1910 NumGPRSpills++; 1911 auto LRPos = llvm::find(UnspilledCS1GPRs, ARM::LR); 1912 if (LRPos != UnspilledCS1GPRs.end()) 1913 UnspilledCS1GPRs.erase(LRPos); 1914 } 1915 auto FPPos = llvm::find(UnspilledCS1GPRs, FramePtr); 1916 if (FPPos != UnspilledCS1GPRs.end()) 1917 UnspilledCS1GPRs.erase(FPPos); 1918 NumGPRSpills++; 1919 if (FramePtr == ARM::R7) 1920 CS1Spilled = true; 1921 } 1922 1923 // This is true when we inserted a spill for a callee-save GPR which is 1924 // not otherwise used by the function. This guaranteees it is possible 1925 // to scavenge a register to hold the address of a stack slot. On Thumb1, 1926 // the register must be a valid operand to tSTRi, i.e. r4-r7. For other 1927 // subtargets, this is any GPR, i.e. r4-r11 or lr. 1928 // 1929 // If we don't insert a spill, we instead allocate an emergency spill 1930 // slot, which can be used by scavenging to spill an arbitrary register. 1931 // 1932 // We currently don't try to figure out whether any specific instruction 1933 // requires scavening an additional register. 1934 bool ExtraCSSpill = false; 1935 1936 if (AFI->isThumb1OnlyFunction()) { 1937 // For Thumb1-only targets, we need some low registers when we save and 1938 // restore the high registers (which aren't allocatable, but could be 1939 // used by inline assembly) because the push/pop instructions can not 1940 // access high registers. If necessary, we might need to push more low 1941 // registers to ensure that there is at least one free that can be used 1942 // for the saving & restoring, and preferably we should ensure that as 1943 // many as are needed are available so that fewer push/pop instructions 1944 // are required. 1945 1946 // Low registers which are not currently pushed, but could be (r4-r7). 1947 SmallVector<unsigned, 4> AvailableRegs; 1948 1949 // Unused argument registers (r0-r3) can be clobbered in the prologue for 1950 // free. 1951 int EntryRegDeficit = 0; 1952 for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) { 1953 if (!MF.getRegInfo().isLiveIn(Reg)) { 1954 --EntryRegDeficit; 1955 LLVM_DEBUG(dbgs() 1956 << printReg(Reg, TRI) 1957 << " is unused argument register, EntryRegDeficit = " 1958 << EntryRegDeficit << "\n"); 1959 } 1960 } 1961 1962 // Unused return registers can be clobbered in the epilogue for free. 1963 int ExitRegDeficit = AFI->getReturnRegsCount() - 4; 1964 LLVM_DEBUG(dbgs() << AFI->getReturnRegsCount() 1965 << " return regs used, ExitRegDeficit = " 1966 << ExitRegDeficit << "\n"); 1967 1968 int RegDeficit = std::max(EntryRegDeficit, ExitRegDeficit); 1969 LLVM_DEBUG(dbgs() << "RegDeficit = " << RegDeficit << "\n"); 1970 1971 // r4-r6 can be used in the prologue if they are pushed by the first push 1972 // instruction. 1973 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) { 1974 if (SavedRegs.test(Reg)) { 1975 --RegDeficit; 1976 LLVM_DEBUG(dbgs() << printReg(Reg, TRI) 1977 << " is saved low register, RegDeficit = " 1978 << RegDeficit << "\n"); 1979 } else { 1980 AvailableRegs.push_back(Reg); 1981 LLVM_DEBUG( 1982 dbgs() 1983 << printReg(Reg, TRI) 1984 << " is non-saved low register, adding to AvailableRegs\n"); 1985 } 1986 } 1987 1988 // r7 can be used if it is not being used as the frame pointer. 1989 if (!HasFP) { 1990 if (SavedRegs.test(ARM::R7)) { 1991 --RegDeficit; 1992 LLVM_DEBUG(dbgs() << "%r7 is saved low register, RegDeficit = " 1993 << RegDeficit << "\n"); 1994 } else { 1995 AvailableRegs.push_back(ARM::R7); 1996 LLVM_DEBUG( 1997 dbgs() 1998 << "%r7 is non-saved low register, adding to AvailableRegs\n"); 1999 } 2000 } 2001 2002 // Each of r8-r11 needs to be copied to a low register, then pushed. 2003 for (unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) { 2004 if (SavedRegs.test(Reg)) { 2005 ++RegDeficit; 2006 LLVM_DEBUG(dbgs() << printReg(Reg, TRI) 2007 << " is saved high register, RegDeficit = " 2008 << RegDeficit << "\n"); 2009 } 2010 } 2011 2012 // LR can only be used by PUSH, not POP, and can't be used at all if the 2013 // llvm.returnaddress intrinsic is used. This is only worth doing if we 2014 // are more limited at function entry than exit. 2015 if ((EntryRegDeficit > ExitRegDeficit) && 2016 !(MF.getRegInfo().isLiveIn(ARM::LR) && 2017 MF.getFrameInfo().isReturnAddressTaken())) { 2018 if (SavedRegs.test(ARM::LR)) { 2019 --RegDeficit; 2020 LLVM_DEBUG(dbgs() << "%lr is saved register, RegDeficit = " 2021 << RegDeficit << "\n"); 2022 } else { 2023 AvailableRegs.push_back(ARM::LR); 2024 LLVM_DEBUG(dbgs() << "%lr is not saved, adding to AvailableRegs\n"); 2025 } 2026 } 2027 2028 // If there are more high registers that need pushing than low registers 2029 // available, push some more low registers so that we can use fewer push 2030 // instructions. This might not reduce RegDeficit all the way to zero, 2031 // because we can only guarantee that r4-r6 are available, but r8-r11 may 2032 // need saving. 2033 LLVM_DEBUG(dbgs() << "Final RegDeficit = " << RegDeficit << "\n"); 2034 for (; RegDeficit > 0 && !AvailableRegs.empty(); --RegDeficit) { 2035 unsigned Reg = AvailableRegs.pop_back_val(); 2036 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI) 2037 << " to make up reg deficit\n"); 2038 SavedRegs.set(Reg); 2039 NumGPRSpills++; 2040 CS1Spilled = true; 2041 assert(!MRI.isReserved(Reg) && "Should not be reserved"); 2042 if (Reg != ARM::LR && !MRI.isPhysRegUsed(Reg)) 2043 ExtraCSSpill = true; 2044 UnspilledCS1GPRs.erase(llvm::find(UnspilledCS1GPRs, Reg)); 2045 if (Reg == ARM::LR) 2046 LRSpilled = true; 2047 } 2048 LLVM_DEBUG(dbgs() << "After adding spills, RegDeficit = " << RegDeficit 2049 << "\n"); 2050 } 2051 2052 // Avoid spilling LR in Thumb1 if there's a tail call: it's expensive to 2053 // restore LR in that case. 2054 bool ExpensiveLRRestore = AFI->isThumb1OnlyFunction() && MFI.hasTailCall(); 2055 2056 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 2057 // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 2058 if (!LRSpilled && CS1Spilled && !ExpensiveLRRestore) { 2059 SavedRegs.set(ARM::LR); 2060 NumGPRSpills++; 2061 SmallVectorImpl<unsigned>::iterator LRPos; 2062 LRPos = llvm::find(UnspilledCS1GPRs, (unsigned)ARM::LR); 2063 if (LRPos != UnspilledCS1GPRs.end()) 2064 UnspilledCS1GPRs.erase(LRPos); 2065 2066 ForceLRSpill = false; 2067 if (!MRI.isReserved(ARM::LR) && !MRI.isPhysRegUsed(ARM::LR) && 2068 !AFI->isThumb1OnlyFunction()) 2069 ExtraCSSpill = true; 2070 } 2071 2072 // If stack and double are 8-byte aligned and we are spilling an odd number 2073 // of GPRs, spill one extra callee save GPR so we won't have to pad between 2074 // the integer and double callee save areas. 2075 LLVM_DEBUG(dbgs() << "NumGPRSpills = " << NumGPRSpills << "\n"); 2076 const Align TargetAlign = getStackAlign(); 2077 if (TargetAlign >= Align(8) && (NumGPRSpills & 1)) { 2078 if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 2079 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 2080 unsigned Reg = UnspilledCS1GPRs[i]; 2081 // Don't spill high register if the function is thumb. In the case of 2082 // Windows on ARM, accept R11 (frame pointer) 2083 if (!AFI->isThumbFunction() || 2084 (STI.isTargetWindows() && Reg == ARM::R11) || 2085 isARMLowRegister(Reg) || 2086 (Reg == ARM::LR && !ExpensiveLRRestore)) { 2087 SavedRegs.set(Reg); 2088 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI) 2089 << " to make up alignment\n"); 2090 if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg) && 2091 !(Reg == ARM::LR && AFI->isThumb1OnlyFunction())) 2092 ExtraCSSpill = true; 2093 break; 2094 } 2095 } 2096 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) { 2097 unsigned Reg = UnspilledCS2GPRs.front(); 2098 SavedRegs.set(Reg); 2099 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI) 2100 << " to make up alignment\n"); 2101 if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg)) 2102 ExtraCSSpill = true; 2103 } 2104 } 2105 2106 // Estimate if we might need to scavenge a register at some point in order 2107 // to materialize a stack offset. If so, either spill one additional 2108 // callee-saved register or reserve a special spill slot to facilitate 2109 // register scavenging. Thumb1 needs a spill slot for stack pointer 2110 // adjustments also, even when the frame itself is small. 2111 if (BigFrameOffsets && !ExtraCSSpill) { 2112 // If any non-reserved CS register isn't spilled, just spill one or two 2113 // extra. That should take care of it! 2114 unsigned NumExtras = TargetAlign.value() / 4; 2115 SmallVector<unsigned, 2> Extras; 2116 while (NumExtras && !UnspilledCS1GPRs.empty()) { 2117 unsigned Reg = UnspilledCS1GPRs.pop_back_val(); 2118 if (!MRI.isReserved(Reg) && 2119 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg))) { 2120 Extras.push_back(Reg); 2121 NumExtras--; 2122 } 2123 } 2124 // For non-Thumb1 functions, also check for hi-reg CS registers 2125 if (!AFI->isThumb1OnlyFunction()) { 2126 while (NumExtras && !UnspilledCS2GPRs.empty()) { 2127 unsigned Reg = UnspilledCS2GPRs.pop_back_val(); 2128 if (!MRI.isReserved(Reg)) { 2129 Extras.push_back(Reg); 2130 NumExtras--; 2131 } 2132 } 2133 } 2134 if (NumExtras == 0) { 2135 for (unsigned Reg : Extras) { 2136 SavedRegs.set(Reg); 2137 if (!MRI.isPhysRegUsed(Reg)) 2138 ExtraCSSpill = true; 2139 } 2140 } 2141 if (!ExtraCSSpill && RS) { 2142 // Reserve a slot closest to SP or frame pointer. 2143 LLVM_DEBUG(dbgs() << "Reserving emergency spill slot\n"); 2144 const TargetRegisterClass &RC = ARM::GPRRegClass; 2145 unsigned Size = TRI->getSpillSize(RC); 2146 Align Alignment = TRI->getSpillAlign(RC); 2147 RS->addScavengingFrameIndex( 2148 MFI.CreateStackObject(Size, Alignment, false)); 2149 } 2150 } 2151 } 2152 2153 if (ForceLRSpill) 2154 SavedRegs.set(ARM::LR); 2155 AFI->setLRIsSpilled(SavedRegs.test(ARM::LR)); 2156 } 2157 2158 void ARMFrameLowering::getCalleeSaves(const MachineFunction &MF, 2159 BitVector &SavedRegs) const { 2160 TargetFrameLowering::getCalleeSaves(MF, SavedRegs); 2161 2162 // If we have the "returned" parameter attribute which guarantees that we 2163 // return the value which was passed in r0 unmodified (e.g. C++ 'structors), 2164 // record that fact for IPRA. 2165 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2166 if (AFI->getPreservesR0()) 2167 SavedRegs.set(ARM::R0); 2168 } 2169 2170 bool ARMFrameLowering::assignCalleeSavedSpillSlots( 2171 MachineFunction &MF, const TargetRegisterInfo *TRI, 2172 std::vector<CalleeSavedInfo> &CSI) const { 2173 // For CMSE entry functions, handle floating-point context as if it was a 2174 // callee-saved register. 2175 if (STI.hasV8_1MMainlineOps() && 2176 MF.getInfo<ARMFunctionInfo>()->isCmseNSEntryFunction()) { 2177 CSI.emplace_back(ARM::FPCXTNS); 2178 CSI.back().setRestored(false); 2179 } 2180 2181 return false; 2182 } 2183 2184 const TargetFrameLowering::SpillSlot * 2185 ARMFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const { 2186 static const SpillSlot FixedSpillOffsets[] = {{ARM::FPCXTNS, -4}}; 2187 NumEntries = array_lengthof(FixedSpillOffsets); 2188 return FixedSpillOffsets; 2189 } 2190 2191 MachineBasicBlock::iterator ARMFrameLowering::eliminateCallFramePseudoInstr( 2192 MachineFunction &MF, MachineBasicBlock &MBB, 2193 MachineBasicBlock::iterator I) const { 2194 const ARMBaseInstrInfo &TII = 2195 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 2196 if (!hasReservedCallFrame(MF)) { 2197 // If we have alloca, convert as follows: 2198 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 2199 // ADJCALLSTACKUP -> add, sp, sp, amount 2200 MachineInstr &Old = *I; 2201 DebugLoc dl = Old.getDebugLoc(); 2202 unsigned Amount = TII.getFrameSize(Old); 2203 if (Amount != 0) { 2204 // We need to keep the stack aligned properly. To do this, we round the 2205 // amount of space needed for the outgoing arguments up to the next 2206 // alignment boundary. 2207 Amount = alignSPAdjust(Amount); 2208 2209 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2210 assert(!AFI->isThumb1OnlyFunction() && 2211 "This eliminateCallFramePseudoInstr does not support Thumb1!"); 2212 bool isARM = !AFI->isThumbFunction(); 2213 2214 // Replace the pseudo instruction with a new instruction... 2215 unsigned Opc = Old.getOpcode(); 2216 int PIdx = Old.findFirstPredOperandIdx(); 2217 ARMCC::CondCodes Pred = 2218 (PIdx == -1) ? ARMCC::AL 2219 : (ARMCC::CondCodes)Old.getOperand(PIdx).getImm(); 2220 unsigned PredReg = TII.getFramePred(Old); 2221 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 2222 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags, 2223 Pred, PredReg); 2224 } else { 2225 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 2226 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags, 2227 Pred, PredReg); 2228 } 2229 } 2230 } 2231 return MBB.erase(I); 2232 } 2233 2234 /// Get the minimum constant for ARM that is greater than or equal to the 2235 /// argument. In ARM, constants can have any value that can be produced by 2236 /// rotating an 8-bit value to the right by an even number of bits within a 2237 /// 32-bit word. 2238 static uint32_t alignToARMConstant(uint32_t Value) { 2239 unsigned Shifted = 0; 2240 2241 if (Value == 0) 2242 return 0; 2243 2244 while (!(Value & 0xC0000000)) { 2245 Value = Value << 2; 2246 Shifted += 2; 2247 } 2248 2249 bool Carry = (Value & 0x00FFFFFF); 2250 Value = ((Value & 0xFF000000) >> 24) + Carry; 2251 2252 if (Value & 0x0000100) 2253 Value = Value & 0x000001FC; 2254 2255 if (Shifted > 24) 2256 Value = Value >> (Shifted - 24); 2257 else 2258 Value = Value << (24 - Shifted); 2259 2260 return Value; 2261 } 2262 2263 // The stack limit in the TCB is set to this many bytes above the actual 2264 // stack limit. 2265 static const uint64_t kSplitStackAvailable = 256; 2266 2267 // Adjust the function prologue to enable split stacks. This currently only 2268 // supports android and linux. 2269 // 2270 // The ABI of the segmented stack prologue is a little arbitrarily chosen, but 2271 // must be well defined in order to allow for consistent implementations of the 2272 // __morestack helper function. The ABI is also not a normal ABI in that it 2273 // doesn't follow the normal calling conventions because this allows the 2274 // prologue of each function to be optimized further. 2275 // 2276 // Currently, the ABI looks like (when calling __morestack) 2277 // 2278 // * r4 holds the minimum stack size requested for this function call 2279 // * r5 holds the stack size of the arguments to the function 2280 // * the beginning of the function is 3 instructions after the call to 2281 // __morestack 2282 // 2283 // Implementations of __morestack should use r4 to allocate a new stack, r5 to 2284 // place the arguments on to the new stack, and the 3-instruction knowledge to 2285 // jump directly to the body of the function when working on the new stack. 2286 // 2287 // An old (and possibly no longer compatible) implementation of __morestack for 2288 // ARM can be found at [1]. 2289 // 2290 // [1] - https://github.com/mozilla/rust/blob/86efd9/src/rt/arch/arm/morestack.S 2291 void ARMFrameLowering::adjustForSegmentedStacks( 2292 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const { 2293 unsigned Opcode; 2294 unsigned CFIIndex; 2295 const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>(); 2296 bool Thumb = ST->isThumb(); 2297 2298 // Sadly, this currently doesn't support varargs, platforms other than 2299 // android/linux. Note that thumb1/thumb2 are support for android/linux. 2300 if (MF.getFunction().isVarArg()) 2301 report_fatal_error("Segmented stacks do not support vararg functions."); 2302 if (!ST->isTargetAndroid() && !ST->isTargetLinux()) 2303 report_fatal_error("Segmented stacks not supported on this platform."); 2304 2305 MachineFrameInfo &MFI = MF.getFrameInfo(); 2306 MachineModuleInfo &MMI = MF.getMMI(); 2307 MCContext &Context = MMI.getContext(); 2308 const MCRegisterInfo *MRI = Context.getRegisterInfo(); 2309 const ARMBaseInstrInfo &TII = 2310 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 2311 ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>(); 2312 DebugLoc DL; 2313 2314 uint64_t StackSize = MFI.getStackSize(); 2315 2316 // Do not generate a prologue for leaf functions with a stack of size zero. 2317 // For non-leaf functions we have to allow for the possibility that the 2318 // callis to a non-split function, as in PR37807. This function could also 2319 // take the address of a non-split function. When the linker tries to adjust 2320 // its non-existent prologue, it would fail with an error. Mark the object 2321 // file so that such failures are not errors. See this Go language bug-report 2322 // https://go-review.googlesource.com/c/go/+/148819/ 2323 if (StackSize == 0 && !MFI.hasTailCall()) { 2324 MF.getMMI().setHasNosplitStack(true); 2325 return; 2326 } 2327 2328 // Use R4 and R5 as scratch registers. 2329 // We save R4 and R5 before use and restore them before leaving the function. 2330 unsigned ScratchReg0 = ARM::R4; 2331 unsigned ScratchReg1 = ARM::R5; 2332 uint64_t AlignedStackSize; 2333 2334 MachineBasicBlock *PrevStackMBB = MF.CreateMachineBasicBlock(); 2335 MachineBasicBlock *PostStackMBB = MF.CreateMachineBasicBlock(); 2336 MachineBasicBlock *AllocMBB = MF.CreateMachineBasicBlock(); 2337 MachineBasicBlock *GetMBB = MF.CreateMachineBasicBlock(); 2338 MachineBasicBlock *McrMBB = MF.CreateMachineBasicBlock(); 2339 2340 // Grab everything that reaches PrologueMBB to update there liveness as well. 2341 SmallPtrSet<MachineBasicBlock *, 8> BeforePrologueRegion; 2342 SmallVector<MachineBasicBlock *, 2> WalkList; 2343 WalkList.push_back(&PrologueMBB); 2344 2345 do { 2346 MachineBasicBlock *CurMBB = WalkList.pop_back_val(); 2347 for (MachineBasicBlock *PredBB : CurMBB->predecessors()) { 2348 if (BeforePrologueRegion.insert(PredBB).second) 2349 WalkList.push_back(PredBB); 2350 } 2351 } while (!WalkList.empty()); 2352 2353 // The order in that list is important. 2354 // The blocks will all be inserted before PrologueMBB using that order. 2355 // Therefore the block that should appear first in the CFG should appear 2356 // first in the list. 2357 MachineBasicBlock *AddedBlocks[] = {PrevStackMBB, McrMBB, GetMBB, AllocMBB, 2358 PostStackMBB}; 2359 2360 for (MachineBasicBlock *B : AddedBlocks) 2361 BeforePrologueRegion.insert(B); 2362 2363 for (const auto &LI : PrologueMBB.liveins()) { 2364 for (MachineBasicBlock *PredBB : BeforePrologueRegion) 2365 PredBB->addLiveIn(LI); 2366 } 2367 2368 // Remove the newly added blocks from the list, since we know 2369 // we do not have to do the following updates for them. 2370 for (MachineBasicBlock *B : AddedBlocks) { 2371 BeforePrologueRegion.erase(B); 2372 MF.insert(PrologueMBB.getIterator(), B); 2373 } 2374 2375 for (MachineBasicBlock *MBB : BeforePrologueRegion) { 2376 // Make sure the LiveIns are still sorted and unique. 2377 MBB->sortUniqueLiveIns(); 2378 // Replace the edges to PrologueMBB by edges to the sequences 2379 // we are about to add. 2380 MBB->ReplaceUsesOfBlockWith(&PrologueMBB, AddedBlocks[0]); 2381 } 2382 2383 // The required stack size that is aligned to ARM constant criterion. 2384 AlignedStackSize = alignToARMConstant(StackSize); 2385 2386 // When the frame size is less than 256 we just compare the stack 2387 // boundary directly to the value of the stack pointer, per gcc. 2388 bool CompareStackPointer = AlignedStackSize < kSplitStackAvailable; 2389 2390 // We will use two of the callee save registers as scratch registers so we 2391 // need to save those registers onto the stack. 2392 // We will use SR0 to hold stack limit and SR1 to hold the stack size 2393 // requested and arguments for __morestack(). 2394 // SR0: Scratch Register #0 2395 // SR1: Scratch Register #1 2396 // push {SR0, SR1} 2397 if (Thumb) { 2398 BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH)) 2399 .add(predOps(ARMCC::AL)) 2400 .addReg(ScratchReg0) 2401 .addReg(ScratchReg1); 2402 } else { 2403 BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD)) 2404 .addReg(ARM::SP, RegState::Define) 2405 .addReg(ARM::SP) 2406 .add(predOps(ARMCC::AL)) 2407 .addReg(ScratchReg0) 2408 .addReg(ScratchReg1); 2409 } 2410 2411 // Emit the relevant DWARF information about the change in stack pointer as 2412 // well as where to find both r4 and r5 (the callee-save registers) 2413 CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 8)); 2414 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2415 .addCFIIndex(CFIIndex); 2416 CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( 2417 nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4)); 2418 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2419 .addCFIIndex(CFIIndex); 2420 CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( 2421 nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8)); 2422 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2423 .addCFIIndex(CFIIndex); 2424 2425 // mov SR1, sp 2426 if (Thumb) { 2427 BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1) 2428 .addReg(ARM::SP) 2429 .add(predOps(ARMCC::AL)); 2430 } else if (CompareStackPointer) { 2431 BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1) 2432 .addReg(ARM::SP) 2433 .add(predOps(ARMCC::AL)) 2434 .add(condCodeOp()); 2435 } 2436 2437 // sub SR1, sp, #StackSize 2438 if (!CompareStackPointer && Thumb) { 2439 BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1) 2440 .add(condCodeOp()) 2441 .addReg(ScratchReg1) 2442 .addImm(AlignedStackSize) 2443 .add(predOps(ARMCC::AL)); 2444 } else if (!CompareStackPointer) { 2445 BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1) 2446 .addReg(ARM::SP) 2447 .addImm(AlignedStackSize) 2448 .add(predOps(ARMCC::AL)) 2449 .add(condCodeOp()); 2450 } 2451 2452 if (Thumb && ST->isThumb1Only()) { 2453 unsigned PCLabelId = ARMFI->createPICLabelUId(); 2454 ARMConstantPoolValue *NewCPV = ARMConstantPoolSymbol::Create( 2455 MF.getFunction().getContext(), "__STACK_LIMIT", PCLabelId, 0); 2456 MachineConstantPool *MCP = MF.getConstantPool(); 2457 unsigned CPI = MCP->getConstantPoolIndex(NewCPV, Align(4)); 2458 2459 // ldr SR0, [pc, offset(STACK_LIMIT)] 2460 BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0) 2461 .addConstantPoolIndex(CPI) 2462 .add(predOps(ARMCC::AL)); 2463 2464 // ldr SR0, [SR0] 2465 BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0) 2466 .addReg(ScratchReg0) 2467 .addImm(0) 2468 .add(predOps(ARMCC::AL)); 2469 } else { 2470 // Get TLS base address from the coprocessor 2471 // mrc p15, #0, SR0, c13, c0, #3 2472 BuildMI(McrMBB, DL, TII.get(Thumb ? ARM::t2MRC : ARM::MRC), 2473 ScratchReg0) 2474 .addImm(15) 2475 .addImm(0) 2476 .addImm(13) 2477 .addImm(0) 2478 .addImm(3) 2479 .add(predOps(ARMCC::AL)); 2480 2481 // Use the last tls slot on android and a private field of the TCP on linux. 2482 assert(ST->isTargetAndroid() || ST->isTargetLinux()); 2483 unsigned TlsOffset = ST->isTargetAndroid() ? 63 : 1; 2484 2485 // Get the stack limit from the right offset 2486 // ldr SR0, [sr0, #4 * TlsOffset] 2487 BuildMI(GetMBB, DL, TII.get(Thumb ? ARM::t2LDRi12 : ARM::LDRi12), 2488 ScratchReg0) 2489 .addReg(ScratchReg0) 2490 .addImm(4 * TlsOffset) 2491 .add(predOps(ARMCC::AL)); 2492 } 2493 2494 // Compare stack limit with stack size requested. 2495 // cmp SR0, SR1 2496 Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr; 2497 BuildMI(GetMBB, DL, TII.get(Opcode)) 2498 .addReg(ScratchReg0) 2499 .addReg(ScratchReg1) 2500 .add(predOps(ARMCC::AL)); 2501 2502 // This jump is taken if StackLimit < SP - stack required. 2503 Opcode = Thumb ? ARM::tBcc : ARM::Bcc; 2504 BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB) 2505 .addImm(ARMCC::LO) 2506 .addReg(ARM::CPSR); 2507 2508 2509 // Calling __morestack(StackSize, Size of stack arguments). 2510 // __morestack knows that the stack size requested is in SR0(r4) 2511 // and amount size of stack arguments is in SR1(r5). 2512 2513 // Pass first argument for the __morestack by Scratch Register #0. 2514 // The amount size of stack required 2515 if (Thumb) { 2516 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0) 2517 .add(condCodeOp()) 2518 .addImm(AlignedStackSize) 2519 .add(predOps(ARMCC::AL)); 2520 } else { 2521 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0) 2522 .addImm(AlignedStackSize) 2523 .add(predOps(ARMCC::AL)) 2524 .add(condCodeOp()); 2525 } 2526 // Pass second argument for the __morestack by Scratch Register #1. 2527 // The amount size of stack consumed to save function arguments. 2528 if (Thumb) { 2529 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1) 2530 .add(condCodeOp()) 2531 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())) 2532 .add(predOps(ARMCC::AL)); 2533 } else { 2534 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1) 2535 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())) 2536 .add(predOps(ARMCC::AL)) 2537 .add(condCodeOp()); 2538 } 2539 2540 // push {lr} - Save return address of this function. 2541 if (Thumb) { 2542 BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH)) 2543 .add(predOps(ARMCC::AL)) 2544 .addReg(ARM::LR); 2545 } else { 2546 BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD)) 2547 .addReg(ARM::SP, RegState::Define) 2548 .addReg(ARM::SP) 2549 .add(predOps(ARMCC::AL)) 2550 .addReg(ARM::LR); 2551 } 2552 2553 // Emit the DWARF info about the change in stack as well as where to find the 2554 // previous link register 2555 CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 12)); 2556 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2557 .addCFIIndex(CFIIndex); 2558 CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( 2559 nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12)); 2560 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2561 .addCFIIndex(CFIIndex); 2562 2563 // Call __morestack(). 2564 if (Thumb) { 2565 BuildMI(AllocMBB, DL, TII.get(ARM::tBL)) 2566 .add(predOps(ARMCC::AL)) 2567 .addExternalSymbol("__morestack"); 2568 } else { 2569 BuildMI(AllocMBB, DL, TII.get(ARM::BL)) 2570 .addExternalSymbol("__morestack"); 2571 } 2572 2573 // pop {lr} - Restore return address of this original function. 2574 if (Thumb) { 2575 if (ST->isThumb1Only()) { 2576 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)) 2577 .add(predOps(ARMCC::AL)) 2578 .addReg(ScratchReg0); 2579 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR) 2580 .addReg(ScratchReg0) 2581 .add(predOps(ARMCC::AL)); 2582 } else { 2583 BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST)) 2584 .addReg(ARM::LR, RegState::Define) 2585 .addReg(ARM::SP, RegState::Define) 2586 .addReg(ARM::SP) 2587 .addImm(4) 2588 .add(predOps(ARMCC::AL)); 2589 } 2590 } else { 2591 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) 2592 .addReg(ARM::SP, RegState::Define) 2593 .addReg(ARM::SP) 2594 .add(predOps(ARMCC::AL)) 2595 .addReg(ARM::LR); 2596 } 2597 2598 // Restore SR0 and SR1 in case of __morestack() was called. 2599 // __morestack() will skip PostStackMBB block so we need to restore 2600 // scratch registers from here. 2601 // pop {SR0, SR1} 2602 if (Thumb) { 2603 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)) 2604 .add(predOps(ARMCC::AL)) 2605 .addReg(ScratchReg0) 2606 .addReg(ScratchReg1); 2607 } else { 2608 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) 2609 .addReg(ARM::SP, RegState::Define) 2610 .addReg(ARM::SP) 2611 .add(predOps(ARMCC::AL)) 2612 .addReg(ScratchReg0) 2613 .addReg(ScratchReg1); 2614 } 2615 2616 // Update the CFA offset now that we've popped 2617 CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0)); 2618 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2619 .addCFIIndex(CFIIndex); 2620 2621 // Return from this function. 2622 BuildMI(AllocMBB, DL, TII.get(ST->getReturnOpcode())).add(predOps(ARMCC::AL)); 2623 2624 // Restore SR0 and SR1 in case of __morestack() was not called. 2625 // pop {SR0, SR1} 2626 if (Thumb) { 2627 BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP)) 2628 .add(predOps(ARMCC::AL)) 2629 .addReg(ScratchReg0) 2630 .addReg(ScratchReg1); 2631 } else { 2632 BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD)) 2633 .addReg(ARM::SP, RegState::Define) 2634 .addReg(ARM::SP) 2635 .add(predOps(ARMCC::AL)) 2636 .addReg(ScratchReg0) 2637 .addReg(ScratchReg1); 2638 } 2639 2640 // Update the CFA offset now that we've popped 2641 CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0)); 2642 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2643 .addCFIIndex(CFIIndex); 2644 2645 // Tell debuggers that r4 and r5 are now the same as they were in the 2646 // previous function, that they're the "Same Value". 2647 CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue( 2648 nullptr, MRI->getDwarfRegNum(ScratchReg0, true))); 2649 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2650 .addCFIIndex(CFIIndex); 2651 CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue( 2652 nullptr, MRI->getDwarfRegNum(ScratchReg1, true))); 2653 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) 2654 .addCFIIndex(CFIIndex); 2655 2656 // Organizing MBB lists 2657 PostStackMBB->addSuccessor(&PrologueMBB); 2658 2659 AllocMBB->addSuccessor(PostStackMBB); 2660 2661 GetMBB->addSuccessor(PostStackMBB); 2662 GetMBB->addSuccessor(AllocMBB); 2663 2664 McrMBB->addSuccessor(GetMBB); 2665 2666 PrevStackMBB->addSuccessor(McrMBB); 2667 2668 #ifdef EXPENSIVE_CHECKS 2669 MF.verify(); 2670 #endif 2671 } 2672