1 //===- ARMFastISel.cpp - ARM FastISel implementation ----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the ARM-specific support for the FastISel class. Some 10 // of the target-specific code is generated by tablegen in the file 11 // ARMGenFastISel.inc, which is #included here. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "ARM.h" 16 #include "ARMBaseInstrInfo.h" 17 #include "ARMBaseRegisterInfo.h" 18 #include "ARMCallingConv.h" 19 #include "ARMConstantPoolValue.h" 20 #include "ARMISelLowering.h" 21 #include "ARMMachineFunctionInfo.h" 22 #include "ARMSubtarget.h" 23 #include "MCTargetDesc/ARMAddressingModes.h" 24 #include "MCTargetDesc/ARMBaseInfo.h" 25 #include "Utils/ARMBaseInfo.h" 26 #include "llvm/ADT/APFloat.h" 27 #include "llvm/ADT/APInt.h" 28 #include "llvm/ADT/DenseMap.h" 29 #include "llvm/ADT/SmallVector.h" 30 #include "llvm/CodeGen/CallingConvLower.h" 31 #include "llvm/CodeGen/FastISel.h" 32 #include "llvm/CodeGen/FunctionLoweringInfo.h" 33 #include "llvm/CodeGen/ISDOpcodes.h" 34 #include "llvm/CodeGen/MachineBasicBlock.h" 35 #include "llvm/CodeGen/MachineConstantPool.h" 36 #include "llvm/CodeGen/MachineFrameInfo.h" 37 #include "llvm/CodeGen/MachineFunction.h" 38 #include "llvm/CodeGen/MachineInstr.h" 39 #include "llvm/CodeGen/MachineInstrBuilder.h" 40 #include "llvm/CodeGen/MachineMemOperand.h" 41 #include "llvm/CodeGen/MachineOperand.h" 42 #include "llvm/CodeGen/MachineRegisterInfo.h" 43 #include "llvm/CodeGen/RuntimeLibcalls.h" 44 #include "llvm/CodeGen/TargetInstrInfo.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/CodeGen/TargetOpcodes.h" 47 #include "llvm/CodeGen/TargetRegisterInfo.h" 48 #include "llvm/CodeGen/ValueTypes.h" 49 #include "llvm/IR/Argument.h" 50 #include "llvm/IR/Attributes.h" 51 #include "llvm/IR/CallingConv.h" 52 #include "llvm/IR/Constant.h" 53 #include "llvm/IR/Constants.h" 54 #include "llvm/IR/DataLayout.h" 55 #include "llvm/IR/DerivedTypes.h" 56 #include "llvm/IR/Function.h" 57 #include "llvm/IR/GetElementPtrTypeIterator.h" 58 #include "llvm/IR/GlobalValue.h" 59 #include "llvm/IR/GlobalVariable.h" 60 #include "llvm/IR/InstrTypes.h" 61 #include "llvm/IR/Instruction.h" 62 #include "llvm/IR/Instructions.h" 63 #include "llvm/IR/IntrinsicInst.h" 64 #include "llvm/IR/Intrinsics.h" 65 #include "llvm/IR/Module.h" 66 #include "llvm/IR/Operator.h" 67 #include "llvm/IR/Type.h" 68 #include "llvm/IR/User.h" 69 #include "llvm/IR/Value.h" 70 #include "llvm/MC/MCInstrDesc.h" 71 #include "llvm/MC/MCRegisterInfo.h" 72 #include "llvm/Support/Casting.h" 73 #include "llvm/Support/Compiler.h" 74 #include "llvm/Support/ErrorHandling.h" 75 #include "llvm/Support/MachineValueType.h" 76 #include "llvm/Support/MathExtras.h" 77 #include "llvm/Target/TargetMachine.h" 78 #include "llvm/Target/TargetOptions.h" 79 #include <cassert> 80 #include <cstdint> 81 #include <utility> 82 83 using namespace llvm; 84 85 namespace { 86 87 // All possible address modes, plus some. 88 struct Address { 89 enum { 90 RegBase, 91 FrameIndexBase 92 } BaseType = RegBase; 93 94 union { 95 unsigned Reg; 96 int FI; 97 } Base; 98 99 int Offset = 0; 100 101 // Innocuous defaults for our address. 102 Address() { 103 Base.Reg = 0; 104 } 105 }; 106 107 class ARMFastISel final : public FastISel { 108 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 109 /// make the right decision when generating code for different targets. 110 const ARMSubtarget *Subtarget; 111 Module &M; 112 const TargetMachine &TM; 113 const TargetInstrInfo &TII; 114 const TargetLowering &TLI; 115 ARMFunctionInfo *AFI; 116 117 // Convenience variables to avoid some queries. 118 bool isThumb2; 119 LLVMContext *Context; 120 121 public: 122 explicit ARMFastISel(FunctionLoweringInfo &funcInfo, 123 const TargetLibraryInfo *libInfo) 124 : FastISel(funcInfo, libInfo), 125 Subtarget( 126 &static_cast<const ARMSubtarget &>(funcInfo.MF->getSubtarget())), 127 M(const_cast<Module &>(*funcInfo.Fn->getParent())), 128 TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()), 129 TLI(*Subtarget->getTargetLowering()) { 130 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>(); 131 isThumb2 = AFI->isThumbFunction(); 132 Context = &funcInfo.Fn->getContext(); 133 } 134 135 private: 136 // Code from FastISel.cpp. 137 138 unsigned fastEmitInst_r(unsigned MachineInstOpcode, 139 const TargetRegisterClass *RC, 140 unsigned Op0, bool Op0IsKill); 141 unsigned fastEmitInst_rr(unsigned MachineInstOpcode, 142 const TargetRegisterClass *RC, 143 unsigned Op0, bool Op0IsKill, 144 unsigned Op1, bool Op1IsKill); 145 unsigned fastEmitInst_ri(unsigned MachineInstOpcode, 146 const TargetRegisterClass *RC, 147 unsigned Op0, bool Op0IsKill, 148 uint64_t Imm); 149 unsigned fastEmitInst_i(unsigned MachineInstOpcode, 150 const TargetRegisterClass *RC, 151 uint64_t Imm); 152 153 // Backend specific FastISel code. 154 155 bool fastSelectInstruction(const Instruction *I) override; 156 unsigned fastMaterializeConstant(const Constant *C) override; 157 unsigned fastMaterializeAlloca(const AllocaInst *AI) override; 158 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, 159 const LoadInst *LI) override; 160 bool fastLowerArguments() override; 161 162 #include "ARMGenFastISel.inc" 163 164 // Instruction selection routines. 165 166 bool SelectLoad(const Instruction *I); 167 bool SelectStore(const Instruction *I); 168 bool SelectBranch(const Instruction *I); 169 bool SelectIndirectBr(const Instruction *I); 170 bool SelectCmp(const Instruction *I); 171 bool SelectFPExt(const Instruction *I); 172 bool SelectFPTrunc(const Instruction *I); 173 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode); 174 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode); 175 bool SelectIToFP(const Instruction *I, bool isSigned); 176 bool SelectFPToI(const Instruction *I, bool isSigned); 177 bool SelectDiv(const Instruction *I, bool isSigned); 178 bool SelectRem(const Instruction *I, bool isSigned); 179 bool SelectCall(const Instruction *I, const char *IntrMemName); 180 bool SelectIntrinsicCall(const IntrinsicInst &I); 181 bool SelectSelect(const Instruction *I); 182 bool SelectRet(const Instruction *I); 183 bool SelectTrunc(const Instruction *I); 184 bool SelectIntExt(const Instruction *I); 185 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy); 186 187 // Utility routines. 188 189 bool isPositionIndependent() const; 190 bool isTypeLegal(Type *Ty, MVT &VT); 191 bool isLoadTypeLegal(Type *Ty, MVT &VT); 192 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value, 193 bool isZExt); 194 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr, 195 unsigned Alignment = 0, bool isZExt = true, 196 bool allocReg = true); 197 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr, 198 unsigned Alignment = 0); 199 bool ARMComputeAddress(const Value *Obj, Address &Addr); 200 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3); 201 bool ARMIsMemCpySmall(uint64_t Len); 202 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len, 203 unsigned Alignment); 204 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt); 205 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT); 206 unsigned ARMMaterializeInt(const Constant *C, MVT VT); 207 unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT); 208 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg); 209 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg); 210 unsigned ARMSelectCallOp(bool UseReg); 211 unsigned ARMLowerPICELF(const GlobalValue *GV, MVT VT); 212 213 const TargetLowering *getTargetLowering() { return &TLI; } 214 215 // Call handling routines. 216 217 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, 218 bool Return, 219 bool isVarArg); 220 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args, 221 SmallVectorImpl<Register> &ArgRegs, 222 SmallVectorImpl<MVT> &ArgVTs, 223 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, 224 SmallVectorImpl<Register> &RegArgs, 225 CallingConv::ID CC, 226 unsigned &NumBytes, 227 bool isVarArg); 228 unsigned getLibcallReg(const Twine &Name); 229 bool FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs, 230 const Instruction *I, CallingConv::ID CC, 231 unsigned &NumBytes, bool isVarArg); 232 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call); 233 234 // OptionalDef handling routines. 235 236 bool isARMNEONPred(const MachineInstr *MI); 237 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR); 238 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); 239 void AddLoadStoreOperands(MVT VT, Address &Addr, 240 const MachineInstrBuilder &MIB, 241 MachineMemOperand::Flags Flags, bool useAM3); 242 }; 243 244 } // end anonymous namespace 245 246 // DefinesOptionalPredicate - This is different from DefinesPredicate in that 247 // we don't care about implicit defs here, just places we'll need to add a 248 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR. 249 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { 250 if (!MI->hasOptionalDef()) 251 return false; 252 253 // Look to see if our OptionalDef is defining CPSR or CCR. 254 for (const MachineOperand &MO : MI->operands()) { 255 if (!MO.isReg() || !MO.isDef()) continue; 256 if (MO.getReg() == ARM::CPSR) 257 *CPSR = true; 258 } 259 return true; 260 } 261 262 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) { 263 const MCInstrDesc &MCID = MI->getDesc(); 264 265 // If we're a thumb2 or not NEON function we'll be handled via isPredicable. 266 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON || 267 AFI->isThumb2Function()) 268 return MI->isPredicable(); 269 270 for (const MCOperandInfo &opInfo : MCID.operands()) 271 if (opInfo.isPredicate()) 272 return true; 273 274 return false; 275 } 276 277 // If the machine is predicable go ahead and add the predicate operands, if 278 // it needs default CC operands add those. 279 // TODO: If we want to support thumb1 then we'll need to deal with optional 280 // CPSR defs that need to be added before the remaining operands. See s_cc_out 281 // for descriptions why. 282 const MachineInstrBuilder & 283 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { 284 MachineInstr *MI = &*MIB; 285 286 // Do we use a predicate? or... 287 // Are we NEON in ARM mode and have a predicate operand? If so, I know 288 // we're not predicable but add it anyways. 289 if (isARMNEONPred(MI)) 290 MIB.add(predOps(ARMCC::AL)); 291 292 // Do we optionally set a predicate? Preds is size > 0 iff the predicate 293 // defines CPSR. All other OptionalDefines in ARM are the CCR register. 294 bool CPSR = false; 295 if (DefinesOptionalPredicate(MI, &CPSR)) 296 MIB.add(CPSR ? t1CondCodeOp() : condCodeOp()); 297 return MIB; 298 } 299 300 unsigned ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode, 301 const TargetRegisterClass *RC, 302 unsigned Op0, bool Op0IsKill) { 303 Register ResultReg = createResultReg(RC); 304 const MCInstrDesc &II = TII.get(MachineInstOpcode); 305 306 // Make sure the input operand is sufficiently constrained to be legal 307 // for this instruction. 308 Op0 = constrainOperandRegClass(II, Op0, 1); 309 if (II.getNumDefs() >= 1) { 310 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, 311 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); 312 } else { 313 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) 314 .addReg(Op0, Op0IsKill * RegState::Kill)); 315 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 316 TII.get(TargetOpcode::COPY), ResultReg) 317 .addReg(II.ImplicitDefs[0])); 318 } 319 return ResultReg; 320 } 321 322 unsigned ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode, 323 const TargetRegisterClass *RC, 324 unsigned Op0, bool Op0IsKill, 325 unsigned Op1, bool Op1IsKill) { 326 unsigned ResultReg = createResultReg(RC); 327 const MCInstrDesc &II = TII.get(MachineInstOpcode); 328 329 // Make sure the input operands are sufficiently constrained to be legal 330 // for this instruction. 331 Op0 = constrainOperandRegClass(II, Op0, 1); 332 Op1 = constrainOperandRegClass(II, Op1, 2); 333 334 if (II.getNumDefs() >= 1) { 335 AddOptionalDefs( 336 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) 337 .addReg(Op0, Op0IsKill * RegState::Kill) 338 .addReg(Op1, Op1IsKill * RegState::Kill)); 339 } else { 340 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) 341 .addReg(Op0, Op0IsKill * RegState::Kill) 342 .addReg(Op1, Op1IsKill * RegState::Kill)); 343 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 344 TII.get(TargetOpcode::COPY), ResultReg) 345 .addReg(II.ImplicitDefs[0])); 346 } 347 return ResultReg; 348 } 349 350 unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode, 351 const TargetRegisterClass *RC, 352 unsigned Op0, bool Op0IsKill, 353 uint64_t Imm) { 354 unsigned ResultReg = createResultReg(RC); 355 const MCInstrDesc &II = TII.get(MachineInstOpcode); 356 357 // Make sure the input operand is sufficiently constrained to be legal 358 // for this instruction. 359 Op0 = constrainOperandRegClass(II, Op0, 1); 360 if (II.getNumDefs() >= 1) { 361 AddOptionalDefs( 362 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) 363 .addReg(Op0, Op0IsKill * RegState::Kill) 364 .addImm(Imm)); 365 } else { 366 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) 367 .addReg(Op0, Op0IsKill * RegState::Kill) 368 .addImm(Imm)); 369 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 370 TII.get(TargetOpcode::COPY), ResultReg) 371 .addReg(II.ImplicitDefs[0])); 372 } 373 return ResultReg; 374 } 375 376 unsigned ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode, 377 const TargetRegisterClass *RC, 378 uint64_t Imm) { 379 unsigned ResultReg = createResultReg(RC); 380 const MCInstrDesc &II = TII.get(MachineInstOpcode); 381 382 if (II.getNumDefs() >= 1) { 383 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, 384 ResultReg).addImm(Imm)); 385 } else { 386 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) 387 .addImm(Imm)); 388 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 389 TII.get(TargetOpcode::COPY), ResultReg) 390 .addReg(II.ImplicitDefs[0])); 391 } 392 return ResultReg; 393 } 394 395 // TODO: Don't worry about 64-bit now, but when this is fixed remove the 396 // checks from the various callers. 397 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) { 398 if (VT == MVT::f64) return 0; 399 400 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); 401 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 402 TII.get(ARM::VMOVSR), MoveReg) 403 .addReg(SrcReg)); 404 return MoveReg; 405 } 406 407 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) { 408 if (VT == MVT::i64) return 0; 409 410 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); 411 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 412 TII.get(ARM::VMOVRS), MoveReg) 413 .addReg(SrcReg)); 414 return MoveReg; 415 } 416 417 // For double width floating point we need to materialize two constants 418 // (the high and the low) into integer registers then use a move to get 419 // the combined constant into an FP reg. 420 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) { 421 const APFloat Val = CFP->getValueAPF(); 422 bool is64bit = VT == MVT::f64; 423 424 // This checks to see if we can use VFP3 instructions to materialize 425 // a constant, otherwise we have to go through the constant pool. 426 if (TLI.isFPImmLegal(Val, VT)) { 427 int Imm; 428 unsigned Opc; 429 if (is64bit) { 430 Imm = ARM_AM::getFP64Imm(Val); 431 Opc = ARM::FCONSTD; 432 } else { 433 Imm = ARM_AM::getFP32Imm(Val); 434 Opc = ARM::FCONSTS; 435 } 436 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 437 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 438 TII.get(Opc), DestReg).addImm(Imm)); 439 return DestReg; 440 } 441 442 // Require VFP2 for loading fp constants. 443 if (!Subtarget->hasVFP2Base()) return false; 444 445 // MachineConstantPool wants an explicit alignment. 446 Align Alignment = DL.getPrefTypeAlign(CFP->getType()); 447 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Alignment); 448 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 449 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; 450 451 // The extra reg is for addrmode5. 452 AddOptionalDefs( 453 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg) 454 .addConstantPoolIndex(Idx) 455 .addReg(0)); 456 return DestReg; 457 } 458 459 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) { 460 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1) 461 return 0; 462 463 // If we can do this in a single instruction without a constant pool entry 464 // do so now. 465 const ConstantInt *CI = cast<ConstantInt>(C); 466 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) { 467 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; 468 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : 469 &ARM::GPRRegClass; 470 unsigned ImmReg = createResultReg(RC); 471 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 472 TII.get(Opc), ImmReg) 473 .addImm(CI->getZExtValue())); 474 return ImmReg; 475 } 476 477 // Use MVN to emit negative constants. 478 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) { 479 unsigned Imm = (unsigned)~(CI->getSExtValue()); 480 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 481 (ARM_AM::getSOImmVal(Imm) != -1); 482 if (UseImm) { 483 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; 484 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : 485 &ARM::GPRRegClass; 486 unsigned ImmReg = createResultReg(RC); 487 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 488 TII.get(Opc), ImmReg) 489 .addImm(Imm)); 490 return ImmReg; 491 } 492 } 493 494 unsigned ResultReg = 0; 495 if (Subtarget->useMovt()) 496 ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 497 498 if (ResultReg) 499 return ResultReg; 500 501 // Load from constant pool. For now 32-bit only. 502 if (VT != MVT::i32) 503 return 0; 504 505 // MachineConstantPool wants an explicit alignment. 506 Align Alignment = DL.getPrefTypeAlign(C->getType()); 507 unsigned Idx = MCP.getConstantPoolIndex(C, Alignment); 508 ResultReg = createResultReg(TLI.getRegClassFor(VT)); 509 if (isThumb2) 510 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 511 TII.get(ARM::t2LDRpci), ResultReg) 512 .addConstantPoolIndex(Idx)); 513 else { 514 // The extra immediate is for addrmode2. 515 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); 516 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 517 TII.get(ARM::LDRcp), ResultReg) 518 .addConstantPoolIndex(Idx) 519 .addImm(0)); 520 } 521 return ResultReg; 522 } 523 524 bool ARMFastISel::isPositionIndependent() const { 525 return TLI.isPositionIndependent(); 526 } 527 528 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) { 529 // For now 32-bit only. 530 if (VT != MVT::i32 || GV->isThreadLocal()) return 0; 531 532 // ROPI/RWPI not currently supported. 533 if (Subtarget->isROPI() || Subtarget->isRWPI()) 534 return 0; 535 536 bool IsIndirect = Subtarget->isGVIndirectSymbol(GV); 537 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass 538 : &ARM::GPRRegClass; 539 unsigned DestReg = createResultReg(RC); 540 541 // FastISel TLS support on non-MachO is broken, punt to SelectionDAG. 542 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 543 bool IsThreadLocal = GVar && GVar->isThreadLocal(); 544 if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0; 545 546 bool IsPositionIndependent = isPositionIndependent(); 547 // Use movw+movt when possible, it avoids constant pool entries. 548 // Non-darwin targets only support static movt relocations in FastISel. 549 if (Subtarget->useMovt() && 550 (Subtarget->isTargetMachO() || !IsPositionIndependent)) { 551 unsigned Opc; 552 unsigned char TF = 0; 553 if (Subtarget->isTargetMachO()) 554 TF = ARMII::MO_NONLAZY; 555 556 if (IsPositionIndependent) 557 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel; 558 else 559 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm; 560 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 561 TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF)); 562 } else { 563 // MachineConstantPool wants an explicit alignment. 564 Align Alignment = DL.getPrefTypeAlign(GV->getType()); 565 566 if (Subtarget->isTargetELF() && IsPositionIndependent) 567 return ARMLowerPICELF(GV, VT); 568 569 // Grab index. 570 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0; 571 unsigned Id = AFI->createPICLabelUId(); 572 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id, 573 ARMCP::CPValue, 574 PCAdj); 575 unsigned Idx = MCP.getConstantPoolIndex(CPV, Alignment); 576 577 // Load value. 578 MachineInstrBuilder MIB; 579 if (isThumb2) { 580 unsigned Opc = IsPositionIndependent ? ARM::t2LDRpci_pic : ARM::t2LDRpci; 581 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), 582 DestReg).addConstantPoolIndex(Idx); 583 if (IsPositionIndependent) 584 MIB.addImm(Id); 585 AddOptionalDefs(MIB); 586 } else { 587 // The extra immediate is for addrmode2. 588 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); 589 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 590 TII.get(ARM::LDRcp), DestReg) 591 .addConstantPoolIndex(Idx) 592 .addImm(0); 593 AddOptionalDefs(MIB); 594 595 if (IsPositionIndependent) { 596 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD; 597 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); 598 599 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 600 DbgLoc, TII.get(Opc), NewDestReg) 601 .addReg(DestReg) 602 .addImm(Id); 603 AddOptionalDefs(MIB); 604 return NewDestReg; 605 } 606 } 607 } 608 609 if (IsIndirect) { 610 MachineInstrBuilder MIB; 611 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); 612 if (isThumb2) 613 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 614 TII.get(ARM::t2LDRi12), NewDestReg) 615 .addReg(DestReg) 616 .addImm(0); 617 else 618 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 619 TII.get(ARM::LDRi12), NewDestReg) 620 .addReg(DestReg) 621 .addImm(0); 622 DestReg = NewDestReg; 623 AddOptionalDefs(MIB); 624 } 625 626 return DestReg; 627 } 628 629 unsigned ARMFastISel::fastMaterializeConstant(const Constant *C) { 630 EVT CEVT = TLI.getValueType(DL, C->getType(), true); 631 632 // Only handle simple types. 633 if (!CEVT.isSimple()) return 0; 634 MVT VT = CEVT.getSimpleVT(); 635 636 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 637 return ARMMaterializeFP(CFP, VT); 638 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 639 return ARMMaterializeGV(GV, VT); 640 else if (isa<ConstantInt>(C)) 641 return ARMMaterializeInt(C, VT); 642 643 return 0; 644 } 645 646 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF); 647 648 unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) { 649 // Don't handle dynamic allocas. 650 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0; 651 652 MVT VT; 653 if (!isLoadTypeLegal(AI->getType(), VT)) return 0; 654 655 DenseMap<const AllocaInst*, int>::iterator SI = 656 FuncInfo.StaticAllocaMap.find(AI); 657 658 // This will get lowered later into the correct offsets and registers 659 // via rewriteXFrameIndex. 660 if (SI != FuncInfo.StaticAllocaMap.end()) { 661 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; 662 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); 663 unsigned ResultReg = createResultReg(RC); 664 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); 665 666 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 667 TII.get(Opc), ResultReg) 668 .addFrameIndex(SI->second) 669 .addImm(0)); 670 return ResultReg; 671 } 672 673 return 0; 674 } 675 676 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) { 677 EVT evt = TLI.getValueType(DL, Ty, true); 678 679 // Only handle simple types. 680 if (evt == MVT::Other || !evt.isSimple()) return false; 681 VT = evt.getSimpleVT(); 682 683 // Handle all legal types, i.e. a register that will directly hold this 684 // value. 685 return TLI.isTypeLegal(VT); 686 } 687 688 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { 689 if (isTypeLegal(Ty, VT)) return true; 690 691 // If this is a type than can be sign or zero-extended to a basic operation 692 // go ahead and accept it now. 693 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) 694 return true; 695 696 return false; 697 } 698 699 // Computes the address to get to an object. 700 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) { 701 // Some boilerplate from the X86 FastISel. 702 const User *U = nullptr; 703 unsigned Opcode = Instruction::UserOp1; 704 if (const Instruction *I = dyn_cast<Instruction>(Obj)) { 705 // Don't walk into other basic blocks unless the object is an alloca from 706 // another block, otherwise it may not have a virtual register assigned. 707 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) || 708 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) { 709 Opcode = I->getOpcode(); 710 U = I; 711 } 712 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) { 713 Opcode = C->getOpcode(); 714 U = C; 715 } 716 717 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType())) 718 if (Ty->getAddressSpace() > 255) 719 // Fast instruction selection doesn't support the special 720 // address spaces. 721 return false; 722 723 switch (Opcode) { 724 default: 725 break; 726 case Instruction::BitCast: 727 // Look through bitcasts. 728 return ARMComputeAddress(U->getOperand(0), Addr); 729 case Instruction::IntToPtr: 730 // Look past no-op inttoptrs. 731 if (TLI.getValueType(DL, U->getOperand(0)->getType()) == 732 TLI.getPointerTy(DL)) 733 return ARMComputeAddress(U->getOperand(0), Addr); 734 break; 735 case Instruction::PtrToInt: 736 // Look past no-op ptrtoints. 737 if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL)) 738 return ARMComputeAddress(U->getOperand(0), Addr); 739 break; 740 case Instruction::GetElementPtr: { 741 Address SavedAddr = Addr; 742 int TmpOffset = Addr.Offset; 743 744 // Iterate through the GEP folding the constants into offsets where 745 // we can. 746 gep_type_iterator GTI = gep_type_begin(U); 747 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); 748 i != e; ++i, ++GTI) { 749 const Value *Op = *i; 750 if (StructType *STy = GTI.getStructTypeOrNull()) { 751 const StructLayout *SL = DL.getStructLayout(STy); 752 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); 753 TmpOffset += SL->getElementOffset(Idx); 754 } else { 755 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType()); 756 while (true) { 757 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { 758 // Constant-offset addressing. 759 TmpOffset += CI->getSExtValue() * S; 760 break; 761 } 762 if (canFoldAddIntoGEP(U, Op)) { 763 // A compatible add with a constant operand. Fold the constant. 764 ConstantInt *CI = 765 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1)); 766 TmpOffset += CI->getSExtValue() * S; 767 // Iterate on the other operand. 768 Op = cast<AddOperator>(Op)->getOperand(0); 769 continue; 770 } 771 // Unsupported 772 goto unsupported_gep; 773 } 774 } 775 } 776 777 // Try to grab the base operand now. 778 Addr.Offset = TmpOffset; 779 if (ARMComputeAddress(U->getOperand(0), Addr)) return true; 780 781 // We failed, restore everything and try the other options. 782 Addr = SavedAddr; 783 784 unsupported_gep: 785 break; 786 } 787 case Instruction::Alloca: { 788 const AllocaInst *AI = cast<AllocaInst>(Obj); 789 DenseMap<const AllocaInst*, int>::iterator SI = 790 FuncInfo.StaticAllocaMap.find(AI); 791 if (SI != FuncInfo.StaticAllocaMap.end()) { 792 Addr.BaseType = Address::FrameIndexBase; 793 Addr.Base.FI = SI->second; 794 return true; 795 } 796 break; 797 } 798 } 799 800 // Try to get this in a register if nothing else has worked. 801 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj); 802 return Addr.Base.Reg != 0; 803 } 804 805 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) { 806 bool needsLowering = false; 807 switch (VT.SimpleTy) { 808 default: llvm_unreachable("Unhandled load/store type!"); 809 case MVT::i1: 810 case MVT::i8: 811 case MVT::i16: 812 case MVT::i32: 813 if (!useAM3) { 814 // Integer loads/stores handle 12-bit offsets. 815 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset); 816 // Handle negative offsets. 817 if (needsLowering && isThumb2) 818 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 && 819 Addr.Offset > -256); 820 } else { 821 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets. 822 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255); 823 } 824 break; 825 case MVT::f32: 826 case MVT::f64: 827 // Floating point operands handle 8-bit offsets. 828 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset); 829 break; 830 } 831 832 // If this is a stack pointer and the offset needs to be simplified then 833 // put the alloca address into a register, set the base type back to 834 // register and continue. This should almost never happen. 835 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) { 836 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass 837 : &ARM::GPRRegClass; 838 unsigned ResultReg = createResultReg(RC); 839 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; 840 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 841 TII.get(Opc), ResultReg) 842 .addFrameIndex(Addr.Base.FI) 843 .addImm(0)); 844 Addr.Base.Reg = ResultReg; 845 Addr.BaseType = Address::RegBase; 846 } 847 848 // Since the offset is too large for the load/store instruction 849 // get the reg+offset into a register. 850 if (needsLowering) { 851 Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg, 852 /*Op0IsKill*/false, Addr.Offset, MVT::i32); 853 Addr.Offset = 0; 854 } 855 } 856 857 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr, 858 const MachineInstrBuilder &MIB, 859 MachineMemOperand::Flags Flags, 860 bool useAM3) { 861 // addrmode5 output depends on the selection dag addressing dividing the 862 // offset by 4 that it then later multiplies. Do this here as well. 863 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64) 864 Addr.Offset /= 4; 865 866 // Frame base works a bit differently. Handle it separately. 867 if (Addr.BaseType == Address::FrameIndexBase) { 868 int FI = Addr.Base.FI; 869 int Offset = Addr.Offset; 870 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand( 871 MachinePointerInfo::getFixedStack(*FuncInfo.MF, FI, Offset), Flags, 872 MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); 873 // Now add the rest of the operands. 874 MIB.addFrameIndex(FI); 875 876 // ARM halfword load/stores and signed byte loads need an additional 877 // operand. 878 if (useAM3) { 879 int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; 880 MIB.addReg(0); 881 MIB.addImm(Imm); 882 } else { 883 MIB.addImm(Addr.Offset); 884 } 885 MIB.addMemOperand(MMO); 886 } else { 887 // Now add the rest of the operands. 888 MIB.addReg(Addr.Base.Reg); 889 890 // ARM halfword load/stores and signed byte loads need an additional 891 // operand. 892 if (useAM3) { 893 int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; 894 MIB.addReg(0); 895 MIB.addImm(Imm); 896 } else { 897 MIB.addImm(Addr.Offset); 898 } 899 } 900 AddOptionalDefs(MIB); 901 } 902 903 bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr, 904 unsigned Alignment, bool isZExt, bool allocReg) { 905 unsigned Opc; 906 bool useAM3 = false; 907 bool needVMOV = false; 908 const TargetRegisterClass *RC; 909 switch (VT.SimpleTy) { 910 // This is mostly going to be Neon/vector support. 911 default: return false; 912 case MVT::i1: 913 case MVT::i8: 914 if (isThumb2) { 915 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) 916 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8; 917 else 918 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12; 919 } else { 920 if (isZExt) { 921 Opc = ARM::LDRBi12; 922 } else { 923 Opc = ARM::LDRSB; 924 useAM3 = true; 925 } 926 } 927 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; 928 break; 929 case MVT::i16: 930 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem()) 931 return false; 932 933 if (isThumb2) { 934 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) 935 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8; 936 else 937 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12; 938 } else { 939 Opc = isZExt ? ARM::LDRH : ARM::LDRSH; 940 useAM3 = true; 941 } 942 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; 943 break; 944 case MVT::i32: 945 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem()) 946 return false; 947 948 if (isThumb2) { 949 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) 950 Opc = ARM::t2LDRi8; 951 else 952 Opc = ARM::t2LDRi12; 953 } else { 954 Opc = ARM::LDRi12; 955 } 956 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; 957 break; 958 case MVT::f32: 959 if (!Subtarget->hasVFP2Base()) return false; 960 // Unaligned loads need special handling. Floats require word-alignment. 961 if (Alignment && Alignment < 4) { 962 needVMOV = true; 963 VT = MVT::i32; 964 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12; 965 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; 966 } else { 967 Opc = ARM::VLDRS; 968 RC = TLI.getRegClassFor(VT); 969 } 970 break; 971 case MVT::f64: 972 // Can load and store double precision even without FeatureFP64 973 if (!Subtarget->hasVFP2Base()) return false; 974 // FIXME: Unaligned loads need special handling. Doublewords require 975 // word-alignment. 976 if (Alignment && Alignment < 4) 977 return false; 978 979 Opc = ARM::VLDRD; 980 RC = TLI.getRegClassFor(VT); 981 break; 982 } 983 // Simplify this down to something we can handle. 984 ARMSimplifyAddress(Addr, VT, useAM3); 985 986 // Create the base instruction, then add the operands. 987 if (allocReg) 988 ResultReg = createResultReg(RC); 989 assert(ResultReg > 255 && "Expected an allocated virtual register."); 990 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 991 TII.get(Opc), ResultReg); 992 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3); 993 994 // If we had an unaligned load of a float we've converted it to an regular 995 // load. Now we must move from the GRP to the FP register. 996 if (needVMOV) { 997 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32)); 998 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 999 TII.get(ARM::VMOVSR), MoveReg) 1000 .addReg(ResultReg)); 1001 ResultReg = MoveReg; 1002 } 1003 return true; 1004 } 1005 1006 bool ARMFastISel::SelectLoad(const Instruction *I) { 1007 // Atomic loads need special handling. 1008 if (cast<LoadInst>(I)->isAtomic()) 1009 return false; 1010 1011 const Value *SV = I->getOperand(0); 1012 if (TLI.supportSwiftError()) { 1013 // Swifterror values can come from either a function parameter with 1014 // swifterror attribute or an alloca with swifterror attribute. 1015 if (const Argument *Arg = dyn_cast<Argument>(SV)) { 1016 if (Arg->hasSwiftErrorAttr()) 1017 return false; 1018 } 1019 1020 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) { 1021 if (Alloca->isSwiftError()) 1022 return false; 1023 } 1024 } 1025 1026 // Verify we have a legal type before going any further. 1027 MVT VT; 1028 if (!isLoadTypeLegal(I->getType(), VT)) 1029 return false; 1030 1031 // See if we can handle this address. 1032 Address Addr; 1033 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false; 1034 1035 Register ResultReg; 1036 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment())) 1037 return false; 1038 updateValueMap(I, ResultReg); 1039 return true; 1040 } 1041 1042 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr, 1043 unsigned Alignment) { 1044 unsigned StrOpc; 1045 bool useAM3 = false; 1046 switch (VT.SimpleTy) { 1047 // This is mostly going to be Neon/vector support. 1048 default: return false; 1049 case MVT::i1: { 1050 unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass 1051 : &ARM::GPRRegClass); 1052 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri; 1053 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); 1054 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1055 TII.get(Opc), Res) 1056 .addReg(SrcReg).addImm(1)); 1057 SrcReg = Res; 1058 LLVM_FALLTHROUGH; 1059 } 1060 case MVT::i8: 1061 if (isThumb2) { 1062 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) 1063 StrOpc = ARM::t2STRBi8; 1064 else 1065 StrOpc = ARM::t2STRBi12; 1066 } else { 1067 StrOpc = ARM::STRBi12; 1068 } 1069 break; 1070 case MVT::i16: 1071 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem()) 1072 return false; 1073 1074 if (isThumb2) { 1075 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) 1076 StrOpc = ARM::t2STRHi8; 1077 else 1078 StrOpc = ARM::t2STRHi12; 1079 } else { 1080 StrOpc = ARM::STRH; 1081 useAM3 = true; 1082 } 1083 break; 1084 case MVT::i32: 1085 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem()) 1086 return false; 1087 1088 if (isThumb2) { 1089 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) 1090 StrOpc = ARM::t2STRi8; 1091 else 1092 StrOpc = ARM::t2STRi12; 1093 } else { 1094 StrOpc = ARM::STRi12; 1095 } 1096 break; 1097 case MVT::f32: 1098 if (!Subtarget->hasVFP2Base()) return false; 1099 // Unaligned stores need special handling. Floats require word-alignment. 1100 if (Alignment && Alignment < 4) { 1101 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32)); 1102 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1103 TII.get(ARM::VMOVRS), MoveReg) 1104 .addReg(SrcReg)); 1105 SrcReg = MoveReg; 1106 VT = MVT::i32; 1107 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12; 1108 } else { 1109 StrOpc = ARM::VSTRS; 1110 } 1111 break; 1112 case MVT::f64: 1113 // Can load and store double precision even without FeatureFP64 1114 if (!Subtarget->hasVFP2Base()) return false; 1115 // FIXME: Unaligned stores need special handling. Doublewords require 1116 // word-alignment. 1117 if (Alignment && Alignment < 4) 1118 return false; 1119 1120 StrOpc = ARM::VSTRD; 1121 break; 1122 } 1123 // Simplify this down to something we can handle. 1124 ARMSimplifyAddress(Addr, VT, useAM3); 1125 1126 // Create the base instruction, then add the operands. 1127 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0); 1128 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1129 TII.get(StrOpc)) 1130 .addReg(SrcReg); 1131 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3); 1132 return true; 1133 } 1134 1135 bool ARMFastISel::SelectStore(const Instruction *I) { 1136 Value *Op0 = I->getOperand(0); 1137 unsigned SrcReg = 0; 1138 1139 // Atomic stores need special handling. 1140 if (cast<StoreInst>(I)->isAtomic()) 1141 return false; 1142 1143 const Value *PtrV = I->getOperand(1); 1144 if (TLI.supportSwiftError()) { 1145 // Swifterror values can come from either a function parameter with 1146 // swifterror attribute or an alloca with swifterror attribute. 1147 if (const Argument *Arg = dyn_cast<Argument>(PtrV)) { 1148 if (Arg->hasSwiftErrorAttr()) 1149 return false; 1150 } 1151 1152 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) { 1153 if (Alloca->isSwiftError()) 1154 return false; 1155 } 1156 } 1157 1158 // Verify we have a legal type before going any further. 1159 MVT VT; 1160 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT)) 1161 return false; 1162 1163 // Get the value to be stored into a register. 1164 SrcReg = getRegForValue(Op0); 1165 if (SrcReg == 0) return false; 1166 1167 // See if we can handle this address. 1168 Address Addr; 1169 if (!ARMComputeAddress(I->getOperand(1), Addr)) 1170 return false; 1171 1172 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment())) 1173 return false; 1174 return true; 1175 } 1176 1177 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) { 1178 switch (Pred) { 1179 // Needs two compares... 1180 case CmpInst::FCMP_ONE: 1181 case CmpInst::FCMP_UEQ: 1182 default: 1183 // AL is our "false" for now. The other two need more compares. 1184 return ARMCC::AL; 1185 case CmpInst::ICMP_EQ: 1186 case CmpInst::FCMP_OEQ: 1187 return ARMCC::EQ; 1188 case CmpInst::ICMP_SGT: 1189 case CmpInst::FCMP_OGT: 1190 return ARMCC::GT; 1191 case CmpInst::ICMP_SGE: 1192 case CmpInst::FCMP_OGE: 1193 return ARMCC::GE; 1194 case CmpInst::ICMP_UGT: 1195 case CmpInst::FCMP_UGT: 1196 return ARMCC::HI; 1197 case CmpInst::FCMP_OLT: 1198 return ARMCC::MI; 1199 case CmpInst::ICMP_ULE: 1200 case CmpInst::FCMP_OLE: 1201 return ARMCC::LS; 1202 case CmpInst::FCMP_ORD: 1203 return ARMCC::VC; 1204 case CmpInst::FCMP_UNO: 1205 return ARMCC::VS; 1206 case CmpInst::FCMP_UGE: 1207 return ARMCC::PL; 1208 case CmpInst::ICMP_SLT: 1209 case CmpInst::FCMP_ULT: 1210 return ARMCC::LT; 1211 case CmpInst::ICMP_SLE: 1212 case CmpInst::FCMP_ULE: 1213 return ARMCC::LE; 1214 case CmpInst::FCMP_UNE: 1215 case CmpInst::ICMP_NE: 1216 return ARMCC::NE; 1217 case CmpInst::ICMP_UGE: 1218 return ARMCC::HS; 1219 case CmpInst::ICMP_ULT: 1220 return ARMCC::LO; 1221 } 1222 } 1223 1224 bool ARMFastISel::SelectBranch(const Instruction *I) { 1225 const BranchInst *BI = cast<BranchInst>(I); 1226 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; 1227 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; 1228 1229 // Simple branch support. 1230 1231 // If we can, avoid recomputing the compare - redoing it could lead to wonky 1232 // behavior. 1233 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { 1234 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) { 1235 // Get the compare predicate. 1236 // Try to take advantage of fallthrough opportunities. 1237 CmpInst::Predicate Predicate = CI->getPredicate(); 1238 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { 1239 std::swap(TBB, FBB); 1240 Predicate = CmpInst::getInversePredicate(Predicate); 1241 } 1242 1243 ARMCC::CondCodes ARMPred = getComparePred(Predicate); 1244 1245 // We may not handle every CC for now. 1246 if (ARMPred == ARMCC::AL) return false; 1247 1248 // Emit the compare. 1249 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned())) 1250 return false; 1251 1252 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; 1253 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc)) 1254 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); 1255 finishCondBranch(BI->getParent(), TBB, FBB); 1256 return true; 1257 } 1258 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) { 1259 MVT SourceVT; 1260 if (TI->hasOneUse() && TI->getParent() == I->getParent() && 1261 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) { 1262 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; 1263 unsigned OpReg = getRegForValue(TI->getOperand(0)); 1264 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); 1265 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1266 TII.get(TstOpc)) 1267 .addReg(OpReg).addImm(1)); 1268 1269 unsigned CCMode = ARMCC::NE; 1270 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { 1271 std::swap(TBB, FBB); 1272 CCMode = ARMCC::EQ; 1273 } 1274 1275 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; 1276 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc)) 1277 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); 1278 1279 finishCondBranch(BI->getParent(), TBB, FBB); 1280 return true; 1281 } 1282 } else if (const ConstantInt *CI = 1283 dyn_cast<ConstantInt>(BI->getCondition())) { 1284 uint64_t Imm = CI->getZExtValue(); 1285 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB; 1286 fastEmitBranch(Target, DbgLoc); 1287 return true; 1288 } 1289 1290 unsigned CmpReg = getRegForValue(BI->getCondition()); 1291 if (CmpReg == 0) return false; 1292 1293 // We've been divorced from our compare! Our block was split, and 1294 // now our compare lives in a predecessor block. We musn't 1295 // re-compare here, as the children of the compare aren't guaranteed 1296 // live across the block boundary (we *could* check for this). 1297 // Regardless, the compare has been done in the predecessor block, 1298 // and it left a value for us in a virtual register. Ergo, we test 1299 // the one-bit value left in the virtual register. 1300 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; 1301 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0); 1302 AddOptionalDefs( 1303 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc)) 1304 .addReg(CmpReg) 1305 .addImm(1)); 1306 1307 unsigned CCMode = ARMCC::NE; 1308 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { 1309 std::swap(TBB, FBB); 1310 CCMode = ARMCC::EQ; 1311 } 1312 1313 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; 1314 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc)) 1315 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); 1316 finishCondBranch(BI->getParent(), TBB, FBB); 1317 return true; 1318 } 1319 1320 bool ARMFastISel::SelectIndirectBr(const Instruction *I) { 1321 unsigned AddrReg = getRegForValue(I->getOperand(0)); 1322 if (AddrReg == 0) return false; 1323 1324 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX; 1325 assert(isThumb2 || Subtarget->hasV4TOps()); 1326 1327 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1328 TII.get(Opc)).addReg(AddrReg)); 1329 1330 const IndirectBrInst *IB = cast<IndirectBrInst>(I); 1331 for (const BasicBlock *SuccBB : IB->successors()) 1332 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[SuccBB]); 1333 1334 return true; 1335 } 1336 1337 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value, 1338 bool isZExt) { 1339 Type *Ty = Src1Value->getType(); 1340 EVT SrcEVT = TLI.getValueType(DL, Ty, true); 1341 if (!SrcEVT.isSimple()) return false; 1342 MVT SrcVT = SrcEVT.getSimpleVT(); 1343 1344 if (Ty->isFloatTy() && !Subtarget->hasVFP2Base()) 1345 return false; 1346 1347 if (Ty->isDoubleTy() && (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64())) 1348 return false; 1349 1350 // Check to see if the 2nd operand is a constant that we can encode directly 1351 // in the compare. 1352 int Imm = 0; 1353 bool UseImm = false; 1354 bool isNegativeImm = false; 1355 // FIXME: At -O0 we don't have anything that canonicalizes operand order. 1356 // Thus, Src1Value may be a ConstantInt, but we're missing it. 1357 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) { 1358 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || 1359 SrcVT == MVT::i1) { 1360 const APInt &CIVal = ConstInt->getValue(); 1361 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue(); 1362 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather 1363 // then a cmn, because there is no way to represent 2147483648 as a 1364 // signed 32-bit int. 1365 if (Imm < 0 && Imm != (int)0x80000000) { 1366 isNegativeImm = true; 1367 Imm = -Imm; 1368 } 1369 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 1370 (ARM_AM::getSOImmVal(Imm) != -1); 1371 } 1372 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) { 1373 if (SrcVT == MVT::f32 || SrcVT == MVT::f64) 1374 if (ConstFP->isZero() && !ConstFP->isNegative()) 1375 UseImm = true; 1376 } 1377 1378 unsigned CmpOpc; 1379 bool isICmp = true; 1380 bool needsExt = false; 1381 switch (SrcVT.SimpleTy) { 1382 default: return false; 1383 // TODO: Verify compares. 1384 case MVT::f32: 1385 isICmp = false; 1386 CmpOpc = UseImm ? ARM::VCMPZS : ARM::VCMPS; 1387 break; 1388 case MVT::f64: 1389 isICmp = false; 1390 CmpOpc = UseImm ? ARM::VCMPZD : ARM::VCMPD; 1391 break; 1392 case MVT::i1: 1393 case MVT::i8: 1394 case MVT::i16: 1395 needsExt = true; 1396 LLVM_FALLTHROUGH; 1397 case MVT::i32: 1398 if (isThumb2) { 1399 if (!UseImm) 1400 CmpOpc = ARM::t2CMPrr; 1401 else 1402 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri; 1403 } else { 1404 if (!UseImm) 1405 CmpOpc = ARM::CMPrr; 1406 else 1407 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri; 1408 } 1409 break; 1410 } 1411 1412 unsigned SrcReg1 = getRegForValue(Src1Value); 1413 if (SrcReg1 == 0) return false; 1414 1415 unsigned SrcReg2 = 0; 1416 if (!UseImm) { 1417 SrcReg2 = getRegForValue(Src2Value); 1418 if (SrcReg2 == 0) return false; 1419 } 1420 1421 // We have i1, i8, or i16, we need to either zero extend or sign extend. 1422 if (needsExt) { 1423 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); 1424 if (SrcReg1 == 0) return false; 1425 if (!UseImm) { 1426 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); 1427 if (SrcReg2 == 0) return false; 1428 } 1429 } 1430 1431 const MCInstrDesc &II = TII.get(CmpOpc); 1432 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); 1433 if (!UseImm) { 1434 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); 1435 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) 1436 .addReg(SrcReg1).addReg(SrcReg2)); 1437 } else { 1438 MachineInstrBuilder MIB; 1439 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) 1440 .addReg(SrcReg1); 1441 1442 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0. 1443 if (isICmp) 1444 MIB.addImm(Imm); 1445 AddOptionalDefs(MIB); 1446 } 1447 1448 // For floating point we need to move the result to a comparison register 1449 // that we can then use for branches. 1450 if (Ty->isFloatTy() || Ty->isDoubleTy()) 1451 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1452 TII.get(ARM::FMSTAT))); 1453 return true; 1454 } 1455 1456 bool ARMFastISel::SelectCmp(const Instruction *I) { 1457 const CmpInst *CI = cast<CmpInst>(I); 1458 1459 // Get the compare predicate. 1460 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate()); 1461 1462 // We may not handle every CC for now. 1463 if (ARMPred == ARMCC::AL) return false; 1464 1465 // Emit the compare. 1466 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned())) 1467 return false; 1468 1469 // Now set a register based on the comparison. Explicitly set the predicates 1470 // here. 1471 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi; 1472 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass 1473 : &ARM::GPRRegClass; 1474 unsigned DestReg = createResultReg(RC); 1475 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0); 1476 unsigned ZeroReg = fastMaterializeConstant(Zero); 1477 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR. 1478 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg) 1479 .addReg(ZeroReg).addImm(1) 1480 .addImm(ARMPred).addReg(ARM::CPSR); 1481 1482 updateValueMap(I, DestReg); 1483 return true; 1484 } 1485 1486 bool ARMFastISel::SelectFPExt(const Instruction *I) { 1487 // Make sure we have VFP and that we're extending float to double. 1488 if (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()) return false; 1489 1490 Value *V = I->getOperand(0); 1491 if (!I->getType()->isDoubleTy() || 1492 !V->getType()->isFloatTy()) return false; 1493 1494 unsigned Op = getRegForValue(V); 1495 if (Op == 0) return false; 1496 1497 unsigned Result = createResultReg(&ARM::DPRRegClass); 1498 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1499 TII.get(ARM::VCVTDS), Result) 1500 .addReg(Op)); 1501 updateValueMap(I, Result); 1502 return true; 1503 } 1504 1505 bool ARMFastISel::SelectFPTrunc(const Instruction *I) { 1506 // Make sure we have VFP and that we're truncating double to float. 1507 if (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64()) return false; 1508 1509 Value *V = I->getOperand(0); 1510 if (!(I->getType()->isFloatTy() && 1511 V->getType()->isDoubleTy())) return false; 1512 1513 unsigned Op = getRegForValue(V); 1514 if (Op == 0) return false; 1515 1516 unsigned Result = createResultReg(&ARM::SPRRegClass); 1517 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1518 TII.get(ARM::VCVTSD), Result) 1519 .addReg(Op)); 1520 updateValueMap(I, Result); 1521 return true; 1522 } 1523 1524 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) { 1525 // Make sure we have VFP. 1526 if (!Subtarget->hasVFP2Base()) return false; 1527 1528 MVT DstVT; 1529 Type *Ty = I->getType(); 1530 if (!isTypeLegal(Ty, DstVT)) 1531 return false; 1532 1533 Value *Src = I->getOperand(0); 1534 EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true); 1535 if (!SrcEVT.isSimple()) 1536 return false; 1537 MVT SrcVT = SrcEVT.getSimpleVT(); 1538 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) 1539 return false; 1540 1541 unsigned SrcReg = getRegForValue(Src); 1542 if (SrcReg == 0) return false; 1543 1544 // Handle sign-extension. 1545 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) { 1546 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32, 1547 /*isZExt*/!isSigned); 1548 if (SrcReg == 0) return false; 1549 } 1550 1551 // The conversion routine works on fp-reg to fp-reg and the operand above 1552 // was an integer, move it to the fp registers if possible. 1553 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg); 1554 if (FP == 0) return false; 1555 1556 unsigned Opc; 1557 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS; 1558 else if (Ty->isDoubleTy() && Subtarget->hasFP64()) 1559 Opc = isSigned ? ARM::VSITOD : ARM::VUITOD; 1560 else return false; 1561 1562 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); 1563 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1564 TII.get(Opc), ResultReg).addReg(FP)); 1565 updateValueMap(I, ResultReg); 1566 return true; 1567 } 1568 1569 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) { 1570 // Make sure we have VFP. 1571 if (!Subtarget->hasVFP2Base()) return false; 1572 1573 MVT DstVT; 1574 Type *RetTy = I->getType(); 1575 if (!isTypeLegal(RetTy, DstVT)) 1576 return false; 1577 1578 unsigned Op = getRegForValue(I->getOperand(0)); 1579 if (Op == 0) return false; 1580 1581 unsigned Opc; 1582 Type *OpTy = I->getOperand(0)->getType(); 1583 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS; 1584 else if (OpTy->isDoubleTy() && Subtarget->hasFP64()) 1585 Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD; 1586 else return false; 1587 1588 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg. 1589 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); 1590 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1591 TII.get(Opc), ResultReg).addReg(Op)); 1592 1593 // This result needs to be in an integer register, but the conversion only 1594 // takes place in fp-regs. 1595 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); 1596 if (IntReg == 0) return false; 1597 1598 updateValueMap(I, IntReg); 1599 return true; 1600 } 1601 1602 bool ARMFastISel::SelectSelect(const Instruction *I) { 1603 MVT VT; 1604 if (!isTypeLegal(I->getType(), VT)) 1605 return false; 1606 1607 // Things need to be register sized for register moves. 1608 if (VT != MVT::i32) return false; 1609 1610 unsigned CondReg = getRegForValue(I->getOperand(0)); 1611 if (CondReg == 0) return false; 1612 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1613 if (Op1Reg == 0) return false; 1614 1615 // Check to see if we can use an immediate in the conditional move. 1616 int Imm = 0; 1617 bool UseImm = false; 1618 bool isNegativeImm = false; 1619 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) { 1620 assert(VT == MVT::i32 && "Expecting an i32."); 1621 Imm = (int)ConstInt->getValue().getZExtValue(); 1622 if (Imm < 0) { 1623 isNegativeImm = true; 1624 Imm = ~Imm; 1625 } 1626 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 1627 (ARM_AM::getSOImmVal(Imm) != -1); 1628 } 1629 1630 unsigned Op2Reg = 0; 1631 if (!UseImm) { 1632 Op2Reg = getRegForValue(I->getOperand(2)); 1633 if (Op2Reg == 0) return false; 1634 } 1635 1636 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; 1637 CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0); 1638 AddOptionalDefs( 1639 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc)) 1640 .addReg(CondReg) 1641 .addImm(1)); 1642 1643 unsigned MovCCOpc; 1644 const TargetRegisterClass *RC; 1645 if (!UseImm) { 1646 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass; 1647 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr; 1648 } else { 1649 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass; 1650 if (!isNegativeImm) 1651 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi; 1652 else 1653 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi; 1654 } 1655 unsigned ResultReg = createResultReg(RC); 1656 if (!UseImm) { 1657 Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1); 1658 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2); 1659 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), 1660 ResultReg) 1661 .addReg(Op2Reg) 1662 .addReg(Op1Reg) 1663 .addImm(ARMCC::NE) 1664 .addReg(ARM::CPSR); 1665 } else { 1666 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1); 1667 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), 1668 ResultReg) 1669 .addReg(Op1Reg) 1670 .addImm(Imm) 1671 .addImm(ARMCC::EQ) 1672 .addReg(ARM::CPSR); 1673 } 1674 updateValueMap(I, ResultReg); 1675 return true; 1676 } 1677 1678 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) { 1679 MVT VT; 1680 Type *Ty = I->getType(); 1681 if (!isTypeLegal(Ty, VT)) 1682 return false; 1683 1684 // If we have integer div support we should have selected this automagically. 1685 // In case we have a real miss go ahead and return false and we'll pick 1686 // it up later. 1687 if (Subtarget->hasDivideInThumbMode()) 1688 return false; 1689 1690 // Otherwise emit a libcall. 1691 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1692 if (VT == MVT::i8) 1693 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8; 1694 else if (VT == MVT::i16) 1695 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16; 1696 else if (VT == MVT::i32) 1697 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32; 1698 else if (VT == MVT::i64) 1699 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64; 1700 else if (VT == MVT::i128) 1701 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128; 1702 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1703 1704 return ARMEmitLibcall(I, LC); 1705 } 1706 1707 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) { 1708 MVT VT; 1709 Type *Ty = I->getType(); 1710 if (!isTypeLegal(Ty, VT)) 1711 return false; 1712 1713 // Many ABIs do not provide a libcall for standalone remainder, so we need to 1714 // use divrem (see the RTABI 4.3.1). Since FastISel can't handle non-double 1715 // multi-reg returns, we'll have to bail out. 1716 if (!TLI.hasStandaloneRem(VT)) { 1717 return false; 1718 } 1719 1720 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1721 if (VT == MVT::i8) 1722 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8; 1723 else if (VT == MVT::i16) 1724 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16; 1725 else if (VT == MVT::i32) 1726 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32; 1727 else if (VT == MVT::i64) 1728 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64; 1729 else if (VT == MVT::i128) 1730 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128; 1731 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1732 1733 return ARMEmitLibcall(I, LC); 1734 } 1735 1736 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) { 1737 EVT DestVT = TLI.getValueType(DL, I->getType(), true); 1738 1739 // We can get here in the case when we have a binary operation on a non-legal 1740 // type and the target independent selector doesn't know how to handle it. 1741 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) 1742 return false; 1743 1744 unsigned Opc; 1745 switch (ISDOpcode) { 1746 default: return false; 1747 case ISD::ADD: 1748 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr; 1749 break; 1750 case ISD::OR: 1751 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr; 1752 break; 1753 case ISD::SUB: 1754 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr; 1755 break; 1756 } 1757 1758 unsigned SrcReg1 = getRegForValue(I->getOperand(0)); 1759 if (SrcReg1 == 0) return false; 1760 1761 // TODO: Often the 2nd operand is an immediate, which can be encoded directly 1762 // in the instruction, rather then materializing the value in a register. 1763 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); 1764 if (SrcReg2 == 0) return false; 1765 1766 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); 1767 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1); 1768 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); 1769 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1770 TII.get(Opc), ResultReg) 1771 .addReg(SrcReg1).addReg(SrcReg2)); 1772 updateValueMap(I, ResultReg); 1773 return true; 1774 } 1775 1776 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) { 1777 EVT FPVT = TLI.getValueType(DL, I->getType(), true); 1778 if (!FPVT.isSimple()) return false; 1779 MVT VT = FPVT.getSimpleVT(); 1780 1781 // FIXME: Support vector types where possible. 1782 if (VT.isVector()) 1783 return false; 1784 1785 // We can get here in the case when we want to use NEON for our fp 1786 // operations, but can't figure out how to. Just use the vfp instructions 1787 // if we have them. 1788 // FIXME: It'd be nice to use NEON instructions. 1789 Type *Ty = I->getType(); 1790 if (Ty->isFloatTy() && !Subtarget->hasVFP2Base()) 1791 return false; 1792 if (Ty->isDoubleTy() && (!Subtarget->hasVFP2Base() || !Subtarget->hasFP64())) 1793 return false; 1794 1795 unsigned Opc; 1796 bool is64bit = VT == MVT::f64 || VT == MVT::i64; 1797 switch (ISDOpcode) { 1798 default: return false; 1799 case ISD::FADD: 1800 Opc = is64bit ? ARM::VADDD : ARM::VADDS; 1801 break; 1802 case ISD::FSUB: 1803 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS; 1804 break; 1805 case ISD::FMUL: 1806 Opc = is64bit ? ARM::VMULD : ARM::VMULS; 1807 break; 1808 } 1809 unsigned Op1 = getRegForValue(I->getOperand(0)); 1810 if (Op1 == 0) return false; 1811 1812 unsigned Op2 = getRegForValue(I->getOperand(1)); 1813 if (Op2 == 0) return false; 1814 1815 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); 1816 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1817 TII.get(Opc), ResultReg) 1818 .addReg(Op1).addReg(Op2)); 1819 updateValueMap(I, ResultReg); 1820 return true; 1821 } 1822 1823 // Call Handling Code 1824 1825 // This is largely taken directly from CCAssignFnForNode 1826 // TODO: We may not support all of this. 1827 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, 1828 bool Return, 1829 bool isVarArg) { 1830 switch (CC) { 1831 default: 1832 report_fatal_error("Unsupported calling convention"); 1833 case CallingConv::Fast: 1834 if (Subtarget->hasVFP2Base() && !isVarArg) { 1835 if (!Subtarget->isAAPCS_ABI()) 1836 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS); 1837 // For AAPCS ABI targets, just use VFP variant of the calling convention. 1838 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1839 } 1840 LLVM_FALLTHROUGH; 1841 case CallingConv::C: 1842 case CallingConv::CXX_FAST_TLS: 1843 // Use target triple & subtarget features to do actual dispatch. 1844 if (Subtarget->isAAPCS_ABI()) { 1845 if (Subtarget->hasVFP2Base() && 1846 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg) 1847 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); 1848 else 1849 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 1850 } else { 1851 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 1852 } 1853 case CallingConv::ARM_AAPCS_VFP: 1854 case CallingConv::Swift: 1855 if (!isVarArg) 1856 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); 1857 // Fall through to soft float variant, variadic functions don't 1858 // use hard floating point ABI. 1859 LLVM_FALLTHROUGH; 1860 case CallingConv::ARM_AAPCS: 1861 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 1862 case CallingConv::ARM_APCS: 1863 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 1864 case CallingConv::GHC: 1865 if (Return) 1866 report_fatal_error("Can't return in GHC call convention"); 1867 else 1868 return CC_ARM_APCS_GHC; 1869 case CallingConv::CFGuard_Check: 1870 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check); 1871 } 1872 } 1873 1874 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args, 1875 SmallVectorImpl<Register> &ArgRegs, 1876 SmallVectorImpl<MVT> &ArgVTs, 1877 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, 1878 SmallVectorImpl<Register> &RegArgs, 1879 CallingConv::ID CC, 1880 unsigned &NumBytes, 1881 bool isVarArg) { 1882 SmallVector<CCValAssign, 16> ArgLocs; 1883 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context); 1884 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, 1885 CCAssignFnForCall(CC, false, isVarArg)); 1886 1887 // Check that we can handle all of the arguments. If we can't, then bail out 1888 // now before we add code to the MBB. 1889 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1890 CCValAssign &VA = ArgLocs[i]; 1891 MVT ArgVT = ArgVTs[VA.getValNo()]; 1892 1893 // We don't handle NEON/vector parameters yet. 1894 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64) 1895 return false; 1896 1897 // Now copy/store arg to correct locations. 1898 if (VA.isRegLoc() && !VA.needsCustom()) { 1899 continue; 1900 } else if (VA.needsCustom()) { 1901 // TODO: We need custom lowering for vector (v2f64) args. 1902 if (VA.getLocVT() != MVT::f64 || 1903 // TODO: Only handle register args for now. 1904 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) 1905 return false; 1906 } else { 1907 switch (ArgVT.SimpleTy) { 1908 default: 1909 return false; 1910 case MVT::i1: 1911 case MVT::i8: 1912 case MVT::i16: 1913 case MVT::i32: 1914 break; 1915 case MVT::f32: 1916 if (!Subtarget->hasVFP2Base()) 1917 return false; 1918 break; 1919 case MVT::f64: 1920 if (!Subtarget->hasVFP2Base()) 1921 return false; 1922 break; 1923 } 1924 } 1925 } 1926 1927 // At the point, we are able to handle the call's arguments in fast isel. 1928 1929 // Get a count of how many bytes are to be pushed on the stack. 1930 NumBytes = CCInfo.getNextStackOffset(); 1931 1932 // Issue CALLSEQ_START 1933 unsigned AdjStackDown = TII.getCallFrameSetupOpcode(); 1934 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1935 TII.get(AdjStackDown)) 1936 .addImm(NumBytes).addImm(0)); 1937 1938 // Process the args. 1939 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1940 CCValAssign &VA = ArgLocs[i]; 1941 const Value *ArgVal = Args[VA.getValNo()]; 1942 Register Arg = ArgRegs[VA.getValNo()]; 1943 MVT ArgVT = ArgVTs[VA.getValNo()]; 1944 1945 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) && 1946 "We don't handle NEON/vector parameters yet."); 1947 1948 // Handle arg promotion, etc. 1949 switch (VA.getLocInfo()) { 1950 case CCValAssign::Full: break; 1951 case CCValAssign::SExt: { 1952 MVT DestVT = VA.getLocVT(); 1953 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false); 1954 assert(Arg != 0 && "Failed to emit a sext"); 1955 ArgVT = DestVT; 1956 break; 1957 } 1958 case CCValAssign::AExt: 1959 // Intentional fall-through. Handle AExt and ZExt. 1960 case CCValAssign::ZExt: { 1961 MVT DestVT = VA.getLocVT(); 1962 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true); 1963 assert(Arg != 0 && "Failed to emit a zext"); 1964 ArgVT = DestVT; 1965 break; 1966 } 1967 case CCValAssign::BCvt: { 1968 unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg, 1969 /*TODO: Kill=*/false); 1970 assert(BC != 0 && "Failed to emit a bitcast!"); 1971 Arg = BC; 1972 ArgVT = VA.getLocVT(); 1973 break; 1974 } 1975 default: llvm_unreachable("Unknown arg promotion!"); 1976 } 1977 1978 // Now copy/store arg to correct locations. 1979 if (VA.isRegLoc() && !VA.needsCustom()) { 1980 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1981 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg); 1982 RegArgs.push_back(VA.getLocReg()); 1983 } else if (VA.needsCustom()) { 1984 // TODO: We need custom lowering for vector (v2f64) args. 1985 assert(VA.getLocVT() == MVT::f64 && 1986 "Custom lowering for v2f64 args not available"); 1987 1988 // FIXME: ArgLocs[++i] may extend beyond ArgLocs.size() 1989 CCValAssign &NextVA = ArgLocs[++i]; 1990 1991 assert(VA.isRegLoc() && NextVA.isRegLoc() && 1992 "We only handle register args!"); 1993 1994 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 1995 TII.get(ARM::VMOVRRD), VA.getLocReg()) 1996 .addReg(NextVA.getLocReg(), RegState::Define) 1997 .addReg(Arg)); 1998 RegArgs.push_back(VA.getLocReg()); 1999 RegArgs.push_back(NextVA.getLocReg()); 2000 } else { 2001 assert(VA.isMemLoc()); 2002 // Need to store on the stack. 2003 2004 // Don't emit stores for undef values. 2005 if (isa<UndefValue>(ArgVal)) 2006 continue; 2007 2008 Address Addr; 2009 Addr.BaseType = Address::RegBase; 2010 Addr.Base.Reg = ARM::SP; 2011 Addr.Offset = VA.getLocMemOffset(); 2012 2013 bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet; 2014 assert(EmitRet && "Could not emit a store for argument!"); 2015 } 2016 } 2017 2018 return true; 2019 } 2020 2021 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs, 2022 const Instruction *I, CallingConv::ID CC, 2023 unsigned &NumBytes, bool isVarArg) { 2024 // Issue CALLSEQ_END 2025 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode(); 2026 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 2027 TII.get(AdjStackUp)) 2028 .addImm(NumBytes).addImm(0)); 2029 2030 // Now the return value. 2031 if (RetVT != MVT::isVoid) { 2032 SmallVector<CCValAssign, 16> RVLocs; 2033 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context); 2034 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg)); 2035 2036 // Copy all of the result registers out of their specified physreg. 2037 if (RVLocs.size() == 2 && RetVT == MVT::f64) { 2038 // For this move we copy into two registers and then move into the 2039 // double fp reg we want. 2040 MVT DestVT = RVLocs[0].getValVT(); 2041 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); 2042 Register ResultReg = createResultReg(DstRC); 2043 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 2044 TII.get(ARM::VMOVDRR), ResultReg) 2045 .addReg(RVLocs[0].getLocReg()) 2046 .addReg(RVLocs[1].getLocReg())); 2047 2048 UsedRegs.push_back(RVLocs[0].getLocReg()); 2049 UsedRegs.push_back(RVLocs[1].getLocReg()); 2050 2051 // Finally update the result. 2052 updateValueMap(I, ResultReg); 2053 } else { 2054 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); 2055 MVT CopyVT = RVLocs[0].getValVT(); 2056 2057 // Special handling for extended integers. 2058 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16) 2059 CopyVT = MVT::i32; 2060 2061 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); 2062 2063 Register ResultReg = createResultReg(DstRC); 2064 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 2065 TII.get(TargetOpcode::COPY), 2066 ResultReg).addReg(RVLocs[0].getLocReg()); 2067 UsedRegs.push_back(RVLocs[0].getLocReg()); 2068 2069 // Finally update the result. 2070 updateValueMap(I, ResultReg); 2071 } 2072 } 2073 2074 return true; 2075 } 2076 2077 bool ARMFastISel::SelectRet(const Instruction *I) { 2078 const ReturnInst *Ret = cast<ReturnInst>(I); 2079 const Function &F = *I->getParent()->getParent(); 2080 const bool IsCmseNSEntry = F.hasFnAttribute("cmse_nonsecure_entry"); 2081 2082 if (!FuncInfo.CanLowerReturn) 2083 return false; 2084 2085 if (TLI.supportSwiftError() && 2086 F.getAttributes().hasAttrSomewhere(Attribute::SwiftError)) 2087 return false; 2088 2089 if (TLI.supportSplitCSR(FuncInfo.MF)) 2090 return false; 2091 2092 // Build a list of return value registers. 2093 SmallVector<unsigned, 4> RetRegs; 2094 2095 CallingConv::ID CC = F.getCallingConv(); 2096 if (Ret->getNumOperands() > 0) { 2097 SmallVector<ISD::OutputArg, 4> Outs; 2098 GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL); 2099 2100 // Analyze operands of the call, assigning locations to each operand. 2101 SmallVector<CCValAssign, 16> ValLocs; 2102 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext()); 2103 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */, 2104 F.isVarArg())); 2105 2106 const Value *RV = Ret->getOperand(0); 2107 unsigned Reg = getRegForValue(RV); 2108 if (Reg == 0) 2109 return false; 2110 2111 // Only handle a single return value for now. 2112 if (ValLocs.size() != 1) 2113 return false; 2114 2115 CCValAssign &VA = ValLocs[0]; 2116 2117 // Don't bother handling odd stuff for now. 2118 if (VA.getLocInfo() != CCValAssign::Full) 2119 return false; 2120 // Only handle register returns for now. 2121 if (!VA.isRegLoc()) 2122 return false; 2123 2124 unsigned SrcReg = Reg + VA.getValNo(); 2125 EVT RVEVT = TLI.getValueType(DL, RV->getType()); 2126 if (!RVEVT.isSimple()) return false; 2127 MVT RVVT = RVEVT.getSimpleVT(); 2128 MVT DestVT = VA.getValVT(); 2129 // Special handling for extended integers. 2130 if (RVVT != DestVT) { 2131 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16) 2132 return false; 2133 2134 assert(DestVT == MVT::i32 && "ARM should always ext to i32"); 2135 2136 // Perform extension if flagged as either zext or sext. Otherwise, do 2137 // nothing. 2138 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { 2139 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt()); 2140 if (SrcReg == 0) return false; 2141 } 2142 } 2143 2144 // Make the copy. 2145 Register DstReg = VA.getLocReg(); 2146 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg); 2147 // Avoid a cross-class copy. This is very unlikely. 2148 if (!SrcRC->contains(DstReg)) 2149 return false; 2150 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 2151 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg); 2152 2153 // Add register to return instruction. 2154 RetRegs.push_back(VA.getLocReg()); 2155 } 2156 2157 unsigned RetOpc; 2158 if (IsCmseNSEntry) 2159 if (isThumb2) 2160 RetOpc = ARM::tBXNS_RET; 2161 else 2162 llvm_unreachable("CMSE not valid for non-Thumb targets"); 2163 else 2164 RetOpc = Subtarget->getReturnOpcode(); 2165 2166 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 2167 TII.get(RetOpc)); 2168 AddOptionalDefs(MIB); 2169 for (unsigned R : RetRegs) 2170 MIB.addReg(R, RegState::Implicit); 2171 return true; 2172 } 2173 2174 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) { 2175 if (UseReg) 2176 return isThumb2 ? ARM::tBLXr : ARM::BLX; 2177 else 2178 return isThumb2 ? ARM::tBL : ARM::BL; 2179 } 2180 2181 unsigned ARMFastISel::getLibcallReg(const Twine &Name) { 2182 // Manually compute the global's type to avoid building it when unnecessary. 2183 Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0); 2184 EVT LCREVT = TLI.getValueType(DL, GVTy); 2185 if (!LCREVT.isSimple()) return 0; 2186 2187 GlobalValue *GV = new GlobalVariable(M, Type::getInt32Ty(*Context), false, 2188 GlobalValue::ExternalLinkage, nullptr, 2189 Name); 2190 assert(GV->getType() == GVTy && "We miscomputed the type for the global!"); 2191 return ARMMaterializeGV(GV, LCREVT.getSimpleVT()); 2192 } 2193 2194 // A quick function that will emit a call for a named libcall in F with the 2195 // vector of passed arguments for the Instruction in I. We can assume that we 2196 // can emit a call for any libcall we can produce. This is an abridged version 2197 // of the full call infrastructure since we won't need to worry about things 2198 // like computed function pointers or strange arguments at call sites. 2199 // TODO: Try to unify this and the normal call bits for ARM, then try to unify 2200 // with X86. 2201 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) { 2202 CallingConv::ID CC = TLI.getLibcallCallingConv(Call); 2203 2204 // Handle *simple* calls for now. 2205 Type *RetTy = I->getType(); 2206 MVT RetVT; 2207 if (RetTy->isVoidTy()) 2208 RetVT = MVT::isVoid; 2209 else if (!isTypeLegal(RetTy, RetVT)) 2210 return false; 2211 2212 // Can't handle non-double multi-reg retvals. 2213 if (RetVT != MVT::isVoid && RetVT != MVT::i32) { 2214 SmallVector<CCValAssign, 16> RVLocs; 2215 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); 2216 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false)); 2217 if (RVLocs.size() >= 2 && RetVT != MVT::f64) 2218 return false; 2219 } 2220 2221 // Set up the argument vectors. 2222 SmallVector<Value*, 8> Args; 2223 SmallVector<Register, 8> ArgRegs; 2224 SmallVector<MVT, 8> ArgVTs; 2225 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 2226 Args.reserve(I->getNumOperands()); 2227 ArgRegs.reserve(I->getNumOperands()); 2228 ArgVTs.reserve(I->getNumOperands()); 2229 ArgFlags.reserve(I->getNumOperands()); 2230 for (Value *Op : I->operands()) { 2231 unsigned Arg = getRegForValue(Op); 2232 if (Arg == 0) return false; 2233 2234 Type *ArgTy = Op->getType(); 2235 MVT ArgVT; 2236 if (!isTypeLegal(ArgTy, ArgVT)) return false; 2237 2238 ISD::ArgFlagsTy Flags; 2239 Flags.setOrigAlign(DL.getABITypeAlign(ArgTy)); 2240 2241 Args.push_back(Op); 2242 ArgRegs.push_back(Arg); 2243 ArgVTs.push_back(ArgVT); 2244 ArgFlags.push_back(Flags); 2245 } 2246 2247 // Handle the arguments now that we've gotten them. 2248 SmallVector<Register, 4> RegArgs; 2249 unsigned NumBytes; 2250 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, 2251 RegArgs, CC, NumBytes, false)) 2252 return false; 2253 2254 Register CalleeReg; 2255 if (Subtarget->genLongCalls()) { 2256 CalleeReg = getLibcallReg(TLI.getLibcallName(Call)); 2257 if (CalleeReg == 0) return false; 2258 } 2259 2260 // Issue the call. 2261 unsigned CallOpc = ARMSelectCallOp(Subtarget->genLongCalls()); 2262 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 2263 DbgLoc, TII.get(CallOpc)); 2264 // BL / BLX don't take a predicate, but tBL / tBLX do. 2265 if (isThumb2) 2266 MIB.add(predOps(ARMCC::AL)); 2267 if (Subtarget->genLongCalls()) 2268 MIB.addReg(CalleeReg); 2269 else 2270 MIB.addExternalSymbol(TLI.getLibcallName(Call)); 2271 2272 // Add implicit physical register uses to the call. 2273 for (Register R : RegArgs) 2274 MIB.addReg(R, RegState::Implicit); 2275 2276 // Add a register mask with the call-preserved registers. 2277 // Proper defs for return values will be added by setPhysRegsDeadExcept(). 2278 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); 2279 2280 // Finish off the call including any return values. 2281 SmallVector<Register, 4> UsedRegs; 2282 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false; 2283 2284 // Set all unused physreg defs as dead. 2285 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); 2286 2287 return true; 2288 } 2289 2290 bool ARMFastISel::SelectCall(const Instruction *I, 2291 const char *IntrMemName = nullptr) { 2292 const CallInst *CI = cast<CallInst>(I); 2293 const Value *Callee = CI->getCalledOperand(); 2294 2295 // Can't handle inline asm. 2296 if (isa<InlineAsm>(Callee)) return false; 2297 2298 // Allow SelectionDAG isel to handle tail calls. 2299 if (CI->isTailCall()) return false; 2300 2301 // Check the calling convention. 2302 CallingConv::ID CC = CI->getCallingConv(); 2303 2304 // TODO: Avoid some calling conventions? 2305 2306 FunctionType *FTy = CI->getFunctionType(); 2307 bool isVarArg = FTy->isVarArg(); 2308 2309 // Handle *simple* calls for now. 2310 Type *RetTy = I->getType(); 2311 MVT RetVT; 2312 if (RetTy->isVoidTy()) 2313 RetVT = MVT::isVoid; 2314 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 && 2315 RetVT != MVT::i8 && RetVT != MVT::i1) 2316 return false; 2317 2318 // Can't handle non-double multi-reg retvals. 2319 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 && 2320 RetVT != MVT::i16 && RetVT != MVT::i32) { 2321 SmallVector<CCValAssign, 16> RVLocs; 2322 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context); 2323 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg)); 2324 if (RVLocs.size() >= 2 && RetVT != MVT::f64) 2325 return false; 2326 } 2327 2328 // Set up the argument vectors. 2329 SmallVector<Value*, 8> Args; 2330 SmallVector<Register, 8> ArgRegs; 2331 SmallVector<MVT, 8> ArgVTs; 2332 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 2333 unsigned arg_size = CI->arg_size(); 2334 Args.reserve(arg_size); 2335 ArgRegs.reserve(arg_size); 2336 ArgVTs.reserve(arg_size); 2337 ArgFlags.reserve(arg_size); 2338 for (auto ArgI = CI->arg_begin(), ArgE = CI->arg_end(); ArgI != ArgE; ++ArgI) { 2339 // If we're lowering a memory intrinsic instead of a regular call, skip the 2340 // last argument, which shouldn't be passed to the underlying function. 2341 if (IntrMemName && ArgE - ArgI <= 1) 2342 break; 2343 2344 ISD::ArgFlagsTy Flags; 2345 unsigned ArgIdx = ArgI - CI->arg_begin(); 2346 if (CI->paramHasAttr(ArgIdx, Attribute::SExt)) 2347 Flags.setSExt(); 2348 if (CI->paramHasAttr(ArgIdx, Attribute::ZExt)) 2349 Flags.setZExt(); 2350 2351 // FIXME: Only handle *easy* calls for now. 2352 if (CI->paramHasAttr(ArgIdx, Attribute::InReg) || 2353 CI->paramHasAttr(ArgIdx, Attribute::StructRet) || 2354 CI->paramHasAttr(ArgIdx, Attribute::SwiftSelf) || 2355 CI->paramHasAttr(ArgIdx, Attribute::SwiftError) || 2356 CI->paramHasAttr(ArgIdx, Attribute::Nest) || 2357 CI->paramHasAttr(ArgIdx, Attribute::ByVal)) 2358 return false; 2359 2360 Type *ArgTy = (*ArgI)->getType(); 2361 MVT ArgVT; 2362 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 && 2363 ArgVT != MVT::i1) 2364 return false; 2365 2366 Register Arg = getRegForValue(*ArgI); 2367 if (!Arg.isValid()) 2368 return false; 2369 2370 Flags.setOrigAlign(DL.getABITypeAlign(ArgTy)); 2371 2372 Args.push_back(*ArgI); 2373 ArgRegs.push_back(Arg); 2374 ArgVTs.push_back(ArgVT); 2375 ArgFlags.push_back(Flags); 2376 } 2377 2378 // Handle the arguments now that we've gotten them. 2379 SmallVector<Register, 4> RegArgs; 2380 unsigned NumBytes; 2381 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, 2382 RegArgs, CC, NumBytes, isVarArg)) 2383 return false; 2384 2385 bool UseReg = false; 2386 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee); 2387 if (!GV || Subtarget->genLongCalls()) UseReg = true; 2388 2389 Register CalleeReg; 2390 if (UseReg) { 2391 if (IntrMemName) 2392 CalleeReg = getLibcallReg(IntrMemName); 2393 else 2394 CalleeReg = getRegForValue(Callee); 2395 2396 if (CalleeReg == 0) return false; 2397 } 2398 2399 // Issue the call. 2400 unsigned CallOpc = ARMSelectCallOp(UseReg); 2401 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 2402 DbgLoc, TII.get(CallOpc)); 2403 2404 // ARM calls don't take a predicate, but tBL / tBLX do. 2405 if(isThumb2) 2406 MIB.add(predOps(ARMCC::AL)); 2407 if (UseReg) 2408 MIB.addReg(CalleeReg); 2409 else if (!IntrMemName) 2410 MIB.addGlobalAddress(GV, 0, 0); 2411 else 2412 MIB.addExternalSymbol(IntrMemName, 0); 2413 2414 // Add implicit physical register uses to the call. 2415 for (Register R : RegArgs) 2416 MIB.addReg(R, RegState::Implicit); 2417 2418 // Add a register mask with the call-preserved registers. 2419 // Proper defs for return values will be added by setPhysRegsDeadExcept(). 2420 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); 2421 2422 // Finish off the call including any return values. 2423 SmallVector<Register, 4> UsedRegs; 2424 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg)) 2425 return false; 2426 2427 // Set all unused physreg defs as dead. 2428 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); 2429 2430 return true; 2431 } 2432 2433 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) { 2434 return Len <= 16; 2435 } 2436 2437 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src, 2438 uint64_t Len, unsigned Alignment) { 2439 // Make sure we don't bloat code by inlining very large memcpy's. 2440 if (!ARMIsMemCpySmall(Len)) 2441 return false; 2442 2443 while (Len) { 2444 MVT VT; 2445 if (!Alignment || Alignment >= 4) { 2446 if (Len >= 4) 2447 VT = MVT::i32; 2448 else if (Len >= 2) 2449 VT = MVT::i16; 2450 else { 2451 assert(Len == 1 && "Expected a length of 1!"); 2452 VT = MVT::i8; 2453 } 2454 } else { 2455 // Bound based on alignment. 2456 if (Len >= 2 && Alignment == 2) 2457 VT = MVT::i16; 2458 else { 2459 VT = MVT::i8; 2460 } 2461 } 2462 2463 bool RV; 2464 Register ResultReg; 2465 RV = ARMEmitLoad(VT, ResultReg, Src); 2466 assert(RV && "Should be able to handle this load."); 2467 RV = ARMEmitStore(VT, ResultReg, Dest); 2468 assert(RV && "Should be able to handle this store."); 2469 (void)RV; 2470 2471 unsigned Size = VT.getSizeInBits()/8; 2472 Len -= Size; 2473 Dest.Offset += Size; 2474 Src.Offset += Size; 2475 } 2476 2477 return true; 2478 } 2479 2480 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) { 2481 // FIXME: Handle more intrinsics. 2482 switch (I.getIntrinsicID()) { 2483 default: return false; 2484 case Intrinsic::frameaddress: { 2485 MachineFrameInfo &MFI = FuncInfo.MF->getFrameInfo(); 2486 MFI.setFrameAddressIsTaken(true); 2487 2488 unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12; 2489 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass 2490 : &ARM::GPRRegClass; 2491 2492 const ARMBaseRegisterInfo *RegInfo = 2493 static_cast<const ARMBaseRegisterInfo *>(Subtarget->getRegisterInfo()); 2494 Register FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF)); 2495 unsigned SrcReg = FramePtr; 2496 2497 // Recursively load frame address 2498 // ldr r0 [fp] 2499 // ldr r0 [r0] 2500 // ldr r0 [r0] 2501 // ... 2502 unsigned DestReg; 2503 unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue(); 2504 while (Depth--) { 2505 DestReg = createResultReg(RC); 2506 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 2507 TII.get(LdrOpc), DestReg) 2508 .addReg(SrcReg).addImm(0)); 2509 SrcReg = DestReg; 2510 } 2511 updateValueMap(&I, SrcReg); 2512 return true; 2513 } 2514 case Intrinsic::memcpy: 2515 case Intrinsic::memmove: { 2516 const MemTransferInst &MTI = cast<MemTransferInst>(I); 2517 // Don't handle volatile. 2518 if (MTI.isVolatile()) 2519 return false; 2520 2521 // Disable inlining for memmove before calls to ComputeAddress. Otherwise, 2522 // we would emit dead code because we don't currently handle memmoves. 2523 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy); 2524 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) { 2525 // Small memcpy's are common enough that we want to do them without a call 2526 // if possible. 2527 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue(); 2528 if (ARMIsMemCpySmall(Len)) { 2529 Address Dest, Src; 2530 if (!ARMComputeAddress(MTI.getRawDest(), Dest) || 2531 !ARMComputeAddress(MTI.getRawSource(), Src)) 2532 return false; 2533 unsigned Alignment = MinAlign(MTI.getDestAlignment(), 2534 MTI.getSourceAlignment()); 2535 if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment)) 2536 return true; 2537 } 2538 } 2539 2540 if (!MTI.getLength()->getType()->isIntegerTy(32)) 2541 return false; 2542 2543 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255) 2544 return false; 2545 2546 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove"; 2547 return SelectCall(&I, IntrMemName); 2548 } 2549 case Intrinsic::memset: { 2550 const MemSetInst &MSI = cast<MemSetInst>(I); 2551 // Don't handle volatile. 2552 if (MSI.isVolatile()) 2553 return false; 2554 2555 if (!MSI.getLength()->getType()->isIntegerTy(32)) 2556 return false; 2557 2558 if (MSI.getDestAddressSpace() > 255) 2559 return false; 2560 2561 return SelectCall(&I, "memset"); 2562 } 2563 case Intrinsic::trap: { 2564 unsigned Opcode; 2565 if (Subtarget->isThumb()) 2566 Opcode = ARM::tTRAP; 2567 else 2568 Opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP; 2569 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode)); 2570 return true; 2571 } 2572 } 2573 } 2574 2575 bool ARMFastISel::SelectTrunc(const Instruction *I) { 2576 // The high bits for a type smaller than the register size are assumed to be 2577 // undefined. 2578 Value *Op = I->getOperand(0); 2579 2580 EVT SrcVT, DestVT; 2581 SrcVT = TLI.getValueType(DL, Op->getType(), true); 2582 DestVT = TLI.getValueType(DL, I->getType(), true); 2583 2584 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) 2585 return false; 2586 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) 2587 return false; 2588 2589 unsigned SrcReg = getRegForValue(Op); 2590 if (!SrcReg) return false; 2591 2592 // Because the high bits are undefined, a truncate doesn't generate 2593 // any code. 2594 updateValueMap(I, SrcReg); 2595 return true; 2596 } 2597 2598 unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, 2599 bool isZExt) { 2600 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8) 2601 return 0; 2602 if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1) 2603 return 0; 2604 2605 // Table of which combinations can be emitted as a single instruction, 2606 // and which will require two. 2607 static const uint8_t isSingleInstrTbl[3][2][2][2] = { 2608 // ARM Thumb 2609 // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops 2610 // ext: s z s z s z s z 2611 /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } }, 2612 /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }, 2613 /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } } 2614 }; 2615 2616 // Target registers for: 2617 // - For ARM can never be PC. 2618 // - For 16-bit Thumb are restricted to lower 8 registers. 2619 // - For 32-bit Thumb are restricted to non-SP and non-PC. 2620 static const TargetRegisterClass *RCTbl[2][2] = { 2621 // Instructions: Two Single 2622 /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass }, 2623 /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass } 2624 }; 2625 2626 // Table governing the instruction(s) to be emitted. 2627 static const struct InstructionTable { 2628 uint32_t Opc : 16; 2629 uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0. 2630 uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi. 2631 uint32_t Imm : 8; // All instructions have either a shift or a mask. 2632 } IT[2][2][3][2] = { 2633 { // Two instructions (first is left shift, second is in this table). 2634 { // ARM Opc S Shift Imm 2635 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 }, 2636 /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } }, 2637 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 }, 2638 /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } }, 2639 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 }, 2640 /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } } 2641 }, 2642 { // Thumb Opc S Shift Imm 2643 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 }, 2644 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } }, 2645 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 }, 2646 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } }, 2647 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 }, 2648 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } } 2649 } 2650 }, 2651 { // Single instruction. 2652 { // ARM Opc S Shift Imm 2653 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, 2654 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } }, 2655 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 }, 2656 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } }, 2657 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, 2658 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } } 2659 }, 2660 { // Thumb Opc S Shift Imm 2661 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, 2662 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } }, 2663 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 }, 2664 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } }, 2665 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 }, 2666 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } } 2667 } 2668 } 2669 }; 2670 2671 unsigned SrcBits = SrcVT.getSizeInBits(); 2672 unsigned DestBits = DestVT.getSizeInBits(); 2673 (void) DestBits; 2674 assert((SrcBits < DestBits) && "can only extend to larger types"); 2675 assert((DestBits == 32 || DestBits == 16 || DestBits == 8) && 2676 "other sizes unimplemented"); 2677 assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) && 2678 "other sizes unimplemented"); 2679 2680 bool hasV6Ops = Subtarget->hasV6Ops(); 2681 unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2} 2682 assert((Bitness < 3) && "sanity-check table bounds"); 2683 2684 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt]; 2685 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr]; 2686 const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt]; 2687 unsigned Opc = ITP->Opc; 2688 assert(ARM::KILL != Opc && "Invalid table entry"); 2689 unsigned hasS = ITP->hasS; 2690 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift; 2691 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) && 2692 "only MOVsi has shift operand addressing mode"); 2693 unsigned Imm = ITP->Imm; 2694 2695 // 16-bit Thumb instructions always set CPSR (unless they're in an IT block). 2696 bool setsCPSR = &ARM::tGPRRegClass == RC; 2697 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi; 2698 unsigned ResultReg; 2699 // MOVsi encodes shift and immediate in shift operand addressing mode. 2700 // The following condition has the same value when emitting two 2701 // instruction sequences: both are shifts. 2702 bool ImmIsSO = (Shift != ARM_AM::no_shift); 2703 2704 // Either one or two instructions are emitted. 2705 // They're always of the form: 2706 // dst = in OP imm 2707 // CPSR is set only by 16-bit Thumb instructions. 2708 // Predicate, if any, is AL. 2709 // S bit, if available, is always 0. 2710 // When two are emitted the first's result will feed as the second's input, 2711 // that value is then dead. 2712 unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2; 2713 for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) { 2714 ResultReg = createResultReg(RC); 2715 bool isLsl = (0 == Instr) && !isSingleInstr; 2716 unsigned Opcode = isLsl ? LSLOpc : Opc; 2717 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift; 2718 unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm; 2719 bool isKill = 1 == Instr; 2720 MachineInstrBuilder MIB = BuildMI( 2721 *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg); 2722 if (setsCPSR) 2723 MIB.addReg(ARM::CPSR, RegState::Define); 2724 SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR); 2725 MIB.addReg(SrcReg, isKill * RegState::Kill) 2726 .addImm(ImmEnc) 2727 .add(predOps(ARMCC::AL)); 2728 if (hasS) 2729 MIB.add(condCodeOp()); 2730 // Second instruction consumes the first's result. 2731 SrcReg = ResultReg; 2732 } 2733 2734 return ResultReg; 2735 } 2736 2737 bool ARMFastISel::SelectIntExt(const Instruction *I) { 2738 // On ARM, in general, integer casts don't involve legal types; this code 2739 // handles promotable integers. 2740 Type *DestTy = I->getType(); 2741 Value *Src = I->getOperand(0); 2742 Type *SrcTy = Src->getType(); 2743 2744 bool isZExt = isa<ZExtInst>(I); 2745 unsigned SrcReg = getRegForValue(Src); 2746 if (!SrcReg) return false; 2747 2748 EVT SrcEVT, DestEVT; 2749 SrcEVT = TLI.getValueType(DL, SrcTy, true); 2750 DestEVT = TLI.getValueType(DL, DestTy, true); 2751 if (!SrcEVT.isSimple()) return false; 2752 if (!DestEVT.isSimple()) return false; 2753 2754 MVT SrcVT = SrcEVT.getSimpleVT(); 2755 MVT DestVT = DestEVT.getSimpleVT(); 2756 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt); 2757 if (ResultReg == 0) return false; 2758 updateValueMap(I, ResultReg); 2759 return true; 2760 } 2761 2762 bool ARMFastISel::SelectShift(const Instruction *I, 2763 ARM_AM::ShiftOpc ShiftTy) { 2764 // We handle thumb2 mode by target independent selector 2765 // or SelectionDAG ISel. 2766 if (isThumb2) 2767 return false; 2768 2769 // Only handle i32 now. 2770 EVT DestVT = TLI.getValueType(DL, I->getType(), true); 2771 if (DestVT != MVT::i32) 2772 return false; 2773 2774 unsigned Opc = ARM::MOVsr; 2775 unsigned ShiftImm; 2776 Value *Src2Value = I->getOperand(1); 2777 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) { 2778 ShiftImm = CI->getZExtValue(); 2779 2780 // Fall back to selection DAG isel if the shift amount 2781 // is zero or greater than the width of the value type. 2782 if (ShiftImm == 0 || ShiftImm >=32) 2783 return false; 2784 2785 Opc = ARM::MOVsi; 2786 } 2787 2788 Value *Src1Value = I->getOperand(0); 2789 unsigned Reg1 = getRegForValue(Src1Value); 2790 if (Reg1 == 0) return false; 2791 2792 unsigned Reg2 = 0; 2793 if (Opc == ARM::MOVsr) { 2794 Reg2 = getRegForValue(Src2Value); 2795 if (Reg2 == 0) return false; 2796 } 2797 2798 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); 2799 if(ResultReg == 0) return false; 2800 2801 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 2802 TII.get(Opc), ResultReg) 2803 .addReg(Reg1); 2804 2805 if (Opc == ARM::MOVsi) 2806 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); 2807 else if (Opc == ARM::MOVsr) { 2808 MIB.addReg(Reg2); 2809 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0)); 2810 } 2811 2812 AddOptionalDefs(MIB); 2813 updateValueMap(I, ResultReg); 2814 return true; 2815 } 2816 2817 // TODO: SoftFP support. 2818 bool ARMFastISel::fastSelectInstruction(const Instruction *I) { 2819 switch (I->getOpcode()) { 2820 case Instruction::Load: 2821 return SelectLoad(I); 2822 case Instruction::Store: 2823 return SelectStore(I); 2824 case Instruction::Br: 2825 return SelectBranch(I); 2826 case Instruction::IndirectBr: 2827 return SelectIndirectBr(I); 2828 case Instruction::ICmp: 2829 case Instruction::FCmp: 2830 return SelectCmp(I); 2831 case Instruction::FPExt: 2832 return SelectFPExt(I); 2833 case Instruction::FPTrunc: 2834 return SelectFPTrunc(I); 2835 case Instruction::SIToFP: 2836 return SelectIToFP(I, /*isSigned*/ true); 2837 case Instruction::UIToFP: 2838 return SelectIToFP(I, /*isSigned*/ false); 2839 case Instruction::FPToSI: 2840 return SelectFPToI(I, /*isSigned*/ true); 2841 case Instruction::FPToUI: 2842 return SelectFPToI(I, /*isSigned*/ false); 2843 case Instruction::Add: 2844 return SelectBinaryIntOp(I, ISD::ADD); 2845 case Instruction::Or: 2846 return SelectBinaryIntOp(I, ISD::OR); 2847 case Instruction::Sub: 2848 return SelectBinaryIntOp(I, ISD::SUB); 2849 case Instruction::FAdd: 2850 return SelectBinaryFPOp(I, ISD::FADD); 2851 case Instruction::FSub: 2852 return SelectBinaryFPOp(I, ISD::FSUB); 2853 case Instruction::FMul: 2854 return SelectBinaryFPOp(I, ISD::FMUL); 2855 case Instruction::SDiv: 2856 return SelectDiv(I, /*isSigned*/ true); 2857 case Instruction::UDiv: 2858 return SelectDiv(I, /*isSigned*/ false); 2859 case Instruction::SRem: 2860 return SelectRem(I, /*isSigned*/ true); 2861 case Instruction::URem: 2862 return SelectRem(I, /*isSigned*/ false); 2863 case Instruction::Call: 2864 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 2865 return SelectIntrinsicCall(*II); 2866 return SelectCall(I); 2867 case Instruction::Select: 2868 return SelectSelect(I); 2869 case Instruction::Ret: 2870 return SelectRet(I); 2871 case Instruction::Trunc: 2872 return SelectTrunc(I); 2873 case Instruction::ZExt: 2874 case Instruction::SExt: 2875 return SelectIntExt(I); 2876 case Instruction::Shl: 2877 return SelectShift(I, ARM_AM::lsl); 2878 case Instruction::LShr: 2879 return SelectShift(I, ARM_AM::lsr); 2880 case Instruction::AShr: 2881 return SelectShift(I, ARM_AM::asr); 2882 default: break; 2883 } 2884 return false; 2885 } 2886 2887 // This table describes sign- and zero-extend instructions which can be 2888 // folded into a preceding load. All of these extends have an immediate 2889 // (sometimes a mask and sometimes a shift) that's applied after 2890 // extension. 2891 static const struct FoldableLoadExtendsStruct { 2892 uint16_t Opc[2]; // ARM, Thumb. 2893 uint8_t ExpectedImm; 2894 uint8_t isZExt : 1; 2895 uint8_t ExpectedVT : 7; 2896 } FoldableLoadExtends[] = { 2897 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 }, 2898 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 }, 2899 { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 }, 2900 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 }, 2901 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 } 2902 }; 2903 2904 /// The specified machine instr operand is a vreg, and that 2905 /// vreg is being provided by the specified load instruction. If possible, 2906 /// try to fold the load as an operand to the instruction, returning true if 2907 /// successful. 2908 bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, 2909 const LoadInst *LI) { 2910 // Verify we have a legal type before going any further. 2911 MVT VT; 2912 if (!isLoadTypeLegal(LI->getType(), VT)) 2913 return false; 2914 2915 // Combine load followed by zero- or sign-extend. 2916 // ldrb r1, [r0] ldrb r1, [r0] 2917 // uxtb r2, r1 => 2918 // mov r3, r2 mov r3, r1 2919 if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm()) 2920 return false; 2921 const uint64_t Imm = MI->getOperand(2).getImm(); 2922 2923 bool Found = false; 2924 bool isZExt; 2925 for (const FoldableLoadExtendsStruct &FLE : FoldableLoadExtends) { 2926 if (FLE.Opc[isThumb2] == MI->getOpcode() && 2927 (uint64_t)FLE.ExpectedImm == Imm && 2928 MVT((MVT::SimpleValueType)FLE.ExpectedVT) == VT) { 2929 Found = true; 2930 isZExt = FLE.isZExt; 2931 } 2932 } 2933 if (!Found) return false; 2934 2935 // See if we can handle this address. 2936 Address Addr; 2937 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false; 2938 2939 Register ResultReg = MI->getOperand(0).getReg(); 2940 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false)) 2941 return false; 2942 MachineBasicBlock::iterator I(MI); 2943 removeDeadCode(I, std::next(I)); 2944 return true; 2945 } 2946 2947 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV, MVT VT) { 2948 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV); 2949 2950 LLVMContext *Context = &MF->getFunction().getContext(); 2951 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2952 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 2953 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create( 2954 GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj, 2955 UseGOT_PREL ? ARMCP::GOT_PREL : ARMCP::no_modifier, 2956 /*AddCurrentAddress=*/UseGOT_PREL); 2957 2958 Align ConstAlign = 2959 MF->getDataLayout().getPrefTypeAlign(Type::getInt32PtrTy(*Context)); 2960 unsigned Idx = MF->getConstantPool()->getConstantPoolIndex(CPV, ConstAlign); 2961 MachineMemOperand *CPMMO = 2962 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF), 2963 MachineMemOperand::MOLoad, 4, Align(4)); 2964 2965 Register TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass); 2966 unsigned Opc = isThumb2 ? ARM::t2LDRpci : ARM::LDRcp; 2967 MachineInstrBuilder MIB = 2968 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), TempReg) 2969 .addConstantPoolIndex(Idx) 2970 .addMemOperand(CPMMO); 2971 if (Opc == ARM::LDRcp) 2972 MIB.addImm(0); 2973 MIB.add(predOps(ARMCC::AL)); 2974 2975 // Fix the address by adding pc. 2976 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 2977 Opc = Subtarget->isThumb() ? ARM::tPICADD : UseGOT_PREL ? ARM::PICLDR 2978 : ARM::PICADD; 2979 DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0); 2980 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg) 2981 .addReg(TempReg) 2982 .addImm(ARMPCLabelIndex); 2983 2984 if (!Subtarget->isThumb()) 2985 MIB.add(predOps(ARMCC::AL)); 2986 2987 if (UseGOT_PREL && Subtarget->isThumb()) { 2988 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); 2989 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 2990 TII.get(ARM::t2LDRi12), NewDestReg) 2991 .addReg(DestReg) 2992 .addImm(0); 2993 DestReg = NewDestReg; 2994 AddOptionalDefs(MIB); 2995 } 2996 return DestReg; 2997 } 2998 2999 bool ARMFastISel::fastLowerArguments() { 3000 if (!FuncInfo.CanLowerReturn) 3001 return false; 3002 3003 const Function *F = FuncInfo.Fn; 3004 if (F->isVarArg()) 3005 return false; 3006 3007 CallingConv::ID CC = F->getCallingConv(); 3008 switch (CC) { 3009 default: 3010 return false; 3011 case CallingConv::Fast: 3012 case CallingConv::C: 3013 case CallingConv::ARM_AAPCS_VFP: 3014 case CallingConv::ARM_AAPCS: 3015 case CallingConv::ARM_APCS: 3016 case CallingConv::Swift: 3017 break; 3018 } 3019 3020 // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments 3021 // which are passed in r0 - r3. 3022 for (const Argument &Arg : F->args()) { 3023 if (Arg.getArgNo() >= 4) 3024 return false; 3025 3026 if (Arg.hasAttribute(Attribute::InReg) || 3027 Arg.hasAttribute(Attribute::StructRet) || 3028 Arg.hasAttribute(Attribute::SwiftSelf) || 3029 Arg.hasAttribute(Attribute::SwiftError) || 3030 Arg.hasAttribute(Attribute::ByVal)) 3031 return false; 3032 3033 Type *ArgTy = Arg.getType(); 3034 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) 3035 return false; 3036 3037 EVT ArgVT = TLI.getValueType(DL, ArgTy); 3038 if (!ArgVT.isSimple()) return false; 3039 switch (ArgVT.getSimpleVT().SimpleTy) { 3040 case MVT::i8: 3041 case MVT::i16: 3042 case MVT::i32: 3043 break; 3044 default: 3045 return false; 3046 } 3047 } 3048 3049 static const MCPhysReg GPRArgRegs[] = { 3050 ARM::R0, ARM::R1, ARM::R2, ARM::R3 3051 }; 3052 3053 const TargetRegisterClass *RC = &ARM::rGPRRegClass; 3054 for (const Argument &Arg : F->args()) { 3055 unsigned ArgNo = Arg.getArgNo(); 3056 unsigned SrcReg = GPRArgRegs[ArgNo]; 3057 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC); 3058 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy. 3059 // Without this, EmitLiveInCopies may eliminate the livein if its only 3060 // use is a bitcast (which isn't turned into an instruction). 3061 unsigned ResultReg = createResultReg(RC); 3062 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, 3063 TII.get(TargetOpcode::COPY), 3064 ResultReg).addReg(DstReg, getKillRegState(true)); 3065 updateValueMap(&Arg, ResultReg); 3066 } 3067 3068 return true; 3069 } 3070 3071 namespace llvm { 3072 3073 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo, 3074 const TargetLibraryInfo *libInfo) { 3075 if (funcInfo.MF->getSubtarget<ARMSubtarget>().useFastISel()) 3076 return new ARMFastISel(funcInfo, libInfo); 3077 3078 return nullptr; 3079 } 3080 3081 } // end namespace llvm 3082