1//===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// This describes the calling conventions for ARM architecture. 9//===----------------------------------------------------------------------===// 10 11/// CCIfAlign - Match of the original alignment of the arg 12class CCIfAlign<string Align, CCAction A>: 13 CCIf<!strconcat("ArgFlags.getNonZeroOrigAlign() == ", Align), A>; 14 15//===----------------------------------------------------------------------===// 16// ARM APCS Calling Convention 17//===----------------------------------------------------------------------===// 18let Entry = 1 in 19def CC_ARM_APCS : CallingConv<[ 20 21 // Handles byval parameters. 22 CCIfByVal<CCPassByVal<4, 4>>, 23 24 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 25 26 // Pass SwiftSelf in a callee saved register. 27 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>, 28 29 // A SwiftError is passed in R8. 30 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>, 31 32 // Handle all vector types as either f64 or v2f64. 33 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 34 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 35 36 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack 37 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>, 38 39 CCIfType<[f32], CCBitConvertToType<i32>>, 40 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 41 42 CCIfType<[i32], CCAssignToStack<4, 4>>, 43 CCIfType<[f64], CCAssignToStack<8, 4>>, 44 CCIfType<[v2f64], CCAssignToStack<16, 4>> 45]>; 46 47let Entry = 1 in 48def RetCC_ARM_APCS : CallingConv<[ 49 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 50 CCIfType<[f32], CCBitConvertToType<i32>>, 51 52 // Pass SwiftSelf in a callee saved register. 53 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>, 54 55 // A SwiftError is returned in R8. 56 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>, 57 58 // Handle all vector types as either f64 or v2f64. 59 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 60 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 61 62 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>, 63 64 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 65 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> 66]>; 67 68//===----------------------------------------------------------------------===// 69// ARM APCS Calling Convention for FastCC (when VFP2 or later is available) 70//===----------------------------------------------------------------------===// 71let Entry = 1 in 72def FastCC_ARM_APCS : CallingConv<[ 73 // Handle all vector types as either f64 or v2f64. 74 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 75 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 76 77 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 78 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 79 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 80 S9, S10, S11, S12, S13, S14, S15]>>, 81 82 // CPRCs may be allocated to co-processor registers or the stack - they 83 // may never be allocated to core registers. 84 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>, 85 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>, 86 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>, 87 88 CCDelegateTo<CC_ARM_APCS> 89]>; 90 91let Entry = 1 in 92def RetFastCC_ARM_APCS : CallingConv<[ 93 // Handle all vector types as either f64 or v2f64. 94 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 95 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 96 97 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 98 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 99 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 100 S9, S10, S11, S12, S13, S14, S15]>>, 101 CCDelegateTo<RetCC_ARM_APCS> 102]>; 103 104//===----------------------------------------------------------------------===// 105// ARM APCS Calling Convention for GHC 106//===----------------------------------------------------------------------===// 107 108let Entry = 1 in 109def CC_ARM_APCS_GHC : CallingConv<[ 110 // Handle all vector types as either f64 or v2f64. 111 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 112 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 113 114 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, 115 CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, 116 CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>, 117 118 // Promote i8/i16 arguments to i32. 119 CCIfType<[i8, i16], CCPromoteToType<i32>>, 120 121 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim 122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>> 123]>; 124 125//===----------------------------------------------------------------------===// 126// ARM AAPCS (EABI) Calling Convention, common parts 127//===----------------------------------------------------------------------===// 128 129def CC_ARM_AAPCS_Common : CallingConv<[ 130 131 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 132 133 // i64/f64 is passed in even pairs of GPRs 134 // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register 135 // (and the same is true for f64 if VFP is not enabled) 136 CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>, 137 CCIfType<[i32], CCIf<"ArgFlags.getNonZeroOrigAlign() != Align(8)", 138 CCAssignToReg<[R0, R1, R2, R3]>>>, 139 140 CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, [R0, R1, R2, R3]>>>, 141 CCIfType<[i32], CCAssignToStackWithShadow<4, 4, [R0, R1, R2, R3]>>, 142 CCIfType<[f16, bf16, f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>, 143 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>, 144 CCIfType<[v2f64], CCIfAlign<"16", 145 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>, 146 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>> 147]>; 148 149def RetCC_ARM_AAPCS_Common : CallingConv<[ 150 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 151 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 152 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> 153]>; 154 155//===----------------------------------------------------------------------===// 156// ARM AAPCS (EABI) Calling Convention 157//===----------------------------------------------------------------------===// 158 159let Entry = 1 in 160def CC_ARM_AAPCS : CallingConv<[ 161 // Handles byval parameters. 162 CCIfByVal<CCPassByVal<4, 4>>, 163 164 // The 'nest' parameter, if any, is passed in R12. 165 CCIfNest<CCAssignToReg<[R12]>>, 166 167 // Handle all vector types as either f64 or v2f64. 168 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 169 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 170 171 // Pass SwiftSelf in a callee saved register. 172 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>, 173 174 // A SwiftError is passed in R8. 175 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>, 176 177 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>, 178 CCIfType<[f32], CCBitConvertToType<i32>>, 179 CCIfType<[f16, bf16], CCCustom<"CC_ARM_AAPCS_Custom_f16">>, 180 CCDelegateTo<CC_ARM_AAPCS_Common> 181]>; 182 183let Entry = 1 in 184def RetCC_ARM_AAPCS : CallingConv<[ 185 // Handle all vector types as either f64 or v2f64. 186 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 187 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 188 189 // Pass SwiftSelf in a callee saved register. 190 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>, 191 192 // A SwiftError is returned in R8. 193 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>, 194 195 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>, 196 CCIfType<[f32], CCBitConvertToType<i32>>, 197 CCIfType<[f16, bf16], CCCustom<"CC_ARM_AAPCS_Custom_f16">>, 198 199 CCDelegateTo<RetCC_ARM_AAPCS_Common> 200]>; 201 202//===----------------------------------------------------------------------===// 203// ARM AAPCS-VFP (EABI) Calling Convention 204// Also used for FastCC (when VFP2 or later is available) 205//===----------------------------------------------------------------------===// 206 207let Entry = 1 in 208def CC_ARM_AAPCS_VFP : CallingConv<[ 209 // Handles byval parameters. 210 CCIfByVal<CCPassByVal<4, 4>>, 211 212 // Handle all vector types as either f64 or v2f64. 213 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 214 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 215 216 // Pass SwiftSelf in a callee saved register. 217 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>, 218 219 // A SwiftError is passed in R8. 220 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>, 221 222 // HFAs are passed in a contiguous block of registers, or on the stack 223 CCIfConsecutiveRegs<CCCustom<"CC_ARM_AAPCS_Custom_Aggregate">>, 224 225 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 226 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 227 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 228 S9, S10, S11, S12, S13, S14, S15]>>, 229 CCIfType<[f16, bf16], CCCustom<"CC_ARM_AAPCS_VFP_Custom_f16">>, 230 CCDelegateTo<CC_ARM_AAPCS_Common> 231]>; 232 233let Entry = 1 in 234def RetCC_ARM_AAPCS_VFP : CallingConv<[ 235 // Handle all vector types as either f64 or v2f64. 236 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>, 237 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 238 239 // Pass SwiftSelf in a callee saved register. 240 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>, 241 242 // A SwiftError is returned in R8. 243 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>, 244 245 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 246 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 247 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 248 S9, S10, S11, S12, S13, S14, S15]>>, 249 CCIfType<[f16, bf16], CCCustom<"CC_ARM_AAPCS_VFP_Custom_f16">>, 250 CCDelegateTo<RetCC_ARM_AAPCS_Common> 251]>; 252 253 254// Windows Control Flow Guard checks take a single argument (the target function 255// address) and have no return value. 256let Entry = 1 in 257def CC_ARM_Win32_CFGuard_Check : CallingConv<[ 258 CCIfType<[i32], CCAssignToReg<[R0]>> 259]>; 260 261 262 263//===----------------------------------------------------------------------===// 264// Callee-saved register lists. 265//===----------------------------------------------------------------------===// 266 267def CSR_NoRegs : CalleeSavedRegs<(add)>; 268def CSR_FPRegs : CalleeSavedRegs<(add (sequence "D%u", 0, 31))>; 269 270def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4, 271 (sequence "D%u", 15, 8))>; 272 273// The Windows Control Flow Guard Check function preserves the same registers as 274// AAPCS, and also preserves all floating point registers. 275def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, 276 R6, R5, R4, (sequence "D%u", 15, 0))>; 277 278// R8 is used to pass swifterror, remove it from CSR. 279def CSR_AAPCS_SwiftError : CalleeSavedRegs<(sub CSR_AAPCS, R8)>; 280 281// R10 is used to pass swiftself, remove it from CSR. 282def CSR_AAPCS_SwiftTail : CalleeSavedRegs<(sub CSR_AAPCS, R10)>; 283 284// The order of callee-saved registers needs to match the order we actually push 285// them in FrameLowering, because this order is what's used by 286// PrologEpilogInserter to allocate frame index slots. So when R7 is the frame 287// pointer, we use this ATPCS alternative. 288def CSR_ATPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4, 289 R11, R10, R9, R8, 290 (sequence "D%u", 15, 8))>; 291 292def CSR_Win_SplitFP : CalleeSavedRegs<(add R10, R9, R8, R7, R6, R5, R4, 293 (sequence "D%u", 15, 8), 294 LR, R11)>; 295 296// R8 is used to pass swifterror, remove it from CSR. 297def CSR_ATPCS_SplitPush_SwiftError : CalleeSavedRegs<(sub CSR_ATPCS_SplitPush, 298 R8)>; 299 300// R10 is used to pass swifterror, remove it from CSR. 301def CSR_ATPCS_SplitPush_SwiftTail : CalleeSavedRegs<(sub CSR_ATPCS_SplitPush, 302 R10)>; 303 304// When enforcing an AAPCS compliant frame chain, R11 is used as the frame 305// pointer even for Thumb targets, where split pushes are necessary. 306// This AAPCS alternative makes sure the frame index slots match the push 307// order in that case. 308def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R11, 309 R7, R6, R5, R4, 310 R10, R9, R8, 311 (sequence "D%u", 15, 8))>; 312 313// Constructors and destructors return 'this' in the ARM C++ ABI; since 'this' 314// and the pointer return value are both passed in R0 in these cases, this can 315// be partially modelled by treating R0 as a callee-saved register 316// Only the resulting RegMask is used; the SaveList is ignored 317def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, 318 R5, R4, (sequence "D%u", 15, 8), 319 R0)>; 320 321// iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register. 322// Also save R7-R4 first to match the stack frame fixed spill areas. 323def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>; 324 325// R8 is used to pass swifterror, remove it from CSR. 326def CSR_iOS_SwiftError : CalleeSavedRegs<(sub CSR_iOS, R8)>; 327 328// R10 is used to pass swiftself, remove it from CSR. 329def CSR_iOS_SwiftTail : CalleeSavedRegs<(sub CSR_iOS, R10)>; 330 331def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4, 332 (sub CSR_AAPCS_ThisReturn, R9))>; 333 334def CSR_iOS_TLSCall 335 : CalleeSavedRegs<(add LR, SP, (sub(sequence "R%u", 12, 1), R9, R12), 336 (sequence "D%u", 31, 0))>; 337 338// C++ TLS access function saves all registers except SP. Try to match 339// the order of CSRs in CSR_iOS. 340def CSR_iOS_CXX_TLS : CalleeSavedRegs<(add CSR_iOS, (sequence "R%u", 12, 1), 341 (sequence "D%u", 31, 0))>; 342 343// CSRs that are handled by prologue, epilogue. 344def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>; 345 346// CSRs that are handled explicitly via copies. 347def CSR_iOS_CXX_TLS_ViaCopy : CalleeSavedRegs<(sub CSR_iOS_CXX_TLS, 348 CSR_iOS_CXX_TLS_PE)>; 349 350// The "interrupt" attribute is used to generate code that is acceptable in 351// exception-handlers of various kinds. It makes us use a different return 352// instruction (handled elsewhere) and affects which registers we must return to 353// our "caller" in the same state as we receive them. 354 355// For most interrupts, all registers except SP and LR are shared with 356// user-space. We mark LR to be saved anyway, since this is what the ARM backend 357// generally does rather than tracking its liveness as a normal register. 358def CSR_GenericInt : CalleeSavedRegs<(add LR, (sequence "R%u", 12, 0))>; 359 360// The fast interrupt handlers have more private state and get their own copies 361// of R8-R12, in addition to SP and LR. As before, mark LR for saving too. 362 363// FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and 364// current frame lowering expects to encounter it while processing callee-saved 365// registers. 366def CSR_FIQ : CalleeSavedRegs<(add LR, R11, (sequence "R%u", 7, 0))>; 367 368 369