xref: /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ARMCallingConv.td (revision 2f513db72b034fd5ef7f080b11be5c711c15186a)
1//===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// This describes the calling conventions for ARM architecture.
9//===----------------------------------------------------------------------===//
10
11/// CCIfAlign - Match of the original alignment of the arg
12class CCIfAlign<string Align, CCAction A>:
13  CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
14
15//===----------------------------------------------------------------------===//
16// ARM APCS Calling Convention
17//===----------------------------------------------------------------------===//
18let Entry = 1 in
19def CC_ARM_APCS : CallingConv<[
20
21  // Handles byval parameters.
22  CCIfByVal<CCPassByVal<4, 4>>,
23
24  CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
25
26  // Pass SwiftSelf in a callee saved register.
27  CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
28
29  // A SwiftError is passed in R8.
30  CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
31
32  // Handle all vector types as either f64 or v2f64.
33  CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
34  CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
35
36  // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
37  CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
38
39  CCIfType<[f32], CCBitConvertToType<i32>>,
40  CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
41
42  CCIfType<[i32], CCAssignToStack<4, 4>>,
43  CCIfType<[f64], CCAssignToStack<8, 4>>,
44  CCIfType<[v2f64], CCAssignToStack<16, 4>>
45]>;
46
47let Entry = 1 in
48def RetCC_ARM_APCS : CallingConv<[
49  CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
50  CCIfType<[f32], CCBitConvertToType<i32>>,
51
52  // Pass SwiftSelf in a callee saved register.
53  CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
54
55  // A SwiftError is returned in R8.
56  CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
57
58  // Handle all vector types as either f64 or v2f64.
59  CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
60  CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
61
62  CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
63
64  CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
65  CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
66]>;
67
68//===----------------------------------------------------------------------===//
69// ARM APCS Calling Convention for FastCC (when VFP2 or later is available)
70//===----------------------------------------------------------------------===//
71let Entry = 1 in
72def FastCC_ARM_APCS : CallingConv<[
73  // Handle all vector types as either f64 or v2f64.
74  CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
75  CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
76
77  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
78  CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
79  CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
80                                 S9, S10, S11, S12, S13, S14, S15]>>,
81
82  // CPRCs may be allocated to co-processor registers or the stack - they
83  // may never be allocated to core registers.
84  CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
85  CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,
86  CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,
87
88  CCDelegateTo<CC_ARM_APCS>
89]>;
90
91let Entry = 1 in
92def RetFastCC_ARM_APCS : CallingConv<[
93  // Handle all vector types as either f64 or v2f64.
94  CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
95  CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
96
97  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
98  CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
99  CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
100                                 S9, S10, S11, S12, S13, S14, S15]>>,
101  CCDelegateTo<RetCC_ARM_APCS>
102]>;
103
104//===----------------------------------------------------------------------===//
105// ARM APCS Calling Convention for GHC
106//===----------------------------------------------------------------------===//
107
108let Entry = 1 in
109def CC_ARM_APCS_GHC : CallingConv<[
110  // Handle all vector types as either f64 or v2f64.
111  CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
112  CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
113
114  CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
115  CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
116  CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
117
118  // Promote i8/i16 arguments to i32.
119  CCIfType<[i8, i16], CCPromoteToType<i32>>,
120
121  // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim
122  CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
123]>;
124
125//===----------------------------------------------------------------------===//
126// ARM AAPCS (EABI) Calling Convention, common parts
127//===----------------------------------------------------------------------===//
128
129def CC_ARM_AAPCS_Common : CallingConv<[
130
131  CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
132
133  // i64/f64 is passed in even pairs of GPRs
134  // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register
135  // (and the same is true for f64 if VFP is not enabled)
136  CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,
137  CCIfType<[i32], CCIf<"ArgFlags.getOrigAlign() != 8",
138                       CCAssignToReg<[R0, R1, R2, R3]>>>,
139
140  CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, [R0, R1, R2, R3]>>>,
141  CCIfType<[i32], CCAssignToStackWithShadow<4, 4, [R0, R1, R2, R3]>>,
142  CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
143  CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>,
144  CCIfType<[v2f64], CCIfAlign<"16",
145           CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>,
146  CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>
147]>;
148
149def RetCC_ARM_AAPCS_Common : CallingConv<[
150  CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
151  CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
152  CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
153]>;
154
155//===----------------------------------------------------------------------===//
156// ARM AAPCS (EABI) Calling Convention
157//===----------------------------------------------------------------------===//
158
159let Entry = 1 in
160def CC_ARM_AAPCS : CallingConv<[
161  // Handles byval parameters.
162  CCIfByVal<CCPassByVal<4, 4>>,
163
164  // The 'nest' parameter, if any, is passed in R12.
165  CCIfNest<CCAssignToReg<[R12]>>,
166
167  // Handle all vector types as either f64 or v2f64.
168  CCIfType<[v1i64, v2i32, v4i16, v4f16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
169  CCIfType<[v2i64, v4i32, v8i16, v8f16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
170
171  // Pass SwiftSelf in a callee saved register.
172  CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
173
174  // A SwiftError is passed in R8.
175  CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
176
177  CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
178  CCIfType<[f32], CCBitConvertToType<i32>>,
179  CCDelegateTo<CC_ARM_AAPCS_Common>
180]>;
181
182let Entry = 1 in
183def RetCC_ARM_AAPCS : CallingConv<[
184  // Handle all vector types as either f64 or v2f64.
185  CCIfType<[v1i64, v2i32, v4i16, v4f16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
186  CCIfType<[v2i64, v4i32, v8i16, v8f16, v8f16,v16i8, v4f32], CCBitConvertToType<v2f64>>,
187
188  // Pass SwiftSelf in a callee saved register.
189  CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
190
191  // A SwiftError is returned in R8.
192  CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
193
194  CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
195  CCIfType<[f32], CCBitConvertToType<i32>>,
196
197  CCDelegateTo<RetCC_ARM_AAPCS_Common>
198]>;
199
200//===----------------------------------------------------------------------===//
201// ARM AAPCS-VFP (EABI) Calling Convention
202// Also used for FastCC (when VFP2 or later is available)
203//===----------------------------------------------------------------------===//
204
205let Entry = 1 in
206def CC_ARM_AAPCS_VFP : CallingConv<[
207  // Handles byval parameters.
208  CCIfByVal<CCPassByVal<4, 4>>,
209
210  // Handle all vector types as either f64 or v2f64.
211  CCIfType<[v1i64, v2i32, v4i16, v4f16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
212  CCIfType<[v2i64, v4i32, v8i16, v8f16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
213
214  // Pass SwiftSelf in a callee saved register.
215  CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
216
217  // A SwiftError is passed in R8.
218  CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
219
220  // HFAs are passed in a contiguous block of registers, or on the stack
221  CCIfConsecutiveRegs<CCCustom<"CC_ARM_AAPCS_Custom_Aggregate">>,
222
223  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
224  CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
225  CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
226                                 S9, S10, S11, S12, S13, S14, S15]>>,
227  CCDelegateTo<CC_ARM_AAPCS_Common>
228]>;
229
230let Entry = 1 in
231def RetCC_ARM_AAPCS_VFP : CallingConv<[
232  // Handle all vector types as either f64 or v2f64.
233  CCIfType<[v1i64, v2i32, v4i16, v4f16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
234  CCIfType<[v2i64, v4i32, v8i16, v8f16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
235
236  // Pass SwiftSelf in a callee saved register.
237  CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
238
239  // A SwiftError is returned in R8.
240  CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
241
242  CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
243  CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
244  CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
245                                      S9, S10, S11, S12, S13, S14, S15]>>,
246  CCDelegateTo<RetCC_ARM_AAPCS_Common>
247]>;
248
249//===----------------------------------------------------------------------===//
250// Callee-saved register lists.
251//===----------------------------------------------------------------------===//
252
253def CSR_NoRegs : CalleeSavedRegs<(add)>;
254def CSR_FPRegs : CalleeSavedRegs<(add (sequence "D%u", 0, 31))>;
255
256def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
257                                     (sequence "D%u", 15, 8))>;
258
259// R8 is used to pass swifterror, remove it from CSR.
260def CSR_AAPCS_SwiftError : CalleeSavedRegs<(sub CSR_AAPCS, R8)>;
261
262// The order of callee-saved registers needs to match the order we actually push
263// them in FrameLowering, because this order is what's used by
264// PrologEpilogInserter to allocate frame index slots. So when R7 is the frame
265// pointer, we use this AAPCS alternative.
266def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
267                                               R11, R10, R9, R8,
268                                               (sequence "D%u", 15, 8))>;
269
270// R8 is used to pass swifterror, remove it from CSR.
271def CSR_AAPCS_SplitPush_SwiftError : CalleeSavedRegs<(sub CSR_AAPCS_SplitPush,
272                                                      R8)>;
273
274// Constructors and destructors return 'this' in the ARM C++ ABI; since 'this'
275// and the pointer return value are both passed in R0 in these cases, this can
276// be partially modelled by treating R0 as a callee-saved register
277// Only the resulting RegMask is used; the SaveList is ignored
278def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
279                                            R5, R4, (sequence "D%u", 15, 8),
280                                            R0)>;
281
282// iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register.
283// Also save R7-R4 first to match the stack frame fixed spill areas.
284def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
285
286// R8 is used to pass swifterror, remove it from CSR.
287def CSR_iOS_SwiftError : CalleeSavedRegs<(sub CSR_iOS, R8)>;
288
289def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
290                                         (sub CSR_AAPCS_ThisReturn, R9))>;
291
292def CSR_iOS_TLSCall
293    : CalleeSavedRegs<(add LR, SP, (sub(sequence "R%u", 12, 1), R9, R12),
294                      (sequence "D%u", 31, 0))>;
295
296// C++ TLS access function saves all registers except SP. Try to match
297// the order of CSRs in CSR_iOS.
298def CSR_iOS_CXX_TLS : CalleeSavedRegs<(add CSR_iOS, (sequence "R%u", 12, 1),
299                                           (sequence "D%u", 31, 0))>;
300
301// CSRs that are handled by prologue, epilogue.
302def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
303
304// CSRs that are handled explicitly via copies.
305def CSR_iOS_CXX_TLS_ViaCopy : CalleeSavedRegs<(sub CSR_iOS_CXX_TLS,
306                                                   CSR_iOS_CXX_TLS_PE)>;
307
308// The "interrupt" attribute is used to generate code that is acceptable in
309// exception-handlers of various kinds. It makes us use a different return
310// instruction (handled elsewhere) and affects which registers we must return to
311// our "caller" in the same state as we receive them.
312
313// For most interrupts, all registers except SP and LR are shared with
314// user-space. We mark LR to be saved anyway, since this is what the ARM backend
315// generally does rather than tracking its liveness as a normal register.
316def CSR_GenericInt : CalleeSavedRegs<(add LR, (sequence "R%u", 12, 0))>;
317
318// The fast interrupt handlers have more private state and get their own copies
319// of R8-R12, in addition to SP and LR. As before, mark LR for saving too.
320
321// FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and
322// current frame lowering expects to encounter it while processing callee-saved
323// registers.
324def CSR_FIQ : CalleeSavedRegs<(add LR, R11, (sequence "R%u", 7, 0))>;
325
326
327