1 //===- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// This file implements the lowering of LLVM calls to machine code calls for 11 /// GlobalISel. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "ARMCallLowering.h" 16 #include "ARMBaseInstrInfo.h" 17 #include "ARMISelLowering.h" 18 #include "ARMSubtarget.h" 19 #include "Utils/ARMBaseInfo.h" 20 #include "llvm/ADT/SmallVector.h" 21 #include "llvm/CodeGen/Analysis.h" 22 #include "llvm/CodeGen/CallingConvLower.h" 23 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" 24 #include "llvm/CodeGen/GlobalISel/Utils.h" 25 #include "llvm/CodeGen/LowLevelType.h" 26 #include "llvm/CodeGen/MachineBasicBlock.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineFunction.h" 29 #include "llvm/CodeGen/MachineInstrBuilder.h" 30 #include "llvm/CodeGen/MachineMemOperand.h" 31 #include "llvm/CodeGen/MachineOperand.h" 32 #include "llvm/CodeGen/MachineRegisterInfo.h" 33 #include "llvm/CodeGen/TargetRegisterInfo.h" 34 #include "llvm/CodeGen/TargetSubtargetInfo.h" 35 #include "llvm/CodeGen/ValueTypes.h" 36 #include "llvm/IR/Attributes.h" 37 #include "llvm/IR/DataLayout.h" 38 #include "llvm/IR/DerivedTypes.h" 39 #include "llvm/IR/Function.h" 40 #include "llvm/IR/Type.h" 41 #include "llvm/IR/Value.h" 42 #include "llvm/Support/Casting.h" 43 #include "llvm/Support/LowLevelTypeImpl.h" 44 #include "llvm/Support/MachineValueType.h" 45 #include <algorithm> 46 #include <cassert> 47 #include <cstdint> 48 #include <utility> 49 50 using namespace llvm; 51 52 ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI) 53 : CallLowering(&TLI) {} 54 55 static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI, 56 Type *T) { 57 if (T->isArrayTy()) 58 return isSupportedType(DL, TLI, T->getArrayElementType()); 59 60 if (T->isStructTy()) { 61 // For now we only allow homogeneous structs that we can manipulate with 62 // G_MERGE_VALUES and G_UNMERGE_VALUES 63 auto StructT = cast<StructType>(T); 64 for (unsigned i = 1, e = StructT->getNumElements(); i != e; ++i) 65 if (StructT->getElementType(i) != StructT->getElementType(0)) 66 return false; 67 return isSupportedType(DL, TLI, StructT->getElementType(0)); 68 } 69 70 EVT VT = TLI.getValueType(DL, T, true); 71 if (!VT.isSimple() || VT.isVector() || 72 !(VT.isInteger() || VT.isFloatingPoint())) 73 return false; 74 75 unsigned VTSize = VT.getSimpleVT().getSizeInBits(); 76 77 if (VTSize == 64) 78 // FIXME: Support i64 too 79 return VT.isFloatingPoint(); 80 81 return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32; 82 } 83 84 namespace { 85 86 /// Helper class for values going out through an ABI boundary (used for handling 87 /// function return values and call parameters). 88 struct OutgoingValueHandler : public CallLowering::ValueHandler { 89 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 90 MachineInstrBuilder &MIB, CCAssignFn *AssignFn) 91 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} 92 93 bool isIncomingArgumentHandler() const override { return false; } 94 95 Register getStackAddress(uint64_t Size, int64_t Offset, 96 MachinePointerInfo &MPO) override { 97 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) && 98 "Unsupported size"); 99 100 LLT p0 = LLT::pointer(0, 32); 101 LLT s32 = LLT::scalar(32); 102 auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP)); 103 104 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); 105 106 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); 107 108 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset); 109 return AddrReg.getReg(0); 110 } 111 112 void assignValueToReg(Register ValVReg, Register PhysReg, 113 CCValAssign &VA) override { 114 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); 115 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); 116 117 assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size"); 118 assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size"); 119 120 Register ExtReg = extendRegister(ValVReg, VA); 121 MIRBuilder.buildCopy(PhysReg, ExtReg); 122 MIB.addUse(PhysReg, RegState::Implicit); 123 } 124 125 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, 126 MachinePointerInfo &MPO, CCValAssign &VA) override { 127 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) && 128 "Unsupported size"); 129 130 Register ExtReg = extendRegister(ValVReg, VA); 131 auto MMO = MIRBuilder.getMF().getMachineMemOperand( 132 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(), 133 Align(1)); 134 MIRBuilder.buildStore(ExtReg, Addr, *MMO); 135 } 136 137 unsigned assignCustomValue(const CallLowering::ArgInfo &Arg, 138 ArrayRef<CCValAssign> VAs) override { 139 assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet"); 140 141 CCValAssign VA = VAs[0]; 142 assert(VA.needsCustom() && "Value doesn't need custom handling"); 143 144 // Custom lowering for other types, such as f16, is currently not supported 145 if (VA.getValVT() != MVT::f64) 146 return 0; 147 148 CCValAssign NextVA = VAs[1]; 149 assert(NextVA.needsCustom() && "Value doesn't need custom handling"); 150 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type"); 151 152 assert(VA.getValNo() == NextVA.getValNo() && 153 "Values belong to different arguments"); 154 155 assert(VA.isRegLoc() && "Value should be in reg"); 156 assert(NextVA.isRegLoc() && "Value should be in reg"); 157 158 Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)), 159 MRI.createGenericVirtualRegister(LLT::scalar(32))}; 160 MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]); 161 162 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle(); 163 if (!IsLittle) 164 std::swap(NewRegs[0], NewRegs[1]); 165 166 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); 167 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); 168 169 return 1; 170 } 171 172 bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT, 173 CCValAssign::LocInfo LocInfo, 174 const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags, 175 CCState &State) override { 176 if (AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State)) 177 return true; 178 179 StackSize = 180 std::max(StackSize, static_cast<uint64_t>(State.getNextStackOffset())); 181 return false; 182 } 183 184 MachineInstrBuilder &MIB; 185 uint64_t StackSize = 0; 186 }; 187 188 } // end anonymous namespace 189 190 void ARMCallLowering::splitToValueTypes(const ArgInfo &OrigArg, 191 SmallVectorImpl<ArgInfo> &SplitArgs, 192 MachineFunction &MF) const { 193 const ARMTargetLowering &TLI = *getTLI<ARMTargetLowering>(); 194 LLVMContext &Ctx = OrigArg.Ty->getContext(); 195 const DataLayout &DL = MF.getDataLayout(); 196 const Function &F = MF.getFunction(); 197 198 SmallVector<EVT, 4> SplitVTs; 199 ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, nullptr, nullptr, 0); 200 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch"); 201 202 if (SplitVTs.size() == 1) { 203 // Even if there is no splitting to do, we still want to replace the 204 // original type (e.g. pointer type -> integer). 205 auto Flags = OrigArg.Flags[0]; 206 Flags.setOrigAlign(DL.getABITypeAlign(OrigArg.Ty)); 207 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx), 208 Flags, OrigArg.IsFixed); 209 return; 210 } 211 212 // Create one ArgInfo for each virtual register. 213 for (unsigned i = 0, e = SplitVTs.size(); i != e; ++i) { 214 EVT SplitVT = SplitVTs[i]; 215 Type *SplitTy = SplitVT.getTypeForEVT(Ctx); 216 auto Flags = OrigArg.Flags[0]; 217 218 Flags.setOrigAlign(DL.getABITypeAlign(SplitTy)); 219 220 bool NeedsConsecutiveRegisters = 221 TLI.functionArgumentNeedsConsecutiveRegisters( 222 SplitTy, F.getCallingConv(), F.isVarArg()); 223 if (NeedsConsecutiveRegisters) { 224 Flags.setInConsecutiveRegs(); 225 if (i == e - 1) 226 Flags.setInConsecutiveRegsLast(); 227 } 228 229 // FIXME: We also want to split SplitTy further. 230 Register PartReg = OrigArg.Regs[i]; 231 SplitArgs.emplace_back(PartReg, SplitTy, Flags, OrigArg.IsFixed); 232 } 233 } 234 235 /// Lower the return value for the already existing \p Ret. This assumes that 236 /// \p MIRBuilder's insertion point is correct. 237 bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder, 238 const Value *Val, ArrayRef<Register> VRegs, 239 MachineInstrBuilder &Ret) const { 240 if (!Val) 241 // Nothing to do here. 242 return true; 243 244 auto &MF = MIRBuilder.getMF(); 245 const auto &F = MF.getFunction(); 246 247 auto DL = MF.getDataLayout(); 248 auto &TLI = *getTLI<ARMTargetLowering>(); 249 if (!isSupportedType(DL, TLI, Val->getType())) 250 return false; 251 252 ArgInfo OrigRetInfo(VRegs, Val->getType()); 253 setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F); 254 255 SmallVector<ArgInfo, 4> SplitRetInfos; 256 splitToValueTypes(OrigRetInfo, SplitRetInfos, MF); 257 258 CCAssignFn *AssignFn = 259 TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg()); 260 261 OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret, AssignFn); 262 return handleAssignments(MIRBuilder, SplitRetInfos, RetHandler); 263 } 264 265 bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, 266 const Value *Val, 267 ArrayRef<Register> VRegs) const { 268 assert(!Val == VRegs.empty() && "Return value without a vreg"); 269 270 auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>(); 271 unsigned Opcode = ST.getReturnOpcode(); 272 auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL)); 273 274 if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret)) 275 return false; 276 277 MIRBuilder.insertInstr(Ret); 278 return true; 279 } 280 281 namespace { 282 283 /// Helper class for values coming in through an ABI boundary (used for handling 284 /// formal arguments and call return values). 285 struct IncomingValueHandler : public CallLowering::ValueHandler { 286 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 287 CCAssignFn AssignFn) 288 : ValueHandler(MIRBuilder, MRI, AssignFn) {} 289 290 bool isIncomingArgumentHandler() const override { return true; } 291 292 Register getStackAddress(uint64_t Size, int64_t Offset, 293 MachinePointerInfo &MPO) override { 294 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) && 295 "Unsupported size"); 296 297 auto &MFI = MIRBuilder.getMF().getFrameInfo(); 298 299 int FI = MFI.CreateFixedObject(Size, Offset, true); 300 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI); 301 302 return MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI) 303 .getReg(0); 304 } 305 306 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, 307 MachinePointerInfo &MPO, CCValAssign &VA) override { 308 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) && 309 "Unsupported size"); 310 311 if (VA.getLocInfo() == CCValAssign::SExt || 312 VA.getLocInfo() == CCValAssign::ZExt) { 313 // If the value is zero- or sign-extended, its size becomes 4 bytes, so 314 // that's what we should load. 315 Size = 4; 316 assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm"); 317 318 auto LoadVReg = buildLoad(LLT::scalar(32), Addr, Size, MPO); 319 MIRBuilder.buildTrunc(ValVReg, LoadVReg); 320 } else { 321 // If the value is not extended, a simple load will suffice. 322 buildLoad(ValVReg, Addr, Size, MPO); 323 } 324 } 325 326 MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, uint64_t Size, 327 MachinePointerInfo &MPO) { 328 MachineFunction &MF = MIRBuilder.getMF(); 329 330 auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size, 331 inferAlignFromPtrInfo(MF, MPO)); 332 return MIRBuilder.buildLoad(Res, Addr, *MMO); 333 } 334 335 void assignValueToReg(Register ValVReg, Register PhysReg, 336 CCValAssign &VA) override { 337 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); 338 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); 339 340 auto ValSize = VA.getValVT().getSizeInBits(); 341 auto LocSize = VA.getLocVT().getSizeInBits(); 342 343 assert(ValSize <= 64 && "Unsupported value size"); 344 assert(LocSize <= 64 && "Unsupported location size"); 345 346 markPhysRegUsed(PhysReg); 347 if (ValSize == LocSize) { 348 MIRBuilder.buildCopy(ValVReg, PhysReg); 349 } else { 350 assert(ValSize < LocSize && "Extensions not supported"); 351 352 // We cannot create a truncating copy, nor a trunc of a physical register. 353 // Therefore, we need to copy the content of the physical register into a 354 // virtual one and then truncate that. 355 auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg); 356 MIRBuilder.buildTrunc(ValVReg, PhysRegToVReg); 357 } 358 } 359 360 unsigned assignCustomValue(const ARMCallLowering::ArgInfo &Arg, 361 ArrayRef<CCValAssign> VAs) override { 362 assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet"); 363 364 CCValAssign VA = VAs[0]; 365 assert(VA.needsCustom() && "Value doesn't need custom handling"); 366 367 // Custom lowering for other types, such as f16, is currently not supported 368 if (VA.getValVT() != MVT::f64) 369 return 0; 370 371 CCValAssign NextVA = VAs[1]; 372 assert(NextVA.needsCustom() && "Value doesn't need custom handling"); 373 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type"); 374 375 assert(VA.getValNo() == NextVA.getValNo() && 376 "Values belong to different arguments"); 377 378 assert(VA.isRegLoc() && "Value should be in reg"); 379 assert(NextVA.isRegLoc() && "Value should be in reg"); 380 381 Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)), 382 MRI.createGenericVirtualRegister(LLT::scalar(32))}; 383 384 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); 385 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); 386 387 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle(); 388 if (!IsLittle) 389 std::swap(NewRegs[0], NewRegs[1]); 390 391 MIRBuilder.buildMerge(Arg.Regs[0], NewRegs); 392 393 return 1; 394 } 395 396 /// Marking a physical register as used is different between formal 397 /// parameters, where it's a basic block live-in, and call returns, where it's 398 /// an implicit-def of the call instruction. 399 virtual void markPhysRegUsed(unsigned PhysReg) = 0; 400 }; 401 402 struct FormalArgHandler : public IncomingValueHandler { 403 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 404 CCAssignFn AssignFn) 405 : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {} 406 407 void markPhysRegUsed(unsigned PhysReg) override { 408 MIRBuilder.getMRI()->addLiveIn(PhysReg); 409 MIRBuilder.getMBB().addLiveIn(PhysReg); 410 } 411 }; 412 413 } // end anonymous namespace 414 415 bool ARMCallLowering::lowerFormalArguments( 416 MachineIRBuilder &MIRBuilder, const Function &F, 417 ArrayRef<ArrayRef<Register>> VRegs) const { 418 auto &TLI = *getTLI<ARMTargetLowering>(); 419 auto Subtarget = TLI.getSubtarget(); 420 421 if (Subtarget->isThumb1Only()) 422 return false; 423 424 // Quick exit if there aren't any args 425 if (F.arg_empty()) 426 return true; 427 428 if (F.isVarArg()) 429 return false; 430 431 auto &MF = MIRBuilder.getMF(); 432 auto &MBB = MIRBuilder.getMBB(); 433 auto DL = MF.getDataLayout(); 434 435 for (auto &Arg : F.args()) { 436 if (!isSupportedType(DL, TLI, Arg.getType())) 437 return false; 438 if (Arg.hasPassPointeeByValueAttr()) 439 return false; 440 } 441 442 CCAssignFn *AssignFn = 443 TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg()); 444 445 FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo(), 446 AssignFn); 447 448 SmallVector<ArgInfo, 8> SplitArgInfos; 449 unsigned Idx = 0; 450 for (auto &Arg : F.args()) { 451 ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType()); 452 453 setArgFlags(OrigArgInfo, Idx + AttributeList::FirstArgIndex, DL, F); 454 splitToValueTypes(OrigArgInfo, SplitArgInfos, MF); 455 456 Idx++; 457 } 458 459 if (!MBB.empty()) 460 MIRBuilder.setInstr(*MBB.begin()); 461 462 if (!handleAssignments(MIRBuilder, SplitArgInfos, ArgHandler)) 463 return false; 464 465 // Move back to the end of the basic block. 466 MIRBuilder.setMBB(MBB); 467 return true; 468 } 469 470 namespace { 471 472 struct CallReturnHandler : public IncomingValueHandler { 473 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 474 MachineInstrBuilder MIB, CCAssignFn *AssignFn) 475 : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} 476 477 void markPhysRegUsed(unsigned PhysReg) override { 478 MIB.addDef(PhysReg, RegState::Implicit); 479 } 480 481 MachineInstrBuilder MIB; 482 }; 483 484 // FIXME: This should move to the ARMSubtarget when it supports all the opcodes. 485 unsigned getCallOpcode(const ARMSubtarget &STI, bool isDirect) { 486 if (isDirect) 487 return STI.isThumb() ? ARM::tBL : ARM::BL; 488 489 if (STI.isThumb()) 490 return ARM::tBLXr; 491 492 if (STI.hasV5TOps()) 493 return ARM::BLX; 494 495 if (STI.hasV4TOps()) 496 return ARM::BX_CALL; 497 498 return ARM::BMOVPCRX_CALL; 499 } 500 } // end anonymous namespace 501 502 bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const { 503 MachineFunction &MF = MIRBuilder.getMF(); 504 const auto &TLI = *getTLI<ARMTargetLowering>(); 505 const auto &DL = MF.getDataLayout(); 506 const auto &STI = MF.getSubtarget<ARMSubtarget>(); 507 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); 508 MachineRegisterInfo &MRI = MF.getRegInfo(); 509 510 if (STI.genLongCalls()) 511 return false; 512 513 if (STI.isThumb1Only()) 514 return false; 515 516 auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN); 517 518 // Create the call instruction so we can add the implicit uses of arg 519 // registers, but don't insert it yet. 520 bool IsDirect = !Info.Callee.isReg(); 521 auto CallOpcode = getCallOpcode(STI, IsDirect); 522 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode); 523 524 bool IsThumb = STI.isThumb(); 525 if (IsThumb) 526 MIB.add(predOps(ARMCC::AL)); 527 528 MIB.add(Info.Callee); 529 if (!IsDirect) { 530 auto CalleeReg = Info.Callee.getReg(); 531 if (CalleeReg && !Register::isPhysicalRegister(CalleeReg)) { 532 unsigned CalleeIdx = IsThumb ? 2 : 0; 533 MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass( 534 MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(), 535 *MIB.getInstr(), MIB->getDesc(), Info.Callee, CalleeIdx)); 536 } 537 } 538 539 MIB.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv)); 540 541 bool IsVarArg = false; 542 SmallVector<ArgInfo, 8> ArgInfos; 543 for (auto Arg : Info.OrigArgs) { 544 if (!isSupportedType(DL, TLI, Arg.Ty)) 545 return false; 546 547 if (!Arg.IsFixed) 548 IsVarArg = true; 549 550 if (Arg.Flags[0].isByVal()) 551 return false; 552 553 splitToValueTypes(Arg, ArgInfos, MF); 554 } 555 556 auto ArgAssignFn = TLI.CCAssignFnForCall(Info.CallConv, IsVarArg); 557 OutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn); 558 if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler)) 559 return false; 560 561 // Now we can add the actual call instruction to the correct basic block. 562 MIRBuilder.insertInstr(MIB); 563 564 if (!Info.OrigRet.Ty->isVoidTy()) { 565 if (!isSupportedType(DL, TLI, Info.OrigRet.Ty)) 566 return false; 567 568 ArgInfos.clear(); 569 splitToValueTypes(Info.OrigRet, ArgInfos, MF); 570 auto RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv, IsVarArg); 571 CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn); 572 if (!handleAssignments(MIRBuilder, ArgInfos, RetHandler)) 573 return false; 574 } 575 576 // We now know the size of the stack - update the ADJCALLSTACKDOWN 577 // accordingly. 578 CallSeqStart.addImm(ArgHandler.StackSize).addImm(0).add(predOps(ARMCC::AL)); 579 580 MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP) 581 .addImm(ArgHandler.StackSize) 582 .addImm(0) 583 .add(predOps(ARMCC::AL)); 584 585 return true; 586 } 587