1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the Base ARM implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H 14 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H 15 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/ADT/DenseMap.h" 18 #include "llvm/ADT/SmallSet.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/MachineInstr.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineOperand.h" 23 #include "llvm/CodeGen/TargetInstrInfo.h" 24 #include "llvm/IR/IntrinsicInst.h" 25 #include "llvm/IR/IntrinsicsARM.h" 26 #include <array> 27 #include <cstdint> 28 29 #define GET_INSTRINFO_HEADER 30 #include "ARMGenInstrInfo.inc" 31 32 namespace llvm { 33 34 class ARMBaseRegisterInfo; 35 class ARMSubtarget; 36 37 class ARMBaseInstrInfo : public ARMGenInstrInfo { 38 const ARMSubtarget &Subtarget; 39 40 protected: 41 // Can be only subclassed. 42 explicit ARMBaseInstrInfo(const ARMSubtarget &STI); 43 44 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, 45 unsigned LoadImmOpc, unsigned LoadOpc) const; 46 47 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI 48 /// and \p DefIdx. 49 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of 50 /// the list is modeled as <Reg:SubReg, SubIdx>. 51 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce 52 /// two elements: 53 /// - %1:sub1, sub0 54 /// - %2<:0>, sub1 55 /// 56 /// \returns true if it is possible to build such an input sequence 57 /// with the pair \p MI, \p DefIdx. False otherwise. 58 /// 59 /// \pre MI.isRegSequenceLike(). 60 bool getRegSequenceLikeInputs( 61 const MachineInstr &MI, unsigned DefIdx, 62 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override; 63 64 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI 65 /// and \p DefIdx. 66 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG. 67 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce: 68 /// - %1:sub1, sub0 69 /// 70 /// \returns true if it is possible to build such an input sequence 71 /// with the pair \p MI, \p DefIdx. False otherwise. 72 /// 73 /// \pre MI.isExtractSubregLike(). 74 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, 75 RegSubRegPairAndIdx &InputReg) const override; 76 77 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI 78 /// and \p DefIdx. 79 /// \p [out] BaseReg and \p [out] InsertedReg contain 80 /// the equivalent inputs of INSERT_SUBREG. 81 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce: 82 /// - BaseReg: %0:sub0 83 /// - InsertedReg: %1:sub1, sub3 84 /// 85 /// \returns true if it is possible to build such an input sequence 86 /// with the pair \p MI, \p DefIdx. False otherwise. 87 /// 88 /// \pre MI.isInsertSubregLike(). 89 bool 90 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, 91 RegSubRegPair &BaseReg, 92 RegSubRegPairAndIdx &InsertedReg) const override; 93 94 /// Commutes the operands in the given instruction. 95 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 96 /// 97 /// Do not call this method for a non-commutable instruction or for 98 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 99 /// Even though the instruction is commutable, the method may still 100 /// fail to commute the operands, null pointer is returned in such cases. 101 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 102 unsigned OpIdx1, 103 unsigned OpIdx2) const override; 104 /// If the specific machine instruction is an instruction that moves/copies 105 /// value from one register to another register return destination and source 106 /// registers as machine operands. 107 Optional<DestSourcePair> 108 isCopyInstrImpl(const MachineInstr &MI) const override; 109 110 /// Specialization of \ref TargetInstrInfo::describeLoadedValue, used to 111 /// enhance debug entry value descriptions for ARM targets. 112 Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI, 113 Register Reg) const override; 114 115 public: 116 // Return whether the target has an explicit NOP encoding. 117 bool hasNOP() const; 118 119 // Return the non-pre/post incrementing version of 'Opc'. Return 0 120 // if there is not such an opcode. 121 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0; 122 123 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 124 MachineInstr &MI, 125 LiveVariables *LV) const override; 126 127 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0; 128 const ARMSubtarget &getSubtarget() const { return Subtarget; } 129 130 ScheduleHazardRecognizer * 131 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 132 const ScheduleDAG *DAG) const override; 133 134 ScheduleHazardRecognizer * 135 CreateTargetMIHazardRecognizer(const InstrItineraryData *II, 136 const ScheduleDAGMI *DAG) const override; 137 138 ScheduleHazardRecognizer * 139 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 140 const ScheduleDAG *DAG) const override; 141 142 // Branch analysis. 143 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 144 MachineBasicBlock *&FBB, 145 SmallVectorImpl<MachineOperand> &Cond, 146 bool AllowModify = false) const override; 147 unsigned removeBranch(MachineBasicBlock &MBB, 148 int *BytesRemoved = nullptr) const override; 149 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 150 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 151 const DebugLoc &DL, 152 int *BytesAdded = nullptr) const override; 153 154 bool 155 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 156 157 // Predication support. 158 bool isPredicated(const MachineInstr &MI) const override; 159 160 // MIR printer helper function to annotate Operands with a comment. 161 std::string 162 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, 163 unsigned OpIdx, 164 const TargetRegisterInfo *TRI) const override; 165 166 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const { 167 int PIdx = MI.findFirstPredOperandIdx(); 168 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm() 169 : ARMCC::AL; 170 } 171 172 bool PredicateInstruction(MachineInstr &MI, 173 ArrayRef<MachineOperand> Pred) const override; 174 175 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 176 ArrayRef<MachineOperand> Pred2) const override; 177 178 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred, 179 bool SkipDead) const override; 180 181 bool isPredicable(const MachineInstr &MI) const override; 182 183 // CPSR defined in instruction 184 static bool isCPSRDefined(const MachineInstr &MI); 185 186 /// GetInstSize - Returns the size of the specified MachineInstr. 187 /// 188 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 189 190 unsigned isLoadFromStackSlot(const MachineInstr &MI, 191 int &FrameIndex) const override; 192 unsigned isStoreToStackSlot(const MachineInstr &MI, 193 int &FrameIndex) const override; 194 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, 195 int &FrameIndex) const override; 196 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, 197 int &FrameIndex) const override; 198 199 void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 200 unsigned SrcReg, bool KillSrc, 201 const ARMSubtarget &Subtarget) const; 202 void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 203 unsigned DestReg, bool KillSrc, 204 const ARMSubtarget &Subtarget) const; 205 206 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 207 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 208 bool KillSrc) const override; 209 210 void storeRegToStackSlot(MachineBasicBlock &MBB, 211 MachineBasicBlock::iterator MBBI, 212 Register SrcReg, bool isKill, int FrameIndex, 213 const TargetRegisterClass *RC, 214 const TargetRegisterInfo *TRI) const override; 215 216 void loadRegFromStackSlot(MachineBasicBlock &MBB, 217 MachineBasicBlock::iterator MBBI, 218 Register DestReg, int FrameIndex, 219 const TargetRegisterClass *RC, 220 const TargetRegisterInfo *TRI) const override; 221 222 bool expandPostRAPseudo(MachineInstr &MI) const override; 223 224 bool shouldSink(const MachineInstr &MI) const override; 225 226 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 227 Register DestReg, unsigned SubIdx, 228 const MachineInstr &Orig, 229 const TargetRegisterInfo &TRI) const override; 230 231 MachineInstr & 232 duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, 233 const MachineInstr &Orig) const override; 234 235 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg, 236 unsigned SubIdx, unsigned State, 237 const TargetRegisterInfo *TRI) const; 238 239 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, 240 const MachineRegisterInfo *MRI) const override; 241 242 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 243 /// determine if two loads are loading from the same base address. It should 244 /// only return true if the base pointers are the same and the only 245 /// differences between the two addresses is the offset. It also returns the 246 /// offsets by reference. 247 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, 248 int64_t &Offset2) const override; 249 250 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 251 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads 252 /// should be scheduled togther. On some targets if two loads are loading from 253 /// addresses in the same cache line, it's better if they are scheduled 254 /// together. This function takes two integers that represent the load offsets 255 /// from the common base address. It returns true if it decides it's desirable 256 /// to schedule the two loads together. "NumLoads" is the number of loads that 257 /// have already been scheduled after Load1. 258 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 259 int64_t Offset1, int64_t Offset2, 260 unsigned NumLoads) const override; 261 262 bool isSchedulingBoundary(const MachineInstr &MI, 263 const MachineBasicBlock *MBB, 264 const MachineFunction &MF) const override; 265 266 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 267 unsigned NumCycles, unsigned ExtraPredCycles, 268 BranchProbability Probability) const override; 269 270 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, 271 unsigned ExtraT, MachineBasicBlock &FMBB, 272 unsigned NumF, unsigned ExtraF, 273 BranchProbability Probability) const override; 274 275 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 276 BranchProbability Probability) const override { 277 return NumCycles == 1; 278 } 279 280 unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, 281 unsigned NumInsts) const override; 282 unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override; 283 284 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 285 MachineBasicBlock &FMBB) const override; 286 287 /// analyzeCompare - For a comparison instruction, return the source registers 288 /// in SrcReg and SrcReg2 if having two register operands, and the value it 289 /// compares against in CmpValue. Return true if the comparison instruction 290 /// can be analyzed. 291 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 292 Register &SrcReg2, int &CmpMask, 293 int &CmpValue) const override; 294 295 /// optimizeCompareInstr - Convert the instruction to set the zero flag so 296 /// that we can remove a "comparison with zero"; Remove a redundant CMP 297 /// instruction if the flags can be updated in the same way by an earlier 298 /// instruction such as SUB. 299 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 300 Register SrcReg2, int CmpMask, int CmpValue, 301 const MachineRegisterInfo *MRI) const override; 302 303 bool analyzeSelect(const MachineInstr &MI, 304 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp, 305 unsigned &FalseOp, bool &Optimizable) const override; 306 307 MachineInstr *optimizeSelect(MachineInstr &MI, 308 SmallPtrSetImpl<MachineInstr *> &SeenMIs, 309 bool) const override; 310 311 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 312 /// instruction, try to fold the immediate into the use instruction. 313 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 314 MachineRegisterInfo *MRI) const override; 315 316 unsigned getNumMicroOps(const InstrItineraryData *ItinData, 317 const MachineInstr &MI) const override; 318 319 int getOperandLatency(const InstrItineraryData *ItinData, 320 const MachineInstr &DefMI, unsigned DefIdx, 321 const MachineInstr &UseMI, 322 unsigned UseIdx) const override; 323 int getOperandLatency(const InstrItineraryData *ItinData, 324 SDNode *DefNode, unsigned DefIdx, 325 SDNode *UseNode, unsigned UseIdx) const override; 326 327 /// VFP/NEON execution domains. 328 std::pair<uint16_t, uint16_t> 329 getExecutionDomain(const MachineInstr &MI) const override; 330 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override; 331 332 unsigned 333 getPartialRegUpdateClearance(const MachineInstr &, unsigned, 334 const TargetRegisterInfo *) const override; 335 void breakPartialRegDependency(MachineInstr &, unsigned, 336 const TargetRegisterInfo *TRI) const override; 337 338 /// Get the number of addresses by LDM or VLDM or zero for unknown. 339 unsigned getNumLDMAddresses(const MachineInstr &MI) const; 340 341 std::pair<unsigned, unsigned> 342 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 343 ArrayRef<std::pair<unsigned, const char *>> 344 getSerializableDirectMachineOperandTargetFlags() const override; 345 ArrayRef<std::pair<unsigned, const char *>> 346 getSerializableBitmaskMachineOperandTargetFlags() const override; 347 348 /// ARM supports the MachineOutliner. 349 bool isFunctionSafeToOutlineFrom(MachineFunction &MF, 350 bool OutlineFromLinkOnceODRs) const override; 351 outliner::OutlinedFunction getOutliningCandidateInfo( 352 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; 353 outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, 354 unsigned Flags) const override; 355 bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, 356 unsigned &Flags) const override; 357 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 358 const outliner::OutlinedFunction &OF) const override; 359 MachineBasicBlock::iterator 360 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 361 MachineBasicBlock::iterator &It, MachineFunction &MF, 362 const outliner::Candidate &C) const override; 363 364 /// Enable outlining by default at -Oz. 365 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override; 366 367 bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override { 368 return MI->getOpcode() == ARM::t2LoopEndDec || 369 MI->getOpcode() == ARM::t2DoLoopStartTP; 370 } 371 372 private: 373 /// Returns an unused general-purpose register which can be used for 374 /// constructing an outlined call if one exists. Returns 0 otherwise. 375 unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const; 376 377 // Adds an instruction which saves the link register on top of the stack into 378 /// the MachineBasicBlock \p MBB at position \p It. 379 void saveLROnStack(MachineBasicBlock &MBB, 380 MachineBasicBlock::iterator It) const; 381 382 /// Adds an instruction which restores the link register from the top the 383 /// stack into the MachineBasicBlock \p MBB at position \p It. 384 void restoreLRFromStack(MachineBasicBlock &MBB, 385 MachineBasicBlock::iterator It) const; 386 387 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It, 388 /// for the case when the LR is saved on the stack. 389 void emitCFIForLRSaveOnStack(MachineBasicBlock &MBB, 390 MachineBasicBlock::iterator It) const; 391 392 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It, 393 /// for the case when the LR is saved in the register \p Reg. 394 void emitCFIForLRSaveToReg(MachineBasicBlock &MBB, 395 MachineBasicBlock::iterator It, 396 Register Reg) const; 397 398 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It, 399 /// after the LR is was restored from the stack. 400 void emitCFIForLRRestoreFromStack(MachineBasicBlock &MBB, 401 MachineBasicBlock::iterator It) const; 402 403 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It, 404 /// after the LR is was restored from a register. 405 void emitCFIForLRRestoreFromReg(MachineBasicBlock &MBB, 406 MachineBasicBlock::iterator It) const; 407 /// \brief Sets the offsets on outlined instructions in \p MBB which use SP 408 /// so that they will be valid post-outlining. 409 /// 410 /// \param MBB A \p MachineBasicBlock in an outlined function. 411 void fixupPostOutline(MachineBasicBlock &MBB) const; 412 413 /// Returns true if the machine instruction offset can handle the stack fixup 414 /// and updates it if requested. 415 bool checkAndUpdateStackOffset(MachineInstr *MI, int64_t Fixup, 416 bool Updt) const; 417 418 unsigned getInstBundleLength(const MachineInstr &MI) const; 419 420 int getVLDMDefCycle(const InstrItineraryData *ItinData, 421 const MCInstrDesc &DefMCID, 422 unsigned DefClass, 423 unsigned DefIdx, unsigned DefAlign) const; 424 int getLDMDefCycle(const InstrItineraryData *ItinData, 425 const MCInstrDesc &DefMCID, 426 unsigned DefClass, 427 unsigned DefIdx, unsigned DefAlign) const; 428 int getVSTMUseCycle(const InstrItineraryData *ItinData, 429 const MCInstrDesc &UseMCID, 430 unsigned UseClass, 431 unsigned UseIdx, unsigned UseAlign) const; 432 int getSTMUseCycle(const InstrItineraryData *ItinData, 433 const MCInstrDesc &UseMCID, 434 unsigned UseClass, 435 unsigned UseIdx, unsigned UseAlign) const; 436 int getOperandLatency(const InstrItineraryData *ItinData, 437 const MCInstrDesc &DefMCID, 438 unsigned DefIdx, unsigned DefAlign, 439 const MCInstrDesc &UseMCID, 440 unsigned UseIdx, unsigned UseAlign) const; 441 442 int getOperandLatencyImpl(const InstrItineraryData *ItinData, 443 const MachineInstr &DefMI, unsigned DefIdx, 444 const MCInstrDesc &DefMCID, unsigned DefAdj, 445 const MachineOperand &DefMO, unsigned Reg, 446 const MachineInstr &UseMI, unsigned UseIdx, 447 const MCInstrDesc &UseMCID, unsigned UseAdj) const; 448 449 unsigned getPredicationCost(const MachineInstr &MI) const override; 450 451 unsigned getInstrLatency(const InstrItineraryData *ItinData, 452 const MachineInstr &MI, 453 unsigned *PredCost = nullptr) const override; 454 455 int getInstrLatency(const InstrItineraryData *ItinData, 456 SDNode *Node) const override; 457 458 bool hasHighOperandLatency(const TargetSchedModel &SchedModel, 459 const MachineRegisterInfo *MRI, 460 const MachineInstr &DefMI, unsigned DefIdx, 461 const MachineInstr &UseMI, 462 unsigned UseIdx) const override; 463 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 464 const MachineInstr &DefMI, 465 unsigned DefIdx) const override; 466 467 /// verifyInstruction - Perform target specific instruction verification. 468 bool verifyInstruction(const MachineInstr &MI, 469 StringRef &ErrInfo) const override; 470 471 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0; 472 473 void expandMEMCPY(MachineBasicBlock::iterator) const; 474 475 /// Identify instructions that can be folded into a MOVCC instruction, and 476 /// return the defining instruction. 477 MachineInstr *canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI, 478 const TargetInstrInfo *TII) const; 479 480 bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 481 AAResults *AA) const override; 482 483 private: 484 /// Modeling special VFP / NEON fp MLA / MLS hazards. 485 486 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal 487 /// MLx table. 488 DenseMap<unsigned, unsigned> MLxEntryMap; 489 490 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause 491 /// stalls when scheduled together with fp MLA / MLS opcodes. 492 SmallSet<unsigned, 16> MLxHazardOpcodes; 493 494 public: 495 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS 496 /// instruction. 497 bool isFpMLxInstruction(unsigned Opcode) const { 498 return MLxEntryMap.count(Opcode); 499 } 500 501 /// isFpMLxInstruction - This version also returns the multiply opcode and the 502 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for 503 /// the MLX instructions with an extra lane operand. 504 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 505 unsigned &AddSubOpc, bool &NegAcc, 506 bool &HasLane) const; 507 508 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode 509 /// will cause stalls when scheduled after (within 4-cycle window) a fp 510 /// MLA / MLS instruction. 511 bool canCauseFpMLxStall(unsigned Opcode) const { 512 return MLxHazardOpcodes.count(Opcode); 513 } 514 515 /// Returns true if the instruction has a shift by immediate that can be 516 /// executed in one cycle less. 517 bool isSwiftFastImmShift(const MachineInstr *MI) const; 518 519 /// Returns predicate register associated with the given frame instruction. 520 unsigned getFramePred(const MachineInstr &MI) const { 521 assert(isFrameInstr(MI)); 522 // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP: 523 // - argument declared in the pattern: 524 // 0 - frame size 525 // 1 - arg of CALLSEQ_START/CALLSEQ_END 526 // 2 - predicate code (like ARMCC::AL) 527 // - added by predOps: 528 // 3 - predicate reg 529 return MI.getOperand(3).getReg(); 530 } 531 532 Optional<RegImmPair> isAddImmediate(const MachineInstr &MI, 533 Register Reg) const override; 534 }; 535 536 /// Get the operands corresponding to the given \p Pred value. By default, the 537 /// predicate register is assumed to be 0 (no register), but you can pass in a 538 /// \p PredReg if that is not the case. 539 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred, 540 unsigned PredReg = 0) { 541 return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)), 542 MachineOperand::CreateReg(PredReg, false)}}; 543 } 544 545 /// Get the operand corresponding to the conditional code result. By default, 546 /// this is 0 (no register). 547 static inline MachineOperand condCodeOp(unsigned CCReg = 0) { 548 return MachineOperand::CreateReg(CCReg, false); 549 } 550 551 /// Get the operand corresponding to the conditional code result for Thumb1. 552 /// This operand will always refer to CPSR and it will have the Define flag set. 553 /// You can optionally set the Dead flag by means of \p isDead. 554 static inline MachineOperand t1CondCodeOp(bool isDead = false) { 555 return MachineOperand::CreateReg(ARM::CPSR, 556 /*Define*/ true, /*Implicit*/ false, 557 /*Kill*/ false, isDead); 558 } 559 560 static inline 561 bool isUncondBranchOpcode(int Opc) { 562 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; 563 } 564 565 // This table shows the VPT instruction variants, i.e. the different 566 // mask field encodings, see also B5.6. Predication/conditional execution in 567 // the ArmARM. 568 static inline bool isVPTOpcode(int Opc) { 569 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 || 570 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 || 571 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 || 572 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 || 573 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 || 574 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r || 575 Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r || 576 Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r || 577 Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r || 578 Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r || 579 Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r || 580 Opc == ARM::MVE_VPST; 581 } 582 583 static inline 584 unsigned VCMPOpcodeToVPT(unsigned Opcode) { 585 switch (Opcode) { 586 default: 587 return 0; 588 case ARM::MVE_VCMPf32: 589 return ARM::MVE_VPTv4f32; 590 case ARM::MVE_VCMPf16: 591 return ARM::MVE_VPTv8f16; 592 case ARM::MVE_VCMPi8: 593 return ARM::MVE_VPTv16i8; 594 case ARM::MVE_VCMPi16: 595 return ARM::MVE_VPTv8i16; 596 case ARM::MVE_VCMPi32: 597 return ARM::MVE_VPTv4i32; 598 case ARM::MVE_VCMPu8: 599 return ARM::MVE_VPTv16u8; 600 case ARM::MVE_VCMPu16: 601 return ARM::MVE_VPTv8u16; 602 case ARM::MVE_VCMPu32: 603 return ARM::MVE_VPTv4u32; 604 case ARM::MVE_VCMPs8: 605 return ARM::MVE_VPTv16s8; 606 case ARM::MVE_VCMPs16: 607 return ARM::MVE_VPTv8s16; 608 case ARM::MVE_VCMPs32: 609 return ARM::MVE_VPTv4s32; 610 611 case ARM::MVE_VCMPf32r: 612 return ARM::MVE_VPTv4f32r; 613 case ARM::MVE_VCMPf16r: 614 return ARM::MVE_VPTv8f16r; 615 case ARM::MVE_VCMPi8r: 616 return ARM::MVE_VPTv16i8r; 617 case ARM::MVE_VCMPi16r: 618 return ARM::MVE_VPTv8i16r; 619 case ARM::MVE_VCMPi32r: 620 return ARM::MVE_VPTv4i32r; 621 case ARM::MVE_VCMPu8r: 622 return ARM::MVE_VPTv16u8r; 623 case ARM::MVE_VCMPu16r: 624 return ARM::MVE_VPTv8u16r; 625 case ARM::MVE_VCMPu32r: 626 return ARM::MVE_VPTv4u32r; 627 case ARM::MVE_VCMPs8r: 628 return ARM::MVE_VPTv16s8r; 629 case ARM::MVE_VCMPs16r: 630 return ARM::MVE_VPTv8s16r; 631 case ARM::MVE_VCMPs32r: 632 return ARM::MVE_VPTv4s32r; 633 } 634 } 635 636 static inline 637 bool isCondBranchOpcode(int Opc) { 638 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; 639 } 640 641 static inline bool isJumpTableBranchOpcode(int Opc) { 642 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 || 643 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr || 644 Opc == ARM::t2BR_JT; 645 } 646 647 static inline bool isLowOverheadTerminatorOpcode(int Opc) { 648 return Opc == ARM::t2DoLoopStartTP || Opc == ARM::t2WhileLoopStart || 649 Opc == ARM::t2LoopEnd || Opc == ARM::t2LoopEndDec; 650 } 651 652 static inline 653 bool isIndirectBranchOpcode(int Opc) { 654 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; 655 } 656 657 static inline bool isIndirectCall(const MachineInstr &MI) { 658 int Opc = MI.getOpcode(); 659 switch (Opc) { 660 // indirect calls: 661 case ARM::BLX: 662 case ARM::BLX_noip: 663 case ARM::BLX_pred: 664 case ARM::BLX_pred_noip: 665 case ARM::BX_CALL: 666 case ARM::BMOVPCRX_CALL: 667 case ARM::TCRETURNri: 668 case ARM::TAILJMPr: 669 case ARM::TAILJMPr4: 670 case ARM::tBLXr: 671 case ARM::tBLXr_noip: 672 case ARM::tBLXNSr: 673 case ARM::tBLXNS_CALL: 674 case ARM::tBX_CALL: 675 case ARM::tTAILJMPr: 676 assert(MI.isCall(MachineInstr::IgnoreBundle)); 677 return true; 678 // direct calls: 679 case ARM::BL: 680 case ARM::BL_pred: 681 case ARM::BMOVPCB_CALL: 682 case ARM::BL_PUSHLR: 683 case ARM::BLXi: 684 case ARM::TCRETURNdi: 685 case ARM::TAILJMPd: 686 case ARM::SVC: 687 case ARM::HVC: 688 case ARM::TPsoft: 689 case ARM::tTAILJMPd: 690 case ARM::t2SMC: 691 case ARM::t2HVC: 692 case ARM::tBL: 693 case ARM::tBLXi: 694 case ARM::tBL_PUSHLR: 695 case ARM::tTAILJMPdND: 696 case ARM::tSVC: 697 case ARM::tTPsoft: 698 assert(MI.isCall(MachineInstr::IgnoreBundle)); 699 return false; 700 } 701 assert(!MI.isCall(MachineInstr::IgnoreBundle)); 702 return false; 703 } 704 705 static inline bool isIndirectControlFlowNotComingBack(const MachineInstr &MI) { 706 int opc = MI.getOpcode(); 707 return MI.isReturn() || isIndirectBranchOpcode(MI.getOpcode()) || 708 isJumpTableBranchOpcode(opc); 709 } 710 711 static inline bool isSpeculationBarrierEndBBOpcode(int Opc) { 712 return Opc == ARM::SpeculationBarrierISBDSBEndBB || 713 Opc == ARM::SpeculationBarrierSBEndBB || 714 Opc == ARM::t2SpeculationBarrierISBDSBEndBB || 715 Opc == ARM::t2SpeculationBarrierSBEndBB; 716 } 717 718 static inline bool isPopOpcode(int Opc) { 719 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET || 720 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD || 721 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD; 722 } 723 724 static inline bool isPushOpcode(int Opc) { 725 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD || 726 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD; 727 } 728 729 static inline bool isSubImmOpcode(int Opc) { 730 return Opc == ARM::SUBri || 731 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 || 732 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 || 733 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri; 734 } 735 736 static inline bool isMovRegOpcode(int Opc) { 737 return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr; 738 } 739 /// isValidCoprocessorNumber - decide whether an explicit coprocessor 740 /// number is legal in generic instructions like CDP. The answer can 741 /// vary with the subtarget. 742 static inline bool isValidCoprocessorNumber(unsigned Num, 743 const FeatureBitset& featureBits) { 744 // In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the 745 // coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is 746 // useful for code which is shared with older architectures which do not know 747 // the new VFP/NEON mnemonics. 748 749 // Armv8-A disallows everything *other* than 111x (CP14 and CP15). 750 if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE) 751 return false; 752 753 // Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15) 754 // which clash with MVE. 755 if (featureBits[ARM::HasV8_1MMainlineOps] && 756 ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE)) 757 return false; 758 759 return true; 760 } 761 762 /// getInstrPredicate - If instruction is predicated, returns its predicate 763 /// condition, otherwise returns AL. It also returns the condition code 764 /// register by reference. 765 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg); 766 767 unsigned getMatchingCondBranchOpcode(unsigned Opc); 768 769 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether 770 /// the instruction is encoded with an 'S' bit is determined by the optional 771 /// CPSR def operand. 772 unsigned convertAddSubFlagsOpcode(unsigned OldOpc); 773 774 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of 775 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2 776 /// code. 777 void emitARMRegPlusImmediate(MachineBasicBlock &MBB, 778 MachineBasicBlock::iterator &MBBI, 779 const DebugLoc &dl, Register DestReg, 780 Register BaseReg, int NumBytes, 781 ARMCC::CondCodes Pred, Register PredReg, 782 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 783 784 void emitT2RegPlusImmediate(MachineBasicBlock &MBB, 785 MachineBasicBlock::iterator &MBBI, 786 const DebugLoc &dl, Register DestReg, 787 Register BaseReg, int NumBytes, 788 ARMCC::CondCodes Pred, Register PredReg, 789 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 790 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 791 MachineBasicBlock::iterator &MBBI, 792 const DebugLoc &dl, Register DestReg, 793 Register BaseReg, int NumBytes, 794 const TargetInstrInfo &TII, 795 const ARMBaseRegisterInfo &MRI, 796 unsigned MIFlags = 0); 797 798 /// Tries to add registers to the reglist of a given base-updating 799 /// push/pop instruction to adjust the stack by an additional 800 /// NumBytes. This can save a few bytes per function in code-size, but 801 /// obviously generates more memory traffic. As such, it only takes 802 /// effect in functions being optimised for size. 803 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, 804 MachineFunction &MF, MachineInstr *MI, 805 unsigned NumBytes); 806 807 /// rewriteARMFrameIndex / rewriteT2FrameIndex - 808 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the 809 /// offset could not be handled directly in MI, and return the left-over 810 /// portion by reference. 811 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 812 Register FrameReg, int &Offset, 813 const ARMBaseInstrInfo &TII); 814 815 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 816 Register FrameReg, int &Offset, 817 const ARMBaseInstrInfo &TII, 818 const TargetRegisterInfo *TRI); 819 820 /// Return true if Reg is defd between From and To 821 bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From, 822 MachineBasicBlock::iterator To, 823 const TargetRegisterInfo *TRI); 824 825 /// Search backwards from a tBcc to find a tCMPi8 against 0, meaning 826 /// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found. 827 MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br, 828 const TargetRegisterInfo *TRI); 829 830 void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB); 831 void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg); 832 833 void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond); 834 void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond, 835 unsigned Inactive); 836 837 /// Returns the number of instructions required to materialize the given 838 /// constant in a register, or 3 if a literal pool load is needed. 839 /// If ForCodesize is specified, an approximate cost in bytes is returned. 840 unsigned ConstantMaterializationCost(unsigned Val, 841 const ARMSubtarget *Subtarget, 842 bool ForCodesize = false); 843 844 /// Returns true if Val1 has a lower Constant Materialization Cost than Val2. 845 /// Uses the cost from ConstantMaterializationCost, first with ForCodesize as 846 /// specified. If the scores are equal, return the comparison for !ForCodesize. 847 bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2, 848 const ARMSubtarget *Subtarget, 849 bool ForCodesize = false); 850 851 // Return the immediate if this is ADDri or SUBri, scaled as appropriate. 852 // Returns 0 for unknown instructions. 853 inline int getAddSubImmediate(MachineInstr &MI) { 854 int Scale = 1; 855 unsigned ImmOp; 856 switch (MI.getOpcode()) { 857 case ARM::t2ADDri: 858 ImmOp = 2; 859 break; 860 case ARM::t2SUBri: 861 case ARM::t2SUBri12: 862 ImmOp = 2; 863 Scale = -1; 864 break; 865 case ARM::tSUBi3: 866 case ARM::tSUBi8: 867 ImmOp = 3; 868 Scale = -1; 869 break; 870 default: 871 return 0; 872 } 873 return Scale * MI.getOperand(ImmOp).getImm(); 874 } 875 876 // Given a memory access Opcode, check that the give Imm would be a valid Offset 877 // for this instruction using its addressing mode. 878 inline bool isLegalAddressImm(unsigned Opcode, int Imm, 879 const TargetInstrInfo *TII) { 880 const MCInstrDesc &Desc = TII->get(Opcode); 881 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 882 switch (AddrMode) { 883 case ARMII::AddrModeT2_i7: 884 return std::abs(Imm) < (((1 << 7) * 1) - 1); 885 case ARMII::AddrModeT2_i7s2: 886 return std::abs(Imm) < (((1 << 7) * 2) - 1) && Imm % 2 == 0; 887 case ARMII::AddrModeT2_i7s4: 888 return std::abs(Imm) < (((1 << 7) * 4) - 1) && Imm % 4 == 0; 889 case ARMII::AddrModeT2_i8: 890 return std::abs(Imm) < (((1 << 8) * 1) - 1); 891 case ARMII::AddrModeT2_i12: 892 return Imm >= 0 && Imm < (((1 << 12) * 1) - 1); 893 default: 894 llvm_unreachable("Unhandled Addressing mode"); 895 } 896 } 897 898 // Return true if the given intrinsic is a gather 899 inline bool isGather(IntrinsicInst *IntInst) { 900 if (IntInst == nullptr) 901 return false; 902 unsigned IntrinsicID = IntInst->getIntrinsicID(); 903 return (IntrinsicID == Intrinsic::masked_gather || 904 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base || 905 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_predicated || 906 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb || 907 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated || 908 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset || 909 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated); 910 } 911 912 // Return true if the given intrinsic is a scatter 913 inline bool isScatter(IntrinsicInst *IntInst) { 914 if (IntInst == nullptr) 915 return false; 916 unsigned IntrinsicID = IntInst->getIntrinsicID(); 917 return (IntrinsicID == Intrinsic::masked_scatter || 918 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base || 919 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_predicated || 920 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb || 921 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb_predicated || 922 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset || 923 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated); 924 } 925 926 // Return true if the given intrinsic is a gather or scatter 927 inline bool isGatherScatter(IntrinsicInst *IntInst) { 928 if (IntInst == nullptr) 929 return false; 930 return isGather(IntInst) || isScatter(IntInst); 931 } 932 933 unsigned getBLXOpcode(const MachineFunction &MF); 934 unsigned gettBLXrOpcode(const MachineFunction &MF); 935 unsigned getBLXpredOpcode(const MachineFunction &MF); 936 937 } // end namespace llvm 938 939 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H 940