1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the Base ARM implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H 14 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H 15 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/ADT/DenseMap.h" 18 #include "llvm/ADT/SmallSet.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/MachineInstr.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineOperand.h" 23 #include "llvm/CodeGen/TargetInstrInfo.h" 24 #include "llvm/IR/IntrinsicInst.h" 25 #include "llvm/IR/IntrinsicsARM.h" 26 #include <array> 27 #include <cstdint> 28 29 #define GET_INSTRINFO_HEADER 30 #include "ARMGenInstrInfo.inc" 31 32 namespace llvm { 33 34 class ARMBaseRegisterInfo; 35 class ARMSubtarget; 36 37 class ARMBaseInstrInfo : public ARMGenInstrInfo { 38 const ARMSubtarget &Subtarget; 39 40 protected: 41 // Can be only subclassed. 42 explicit ARMBaseInstrInfo(const ARMSubtarget &STI); 43 44 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, 45 unsigned LoadImmOpc, unsigned LoadOpc) const; 46 47 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI 48 /// and \p DefIdx. 49 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of 50 /// the list is modeled as <Reg:SubReg, SubIdx>. 51 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce 52 /// two elements: 53 /// - %1:sub1, sub0 54 /// - %2<:0>, sub1 55 /// 56 /// \returns true if it is possible to build such an input sequence 57 /// with the pair \p MI, \p DefIdx. False otherwise. 58 /// 59 /// \pre MI.isRegSequenceLike(). 60 bool getRegSequenceLikeInputs( 61 const MachineInstr &MI, unsigned DefIdx, 62 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override; 63 64 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI 65 /// and \p DefIdx. 66 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG. 67 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce: 68 /// - %1:sub1, sub0 69 /// 70 /// \returns true if it is possible to build such an input sequence 71 /// with the pair \p MI, \p DefIdx. False otherwise. 72 /// 73 /// \pre MI.isExtractSubregLike(). 74 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, 75 RegSubRegPairAndIdx &InputReg) const override; 76 77 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI 78 /// and \p DefIdx. 79 /// \p [out] BaseReg and \p [out] InsertedReg contain 80 /// the equivalent inputs of INSERT_SUBREG. 81 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce: 82 /// - BaseReg: %0:sub0 83 /// - InsertedReg: %1:sub1, sub3 84 /// 85 /// \returns true if it is possible to build such an input sequence 86 /// with the pair \p MI, \p DefIdx. False otherwise. 87 /// 88 /// \pre MI.isInsertSubregLike(). 89 bool 90 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, 91 RegSubRegPair &BaseReg, 92 RegSubRegPairAndIdx &InsertedReg) const override; 93 94 /// Commutes the operands in the given instruction. 95 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 96 /// 97 /// Do not call this method for a non-commutable instruction or for 98 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 99 /// Even though the instruction is commutable, the method may still 100 /// fail to commute the operands, null pointer is returned in such cases. 101 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 102 unsigned OpIdx1, 103 unsigned OpIdx2) const override; 104 /// If the specific machine instruction is an instruction that moves/copies 105 /// value from one register to another register return destination and source 106 /// registers as machine operands. 107 Optional<DestSourcePair> 108 isCopyInstrImpl(const MachineInstr &MI) const override; 109 110 /// Specialization of \ref TargetInstrInfo::describeLoadedValue, used to 111 /// enhance debug entry value descriptions for ARM targets. 112 Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI, 113 Register Reg) const override; 114 115 public: 116 // Return whether the target has an explicit NOP encoding. 117 bool hasNOP() const; 118 119 // Return the non-pre/post incrementing version of 'Opc'. Return 0 120 // if there is not such an opcode. 121 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0; 122 123 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 124 MachineInstr &MI, 125 LiveVariables *LV) const override; 126 127 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0; 128 const ARMSubtarget &getSubtarget() const { return Subtarget; } 129 130 ScheduleHazardRecognizer * 131 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 132 const ScheduleDAG *DAG) const override; 133 134 ScheduleHazardRecognizer * 135 CreateTargetMIHazardRecognizer(const InstrItineraryData *II, 136 const ScheduleDAGMI *DAG) const override; 137 138 ScheduleHazardRecognizer * 139 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 140 const ScheduleDAG *DAG) const override; 141 142 // Branch analysis. 143 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 144 MachineBasicBlock *&FBB, 145 SmallVectorImpl<MachineOperand> &Cond, 146 bool AllowModify = false) const override; 147 unsigned removeBranch(MachineBasicBlock &MBB, 148 int *BytesRemoved = nullptr) const override; 149 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 150 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 151 const DebugLoc &DL, 152 int *BytesAdded = nullptr) const override; 153 154 bool 155 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 156 157 // Predication support. 158 bool isPredicated(const MachineInstr &MI) const override; 159 160 // MIR printer helper function to annotate Operands with a comment. 161 std::string 162 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, 163 unsigned OpIdx, 164 const TargetRegisterInfo *TRI) const override; 165 166 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const { 167 int PIdx = MI.findFirstPredOperandIdx(); 168 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm() 169 : ARMCC::AL; 170 } 171 172 bool PredicateInstruction(MachineInstr &MI, 173 ArrayRef<MachineOperand> Pred) const override; 174 175 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 176 ArrayRef<MachineOperand> Pred2) const override; 177 178 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred, 179 bool SkipDead) const override; 180 181 bool isPredicable(const MachineInstr &MI) const override; 182 183 // CPSR defined in instruction 184 static bool isCPSRDefined(const MachineInstr &MI); 185 186 /// GetInstSize - Returns the size of the specified MachineInstr. 187 /// 188 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 189 190 unsigned isLoadFromStackSlot(const MachineInstr &MI, 191 int &FrameIndex) const override; 192 unsigned isStoreToStackSlot(const MachineInstr &MI, 193 int &FrameIndex) const override; 194 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, 195 int &FrameIndex) const override; 196 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, 197 int &FrameIndex) const override; 198 199 void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 200 unsigned SrcReg, bool KillSrc, 201 const ARMSubtarget &Subtarget) const; 202 void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 203 unsigned DestReg, bool KillSrc, 204 const ARMSubtarget &Subtarget) const; 205 206 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 207 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 208 bool KillSrc) const override; 209 210 void storeRegToStackSlot(MachineBasicBlock &MBB, 211 MachineBasicBlock::iterator MBBI, 212 Register SrcReg, bool isKill, int FrameIndex, 213 const TargetRegisterClass *RC, 214 const TargetRegisterInfo *TRI) const override; 215 216 void loadRegFromStackSlot(MachineBasicBlock &MBB, 217 MachineBasicBlock::iterator MBBI, 218 Register DestReg, int FrameIndex, 219 const TargetRegisterClass *RC, 220 const TargetRegisterInfo *TRI) const override; 221 222 bool expandPostRAPseudo(MachineInstr &MI) const override; 223 224 bool shouldSink(const MachineInstr &MI) const override; 225 226 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 227 Register DestReg, unsigned SubIdx, 228 const MachineInstr &Orig, 229 const TargetRegisterInfo &TRI) const override; 230 231 MachineInstr & 232 duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, 233 const MachineInstr &Orig) const override; 234 235 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg, 236 unsigned SubIdx, unsigned State, 237 const TargetRegisterInfo *TRI) const; 238 239 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, 240 const MachineRegisterInfo *MRI) const override; 241 242 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 243 /// determine if two loads are loading from the same base address. It should 244 /// only return true if the base pointers are the same and the only 245 /// differences between the two addresses is the offset. It also returns the 246 /// offsets by reference. 247 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, 248 int64_t &Offset2) const override; 249 250 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 251 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads 252 /// should be scheduled togther. On some targets if two loads are loading from 253 /// addresses in the same cache line, it's better if they are scheduled 254 /// together. This function takes two integers that represent the load offsets 255 /// from the common base address. It returns true if it decides it's desirable 256 /// to schedule the two loads together. "NumLoads" is the number of loads that 257 /// have already been scheduled after Load1. 258 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 259 int64_t Offset1, int64_t Offset2, 260 unsigned NumLoads) const override; 261 262 bool isSchedulingBoundary(const MachineInstr &MI, 263 const MachineBasicBlock *MBB, 264 const MachineFunction &MF) const override; 265 266 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 267 unsigned NumCycles, unsigned ExtraPredCycles, 268 BranchProbability Probability) const override; 269 270 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, 271 unsigned ExtraT, MachineBasicBlock &FMBB, 272 unsigned NumF, unsigned ExtraF, 273 BranchProbability Probability) const override; 274 275 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 276 BranchProbability Probability) const override { 277 return NumCycles == 1; 278 } 279 280 unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, 281 unsigned NumInsts) const override; 282 unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override; 283 284 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 285 MachineBasicBlock &FMBB) const override; 286 287 /// analyzeCompare - For a comparison instruction, return the source registers 288 /// in SrcReg and SrcReg2 if having two register operands, and the value it 289 /// compares against in CmpValue. Return true if the comparison instruction 290 /// can be analyzed. 291 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 292 Register &SrcReg2, int &CmpMask, 293 int &CmpValue) const override; 294 295 /// optimizeCompareInstr - Convert the instruction to set the zero flag so 296 /// that we can remove a "comparison with zero"; Remove a redundant CMP 297 /// instruction if the flags can be updated in the same way by an earlier 298 /// instruction such as SUB. 299 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 300 Register SrcReg2, int CmpMask, int CmpValue, 301 const MachineRegisterInfo *MRI) const override; 302 303 bool analyzeSelect(const MachineInstr &MI, 304 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp, 305 unsigned &FalseOp, bool &Optimizable) const override; 306 307 MachineInstr *optimizeSelect(MachineInstr &MI, 308 SmallPtrSetImpl<MachineInstr *> &SeenMIs, 309 bool) const override; 310 311 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 312 /// instruction, try to fold the immediate into the use instruction. 313 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 314 MachineRegisterInfo *MRI) const override; 315 316 unsigned getNumMicroOps(const InstrItineraryData *ItinData, 317 const MachineInstr &MI) const override; 318 319 int getOperandLatency(const InstrItineraryData *ItinData, 320 const MachineInstr &DefMI, unsigned DefIdx, 321 const MachineInstr &UseMI, 322 unsigned UseIdx) const override; 323 int getOperandLatency(const InstrItineraryData *ItinData, 324 SDNode *DefNode, unsigned DefIdx, 325 SDNode *UseNode, unsigned UseIdx) const override; 326 327 /// VFP/NEON execution domains. 328 std::pair<uint16_t, uint16_t> 329 getExecutionDomain(const MachineInstr &MI) const override; 330 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override; 331 332 unsigned 333 getPartialRegUpdateClearance(const MachineInstr &, unsigned, 334 const TargetRegisterInfo *) const override; 335 void breakPartialRegDependency(MachineInstr &, unsigned, 336 const TargetRegisterInfo *TRI) const override; 337 338 /// Get the number of addresses by LDM or VLDM or zero for unknown. 339 unsigned getNumLDMAddresses(const MachineInstr &MI) const; 340 341 std::pair<unsigned, unsigned> 342 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 343 ArrayRef<std::pair<unsigned, const char *>> 344 getSerializableDirectMachineOperandTargetFlags() const override; 345 ArrayRef<std::pair<unsigned, const char *>> 346 getSerializableBitmaskMachineOperandTargetFlags() const override; 347 348 /// ARM supports the MachineOutliner. 349 bool isFunctionSafeToOutlineFrom(MachineFunction &MF, 350 bool OutlineFromLinkOnceODRs) const override; 351 outliner::OutlinedFunction getOutliningCandidateInfo( 352 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; 353 outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, 354 unsigned Flags) const override; 355 bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, 356 unsigned &Flags) const override; 357 void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 358 const outliner::OutlinedFunction &OF) const override; 359 MachineBasicBlock::iterator 360 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 361 MachineBasicBlock::iterator &It, MachineFunction &MF, 362 const outliner::Candidate &C) const override; 363 364 /// Enable outlining by default at -Oz. 365 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override; 366 367 bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override { 368 return MI->getOpcode() == ARM::t2LoopEndDec || 369 MI->getOpcode() == ARM::t2DoLoopStartTP || 370 MI->getOpcode() == ARM::t2WhileLoopStartLR || 371 MI->getOpcode() == ARM::t2WhileLoopStartTP; 372 } 373 374 private: 375 /// Returns an unused general-purpose register which can be used for 376 /// constructing an outlined call if one exists. Returns 0 otherwise. 377 unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const; 378 379 // Adds an instruction which saves the link register on top of the stack into 380 /// the MachineBasicBlock \p MBB at position \p It. 381 void saveLROnStack(MachineBasicBlock &MBB, 382 MachineBasicBlock::iterator It) const; 383 384 /// Adds an instruction which restores the link register from the top the 385 /// stack into the MachineBasicBlock \p MBB at position \p It. 386 void restoreLRFromStack(MachineBasicBlock &MBB, 387 MachineBasicBlock::iterator It) const; 388 389 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It, 390 /// for the case when the LR is saved on the stack. 391 void emitCFIForLRSaveOnStack(MachineBasicBlock &MBB, 392 MachineBasicBlock::iterator It) const; 393 394 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It, 395 /// for the case when the LR is saved in the register \p Reg. 396 void emitCFIForLRSaveToReg(MachineBasicBlock &MBB, 397 MachineBasicBlock::iterator It, 398 Register Reg) const; 399 400 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It, 401 /// after the LR is was restored from the stack. 402 void emitCFIForLRRestoreFromStack(MachineBasicBlock &MBB, 403 MachineBasicBlock::iterator It) const; 404 405 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It, 406 /// after the LR is was restored from a register. 407 void emitCFIForLRRestoreFromReg(MachineBasicBlock &MBB, 408 MachineBasicBlock::iterator It) const; 409 /// \brief Sets the offsets on outlined instructions in \p MBB which use SP 410 /// so that they will be valid post-outlining. 411 /// 412 /// \param MBB A \p MachineBasicBlock in an outlined function. 413 void fixupPostOutline(MachineBasicBlock &MBB) const; 414 415 /// Returns true if the machine instruction offset can handle the stack fixup 416 /// and updates it if requested. 417 bool checkAndUpdateStackOffset(MachineInstr *MI, int64_t Fixup, 418 bool Updt) const; 419 420 unsigned getInstBundleLength(const MachineInstr &MI) const; 421 422 int getVLDMDefCycle(const InstrItineraryData *ItinData, 423 const MCInstrDesc &DefMCID, 424 unsigned DefClass, 425 unsigned DefIdx, unsigned DefAlign) const; 426 int getLDMDefCycle(const InstrItineraryData *ItinData, 427 const MCInstrDesc &DefMCID, 428 unsigned DefClass, 429 unsigned DefIdx, unsigned DefAlign) const; 430 int getVSTMUseCycle(const InstrItineraryData *ItinData, 431 const MCInstrDesc &UseMCID, 432 unsigned UseClass, 433 unsigned UseIdx, unsigned UseAlign) const; 434 int getSTMUseCycle(const InstrItineraryData *ItinData, 435 const MCInstrDesc &UseMCID, 436 unsigned UseClass, 437 unsigned UseIdx, unsigned UseAlign) const; 438 int getOperandLatency(const InstrItineraryData *ItinData, 439 const MCInstrDesc &DefMCID, 440 unsigned DefIdx, unsigned DefAlign, 441 const MCInstrDesc &UseMCID, 442 unsigned UseIdx, unsigned UseAlign) const; 443 444 int getOperandLatencyImpl(const InstrItineraryData *ItinData, 445 const MachineInstr &DefMI, unsigned DefIdx, 446 const MCInstrDesc &DefMCID, unsigned DefAdj, 447 const MachineOperand &DefMO, unsigned Reg, 448 const MachineInstr &UseMI, unsigned UseIdx, 449 const MCInstrDesc &UseMCID, unsigned UseAdj) const; 450 451 unsigned getPredicationCost(const MachineInstr &MI) const override; 452 453 unsigned getInstrLatency(const InstrItineraryData *ItinData, 454 const MachineInstr &MI, 455 unsigned *PredCost = nullptr) const override; 456 457 int getInstrLatency(const InstrItineraryData *ItinData, 458 SDNode *Node) const override; 459 460 bool hasHighOperandLatency(const TargetSchedModel &SchedModel, 461 const MachineRegisterInfo *MRI, 462 const MachineInstr &DefMI, unsigned DefIdx, 463 const MachineInstr &UseMI, 464 unsigned UseIdx) const override; 465 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 466 const MachineInstr &DefMI, 467 unsigned DefIdx) const override; 468 469 /// verifyInstruction - Perform target specific instruction verification. 470 bool verifyInstruction(const MachineInstr &MI, 471 StringRef &ErrInfo) const override; 472 473 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0; 474 475 void expandMEMCPY(MachineBasicBlock::iterator) const; 476 477 /// Identify instructions that can be folded into a MOVCC instruction, and 478 /// return the defining instruction. 479 MachineInstr *canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI, 480 const TargetInstrInfo *TII) const; 481 482 bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 483 AAResults *AA) const override; 484 485 private: 486 /// Modeling special VFP / NEON fp MLA / MLS hazards. 487 488 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal 489 /// MLx table. 490 DenseMap<unsigned, unsigned> MLxEntryMap; 491 492 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause 493 /// stalls when scheduled together with fp MLA / MLS opcodes. 494 SmallSet<unsigned, 16> MLxHazardOpcodes; 495 496 public: 497 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS 498 /// instruction. 499 bool isFpMLxInstruction(unsigned Opcode) const { 500 return MLxEntryMap.count(Opcode); 501 } 502 503 /// isFpMLxInstruction - This version also returns the multiply opcode and the 504 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for 505 /// the MLX instructions with an extra lane operand. 506 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 507 unsigned &AddSubOpc, bool &NegAcc, 508 bool &HasLane) const; 509 510 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode 511 /// will cause stalls when scheduled after (within 4-cycle window) a fp 512 /// MLA / MLS instruction. 513 bool canCauseFpMLxStall(unsigned Opcode) const { 514 return MLxHazardOpcodes.count(Opcode); 515 } 516 517 /// Returns true if the instruction has a shift by immediate that can be 518 /// executed in one cycle less. 519 bool isSwiftFastImmShift(const MachineInstr *MI) const; 520 521 /// Returns predicate register associated with the given frame instruction. 522 unsigned getFramePred(const MachineInstr &MI) const { 523 assert(isFrameInstr(MI)); 524 // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP: 525 // - argument declared in the pattern: 526 // 0 - frame size 527 // 1 - arg of CALLSEQ_START/CALLSEQ_END 528 // 2 - predicate code (like ARMCC::AL) 529 // - added by predOps: 530 // 3 - predicate reg 531 return MI.getOperand(3).getReg(); 532 } 533 534 Optional<RegImmPair> isAddImmediate(const MachineInstr &MI, 535 Register Reg) const override; 536 }; 537 538 /// Get the operands corresponding to the given \p Pred value. By default, the 539 /// predicate register is assumed to be 0 (no register), but you can pass in a 540 /// \p PredReg if that is not the case. 541 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred, 542 unsigned PredReg = 0) { 543 return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)), 544 MachineOperand::CreateReg(PredReg, false)}}; 545 } 546 547 /// Get the operand corresponding to the conditional code result. By default, 548 /// this is 0 (no register). 549 static inline MachineOperand condCodeOp(unsigned CCReg = 0) { 550 return MachineOperand::CreateReg(CCReg, false); 551 } 552 553 /// Get the operand corresponding to the conditional code result for Thumb1. 554 /// This operand will always refer to CPSR and it will have the Define flag set. 555 /// You can optionally set the Dead flag by means of \p isDead. 556 static inline MachineOperand t1CondCodeOp(bool isDead = false) { 557 return MachineOperand::CreateReg(ARM::CPSR, 558 /*Define*/ true, /*Implicit*/ false, 559 /*Kill*/ false, isDead); 560 } 561 562 static inline 563 bool isUncondBranchOpcode(int Opc) { 564 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; 565 } 566 567 // This table shows the VPT instruction variants, i.e. the different 568 // mask field encodings, see also B5.6. Predication/conditional execution in 569 // the ArmARM. 570 static inline bool isVPTOpcode(int Opc) { 571 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 || 572 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 || 573 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 || 574 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 || 575 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 || 576 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r || 577 Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r || 578 Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r || 579 Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r || 580 Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r || 581 Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r || 582 Opc == ARM::MVE_VPST; 583 } 584 585 static inline 586 unsigned VCMPOpcodeToVPT(unsigned Opcode) { 587 switch (Opcode) { 588 default: 589 return 0; 590 case ARM::MVE_VCMPf32: 591 return ARM::MVE_VPTv4f32; 592 case ARM::MVE_VCMPf16: 593 return ARM::MVE_VPTv8f16; 594 case ARM::MVE_VCMPi8: 595 return ARM::MVE_VPTv16i8; 596 case ARM::MVE_VCMPi16: 597 return ARM::MVE_VPTv8i16; 598 case ARM::MVE_VCMPi32: 599 return ARM::MVE_VPTv4i32; 600 case ARM::MVE_VCMPu8: 601 return ARM::MVE_VPTv16u8; 602 case ARM::MVE_VCMPu16: 603 return ARM::MVE_VPTv8u16; 604 case ARM::MVE_VCMPu32: 605 return ARM::MVE_VPTv4u32; 606 case ARM::MVE_VCMPs8: 607 return ARM::MVE_VPTv16s8; 608 case ARM::MVE_VCMPs16: 609 return ARM::MVE_VPTv8s16; 610 case ARM::MVE_VCMPs32: 611 return ARM::MVE_VPTv4s32; 612 613 case ARM::MVE_VCMPf32r: 614 return ARM::MVE_VPTv4f32r; 615 case ARM::MVE_VCMPf16r: 616 return ARM::MVE_VPTv8f16r; 617 case ARM::MVE_VCMPi8r: 618 return ARM::MVE_VPTv16i8r; 619 case ARM::MVE_VCMPi16r: 620 return ARM::MVE_VPTv8i16r; 621 case ARM::MVE_VCMPi32r: 622 return ARM::MVE_VPTv4i32r; 623 case ARM::MVE_VCMPu8r: 624 return ARM::MVE_VPTv16u8r; 625 case ARM::MVE_VCMPu16r: 626 return ARM::MVE_VPTv8u16r; 627 case ARM::MVE_VCMPu32r: 628 return ARM::MVE_VPTv4u32r; 629 case ARM::MVE_VCMPs8r: 630 return ARM::MVE_VPTv16s8r; 631 case ARM::MVE_VCMPs16r: 632 return ARM::MVE_VPTv8s16r; 633 case ARM::MVE_VCMPs32r: 634 return ARM::MVE_VPTv4s32r; 635 } 636 } 637 638 static inline 639 bool isCondBranchOpcode(int Opc) { 640 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; 641 } 642 643 static inline bool isJumpTableBranchOpcode(int Opc) { 644 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 || 645 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr || 646 Opc == ARM::t2BR_JT; 647 } 648 649 static inline 650 bool isIndirectBranchOpcode(int Opc) { 651 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; 652 } 653 654 static inline bool isIndirectCall(const MachineInstr &MI) { 655 int Opc = MI.getOpcode(); 656 switch (Opc) { 657 // indirect calls: 658 case ARM::BLX: 659 case ARM::BLX_noip: 660 case ARM::BLX_pred: 661 case ARM::BLX_pred_noip: 662 case ARM::BX_CALL: 663 case ARM::BMOVPCRX_CALL: 664 case ARM::TCRETURNri: 665 case ARM::TAILJMPr: 666 case ARM::TAILJMPr4: 667 case ARM::tBLXr: 668 case ARM::tBLXr_noip: 669 case ARM::tBLXNSr: 670 case ARM::tBLXNS_CALL: 671 case ARM::tBX_CALL: 672 case ARM::tTAILJMPr: 673 assert(MI.isCall(MachineInstr::IgnoreBundle)); 674 return true; 675 // direct calls: 676 case ARM::BL: 677 case ARM::BL_pred: 678 case ARM::BMOVPCB_CALL: 679 case ARM::BL_PUSHLR: 680 case ARM::BLXi: 681 case ARM::TCRETURNdi: 682 case ARM::TAILJMPd: 683 case ARM::SVC: 684 case ARM::HVC: 685 case ARM::TPsoft: 686 case ARM::tTAILJMPd: 687 case ARM::t2SMC: 688 case ARM::t2HVC: 689 case ARM::tBL: 690 case ARM::tBLXi: 691 case ARM::tBL_PUSHLR: 692 case ARM::tTAILJMPdND: 693 case ARM::tSVC: 694 case ARM::tTPsoft: 695 assert(MI.isCall(MachineInstr::IgnoreBundle)); 696 return false; 697 } 698 assert(!MI.isCall(MachineInstr::IgnoreBundle)); 699 return false; 700 } 701 702 static inline bool isIndirectControlFlowNotComingBack(const MachineInstr &MI) { 703 int opc = MI.getOpcode(); 704 return MI.isReturn() || isIndirectBranchOpcode(MI.getOpcode()) || 705 isJumpTableBranchOpcode(opc); 706 } 707 708 static inline bool isSpeculationBarrierEndBBOpcode(int Opc) { 709 return Opc == ARM::SpeculationBarrierISBDSBEndBB || 710 Opc == ARM::SpeculationBarrierSBEndBB || 711 Opc == ARM::t2SpeculationBarrierISBDSBEndBB || 712 Opc == ARM::t2SpeculationBarrierSBEndBB; 713 } 714 715 static inline bool isPopOpcode(int Opc) { 716 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET || 717 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD || 718 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD; 719 } 720 721 static inline bool isPushOpcode(int Opc) { 722 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD || 723 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD; 724 } 725 726 static inline bool isSubImmOpcode(int Opc) { 727 return Opc == ARM::SUBri || 728 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 || 729 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 || 730 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri; 731 } 732 733 static inline bool isMovRegOpcode(int Opc) { 734 return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr; 735 } 736 /// isValidCoprocessorNumber - decide whether an explicit coprocessor 737 /// number is legal in generic instructions like CDP. The answer can 738 /// vary with the subtarget. 739 static inline bool isValidCoprocessorNumber(unsigned Num, 740 const FeatureBitset& featureBits) { 741 // In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the 742 // coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is 743 // useful for code which is shared with older architectures which do not know 744 // the new VFP/NEON mnemonics. 745 746 // Armv8-A disallows everything *other* than 111x (CP14 and CP15). 747 if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE) 748 return false; 749 750 // Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15) 751 // which clash with MVE. 752 if (featureBits[ARM::HasV8_1MMainlineOps] && 753 ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE)) 754 return false; 755 756 return true; 757 } 758 759 /// getInstrPredicate - If instruction is predicated, returns its predicate 760 /// condition, otherwise returns AL. It also returns the condition code 761 /// register by reference. 762 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg); 763 764 unsigned getMatchingCondBranchOpcode(unsigned Opc); 765 766 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether 767 /// the instruction is encoded with an 'S' bit is determined by the optional 768 /// CPSR def operand. 769 unsigned convertAddSubFlagsOpcode(unsigned OldOpc); 770 771 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of 772 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2 773 /// code. 774 void emitARMRegPlusImmediate(MachineBasicBlock &MBB, 775 MachineBasicBlock::iterator &MBBI, 776 const DebugLoc &dl, Register DestReg, 777 Register BaseReg, int NumBytes, 778 ARMCC::CondCodes Pred, Register PredReg, 779 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 780 781 void emitT2RegPlusImmediate(MachineBasicBlock &MBB, 782 MachineBasicBlock::iterator &MBBI, 783 const DebugLoc &dl, Register DestReg, 784 Register BaseReg, int NumBytes, 785 ARMCC::CondCodes Pred, Register PredReg, 786 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 787 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 788 MachineBasicBlock::iterator &MBBI, 789 const DebugLoc &dl, Register DestReg, 790 Register BaseReg, int NumBytes, 791 const TargetInstrInfo &TII, 792 const ARMBaseRegisterInfo &MRI, 793 unsigned MIFlags = 0); 794 795 /// Tries to add registers to the reglist of a given base-updating 796 /// push/pop instruction to adjust the stack by an additional 797 /// NumBytes. This can save a few bytes per function in code-size, but 798 /// obviously generates more memory traffic. As such, it only takes 799 /// effect in functions being optimised for size. 800 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, 801 MachineFunction &MF, MachineInstr *MI, 802 unsigned NumBytes); 803 804 /// rewriteARMFrameIndex / rewriteT2FrameIndex - 805 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the 806 /// offset could not be handled directly in MI, and return the left-over 807 /// portion by reference. 808 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 809 Register FrameReg, int &Offset, 810 const ARMBaseInstrInfo &TII); 811 812 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 813 Register FrameReg, int &Offset, 814 const ARMBaseInstrInfo &TII, 815 const TargetRegisterInfo *TRI); 816 817 /// Return true if Reg is defd between From and To 818 bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From, 819 MachineBasicBlock::iterator To, 820 const TargetRegisterInfo *TRI); 821 822 /// Search backwards from a tBcc to find a tCMPi8 against 0, meaning 823 /// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found. 824 MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br, 825 const TargetRegisterInfo *TRI); 826 827 void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB); 828 void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg); 829 830 void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond); 831 void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond, 832 unsigned Inactive); 833 834 /// Returns the number of instructions required to materialize the given 835 /// constant in a register, or 3 if a literal pool load is needed. 836 /// If ForCodesize is specified, an approximate cost in bytes is returned. 837 unsigned ConstantMaterializationCost(unsigned Val, 838 const ARMSubtarget *Subtarget, 839 bool ForCodesize = false); 840 841 /// Returns true if Val1 has a lower Constant Materialization Cost than Val2. 842 /// Uses the cost from ConstantMaterializationCost, first with ForCodesize as 843 /// specified. If the scores are equal, return the comparison for !ForCodesize. 844 bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2, 845 const ARMSubtarget *Subtarget, 846 bool ForCodesize = false); 847 848 // Return the immediate if this is ADDri or SUBri, scaled as appropriate. 849 // Returns 0 for unknown instructions. 850 inline int getAddSubImmediate(MachineInstr &MI) { 851 int Scale = 1; 852 unsigned ImmOp; 853 switch (MI.getOpcode()) { 854 case ARM::t2ADDri: 855 ImmOp = 2; 856 break; 857 case ARM::t2SUBri: 858 case ARM::t2SUBri12: 859 ImmOp = 2; 860 Scale = -1; 861 break; 862 case ARM::tSUBi3: 863 case ARM::tSUBi8: 864 ImmOp = 3; 865 Scale = -1; 866 break; 867 default: 868 return 0; 869 } 870 return Scale * MI.getOperand(ImmOp).getImm(); 871 } 872 873 // Given a memory access Opcode, check that the give Imm would be a valid Offset 874 // for this instruction using its addressing mode. 875 inline bool isLegalAddressImm(unsigned Opcode, int Imm, 876 const TargetInstrInfo *TII) { 877 const MCInstrDesc &Desc = TII->get(Opcode); 878 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 879 switch (AddrMode) { 880 case ARMII::AddrModeT2_i7: 881 return std::abs(Imm) < (((1 << 7) * 1) - 1); 882 case ARMII::AddrModeT2_i7s2: 883 return std::abs(Imm) < (((1 << 7) * 2) - 1) && Imm % 2 == 0; 884 case ARMII::AddrModeT2_i7s4: 885 return std::abs(Imm) < (((1 << 7) * 4) - 1) && Imm % 4 == 0; 886 case ARMII::AddrModeT2_i8: 887 return std::abs(Imm) < (((1 << 8) * 1) - 1); 888 case ARMII::AddrMode2: 889 return std::abs(Imm) < (((1 << 12) * 1) - 1); 890 case ARMII::AddrModeT2_i12: 891 return Imm >= 0 && Imm < (((1 << 12) * 1) - 1); 892 case ARMII::AddrModeT2_i8s4: 893 return std::abs(Imm) < (((1 << 8) * 4) - 1) && Imm % 4 == 0; 894 default: 895 llvm_unreachable("Unhandled Addressing mode"); 896 } 897 } 898 899 // Return true if the given intrinsic is a gather 900 inline bool isGather(IntrinsicInst *IntInst) { 901 if (IntInst == nullptr) 902 return false; 903 unsigned IntrinsicID = IntInst->getIntrinsicID(); 904 return (IntrinsicID == Intrinsic::masked_gather || 905 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base || 906 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_predicated || 907 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb || 908 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated || 909 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset || 910 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated); 911 } 912 913 // Return true if the given intrinsic is a scatter 914 inline bool isScatter(IntrinsicInst *IntInst) { 915 if (IntInst == nullptr) 916 return false; 917 unsigned IntrinsicID = IntInst->getIntrinsicID(); 918 return (IntrinsicID == Intrinsic::masked_scatter || 919 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base || 920 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_predicated || 921 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb || 922 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb_predicated || 923 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset || 924 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated); 925 } 926 927 // Return true if the given intrinsic is a gather or scatter 928 inline bool isGatherScatter(IntrinsicInst *IntInst) { 929 if (IntInst == nullptr) 930 return false; 931 return isGather(IntInst) || isScatter(IntInst); 932 } 933 934 unsigned getBLXOpcode(const MachineFunction &MF); 935 unsigned gettBLXrOpcode(const MachineFunction &MF); 936 unsigned getBLXpredOpcode(const MachineFunction &MF); 937 938 } // end namespace llvm 939 940 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H 941