xref: /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ARMAsmPrinter.cpp (revision 7ef62cebc2f965b0f640263e179276928885e33d)
1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to GAS-format ARM assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMAsmPrinter.h"
15 #include "ARM.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMTargetMachine.h"
19 #include "ARMTargetObjectFile.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "MCTargetDesc/ARMInstPrinter.h"
22 #include "MCTargetDesc/ARMMCExpr.h"
23 #include "TargetInfo/ARMTargetInfo.h"
24 #include "llvm/ADT/SmallString.h"
25 #include "llvm/BinaryFormat/COFF.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/Mangler.h"
32 #include "llvm/IR/Module.h"
33 #include "llvm/IR/Type.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCAssembler.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCELFStreamer.h"
38 #include "llvm/MC/MCInst.h"
39 #include "llvm/MC/MCInstBuilder.h"
40 #include "llvm/MC/MCObjectStreamer.h"
41 #include "llvm/MC/MCStreamer.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/MC/TargetRegistry.h"
44 #include "llvm/Support/ARMBuildAttributes.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/TargetParser.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetMachine.h"
50 using namespace llvm;
51 
52 #define DEBUG_TYPE "asm-printer"
53 
54 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
55                              std::unique_ptr<MCStreamer> Streamer)
56     : AsmPrinter(TM, std::move(Streamer)), Subtarget(nullptr), AFI(nullptr),
57       MCP(nullptr), InConstantPool(false), OptimizationGoals(-1) {}
58 
59 void ARMAsmPrinter::emitFunctionBodyEnd() {
60   // Make sure to terminate any constant pools that were at the end
61   // of the function.
62   if (!InConstantPool)
63     return;
64   InConstantPool = false;
65   OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
66 }
67 
68 void ARMAsmPrinter::emitFunctionEntryLabel() {
69   if (AFI->isThumbFunction()) {
70     OutStreamer->emitAssemblerFlag(MCAF_Code16);
71     OutStreamer->emitThumbFunc(CurrentFnSym);
72   } else {
73     OutStreamer->emitAssemblerFlag(MCAF_Code32);
74   }
75 
76   // Emit symbol for CMSE non-secure entry point
77   if (AFI->isCmseNSEntryFunction()) {
78     MCSymbol *S =
79         OutContext.getOrCreateSymbol("__acle_se_" + CurrentFnSym->getName());
80     emitLinkage(&MF->getFunction(), S);
81     OutStreamer->emitSymbolAttribute(S, MCSA_ELF_TypeFunction);
82     OutStreamer->emitLabel(S);
83   }
84   AsmPrinter::emitFunctionEntryLabel();
85 }
86 
87 void ARMAsmPrinter::emitXXStructor(const DataLayout &DL, const Constant *CV) {
88   uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType());
89   assert(Size && "C++ constructor pointer had zero size!");
90 
91   const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
92   assert(GV && "C++ constructor pointer was not a GlobalValue!");
93 
94   const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
95                                                            ARMII::MO_NO_FLAG),
96                                             (Subtarget->isTargetELF()
97                                              ? MCSymbolRefExpr::VK_ARM_TARGET1
98                                              : MCSymbolRefExpr::VK_None),
99                                             OutContext);
100 
101   OutStreamer->emitValue(E, Size);
102 }
103 
104 void ARMAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
105   if (PromotedGlobals.count(GV))
106     // The global was promoted into a constant pool. It should not be emitted.
107     return;
108   AsmPrinter::emitGlobalVariable(GV);
109 }
110 
111 /// runOnMachineFunction - This uses the emitInstruction()
112 /// method to print assembly for each instruction.
113 ///
114 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
115   AFI = MF.getInfo<ARMFunctionInfo>();
116   MCP = MF.getConstantPool();
117   Subtarget = &MF.getSubtarget<ARMSubtarget>();
118 
119   SetupMachineFunction(MF);
120   const Function &F = MF.getFunction();
121   const TargetMachine& TM = MF.getTarget();
122 
123   // Collect all globals that had their storage promoted to a constant pool.
124   // Functions are emitted before variables, so this accumulates promoted
125   // globals from all functions in PromotedGlobals.
126   for (const auto *GV : AFI->getGlobalsPromotedToConstantPool())
127     PromotedGlobals.insert(GV);
128 
129   // Calculate this function's optimization goal.
130   unsigned OptimizationGoal;
131   if (F.hasOptNone())
132     // For best debugging illusion, speed and small size sacrificed
133     OptimizationGoal = 6;
134   else if (F.hasMinSize())
135     // Aggressively for small size, speed and debug illusion sacrificed
136     OptimizationGoal = 4;
137   else if (F.hasOptSize())
138     // For small size, but speed and debugging illusion preserved
139     OptimizationGoal = 3;
140   else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
141     // Aggressively for speed, small size and debug illusion sacrificed
142     OptimizationGoal = 2;
143   else if (TM.getOptLevel() > CodeGenOpt::None)
144     // For speed, but small size and good debug illusion preserved
145     OptimizationGoal = 1;
146   else // TM.getOptLevel() == CodeGenOpt::None
147     // For good debugging, but speed and small size preserved
148     OptimizationGoal = 5;
149 
150   // Combine a new optimization goal with existing ones.
151   if (OptimizationGoals == -1) // uninitialized goals
152     OptimizationGoals = OptimizationGoal;
153   else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
154     OptimizationGoals = 0;
155 
156   if (Subtarget->isTargetCOFF()) {
157     bool Internal = F.hasInternalLinkage();
158     COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
159                                             : COFF::IMAGE_SYM_CLASS_EXTERNAL;
160     int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
161 
162     OutStreamer->beginCOFFSymbolDef(CurrentFnSym);
163     OutStreamer->emitCOFFSymbolStorageClass(Scl);
164     OutStreamer->emitCOFFSymbolType(Type);
165     OutStreamer->endCOFFSymbolDef();
166   }
167 
168   // Emit the rest of the function body.
169   emitFunctionBody();
170 
171   // Emit the XRay table for this function.
172   emitXRayTable();
173 
174   // If we need V4T thumb mode Register Indirect Jump pads, emit them.
175   // These are created per function, rather than per TU, since it's
176   // relatively easy to exceed the thumb branch range within a TU.
177   if (! ThumbIndirectPads.empty()) {
178     OutStreamer->emitAssemblerFlag(MCAF_Code16);
179     emitAlignment(Align(2));
180     for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
181       OutStreamer->emitLabel(TIP.second);
182       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
183         .addReg(TIP.first)
184         // Add predicate operands.
185         .addImm(ARMCC::AL)
186         .addReg(0));
187     }
188     ThumbIndirectPads.clear();
189   }
190 
191   // We didn't modify anything.
192   return false;
193 }
194 
195 void ARMAsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
196                                        raw_ostream &O) {
197   assert(MO.isGlobal() && "caller should check MO.isGlobal");
198   unsigned TF = MO.getTargetFlags();
199   if (TF & ARMII::MO_LO16)
200     O << ":lower16:";
201   else if (TF & ARMII::MO_HI16)
202     O << ":upper16:";
203   GetARMGVSymbol(MO.getGlobal(), TF)->print(O, MAI);
204   printOffset(MO.getOffset(), O);
205 }
206 
207 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
208                                  raw_ostream &O) {
209   const MachineOperand &MO = MI->getOperand(OpNum);
210 
211   switch (MO.getType()) {
212   default: llvm_unreachable("<unknown operand type>");
213   case MachineOperand::MO_Register: {
214     Register Reg = MO.getReg();
215     assert(Reg.isPhysical());
216     assert(!MO.getSubReg() && "Subregs should be eliminated!");
217     if(ARM::GPRPairRegClass.contains(Reg)) {
218       const MachineFunction &MF = *MI->getParent()->getParent();
219       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
220       Reg = TRI->getSubReg(Reg, ARM::gsub_0);
221     }
222     O << ARMInstPrinter::getRegisterName(Reg);
223     break;
224   }
225   case MachineOperand::MO_Immediate: {
226     O << '#';
227     unsigned TF = MO.getTargetFlags();
228     if (TF == ARMII::MO_LO16)
229       O << ":lower16:";
230     else if (TF == ARMII::MO_HI16)
231       O << ":upper16:";
232     O << MO.getImm();
233     break;
234   }
235   case MachineOperand::MO_MachineBasicBlock:
236     MO.getMBB()->getSymbol()->print(O, MAI);
237     return;
238   case MachineOperand::MO_GlobalAddress: {
239     PrintSymbolOperand(MO, O);
240     break;
241   }
242   case MachineOperand::MO_ConstantPoolIndex:
243     if (Subtarget->genExecuteOnly())
244       llvm_unreachable("execute-only should not generate constant pools");
245     GetCPISymbol(MO.getIndex())->print(O, MAI);
246     break;
247   }
248 }
249 
250 MCSymbol *ARMAsmPrinter::GetCPISymbol(unsigned CPID) const {
251   // The AsmPrinter::GetCPISymbol superclass method tries to use CPID as
252   // indexes in MachineConstantPool, which isn't in sync with indexes used here.
253   const DataLayout &DL = getDataLayout();
254   return OutContext.getOrCreateSymbol(Twine(DL.getPrivateGlobalPrefix()) +
255                                       "CPI" + Twine(getFunctionNumber()) + "_" +
256                                       Twine(CPID));
257 }
258 
259 //===--------------------------------------------------------------------===//
260 
261 MCSymbol *ARMAsmPrinter::
262 GetARMJTIPICJumpTableLabel(unsigned uid) const {
263   const DataLayout &DL = getDataLayout();
264   SmallString<60> Name;
265   raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
266                             << getFunctionNumber() << '_' << uid;
267   return OutContext.getOrCreateSymbol(Name);
268 }
269 
270 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
271                                     const char *ExtraCode, raw_ostream &O) {
272   // Does this asm operand have a single letter operand modifier?
273   if (ExtraCode && ExtraCode[0]) {
274     if (ExtraCode[1] != 0) return true; // Unknown modifier.
275 
276     switch (ExtraCode[0]) {
277     default:
278       // See if this is a generic print operand
279       return AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
280     case 'P': // Print a VFP double precision register.
281     case 'q': // Print a NEON quad precision register.
282       printOperand(MI, OpNum, O);
283       return false;
284     case 'y': // Print a VFP single precision register as indexed double.
285       if (MI->getOperand(OpNum).isReg()) {
286         MCRegister Reg = MI->getOperand(OpNum).getReg().asMCReg();
287         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
288         // Find the 'd' register that has this 's' register as a sub-register,
289         // and determine the lane number.
290         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
291           if (!ARM::DPRRegClass.contains(*SR))
292             continue;
293           bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
294           O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
295           return false;
296         }
297       }
298       return true;
299     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
300       if (!MI->getOperand(OpNum).isImm())
301         return true;
302       O << ~(MI->getOperand(OpNum).getImm());
303       return false;
304     case 'L': // The low 16 bits of an immediate constant.
305       if (!MI->getOperand(OpNum).isImm())
306         return true;
307       O << (MI->getOperand(OpNum).getImm() & 0xffff);
308       return false;
309     case 'M': { // A register range suitable for LDM/STM.
310       if (!MI->getOperand(OpNum).isReg())
311         return true;
312       const MachineOperand &MO = MI->getOperand(OpNum);
313       Register RegBegin = MO.getReg();
314       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
315       // already got the operands in registers that are operands to the
316       // inline asm statement.
317       O << "{";
318       if (ARM::GPRPairRegClass.contains(RegBegin)) {
319         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
320         Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
321         O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
322         RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
323       }
324       O << ARMInstPrinter::getRegisterName(RegBegin);
325 
326       // FIXME: The register allocator not only may not have given us the
327       // registers in sequence, but may not be in ascending registers. This
328       // will require changes in the register allocator that'll need to be
329       // propagated down here if the operands change.
330       unsigned RegOps = OpNum + 1;
331       while (MI->getOperand(RegOps).isReg()) {
332         O << ", "
333           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
334         RegOps++;
335       }
336 
337       O << "}";
338 
339       return false;
340     }
341     case 'R': // The most significant register of a pair.
342     case 'Q': { // The least significant register of a pair.
343       if (OpNum == 0)
344         return true;
345       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
346       if (!FlagsOP.isImm())
347         return true;
348       unsigned Flags = FlagsOP.getImm();
349 
350       // This operand may not be the one that actually provides the register. If
351       // it's tied to a previous one then we should refer instead to that one
352       // for registers and their classes.
353       unsigned TiedIdx;
354       if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
355         for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
356           unsigned OpFlags = MI->getOperand(OpNum).getImm();
357           OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
358         }
359         Flags = MI->getOperand(OpNum).getImm();
360 
361         // Later code expects OpNum to be pointing at the register rather than
362         // the flags.
363         OpNum += 1;
364       }
365 
366       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
367       unsigned RC;
368       bool FirstHalf;
369       const ARMBaseTargetMachine &ATM =
370         static_cast<const ARMBaseTargetMachine &>(TM);
371 
372       // 'Q' should correspond to the low order register and 'R' to the high
373       // order register.  Whether this corresponds to the upper or lower half
374       // depends on the endianess mode.
375       if (ExtraCode[0] == 'Q')
376         FirstHalf = ATM.isLittleEndian();
377       else
378         // ExtraCode[0] == 'R'.
379         FirstHalf = !ATM.isLittleEndian();
380       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
381       if (InlineAsm::hasRegClassConstraint(Flags, RC) &&
382           ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {
383         if (NumVals != 1)
384           return true;
385         const MachineOperand &MO = MI->getOperand(OpNum);
386         if (!MO.isReg())
387           return true;
388         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
389         Register Reg =
390             TRI->getSubReg(MO.getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1);
391         O << ARMInstPrinter::getRegisterName(Reg);
392         return false;
393       }
394       if (NumVals != 2)
395         return true;
396       unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
397       if (RegOp >= MI->getNumOperands())
398         return true;
399       const MachineOperand &MO = MI->getOperand(RegOp);
400       if (!MO.isReg())
401         return true;
402       Register Reg = MO.getReg();
403       O << ARMInstPrinter::getRegisterName(Reg);
404       return false;
405     }
406 
407     case 'e': // The low doubleword register of a NEON quad register.
408     case 'f': { // The high doubleword register of a NEON quad register.
409       if (!MI->getOperand(OpNum).isReg())
410         return true;
411       Register Reg = MI->getOperand(OpNum).getReg();
412       if (!ARM::QPRRegClass.contains(Reg))
413         return true;
414       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
415       Register SubReg =
416           TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1);
417       O << ARMInstPrinter::getRegisterName(SubReg);
418       return false;
419     }
420 
421     // This modifier is not yet supported.
422     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
423       return true;
424     case 'H': { // The highest-numbered register of a pair.
425       const MachineOperand &MO = MI->getOperand(OpNum);
426       if (!MO.isReg())
427         return true;
428       const MachineFunction &MF = *MI->getParent()->getParent();
429       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
430       Register Reg = MO.getReg();
431       if(!ARM::GPRPairRegClass.contains(Reg))
432         return false;
433       Reg = TRI->getSubReg(Reg, ARM::gsub_1);
434       O << ARMInstPrinter::getRegisterName(Reg);
435       return false;
436     }
437     }
438   }
439 
440   printOperand(MI, OpNum, O);
441   return false;
442 }
443 
444 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
445                                           unsigned OpNum, const char *ExtraCode,
446                                           raw_ostream &O) {
447   // Does this asm operand have a single letter operand modifier?
448   if (ExtraCode && ExtraCode[0]) {
449     if (ExtraCode[1] != 0) return true; // Unknown modifier.
450 
451     switch (ExtraCode[0]) {
452       case 'A': // A memory operand for a VLD1/VST1 instruction.
453       default: return true;  // Unknown modifier.
454       case 'm': // The base register of a memory operand.
455         if (!MI->getOperand(OpNum).isReg())
456           return true;
457         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
458         return false;
459     }
460   }
461 
462   const MachineOperand &MO = MI->getOperand(OpNum);
463   assert(MO.isReg() && "unexpected inline asm memory operand");
464   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
465   return false;
466 }
467 
468 static bool isThumb(const MCSubtargetInfo& STI) {
469   return STI.getFeatureBits()[ARM::ModeThumb];
470 }
471 
472 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
473                                      const MCSubtargetInfo *EndInfo) const {
474   // If either end mode is unknown (EndInfo == NULL) or different than
475   // the start mode, then restore the start mode.
476   const bool WasThumb = isThumb(StartInfo);
477   if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
478     OutStreamer->emitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
479   }
480 }
481 
482 void ARMAsmPrinter::emitStartOfAsmFile(Module &M) {
483   const Triple &TT = TM.getTargetTriple();
484   // Use unified assembler syntax.
485   OutStreamer->emitAssemblerFlag(MCAF_SyntaxUnified);
486 
487   // Emit ARM Build Attributes
488   if (TT.isOSBinFormatELF())
489     emitAttributes();
490 
491   // Use the triple's architecture and subarchitecture to determine
492   // if we're thumb for the purposes of the top level code16 assembler
493   // flag.
494   if (!M.getModuleInlineAsm().empty() && TT.isThumb())
495     OutStreamer->emitAssemblerFlag(MCAF_Code16);
496 }
497 
498 static void
499 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
500                          MachineModuleInfoImpl::StubValueTy &MCSym) {
501   // L_foo$stub:
502   OutStreamer.emitLabel(StubLabel);
503   //   .indirect_symbol _foo
504   OutStreamer.emitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
505 
506   if (MCSym.getInt())
507     // External to current translation unit.
508     OutStreamer.emitIntValue(0, 4/*size*/);
509   else
510     // Internal to current translation unit.
511     //
512     // When we place the LSDA into the TEXT section, the type info
513     // pointers need to be indirect and pc-rel. We accomplish this by
514     // using NLPs; however, sometimes the types are local to the file.
515     // We need to fill in the value for the NLP in those cases.
516     OutStreamer.emitValue(
517         MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
518         4 /*size*/);
519 }
520 
521 
522 void ARMAsmPrinter::emitEndOfAsmFile(Module &M) {
523   const Triple &TT = TM.getTargetTriple();
524   if (TT.isOSBinFormatMachO()) {
525     // All darwin targets use mach-o.
526     const TargetLoweringObjectFileMachO &TLOFMacho =
527       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
528     MachineModuleInfoMachO &MMIMacho =
529       MMI->getObjFileInfo<MachineModuleInfoMachO>();
530 
531     // Output non-lazy-pointers for external and common global variables.
532     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
533 
534     if (!Stubs.empty()) {
535       // Switch with ".non_lazy_symbol_pointer" directive.
536       OutStreamer->switchSection(TLOFMacho.getNonLazySymbolPointerSection());
537       emitAlignment(Align(4));
538 
539       for (auto &Stub : Stubs)
540         emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
541 
542       Stubs.clear();
543       OutStreamer->addBlankLine();
544     }
545 
546     Stubs = MMIMacho.GetThreadLocalGVStubList();
547     if (!Stubs.empty()) {
548       // Switch with ".non_lazy_symbol_pointer" directive.
549       OutStreamer->switchSection(TLOFMacho.getThreadLocalPointerSection());
550       emitAlignment(Align(4));
551 
552       for (auto &Stub : Stubs)
553         emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
554 
555       Stubs.clear();
556       OutStreamer->addBlankLine();
557     }
558 
559     // Funny Darwin hack: This flag tells the linker that no global symbols
560     // contain code that falls through to other global symbols (e.g. the obvious
561     // implementation of multiple entry points).  If this doesn't occur, the
562     // linker can safely perform dead code stripping.  Since LLVM never
563     // generates code that does this, it is always safe to set.
564     OutStreamer->emitAssemblerFlag(MCAF_SubsectionsViaSymbols);
565   }
566 
567   // The last attribute to be emitted is ABI_optimization_goals
568   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
569   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
570 
571   if (OptimizationGoals > 0 &&
572       (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
573        Subtarget->isTargetMuslAEABI()))
574     ATS.emitAttribute(ARMBuildAttrs::ABI_optimization_goals, OptimizationGoals);
575   OptimizationGoals = -1;
576 
577   ATS.finishAttributeSection();
578 }
579 
580 //===----------------------------------------------------------------------===//
581 // Helper routines for emitStartOfAsmFile() and emitEndOfAsmFile()
582 // FIXME:
583 // The following seem like one-off assembler flags, but they actually need
584 // to appear in the .ARM.attributes section in ELF.
585 // Instead of subclassing the MCELFStreamer, we do the work here.
586 
587  // Returns true if all functions have the same function attribute value.
588  // It also returns true when the module has no functions.
589 static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr,
590                                                StringRef Value) {
591    return !any_of(M, [&](const Function &F) {
592        return F.getFnAttribute(Attr).getValueAsString() != Value;
593    });
594 }
595 // Returns true if all functions have the same denormal mode.
596 // It also returns true when the module has no functions.
597 static bool checkDenormalAttributeConsistency(const Module &M,
598                                               StringRef Attr,
599                                               DenormalMode Value) {
600   return !any_of(M, [&](const Function &F) {
601     StringRef AttrVal = F.getFnAttribute(Attr).getValueAsString();
602     return parseDenormalFPAttribute(AttrVal) != Value;
603   });
604 }
605 
606 void ARMAsmPrinter::emitAttributes() {
607   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
608   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
609 
610   ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
611 
612   ATS.switchVendor("aeabi");
613 
614   // Compute ARM ELF Attributes based on the default subtarget that
615   // we'd have constructed. The existing ARM behavior isn't LTO clean
616   // anyhow.
617   // FIXME: For ifunc related functions we could iterate over and look
618   // for a feature string that doesn't match the default one.
619   const Triple &TT = TM.getTargetTriple();
620   StringRef CPU = TM.getTargetCPU();
621   StringRef FS = TM.getTargetFeatureString();
622   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
623   if (!FS.empty()) {
624     if (!ArchFS.empty())
625       ArchFS = (Twine(ArchFS) + "," + FS).str();
626     else
627       ArchFS = std::string(FS);
628   }
629   const ARMBaseTargetMachine &ATM =
630       static_cast<const ARMBaseTargetMachine &>(TM);
631   const ARMSubtarget STI(TT, std::string(CPU), ArchFS, ATM,
632                          ATM.isLittleEndian());
633 
634   // Emit build attributes for the available hardware.
635   ATS.emitTargetAttributes(STI);
636 
637   // RW data addressing.
638   if (isPositionIndependent()) {
639     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
640                       ARMBuildAttrs::AddressRWPCRel);
641   } else if (STI.isRWPI()) {
642     // RWPI specific attributes.
643     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
644                       ARMBuildAttrs::AddressRWSBRel);
645   }
646 
647   // RO data addressing.
648   if (isPositionIndependent() || STI.isROPI()) {
649     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
650                       ARMBuildAttrs::AddressROPCRel);
651   }
652 
653   // GOT use.
654   if (isPositionIndependent()) {
655     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
656                       ARMBuildAttrs::AddressGOT);
657   } else {
658     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
659                       ARMBuildAttrs::AddressDirect);
660   }
661 
662   // Set FP Denormals.
663   if (checkDenormalAttributeConsistency(*MMI->getModule(), "denormal-fp-math",
664                                         DenormalMode::getPreserveSign()))
665     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
666                       ARMBuildAttrs::PreserveFPSign);
667   else if (checkDenormalAttributeConsistency(*MMI->getModule(),
668                                              "denormal-fp-math",
669                                              DenormalMode::getPositiveZero()))
670     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
671                       ARMBuildAttrs::PositiveZero);
672   else if (!TM.Options.UnsafeFPMath)
673     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
674                       ARMBuildAttrs::IEEEDenormals);
675   else {
676     if (!STI.hasVFP2Base()) {
677       // When the target doesn't have an FPU (by design or
678       // intention), the assumptions made on the software support
679       // mirror that of the equivalent hardware support *if it
680       // existed*. For v7 and better we indicate that denormals are
681       // flushed preserving sign, and for V6 we indicate that
682       // denormals are flushed to positive zero.
683       if (STI.hasV7Ops())
684         ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
685                           ARMBuildAttrs::PreserveFPSign);
686     } else if (STI.hasVFP3Base()) {
687       // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
688       // the sign bit of the zero matches the sign bit of the input or
689       // result that is being flushed to zero.
690       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
691                         ARMBuildAttrs::PreserveFPSign);
692     }
693     // For VFPv2 implementations it is implementation defined as
694     // to whether denormals are flushed to positive zero or to
695     // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
696     // LLVM has chosen to flush this to positive zero (most likely for
697     // GCC compatibility), so that's the chosen value here (the
698     // absence of its emission implies zero).
699   }
700 
701   // Set FP exceptions and rounding
702   if (checkFunctionsAttributeConsistency(*MMI->getModule(),
703                                          "no-trapping-math", "true") ||
704       TM.Options.NoTrappingFPMath)
705     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
706                       ARMBuildAttrs::Not_Allowed);
707   else if (!TM.Options.UnsafeFPMath) {
708     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
709 
710     // If the user has permitted this code to choose the IEEE 754
711     // rounding at run-time, emit the rounding attribute.
712     if (TM.Options.HonorSignDependentRoundingFPMathOption)
713       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
714   }
715 
716   // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
717   // equivalent of GCC's -ffinite-math-only flag.
718   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
719     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
720                       ARMBuildAttrs::Allowed);
721   else
722     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
723                       ARMBuildAttrs::AllowIEEE754);
724 
725   // FIXME: add more flags to ARMBuildAttributes.h
726   // 8-bytes alignment stuff.
727   ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
728   ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
729 
730   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
731   if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
732     ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
733 
734   // FIXME: To support emitting this build attribute as GCC does, the
735   // -mfp16-format option and associated plumbing must be
736   // supported. For now the __fp16 type is exposed by default, so this
737   // attribute should be emitted with value 1.
738   ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
739                     ARMBuildAttrs::FP16FormatIEEE);
740 
741   if (const Module *SourceModule = MMI->getModule()) {
742     // ABI_PCS_wchar_t to indicate wchar_t width
743     // FIXME: There is no way to emit value 0 (wchar_t prohibited).
744     if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
745             SourceModule->getModuleFlag("wchar_size"))) {
746       int WCharWidth = WCharWidthValue->getZExtValue();
747       assert((WCharWidth == 2 || WCharWidth == 4) &&
748              "wchar_t width must be 2 or 4 bytes");
749       ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
750     }
751 
752     // ABI_enum_size to indicate enum width
753     // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
754     //        (all enums contain a value needing 32 bits to encode).
755     if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
756             SourceModule->getModuleFlag("min_enum_size"))) {
757       int EnumWidth = EnumWidthValue->getZExtValue();
758       assert((EnumWidth == 1 || EnumWidth == 4) &&
759              "Minimum enum width must be 1 or 4 bytes");
760       int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
761       ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
762     }
763 
764     auto *PACValue = mdconst::extract_or_null<ConstantInt>(
765         SourceModule->getModuleFlag("sign-return-address"));
766     if (PACValue && PACValue->getZExtValue() == 1) {
767       // If "+pacbti" is used as an architecture extension,
768       // Tag_PAC_extension is emitted in
769       // ARMTargetStreamer::emitTargetAttributes().
770       if (!STI.hasPACBTI()) {
771         ATS.emitAttribute(ARMBuildAttrs::PAC_extension,
772                           ARMBuildAttrs::AllowPACInNOPSpace);
773       }
774       ATS.emitAttribute(ARMBuildAttrs::PACRET_use, ARMBuildAttrs::PACRETUsed);
775     }
776 
777     auto *BTIValue = mdconst::extract_or_null<ConstantInt>(
778         SourceModule->getModuleFlag("branch-target-enforcement"));
779     if (BTIValue && BTIValue->getZExtValue() == 1) {
780       // If "+pacbti" is used as an architecture extension,
781       // Tag_BTI_extension is emitted in
782       // ARMTargetStreamer::emitTargetAttributes().
783       if (!STI.hasPACBTI()) {
784         ATS.emitAttribute(ARMBuildAttrs::BTI_extension,
785                           ARMBuildAttrs::AllowBTIInNOPSpace);
786       }
787       ATS.emitAttribute(ARMBuildAttrs::BTI_use, ARMBuildAttrs::BTIUsed);
788     }
789   }
790 
791   // We currently do not support using R9 as the TLS pointer.
792   if (STI.isRWPI())
793     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
794                       ARMBuildAttrs::R9IsSB);
795   else if (STI.isR9Reserved())
796     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
797                       ARMBuildAttrs::R9Reserved);
798   else
799     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
800                       ARMBuildAttrs::R9IsGPR);
801 }
802 
803 //===----------------------------------------------------------------------===//
804 
805 static MCSymbol *getBFLabel(StringRef Prefix, unsigned FunctionNumber,
806                              unsigned LabelId, MCContext &Ctx) {
807 
808   MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
809                        + "BF" + Twine(FunctionNumber) + "_" + Twine(LabelId));
810   return Label;
811 }
812 
813 static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
814                              unsigned LabelId, MCContext &Ctx) {
815 
816   MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
817                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
818   return Label;
819 }
820 
821 static MCSymbolRefExpr::VariantKind
822 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
823   switch (Modifier) {
824   case ARMCP::no_modifier:
825     return MCSymbolRefExpr::VK_None;
826   case ARMCP::TLSGD:
827     return MCSymbolRefExpr::VK_TLSGD;
828   case ARMCP::TPOFF:
829     return MCSymbolRefExpr::VK_TPOFF;
830   case ARMCP::GOTTPOFF:
831     return MCSymbolRefExpr::VK_GOTTPOFF;
832   case ARMCP::SBREL:
833     return MCSymbolRefExpr::VK_ARM_SBREL;
834   case ARMCP::GOT_PREL:
835     return MCSymbolRefExpr::VK_ARM_GOT_PREL;
836   case ARMCP::SECREL:
837     return MCSymbolRefExpr::VK_SECREL;
838   }
839   llvm_unreachable("Invalid ARMCPModifier!");
840 }
841 
842 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
843                                         unsigned char TargetFlags) {
844   if (Subtarget->isTargetMachO()) {
845     bool IsIndirect =
846         (TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
847 
848     if (!IsIndirect)
849       return getSymbol(GV);
850 
851     // FIXME: Remove this when Darwin transition to @GOT like syntax.
852     MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
853     MachineModuleInfoMachO &MMIMachO =
854       MMI->getObjFileInfo<MachineModuleInfoMachO>();
855     MachineModuleInfoImpl::StubValueTy &StubSym =
856         GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(MCSym)
857                             : MMIMachO.getGVStubEntry(MCSym);
858 
859     if (!StubSym.getPointer())
860       StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
861                                                    !GV->hasInternalLinkage());
862     return MCSym;
863   } else if (Subtarget->isTargetCOFF()) {
864     assert(Subtarget->isTargetWindows() &&
865            "Windows is the only supported COFF target");
866 
867     bool IsIndirect =
868         (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB));
869     if (!IsIndirect)
870       return getSymbol(GV);
871 
872     SmallString<128> Name;
873     if (TargetFlags & ARMII::MO_DLLIMPORT)
874       Name = "__imp_";
875     else if (TargetFlags & ARMII::MO_COFFSTUB)
876       Name = ".refptr.";
877     getNameWithPrefix(Name, GV);
878 
879     MCSymbol *MCSym = OutContext.getOrCreateSymbol(Name);
880 
881     if (TargetFlags & ARMII::MO_COFFSTUB) {
882       MachineModuleInfoCOFF &MMICOFF =
883           MMI->getObjFileInfo<MachineModuleInfoCOFF>();
884       MachineModuleInfoImpl::StubValueTy &StubSym =
885           MMICOFF.getGVStubEntry(MCSym);
886 
887       if (!StubSym.getPointer())
888         StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV), true);
889     }
890 
891     return MCSym;
892   } else if (Subtarget->isTargetELF()) {
893     return getSymbolPreferLocal(*GV);
894   }
895   llvm_unreachable("unexpected target");
896 }
897 
898 void ARMAsmPrinter::emitMachineConstantPoolValue(
899     MachineConstantPoolValue *MCPV) {
900   const DataLayout &DL = getDataLayout();
901   int Size = DL.getTypeAllocSize(MCPV->getType());
902 
903   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
904 
905   if (ACPV->isPromotedGlobal()) {
906     // This constant pool entry is actually a global whose storage has been
907     // promoted into the constant pool. This global may be referenced still
908     // by debug information, and due to the way AsmPrinter is set up, the debug
909     // info is immutable by the time we decide to promote globals to constant
910     // pools. Because of this, we need to ensure we emit a symbol for the global
911     // with private linkage (the default) so debug info can refer to it.
912     //
913     // However, if this global is promoted into several functions we must ensure
914     // we don't try and emit duplicate symbols!
915     auto *ACPC = cast<ARMConstantPoolConstant>(ACPV);
916     for (const auto *GV : ACPC->promotedGlobals()) {
917       if (!EmittedPromotedGlobalLabels.count(GV)) {
918         MCSymbol *GVSym = getSymbol(GV);
919         OutStreamer->emitLabel(GVSym);
920         EmittedPromotedGlobalLabels.insert(GV);
921       }
922     }
923     return emitGlobalConstant(DL, ACPC->getPromotedGlobalInit());
924   }
925 
926   MCSymbol *MCSym;
927   if (ACPV->isLSDA()) {
928     MCSym = getMBBExceptionSym(MF->front());
929   } else if (ACPV->isBlockAddress()) {
930     const BlockAddress *BA =
931       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
932     MCSym = GetBlockAddressSymbol(BA);
933   } else if (ACPV->isGlobalValue()) {
934     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
935 
936     // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
937     // flag the global as MO_NONLAZY.
938     unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
939     MCSym = GetARMGVSymbol(GV, TF);
940   } else if (ACPV->isMachineBasicBlock()) {
941     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
942     MCSym = MBB->getSymbol();
943   } else {
944     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
945     auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
946     MCSym = GetExternalSymbolSymbol(Sym);
947   }
948 
949   // Create an MCSymbol for the reference.
950   const MCExpr *Expr =
951     MCSymbolRefExpr::create(MCSym, getModifierVariantKind(ACPV->getModifier()),
952                             OutContext);
953 
954   if (ACPV->getPCAdjustment()) {
955     MCSymbol *PCLabel =
956         getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
957                     ACPV->getLabelId(), OutContext);
958     const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
959     PCRelExpr =
960       MCBinaryExpr::createAdd(PCRelExpr,
961                               MCConstantExpr::create(ACPV->getPCAdjustment(),
962                                                      OutContext),
963                               OutContext);
964     if (ACPV->mustAddCurrentAddress()) {
965       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
966       // label, so just emit a local label end reference that instead.
967       MCSymbol *DotSym = OutContext.createTempSymbol();
968       OutStreamer->emitLabel(DotSym);
969       const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
970       PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
971     }
972     Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
973   }
974   OutStreamer->emitValue(Expr, Size);
975 }
976 
977 void ARMAsmPrinter::emitJumpTableAddrs(const MachineInstr *MI) {
978   const MachineOperand &MO1 = MI->getOperand(1);
979   unsigned JTI = MO1.getIndex();
980 
981   // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
982   // ARM mode tables.
983   emitAlignment(Align(4));
984 
985   // Emit a label for the jump table.
986   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
987   OutStreamer->emitLabel(JTISymbol);
988 
989   // Mark the jump table as data-in-code.
990   OutStreamer->emitDataRegion(MCDR_DataRegionJT32);
991 
992   // Emit each entry of the table.
993   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
994   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
995   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
996 
997   for (MachineBasicBlock *MBB : JTBBs) {
998     // Construct an MCExpr for the entry. We want a value of the form:
999     // (BasicBlockAddr - TableBeginAddr)
1000     //
1001     // For example, a table with entries jumping to basic blocks BB0 and BB1
1002     // would look like:
1003     // LJTI_0_0:
1004     //    .word (LBB0 - LJTI_0_0)
1005     //    .word (LBB1 - LJTI_0_0)
1006     const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
1007 
1008     if (isPositionIndependent() || Subtarget->isROPI())
1009       Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
1010                                                                    OutContext),
1011                                      OutContext);
1012     // If we're generating a table of Thumb addresses in static relocation
1013     // model, we need to add one to keep interworking correctly.
1014     else if (AFI->isThumbFunction())
1015       Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(1,OutContext),
1016                                      OutContext);
1017     OutStreamer->emitValue(Expr, 4);
1018   }
1019   // Mark the end of jump table data-in-code region.
1020   OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1021 }
1022 
1023 void ARMAsmPrinter::emitJumpTableInsts(const MachineInstr *MI) {
1024   const MachineOperand &MO1 = MI->getOperand(1);
1025   unsigned JTI = MO1.getIndex();
1026 
1027   // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
1028   // ARM mode tables.
1029   emitAlignment(Align(4));
1030 
1031   // Emit a label for the jump table.
1032   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1033   OutStreamer->emitLabel(JTISymbol);
1034 
1035   // Emit each entry of the table.
1036   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1037   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1038   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1039 
1040   for (MachineBasicBlock *MBB : JTBBs) {
1041     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1042                                                           OutContext);
1043     // If this isn't a TBB or TBH, the entries are direct branch instructions.
1044     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2B)
1045         .addExpr(MBBSymbolExpr)
1046         .addImm(ARMCC::AL)
1047         .addReg(0));
1048   }
1049 }
1050 
1051 void ARMAsmPrinter::emitJumpTableTBInst(const MachineInstr *MI,
1052                                         unsigned OffsetWidth) {
1053   assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1054   const MachineOperand &MO1 = MI->getOperand(1);
1055   unsigned JTI = MO1.getIndex();
1056 
1057   if (Subtarget->isThumb1Only())
1058     emitAlignment(Align(4));
1059 
1060   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1061   OutStreamer->emitLabel(JTISymbol);
1062 
1063   // Emit each entry of the table.
1064   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1065   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1066   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1067 
1068   // Mark the jump table as data-in-code.
1069   OutStreamer->emitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1070                                                : MCDR_DataRegionJT16);
1071 
1072   for (auto *MBB : JTBBs) {
1073     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1074                                                           OutContext);
1075     // Otherwise it's an offset from the dispatch instruction. Construct an
1076     // MCExpr for the entry. We want a value of the form:
1077     // (BasicBlockAddr - TBBInstAddr + 4) / 2
1078     //
1079     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1080     // would look like:
1081     // LJTI_0_0:
1082     //    .byte (LBB0 - (LCPI0_0 + 4)) / 2
1083     //    .byte (LBB1 - (LCPI0_0 + 4)) / 2
1084     // where LCPI0_0 is a label defined just before the TBB instruction using
1085     // this table.
1086     MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1087     const MCExpr *Expr = MCBinaryExpr::createAdd(
1088         MCSymbolRefExpr::create(TBInstPC, OutContext),
1089         MCConstantExpr::create(4, OutContext), OutContext);
1090     Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1091     Expr = MCBinaryExpr::createDiv(Expr, MCConstantExpr::create(2, OutContext),
1092                                    OutContext);
1093     OutStreamer->emitValue(Expr, OffsetWidth);
1094   }
1095   // Mark the end of jump table data-in-code region. 32-bit offsets use
1096   // actual branch instructions here, so we don't mark those as a data-region
1097   // at all.
1098   OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1099 
1100   // Make sure the next instruction is 2-byte aligned.
1101   emitAlignment(Align(2));
1102 }
1103 
1104 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1105   assert(MI->getFlag(MachineInstr::FrameSetup) &&
1106       "Only instruction which are involved into frame setup code are allowed");
1107 
1108   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1109   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1110   const MachineFunction &MF = *MI->getParent()->getParent();
1111   const TargetRegisterInfo *TargetRegInfo =
1112     MF.getSubtarget().getRegisterInfo();
1113   const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
1114 
1115   Register FramePtr = TargetRegInfo->getFrameRegister(MF);
1116   unsigned Opc = MI->getOpcode();
1117   unsigned SrcReg, DstReg;
1118 
1119   switch (Opc) {
1120   case ARM::tPUSH:
1121     // special case: tPUSH does not have src/dst regs.
1122     SrcReg = DstReg = ARM::SP;
1123     break;
1124   case ARM::tLDRpci:
1125   case ARM::t2MOVi16:
1126   case ARM::t2MOVTi16:
1127     // special cases:
1128     // 1) for Thumb1 code we sometimes materialize the constant via constpool
1129     //    load.
1130     // 2) for Thumb2 execute only code we materialize the constant via
1131     //    immediate constants in 2 separate instructions (MOVW/MOVT).
1132     SrcReg = ~0U;
1133     DstReg = MI->getOperand(0).getReg();
1134     break;
1135   default:
1136     SrcReg = MI->getOperand(1).getReg();
1137     DstReg = MI->getOperand(0).getReg();
1138     break;
1139   }
1140 
1141   // Try to figure out the unwinding opcode out of src / dst regs.
1142   if (MI->mayStore()) {
1143     // Register saves.
1144     assert(DstReg == ARM::SP &&
1145            "Only stack pointer as a destination reg is supported");
1146 
1147     SmallVector<unsigned, 4> RegList;
1148     // Skip src & dst reg, and pred ops.
1149     unsigned StartOp = 2 + 2;
1150     // Use all the operands.
1151     unsigned NumOffset = 0;
1152     // Amount of SP adjustment folded into a push, before the
1153     // registers are stored (pad at higher addresses).
1154     unsigned PadBefore = 0;
1155     // Amount of SP adjustment folded into a push, after the
1156     // registers are stored (pad at lower addresses).
1157     unsigned PadAfter = 0;
1158 
1159     switch (Opc) {
1160     default:
1161       MI->print(errs());
1162       llvm_unreachable("Unsupported opcode for unwinding information");
1163     case ARM::tPUSH:
1164       // Special case here: no src & dst reg, but two extra imp ops.
1165       StartOp = 2; NumOffset = 2;
1166       [[fallthrough]];
1167     case ARM::STMDB_UPD:
1168     case ARM::t2STMDB_UPD:
1169     case ARM::VSTMDDB_UPD:
1170       assert(SrcReg == ARM::SP &&
1171              "Only stack pointer as a source reg is supported");
1172       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1173            i != NumOps; ++i) {
1174         const MachineOperand &MO = MI->getOperand(i);
1175         // Actually, there should never be any impdef stuff here. Skip it
1176         // temporary to workaround PR11902.
1177         if (MO.isImplicit())
1178           continue;
1179         // Registers, pushed as a part of folding an SP update into the
1180         // push instruction are marked as undef and should not be
1181         // restored when unwinding, because the function can modify the
1182         // corresponding stack slots.
1183         if (MO.isUndef()) {
1184           assert(RegList.empty() &&
1185                  "Pad registers must come before restored ones");
1186           unsigned Width =
1187             TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8;
1188           PadAfter += Width;
1189           continue;
1190         }
1191         // Check for registers that are remapped (for a Thumb1 prologue that
1192         // saves high registers).
1193         Register Reg = MO.getReg();
1194         if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Reg))
1195           Reg = RemappedReg;
1196         RegList.push_back(Reg);
1197       }
1198       break;
1199     case ARM::STR_PRE_IMM:
1200     case ARM::STR_PRE_REG:
1201     case ARM::t2STR_PRE:
1202       assert(MI->getOperand(2).getReg() == ARM::SP &&
1203              "Only stack pointer as a source reg is supported");
1204       if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1205         SrcReg = RemappedReg;
1206 
1207       RegList.push_back(SrcReg);
1208       break;
1209     case ARM::t2STRD_PRE:
1210       assert(MI->getOperand(3).getReg() == ARM::SP &&
1211              "Only stack pointer as a source reg is supported");
1212       SrcReg = MI->getOperand(1).getReg();
1213       if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1214         SrcReg = RemappedReg;
1215       RegList.push_back(SrcReg);
1216       SrcReg = MI->getOperand(2).getReg();
1217       if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1218         SrcReg = RemappedReg;
1219       RegList.push_back(SrcReg);
1220       PadBefore = -MI->getOperand(4).getImm() - 8;
1221       break;
1222     }
1223     if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1224       if (PadBefore)
1225         ATS.emitPad(PadBefore);
1226       ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1227       // Account for the SP adjustment, folded into the push.
1228       if (PadAfter)
1229         ATS.emitPad(PadAfter);
1230     }
1231   } else {
1232     // Changes of stack / frame pointer.
1233     if (SrcReg == ARM::SP) {
1234       int64_t Offset = 0;
1235       switch (Opc) {
1236       default:
1237         MI->print(errs());
1238         llvm_unreachable("Unsupported opcode for unwinding information");
1239       case ARM::MOVr:
1240       case ARM::tMOVr:
1241         Offset = 0;
1242         break;
1243       case ARM::ADDri:
1244       case ARM::t2ADDri:
1245       case ARM::t2ADDri12:
1246       case ARM::t2ADDspImm:
1247       case ARM::t2ADDspImm12:
1248         Offset = -MI->getOperand(2).getImm();
1249         break;
1250       case ARM::SUBri:
1251       case ARM::t2SUBri:
1252       case ARM::t2SUBri12:
1253       case ARM::t2SUBspImm:
1254       case ARM::t2SUBspImm12:
1255         Offset = MI->getOperand(2).getImm();
1256         break;
1257       case ARM::tSUBspi:
1258         Offset = MI->getOperand(2).getImm()*4;
1259         break;
1260       case ARM::tADDspi:
1261       case ARM::tADDrSPi:
1262         Offset = -MI->getOperand(2).getImm()*4;
1263         break;
1264       case ARM::tADDhirr:
1265         Offset =
1266             -AFI->EHPrologueOffsetInRegs.lookup(MI->getOperand(2).getReg());
1267         break;
1268       }
1269 
1270       if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1271         if (DstReg == FramePtr && FramePtr != ARM::SP)
1272           // Set-up of the frame pointer. Positive values correspond to "add"
1273           // instruction.
1274           ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1275         else if (DstReg == ARM::SP) {
1276           // Change of SP by an offset. Positive values correspond to "sub"
1277           // instruction.
1278           ATS.emitPad(Offset);
1279         } else {
1280           // Move of SP to a register.  Positive values correspond to an "add"
1281           // instruction.
1282           ATS.emitMovSP(DstReg, -Offset);
1283         }
1284       }
1285     } else if (DstReg == ARM::SP) {
1286       MI->print(errs());
1287       llvm_unreachable("Unsupported opcode for unwinding information");
1288     } else {
1289       int64_t Offset = 0;
1290       switch (Opc) {
1291       case ARM::tMOVr:
1292         // If a Thumb1 function spills r8-r11, we copy the values to low
1293         // registers before pushing them. Record the copy so we can emit the
1294         // correct ".save" later.
1295         AFI->EHPrologueRemappedRegs[DstReg] = SrcReg;
1296         break;
1297       case ARM::tLDRpci: {
1298         // Grab the constpool index and check, whether it corresponds to
1299         // original or cloned constpool entry.
1300         unsigned CPI = MI->getOperand(1).getIndex();
1301         const MachineConstantPool *MCP = MF.getConstantPool();
1302         if (CPI >= MCP->getConstants().size())
1303           CPI = AFI->getOriginalCPIdx(CPI);
1304         assert(CPI != -1U && "Invalid constpool index");
1305 
1306         // Derive the actual offset.
1307         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1308         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1309         Offset = cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1310         AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1311         break;
1312       }
1313       case ARM::t2MOVi16:
1314         Offset = MI->getOperand(1).getImm();
1315         AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1316         break;
1317       case ARM::t2MOVTi16:
1318         Offset = MI->getOperand(2).getImm();
1319         AFI->EHPrologueOffsetInRegs[DstReg] |= (Offset << 16);
1320         break;
1321       case ARM::t2PAC:
1322       case ARM::t2PACBTI:
1323         AFI->EHPrologueRemappedRegs[ARM::R12] = ARM::RA_AUTH_CODE;
1324         break;
1325       default:
1326         MI->print(errs());
1327         llvm_unreachable("Unsupported opcode for unwinding information");
1328       }
1329     }
1330   }
1331 }
1332 
1333 // Simple pseudo-instructions have their lowering (with expansion to real
1334 // instructions) auto-generated.
1335 #include "ARMGenMCPseudoLowering.inc"
1336 
1337 void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
1338   // TODOD FIXME: Enable feature predicate checks once all the test pass.
1339   // ARM_MC::verifyInstructionPredicates(MI->getOpcode(),
1340   //                                   getSubtargetInfo().getFeatureBits());
1341 
1342   const DataLayout &DL = getDataLayout();
1343   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1344   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1345 
1346   // If we just ended a constant pool, mark it as such.
1347   if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1348     OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1349     InConstantPool = false;
1350   }
1351 
1352   // Emit unwinding stuff for frame-related instructions
1353   if (Subtarget->isTargetEHABICompatible() &&
1354        MI->getFlag(MachineInstr::FrameSetup))
1355     EmitUnwindingInstruction(MI);
1356 
1357   // Do any auto-generated pseudo lowerings.
1358   if (emitPseudoExpansionLowering(*OutStreamer, MI))
1359     return;
1360 
1361   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1362          "Pseudo flag setting opcode should be expanded early");
1363 
1364   // Check for manual lowerings.
1365   unsigned Opc = MI->getOpcode();
1366   switch (Opc) {
1367   case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1368   case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1369   case ARM::LEApcrel:
1370   case ARM::tLEApcrel:
1371   case ARM::t2LEApcrel: {
1372     // FIXME: Need to also handle globals and externals
1373     MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1374     EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1375                                                ARM::t2LEApcrel ? ARM::t2ADR
1376                   : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1377                      : ARM::ADR))
1378       .addReg(MI->getOperand(0).getReg())
1379       .addExpr(MCSymbolRefExpr::create(CPISymbol, OutContext))
1380       // Add predicate operands.
1381       .addImm(MI->getOperand(2).getImm())
1382       .addReg(MI->getOperand(3).getReg()));
1383     return;
1384   }
1385   case ARM::LEApcrelJT:
1386   case ARM::tLEApcrelJT:
1387   case ARM::t2LEApcrelJT: {
1388     MCSymbol *JTIPICSymbol =
1389       GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1390     EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1391                                                ARM::t2LEApcrelJT ? ARM::t2ADR
1392                   : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1393                      : ARM::ADR))
1394       .addReg(MI->getOperand(0).getReg())
1395       .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
1396       // Add predicate operands.
1397       .addImm(MI->getOperand(2).getImm())
1398       .addReg(MI->getOperand(3).getReg()));
1399     return;
1400   }
1401   // Darwin call instructions are just normal call instructions with different
1402   // clobber semantics (they clobber R9).
1403   case ARM::BX_CALL: {
1404     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1405       .addReg(ARM::LR)
1406       .addReg(ARM::PC)
1407       // Add predicate operands.
1408       .addImm(ARMCC::AL)
1409       .addReg(0)
1410       // Add 's' bit operand (always reg0 for this)
1411       .addReg(0));
1412 
1413     assert(Subtarget->hasV4TOps());
1414     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
1415       .addReg(MI->getOperand(0).getReg()));
1416     return;
1417   }
1418   case ARM::tBX_CALL: {
1419     if (Subtarget->hasV5TOps())
1420       llvm_unreachable("Expected BLX to be selected for v5t+");
1421 
1422     // On ARM v4t, when doing a call from thumb mode, we need to ensure
1423     // that the saved lr has its LSB set correctly (the arch doesn't
1424     // have blx).
1425     // So here we generate a bl to a small jump pad that does bx rN.
1426     // The jump pads are emitted after the function body.
1427 
1428     Register TReg = MI->getOperand(0).getReg();
1429     MCSymbol *TRegSym = nullptr;
1430     for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
1431       if (TIP.first == TReg) {
1432         TRegSym = TIP.second;
1433         break;
1434       }
1435     }
1436 
1437     if (!TRegSym) {
1438       TRegSym = OutContext.createTempSymbol();
1439       ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1440     }
1441 
1442     // Create a link-saving branch to the Reg Indirect Jump Pad.
1443     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBL)
1444         // Predicate comes first here.
1445         .addImm(ARMCC::AL).addReg(0)
1446         .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1447     return;
1448   }
1449   case ARM::BMOVPCRX_CALL: {
1450     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1451       .addReg(ARM::LR)
1452       .addReg(ARM::PC)
1453       // Add predicate operands.
1454       .addImm(ARMCC::AL)
1455       .addReg(0)
1456       // Add 's' bit operand (always reg0 for this)
1457       .addReg(0));
1458 
1459     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1460       .addReg(ARM::PC)
1461       .addReg(MI->getOperand(0).getReg())
1462       // Add predicate operands.
1463       .addImm(ARMCC::AL)
1464       .addReg(0)
1465       // Add 's' bit operand (always reg0 for this)
1466       .addReg(0));
1467     return;
1468   }
1469   case ARM::BMOVPCB_CALL: {
1470     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1471       .addReg(ARM::LR)
1472       .addReg(ARM::PC)
1473       // Add predicate operands.
1474       .addImm(ARMCC::AL)
1475       .addReg(0)
1476       // Add 's' bit operand (always reg0 for this)
1477       .addReg(0));
1478 
1479     const MachineOperand &Op = MI->getOperand(0);
1480     const GlobalValue *GV = Op.getGlobal();
1481     const unsigned TF = Op.getTargetFlags();
1482     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1483     const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1484     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc)
1485       .addExpr(GVSymExpr)
1486       // Add predicate operands.
1487       .addImm(ARMCC::AL)
1488       .addReg(0));
1489     return;
1490   }
1491   case ARM::MOVi16_ga_pcrel:
1492   case ARM::t2MOVi16_ga_pcrel: {
1493     MCInst TmpInst;
1494     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1495     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1496 
1497     unsigned TF = MI->getOperand(1).getTargetFlags();
1498     const GlobalValue *GV = MI->getOperand(1).getGlobal();
1499     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1500     const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1501 
1502     MCSymbol *LabelSym =
1503         getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1504                     MI->getOperand(2).getImm(), OutContext);
1505     const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1506     unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1507     const MCExpr *PCRelExpr =
1508       ARMMCExpr::createLower16(MCBinaryExpr::createSub(GVSymExpr,
1509                                       MCBinaryExpr::createAdd(LabelSymExpr,
1510                                       MCConstantExpr::create(PCAdj, OutContext),
1511                                       OutContext), OutContext), OutContext);
1512       TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1513 
1514     // Add predicate operands.
1515     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1516     TmpInst.addOperand(MCOperand::createReg(0));
1517     // Add 's' bit operand (always reg0 for this)
1518     TmpInst.addOperand(MCOperand::createReg(0));
1519     EmitToStreamer(*OutStreamer, TmpInst);
1520     return;
1521   }
1522   case ARM::MOVTi16_ga_pcrel:
1523   case ARM::t2MOVTi16_ga_pcrel: {
1524     MCInst TmpInst;
1525     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1526                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
1527     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1528     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1529 
1530     unsigned TF = MI->getOperand(2).getTargetFlags();
1531     const GlobalValue *GV = MI->getOperand(2).getGlobal();
1532     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1533     const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1534 
1535     MCSymbol *LabelSym =
1536         getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1537                     MI->getOperand(3).getImm(), OutContext);
1538     const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1539     unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1540     const MCExpr *PCRelExpr =
1541         ARMMCExpr::createUpper16(MCBinaryExpr::createSub(GVSymExpr,
1542                                    MCBinaryExpr::createAdd(LabelSymExpr,
1543                                       MCConstantExpr::create(PCAdj, OutContext),
1544                                           OutContext), OutContext), OutContext);
1545       TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1546     // Add predicate operands.
1547     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1548     TmpInst.addOperand(MCOperand::createReg(0));
1549     // Add 's' bit operand (always reg0 for this)
1550     TmpInst.addOperand(MCOperand::createReg(0));
1551     EmitToStreamer(*OutStreamer, TmpInst);
1552     return;
1553   }
1554   case ARM::t2BFi:
1555   case ARM::t2BFic:
1556   case ARM::t2BFLi:
1557   case ARM::t2BFr:
1558   case ARM::t2BFLr: {
1559     // This is a Branch Future instruction.
1560 
1561     const MCExpr *BranchLabel = MCSymbolRefExpr::create(
1562         getBFLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1563                    MI->getOperand(0).getIndex(), OutContext),
1564         OutContext);
1565 
1566     auto MCInst = MCInstBuilder(Opc).addExpr(BranchLabel);
1567     if (MI->getOperand(1).isReg()) {
1568       // For BFr/BFLr
1569       MCInst.addReg(MI->getOperand(1).getReg());
1570     } else {
1571       // For BFi/BFLi/BFic
1572       const MCExpr *BranchTarget;
1573       if (MI->getOperand(1).isMBB())
1574         BranchTarget = MCSymbolRefExpr::create(
1575             MI->getOperand(1).getMBB()->getSymbol(), OutContext);
1576       else if (MI->getOperand(1).isGlobal()) {
1577         const GlobalValue *GV = MI->getOperand(1).getGlobal();
1578         BranchTarget = MCSymbolRefExpr::create(
1579             GetARMGVSymbol(GV, MI->getOperand(1).getTargetFlags()), OutContext);
1580       } else if (MI->getOperand(1).isSymbol()) {
1581         BranchTarget = MCSymbolRefExpr::create(
1582             GetExternalSymbolSymbol(MI->getOperand(1).getSymbolName()),
1583             OutContext);
1584       } else
1585         llvm_unreachable("Unhandled operand kind in Branch Future instruction");
1586 
1587       MCInst.addExpr(BranchTarget);
1588     }
1589 
1590     if (Opc == ARM::t2BFic) {
1591       const MCExpr *ElseLabel = MCSymbolRefExpr::create(
1592           getBFLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1593                      MI->getOperand(2).getIndex(), OutContext),
1594           OutContext);
1595       MCInst.addExpr(ElseLabel);
1596       MCInst.addImm(MI->getOperand(3).getImm());
1597     } else {
1598       MCInst.addImm(MI->getOperand(2).getImm())
1599           .addReg(MI->getOperand(3).getReg());
1600     }
1601 
1602     EmitToStreamer(*OutStreamer, MCInst);
1603     return;
1604   }
1605   case ARM::t2BF_LabelPseudo: {
1606     // This is a pseudo op for a label used by a branch future instruction
1607 
1608     // Emit the label.
1609     OutStreamer->emitLabel(getBFLabel(DL.getPrivateGlobalPrefix(),
1610                                        getFunctionNumber(),
1611                                        MI->getOperand(0).getIndex(), OutContext));
1612     return;
1613   }
1614   case ARM::tPICADD: {
1615     // This is a pseudo op for a label + instruction sequence, which looks like:
1616     // LPC0:
1617     //     add r0, pc
1618     // This adds the address of LPC0 to r0.
1619 
1620     // Emit the label.
1621     OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1622                                        getFunctionNumber(),
1623                                        MI->getOperand(2).getImm(), OutContext));
1624 
1625     // Form and emit the add.
1626     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1627       .addReg(MI->getOperand(0).getReg())
1628       .addReg(MI->getOperand(0).getReg())
1629       .addReg(ARM::PC)
1630       // Add predicate operands.
1631       .addImm(ARMCC::AL)
1632       .addReg(0));
1633     return;
1634   }
1635   case ARM::PICADD: {
1636     // This is a pseudo op for a label + instruction sequence, which looks like:
1637     // LPC0:
1638     //     add r0, pc, r0
1639     // This adds the address of LPC0 to r0.
1640 
1641     // Emit the label.
1642     OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1643                                        getFunctionNumber(),
1644                                        MI->getOperand(2).getImm(), OutContext));
1645 
1646     // Form and emit the add.
1647     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
1648       .addReg(MI->getOperand(0).getReg())
1649       .addReg(ARM::PC)
1650       .addReg(MI->getOperand(1).getReg())
1651       // Add predicate operands.
1652       .addImm(MI->getOperand(3).getImm())
1653       .addReg(MI->getOperand(4).getReg())
1654       // Add 's' bit operand (always reg0 for this)
1655       .addReg(0));
1656     return;
1657   }
1658   case ARM::PICSTR:
1659   case ARM::PICSTRB:
1660   case ARM::PICSTRH:
1661   case ARM::PICLDR:
1662   case ARM::PICLDRB:
1663   case ARM::PICLDRH:
1664   case ARM::PICLDRSB:
1665   case ARM::PICLDRSH: {
1666     // This is a pseudo op for a label + instruction sequence, which looks like:
1667     // LPC0:
1668     //     OP r0, [pc, r0]
1669     // The LCP0 label is referenced by a constant pool entry in order to get
1670     // a PC-relative address at the ldr instruction.
1671 
1672     // Emit the label.
1673     OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1674                                        getFunctionNumber(),
1675                                        MI->getOperand(2).getImm(), OutContext));
1676 
1677     // Form and emit the load
1678     unsigned Opcode;
1679     switch (MI->getOpcode()) {
1680     default:
1681       llvm_unreachable("Unexpected opcode!");
1682     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
1683     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
1684     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
1685     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
1686     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
1687     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
1688     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1689     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1690     }
1691     EmitToStreamer(*OutStreamer, MCInstBuilder(Opcode)
1692       .addReg(MI->getOperand(0).getReg())
1693       .addReg(ARM::PC)
1694       .addReg(MI->getOperand(1).getReg())
1695       .addImm(0)
1696       // Add predicate operands.
1697       .addImm(MI->getOperand(3).getImm())
1698       .addReg(MI->getOperand(4).getReg()));
1699 
1700     return;
1701   }
1702   case ARM::CONSTPOOL_ENTRY: {
1703     if (Subtarget->genExecuteOnly())
1704       llvm_unreachable("execute-only should not generate constant pools");
1705 
1706     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1707     /// in the function.  The first operand is the ID# for this instruction, the
1708     /// second is the index into the MachineConstantPool that this is, the third
1709     /// is the size in bytes of this constant pool entry.
1710     /// The required alignment is specified on the basic block holding this MI.
1711     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1712     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
1713 
1714     // If this is the first entry of the pool, mark it.
1715     if (!InConstantPool) {
1716       OutStreamer->emitDataRegion(MCDR_DataRegion);
1717       InConstantPool = true;
1718     }
1719 
1720     OutStreamer->emitLabel(GetCPISymbol(LabelId));
1721 
1722     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1723     if (MCPE.isMachineConstantPoolEntry())
1724       emitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1725     else
1726       emitGlobalConstant(DL, MCPE.Val.ConstVal);
1727     return;
1728   }
1729   case ARM::JUMPTABLE_ADDRS:
1730     emitJumpTableAddrs(MI);
1731     return;
1732   case ARM::JUMPTABLE_INSTS:
1733     emitJumpTableInsts(MI);
1734     return;
1735   case ARM::JUMPTABLE_TBB:
1736   case ARM::JUMPTABLE_TBH:
1737     emitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1738     return;
1739   case ARM::t2BR_JT: {
1740     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1741       .addReg(ARM::PC)
1742       .addReg(MI->getOperand(0).getReg())
1743       // Add predicate operands.
1744       .addImm(ARMCC::AL)
1745       .addReg(0));
1746     return;
1747   }
1748   case ARM::t2TBB_JT:
1749   case ARM::t2TBH_JT: {
1750     unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1751     // Lower and emit the PC label, then the instruction itself.
1752     OutStreamer->emitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1753     EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
1754                                      .addReg(MI->getOperand(0).getReg())
1755                                      .addReg(MI->getOperand(1).getReg())
1756                                      // Add predicate operands.
1757                                      .addImm(ARMCC::AL)
1758                                      .addReg(0));
1759     return;
1760   }
1761   case ARM::tTBB_JT:
1762   case ARM::tTBH_JT: {
1763 
1764     bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
1765     Register Base = MI->getOperand(0).getReg();
1766     Register Idx = MI->getOperand(1).getReg();
1767     assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
1768 
1769     // Multiply up idx if necessary.
1770     if (!Is8Bit)
1771       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri)
1772                                        .addReg(Idx)
1773                                        .addReg(ARM::CPSR)
1774                                        .addReg(Idx)
1775                                        .addImm(1)
1776                                        // Add predicate operands.
1777                                        .addImm(ARMCC::AL)
1778                                        .addReg(0));
1779 
1780     if (Base == ARM::PC) {
1781       // TBB [base, idx] =
1782       //    ADDS idx, idx, base
1783       //    LDRB idx, [idx, #4] ; or LDRH if TBH
1784       //    LSLS idx, #1
1785       //    ADDS pc, pc, idx
1786 
1787       // When using PC as the base, it's important that there is no padding
1788       // between the last ADDS and the start of the jump table. The jump table
1789       // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
1790       //
1791       // FIXME: Ideally we could vary the LDRB index based on the padding
1792       // between the sequence and jump table, however that relies on MCExprs
1793       // for load indexes which are currently not supported.
1794       OutStreamer->emitCodeAlignment(Align(4), &getSubtargetInfo());
1795       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1796                                        .addReg(Idx)
1797                                        .addReg(Idx)
1798                                        .addReg(Base)
1799                                        // Add predicate operands.
1800                                        .addImm(ARMCC::AL)
1801                                        .addReg(0));
1802 
1803       unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
1804       EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
1805                                        .addReg(Idx)
1806                                        .addReg(Idx)
1807                                        .addImm(Is8Bit ? 4 : 2)
1808                                        // Add predicate operands.
1809                                        .addImm(ARMCC::AL)
1810                                        .addReg(0));
1811     } else {
1812       // TBB [base, idx] =
1813       //    LDRB idx, [base, idx] ; or LDRH if TBH
1814       //    LSLS idx, #1
1815       //    ADDS pc, pc, idx
1816 
1817       unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
1818       EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
1819                                        .addReg(Idx)
1820                                        .addReg(Base)
1821                                        .addReg(Idx)
1822                                        // Add predicate operands.
1823                                        .addImm(ARMCC::AL)
1824                                        .addReg(0));
1825     }
1826 
1827     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri)
1828                                      .addReg(Idx)
1829                                      .addReg(ARM::CPSR)
1830                                      .addReg(Idx)
1831                                      .addImm(1)
1832                                      // Add predicate operands.
1833                                      .addImm(ARMCC::AL)
1834                                      .addReg(0));
1835 
1836     OutStreamer->emitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1837     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1838                                      .addReg(ARM::PC)
1839                                      .addReg(ARM::PC)
1840                                      .addReg(Idx)
1841                                      // Add predicate operands.
1842                                      .addImm(ARMCC::AL)
1843                                      .addReg(0));
1844     return;
1845   }
1846   case ARM::tBR_JTr:
1847   case ARM::BR_JTr: {
1848     // mov pc, target
1849     MCInst TmpInst;
1850     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1851       ARM::MOVr : ARM::tMOVr;
1852     TmpInst.setOpcode(Opc);
1853     TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1854     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1855     // Add predicate operands.
1856     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1857     TmpInst.addOperand(MCOperand::createReg(0));
1858     // Add 's' bit operand (always reg0 for this)
1859     if (Opc == ARM::MOVr)
1860       TmpInst.addOperand(MCOperand::createReg(0));
1861     EmitToStreamer(*OutStreamer, TmpInst);
1862     return;
1863   }
1864   case ARM::BR_JTm_i12: {
1865     // ldr pc, target
1866     MCInst TmpInst;
1867     TmpInst.setOpcode(ARM::LDRi12);
1868     TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1869     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1870     TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1871     // Add predicate operands.
1872     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1873     TmpInst.addOperand(MCOperand::createReg(0));
1874     EmitToStreamer(*OutStreamer, TmpInst);
1875     return;
1876   }
1877   case ARM::BR_JTm_rs: {
1878     // ldr pc, target
1879     MCInst TmpInst;
1880     TmpInst.setOpcode(ARM::LDRrs);
1881     TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1882     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1883     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1884     TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1885     // Add predicate operands.
1886     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1887     TmpInst.addOperand(MCOperand::createReg(0));
1888     EmitToStreamer(*OutStreamer, TmpInst);
1889     return;
1890   }
1891   case ARM::BR_JTadd: {
1892     // add pc, target, idx
1893     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
1894       .addReg(ARM::PC)
1895       .addReg(MI->getOperand(0).getReg())
1896       .addReg(MI->getOperand(1).getReg())
1897       // Add predicate operands.
1898       .addImm(ARMCC::AL)
1899       .addReg(0)
1900       // Add 's' bit operand (always reg0 for this)
1901       .addReg(0));
1902     return;
1903   }
1904   case ARM::SPACE:
1905     OutStreamer->emitZeros(MI->getOperand(1).getImm());
1906     return;
1907   case ARM::TRAP: {
1908     // Non-Darwin binutils don't yet support the "trap" mnemonic.
1909     // FIXME: Remove this special case when they do.
1910     if (!Subtarget->isTargetMachO()) {
1911       uint32_t Val = 0xe7ffdefeUL;
1912       OutStreamer->AddComment("trap");
1913       ATS.emitInst(Val);
1914       return;
1915     }
1916     break;
1917   }
1918   case ARM::TRAPNaCl: {
1919     uint32_t Val = 0xe7fedef0UL;
1920     OutStreamer->AddComment("trap");
1921     ATS.emitInst(Val);
1922     return;
1923   }
1924   case ARM::tTRAP: {
1925     // Non-Darwin binutils don't yet support the "trap" mnemonic.
1926     // FIXME: Remove this special case when they do.
1927     if (!Subtarget->isTargetMachO()) {
1928       uint16_t Val = 0xdefe;
1929       OutStreamer->AddComment("trap");
1930       ATS.emitInst(Val, 'n');
1931       return;
1932     }
1933     break;
1934   }
1935   case ARM::t2Int_eh_sjlj_setjmp:
1936   case ARM::t2Int_eh_sjlj_setjmp_nofp:
1937   case ARM::tInt_eh_sjlj_setjmp: {
1938     // Two incoming args: GPR:$src, GPR:$val
1939     // mov $val, pc
1940     // adds $val, #7
1941     // str $val, [$src, #4]
1942     // movs r0, #0
1943     // b LSJLJEH
1944     // movs r0, #1
1945     // LSJLJEH:
1946     Register SrcReg = MI->getOperand(0).getReg();
1947     Register ValReg = MI->getOperand(1).getReg();
1948     MCSymbol *Label = OutContext.createTempSymbol("SJLJEH");
1949     OutStreamer->AddComment("eh_setjmp begin");
1950     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1951       .addReg(ValReg)
1952       .addReg(ARM::PC)
1953       // Predicate.
1954       .addImm(ARMCC::AL)
1955       .addReg(0));
1956 
1957     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi3)
1958       .addReg(ValReg)
1959       // 's' bit operand
1960       .addReg(ARM::CPSR)
1961       .addReg(ValReg)
1962       .addImm(7)
1963       // Predicate.
1964       .addImm(ARMCC::AL)
1965       .addReg(0));
1966 
1967     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSTRi)
1968       .addReg(ValReg)
1969       .addReg(SrcReg)
1970       // The offset immediate is #4. The operand value is scaled by 4 for the
1971       // tSTR instruction.
1972       .addImm(1)
1973       // Predicate.
1974       .addImm(ARMCC::AL)
1975       .addReg(0));
1976 
1977     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
1978       .addReg(ARM::R0)
1979       .addReg(ARM::CPSR)
1980       .addImm(0)
1981       // Predicate.
1982       .addImm(ARMCC::AL)
1983       .addReg(0));
1984 
1985     const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
1986     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tB)
1987       .addExpr(SymbolExpr)
1988       .addImm(ARMCC::AL)
1989       .addReg(0));
1990 
1991     OutStreamer->AddComment("eh_setjmp end");
1992     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
1993       .addReg(ARM::R0)
1994       .addReg(ARM::CPSR)
1995       .addImm(1)
1996       // Predicate.
1997       .addImm(ARMCC::AL)
1998       .addReg(0));
1999 
2000     OutStreamer->emitLabel(Label);
2001     return;
2002   }
2003 
2004   case ARM::Int_eh_sjlj_setjmp_nofp:
2005   case ARM::Int_eh_sjlj_setjmp: {
2006     // Two incoming args: GPR:$src, GPR:$val
2007     // add $val, pc, #8
2008     // str $val, [$src, #+4]
2009     // mov r0, #0
2010     // add pc, pc, #0
2011     // mov r0, #1
2012     Register SrcReg = MI->getOperand(0).getReg();
2013     Register ValReg = MI->getOperand(1).getReg();
2014 
2015     OutStreamer->AddComment("eh_setjmp begin");
2016     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
2017       .addReg(ValReg)
2018       .addReg(ARM::PC)
2019       .addImm(8)
2020       // Predicate.
2021       .addImm(ARMCC::AL)
2022       .addReg(0)
2023       // 's' bit operand (always reg0 for this).
2024       .addReg(0));
2025 
2026     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STRi12)
2027       .addReg(ValReg)
2028       .addReg(SrcReg)
2029       .addImm(4)
2030       // Predicate.
2031       .addImm(ARMCC::AL)
2032       .addReg(0));
2033 
2034     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
2035       .addReg(ARM::R0)
2036       .addImm(0)
2037       // Predicate.
2038       .addImm(ARMCC::AL)
2039       .addReg(0)
2040       // 's' bit operand (always reg0 for this).
2041       .addReg(0));
2042 
2043     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
2044       .addReg(ARM::PC)
2045       .addReg(ARM::PC)
2046       .addImm(0)
2047       // Predicate.
2048       .addImm(ARMCC::AL)
2049       .addReg(0)
2050       // 's' bit operand (always reg0 for this).
2051       .addReg(0));
2052 
2053     OutStreamer->AddComment("eh_setjmp end");
2054     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
2055       .addReg(ARM::R0)
2056       .addImm(1)
2057       // Predicate.
2058       .addImm(ARMCC::AL)
2059       .addReg(0)
2060       // 's' bit operand (always reg0 for this).
2061       .addReg(0));
2062     return;
2063   }
2064   case ARM::Int_eh_sjlj_longjmp: {
2065     // ldr sp, [$src, #8]
2066     // ldr $scratch, [$src, #4]
2067     // ldr r7, [$src]
2068     // bx $scratch
2069     Register SrcReg = MI->getOperand(0).getReg();
2070     Register ScratchReg = MI->getOperand(1).getReg();
2071     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
2072       .addReg(ARM::SP)
2073       .addReg(SrcReg)
2074       .addImm(8)
2075       // Predicate.
2076       .addImm(ARMCC::AL)
2077       .addReg(0));
2078 
2079     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
2080       .addReg(ScratchReg)
2081       .addReg(SrcReg)
2082       .addImm(4)
2083       // Predicate.
2084       .addImm(ARMCC::AL)
2085       .addReg(0));
2086 
2087     const MachineFunction &MF = *MI->getParent()->getParent();
2088     const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
2089 
2090     if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2091       // These platforms always use the same frame register
2092       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
2093                                        .addReg(STI.getFramePointerReg())
2094                                        .addReg(SrcReg)
2095                                        .addImm(0)
2096                                        // Predicate.
2097                                        .addImm(ARMCC::AL)
2098                                        .addReg(0));
2099     } else {
2100       // If the calling code might use either R7 or R11 as
2101       // frame pointer register, restore it into both.
2102       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
2103         .addReg(ARM::R7)
2104         .addReg(SrcReg)
2105         .addImm(0)
2106         // Predicate.
2107         .addImm(ARMCC::AL)
2108         .addReg(0));
2109       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
2110         .addReg(ARM::R11)
2111         .addReg(SrcReg)
2112         .addImm(0)
2113         // Predicate.
2114         .addImm(ARMCC::AL)
2115         .addReg(0));
2116     }
2117 
2118     assert(Subtarget->hasV4TOps());
2119     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
2120       .addReg(ScratchReg)
2121       // Predicate.
2122       .addImm(ARMCC::AL)
2123       .addReg(0));
2124     return;
2125   }
2126   case ARM::tInt_eh_sjlj_longjmp: {
2127     // ldr $scratch, [$src, #8]
2128     // mov sp, $scratch
2129     // ldr $scratch, [$src, #4]
2130     // ldr r7, [$src]
2131     // bx $scratch
2132     Register SrcReg = MI->getOperand(0).getReg();
2133     Register ScratchReg = MI->getOperand(1).getReg();
2134 
2135     const MachineFunction &MF = *MI->getParent()->getParent();
2136     const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
2137 
2138     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
2139       .addReg(ScratchReg)
2140       .addReg(SrcReg)
2141       // The offset immediate is #8. The operand value is scaled by 4 for the
2142       // tLDR instruction.
2143       .addImm(2)
2144       // Predicate.
2145       .addImm(ARMCC::AL)
2146       .addReg(0));
2147 
2148     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
2149       .addReg(ARM::SP)
2150       .addReg(ScratchReg)
2151       // Predicate.
2152       .addImm(ARMCC::AL)
2153       .addReg(0));
2154 
2155     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
2156       .addReg(ScratchReg)
2157       .addReg(SrcReg)
2158       .addImm(1)
2159       // Predicate.
2160       .addImm(ARMCC::AL)
2161       .addReg(0));
2162 
2163     if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2164       // These platforms always use the same frame register
2165       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
2166                                        .addReg(STI.getFramePointerReg())
2167                                        .addReg(SrcReg)
2168                                        .addImm(0)
2169                                        // Predicate.
2170                                        .addImm(ARMCC::AL)
2171                                        .addReg(0));
2172     } else {
2173       // If the calling code might use either R7 or R11 as
2174       // frame pointer register, restore it into both.
2175       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
2176         .addReg(ARM::R7)
2177         .addReg(SrcReg)
2178         .addImm(0)
2179         // Predicate.
2180         .addImm(ARMCC::AL)
2181         .addReg(0));
2182       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
2183         .addReg(ARM::R11)
2184         .addReg(SrcReg)
2185         .addImm(0)
2186         // Predicate.
2187         .addImm(ARMCC::AL)
2188         .addReg(0));
2189     }
2190 
2191     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
2192       .addReg(ScratchReg)
2193       // Predicate.
2194       .addImm(ARMCC::AL)
2195       .addReg(0));
2196     return;
2197   }
2198   case ARM::tInt_WIN_eh_sjlj_longjmp: {
2199     // ldr.w r11, [$src, #0]
2200     // ldr.w  sp, [$src, #8]
2201     // ldr.w  pc, [$src, #4]
2202 
2203     Register SrcReg = MI->getOperand(0).getReg();
2204 
2205     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2206                                      .addReg(ARM::R11)
2207                                      .addReg(SrcReg)
2208                                      .addImm(0)
2209                                      // Predicate
2210                                      .addImm(ARMCC::AL)
2211                                      .addReg(0));
2212     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2213                                      .addReg(ARM::SP)
2214                                      .addReg(SrcReg)
2215                                      .addImm(8)
2216                                      // Predicate
2217                                      .addImm(ARMCC::AL)
2218                                      .addReg(0));
2219     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2220                                      .addReg(ARM::PC)
2221                                      .addReg(SrcReg)
2222                                      .addImm(4)
2223                                      // Predicate
2224                                      .addImm(ARMCC::AL)
2225                                      .addReg(0));
2226     return;
2227   }
2228   case ARM::PATCHABLE_FUNCTION_ENTER:
2229     LowerPATCHABLE_FUNCTION_ENTER(*MI);
2230     return;
2231   case ARM::PATCHABLE_FUNCTION_EXIT:
2232     LowerPATCHABLE_FUNCTION_EXIT(*MI);
2233     return;
2234   case ARM::PATCHABLE_TAIL_CALL:
2235     LowerPATCHABLE_TAIL_CALL(*MI);
2236     return;
2237   case ARM::SpeculationBarrierISBDSBEndBB: {
2238     // Print DSB SYS + ISB
2239     MCInst TmpInstDSB;
2240     TmpInstDSB.setOpcode(ARM::DSB);
2241     TmpInstDSB.addOperand(MCOperand::createImm(0xf));
2242     EmitToStreamer(*OutStreamer, TmpInstDSB);
2243     MCInst TmpInstISB;
2244     TmpInstISB.setOpcode(ARM::ISB);
2245     TmpInstISB.addOperand(MCOperand::createImm(0xf));
2246     EmitToStreamer(*OutStreamer, TmpInstISB);
2247     return;
2248   }
2249   case ARM::t2SpeculationBarrierISBDSBEndBB: {
2250     // Print DSB SYS + ISB
2251     MCInst TmpInstDSB;
2252     TmpInstDSB.setOpcode(ARM::t2DSB);
2253     TmpInstDSB.addOperand(MCOperand::createImm(0xf));
2254     TmpInstDSB.addOperand(MCOperand::createImm(ARMCC::AL));
2255     TmpInstDSB.addOperand(MCOperand::createReg(0));
2256     EmitToStreamer(*OutStreamer, TmpInstDSB);
2257     MCInst TmpInstISB;
2258     TmpInstISB.setOpcode(ARM::t2ISB);
2259     TmpInstISB.addOperand(MCOperand::createImm(0xf));
2260     TmpInstISB.addOperand(MCOperand::createImm(ARMCC::AL));
2261     TmpInstISB.addOperand(MCOperand::createReg(0));
2262     EmitToStreamer(*OutStreamer, TmpInstISB);
2263     return;
2264   }
2265   case ARM::SpeculationBarrierSBEndBB: {
2266     // Print SB
2267     MCInst TmpInstSB;
2268     TmpInstSB.setOpcode(ARM::SB);
2269     EmitToStreamer(*OutStreamer, TmpInstSB);
2270     return;
2271   }
2272   case ARM::t2SpeculationBarrierSBEndBB: {
2273     // Print SB
2274     MCInst TmpInstSB;
2275     TmpInstSB.setOpcode(ARM::t2SB);
2276     EmitToStreamer(*OutStreamer, TmpInstSB);
2277     return;
2278   }
2279 
2280   case ARM::SEH_StackAlloc:
2281     ATS.emitARMWinCFIAllocStack(MI->getOperand(0).getImm(),
2282                                 MI->getOperand(1).getImm());
2283     return;
2284 
2285   case ARM::SEH_SaveRegs:
2286   case ARM::SEH_SaveRegs_Ret:
2287     ATS.emitARMWinCFISaveRegMask(MI->getOperand(0).getImm(),
2288                                  MI->getOperand(1).getImm());
2289     return;
2290 
2291   case ARM::SEH_SaveSP:
2292     ATS.emitARMWinCFISaveSP(MI->getOperand(0).getImm());
2293     return;
2294 
2295   case ARM::SEH_SaveFRegs:
2296     ATS.emitARMWinCFISaveFRegs(MI->getOperand(0).getImm(),
2297                                MI->getOperand(1).getImm());
2298     return;
2299 
2300   case ARM::SEH_SaveLR:
2301     ATS.emitARMWinCFISaveLR(MI->getOperand(0).getImm());
2302     return;
2303 
2304   case ARM::SEH_Nop:
2305   case ARM::SEH_Nop_Ret:
2306     ATS.emitARMWinCFINop(MI->getOperand(0).getImm());
2307     return;
2308 
2309   case ARM::SEH_PrologEnd:
2310     ATS.emitARMWinCFIPrologEnd(/*Fragment=*/false);
2311     return;
2312 
2313   case ARM::SEH_EpilogStart:
2314     ATS.emitARMWinCFIEpilogStart(ARMCC::AL);
2315     return;
2316 
2317   case ARM::SEH_EpilogEnd:
2318     ATS.emitARMWinCFIEpilogEnd();
2319     return;
2320   }
2321 
2322   MCInst TmpInst;
2323   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2324 
2325   EmitToStreamer(*OutStreamer, TmpInst);
2326 }
2327 
2328 //===----------------------------------------------------------------------===//
2329 // Target Registry Stuff
2330 //===----------------------------------------------------------------------===//
2331 
2332 // Force static initialization.
2333 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMAsmPrinter() {
2334   RegisterAsmPrinter<ARMAsmPrinter> X(getTheARMLETarget());
2335   RegisterAsmPrinter<ARMAsmPrinter> Y(getTheARMBETarget());
2336   RegisterAsmPrinter<ARMAsmPrinter> A(getTheThumbLETarget());
2337   RegisterAsmPrinter<ARMAsmPrinter> B(getTheThumbBETarget());
2338 }
2339