1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// ARM Subtarget state. 20// 21 22def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", 23 "true", "Thumb mode">; 24 25def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat", 26 "true", "Use software floating " 27 "point features.">; 28 29 30//===----------------------------------------------------------------------===// 31// ARM Subtarget features. 32// 33 34// Floating Point, HW Division and Neon Support 35 36// FP loads/stores/moves, shared between VFP and MVE (even in the integer-only 37// version). 38def FeatureFPRegs : SubtargetFeature<"fpregs", "HasFPRegs", "true", 39 "Enable FP registers">; 40 41// 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16 42// extension) and MVE (even in the integer-only version). 43def FeatureFPRegs16 : SubtargetFeature<"fpregs16", "HasFPRegs16", "true", 44 "Enable 16-bit FP registers", 45 [FeatureFPRegs]>; 46 47def FeatureFPRegs64 : SubtargetFeature<"fpregs64", "HasFPRegs64", "true", 48 "Enable 64-bit FP registers", 49 [FeatureFPRegs]>; 50 51def FeatureFP64 : SubtargetFeature<"fp64", "HasFP64", "true", 52 "Floating point unit supports " 53 "double precision", 54 [FeatureFPRegs64]>; 55 56def FeatureD32 : SubtargetFeature<"d32", "HasD32", "true", 57 "Extend FP to 32 double registers">; 58 59multiclass VFPver<string name, string query, string description, 60 list<SubtargetFeature> prev, 61 list<SubtargetFeature> otherimplies, 62 list<SubtargetFeature> vfp2prev = []> { 63 def _D16_SP: SubtargetFeature< 64 name#"d16sp", query#"D16SP", "true", 65 description#" with only 16 d-registers and no double precision", 66 !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) # 67 !foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) # 68 otherimplies>; 69 def _SP: SubtargetFeature< 70 name#"sp", query#"SP", "true", 71 description#" with no double precision", 72 !foreach(v, prev, !cast<SubtargetFeature>(v # "_SP")) # 73 otherimplies # [FeatureD32, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; 74 def _D16: SubtargetFeature< 75 name#"d16", query#"D16", "true", 76 description#" with only 16 d-registers", 77 !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) # 78 vfp2prev # 79 otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; 80 def "": SubtargetFeature< 81 name, query, "true", description, 82 prev # otherimplies # [ 83 !cast<SubtargetFeature>(NAME # "_D16"), 84 !cast<SubtargetFeature>(NAME # "_SP")]>; 85} 86 87def FeatureVFP2_SP : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true", 88 "Enable VFP2 instructions with " 89 "no double precision", 90 [FeatureFPRegs]>; 91 92def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 93 "Enable VFP2 instructions", 94 [FeatureFP64, FeatureVFP2_SP]>; 95 96defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions", 97 [], [], [FeatureVFP2]>; 98 99def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 100 "Enable NEON instructions", 101 [FeatureVFP3]>; 102 103def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 104 "Enable half-precision " 105 "floating point">; 106 107defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions", 108 [FeatureVFP3], [FeatureFP16]>; 109 110defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP", 111 [FeatureVFP4], []>; 112 113def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 114 "Enable full half-precision " 115 "floating point", 116 [FeatureFPARMv8_D16_SP, FeatureFPRegs16]>; 117 118def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 119 "Enable full half-precision " 120 "floating point fml instructions", 121 [FeatureFullFP16]>; 122 123def FeatureHWDivThumb : SubtargetFeature<"hwdiv", 124 "HasHardwareDivideInThumb", "true", 125 "Enable divide instructions in Thumb">; 126 127def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 128 "HasHardwareDivideInARM", "true", 129 "Enable divide instructions in ARM mode">; 130 131// Atomic Support 132def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 133 "Has data barrier (dmb/dsb) instructions">; 134 135def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", 136 "Has v7 clrex instruction">; 137 138def FeatureDFB : SubtargetFeature<"dfb", "HasFullDataBarrier", "true", 139 "Has full data barrier (dfb) instruction">; 140 141def FeatureAcquireRelease : SubtargetFeature<"acquire-release", 142 "HasAcquireRelease", "true", 143 "Has v8 acquire/release (lda/ldaex " 144 " etc) instructions">; 145 146 147def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 148 "FP compare + branch is slow">; 149 150def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 151 "Enable support for Performance " 152 "Monitor extensions">; 153 154 155// TrustZone Security Extensions 156def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 157 "Enable support for TrustZone " 158 "security extensions">; 159 160def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", 161 "Enable support for ARMv8-M " 162 "Security Extensions">; 163 164def FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true", 165 "Enable SHA1 and SHA256 support", [FeatureNEON]>; 166 167def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 168 "Enable AES support", [FeatureNEON]>; 169 170def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 171 "Enable support for " 172 "Cryptography extensions", 173 [FeatureNEON, FeatureSHA2, FeatureAES]>; 174 175def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 176 "Enable support for CRC instructions">; 177 178def FeatureDotProd : SubtargetFeature<"dotprod", "HasDotProd", "true", 179 "Enable support for dot product instructions", 180 [FeatureNEON]>; 181 182// Not to be confused with FeatureHasRetAddrStack (return address stack) 183def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 184 "Enable Reliability, Availability " 185 "and Serviceability extensions">; 186 187// Fast computation of non-negative address offsets 188def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true", 189 "Enable fast computation of " 190 "positive address offsets">; 191 192// Fast execution of AES crypto operations 193def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true", 194 "CPU fuses AES crypto operations">; 195 196// Fast execution of bottom and top halves of literal generation 197def FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true", 198 "CPU fuses literal generation operations">; 199 200// The way of reading thread pointer 201def FeatureReadTp : SubtargetFeature<"read-tp-hard", "ReadTPHard", "true", 202 "Reading thread pointer from register">; 203 204// Cyclone can zero VFP registers in 0 cycles. 205def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 206 "Has zero-cycle zeroing instructions">; 207 208// Whether it is profitable to unpredicate certain instructions during if-conversion 209def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr", 210 "IsProfitableToUnpredicate", "true", 211 "Is profitable to unpredicate">; 212 213// Some targets (e.g. Swift) have microcoded VGETLNi32. 214def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32", 215 "HasSlowVGETLNi32", "true", 216 "Has slow VGETLNi32 - prefer VMOV">; 217 218// Some targets (e.g. Swift) have microcoded VDUP32. 219def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", 220 "true", 221 "Has slow VDUP32 - prefer VMOV">; 222 223// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON 224// for scalar FP, as this allows more effective execution domain optimization. 225def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR", 226 "true", "Prefer VMOVSR">; 227 228// Swift has ISHST barriers compatible with Atomic Release semantics but weaker 229// than ISH 230def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST", 231 "true", "Prefer ISHST barriers">; 232 233// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU. 234def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", 235 "true", 236 "Has muxed AGU and NEON/FPU">; 237 238// Whether VLDM/VSTM starting with odd register number need more microops 239// than single VLDRS 240def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister", 241 "true", "VLDM/VSTM starting " 242 "with an odd register is slow">; 243 244// Some targets have a renaming dependency when loading into D subregisters. 245def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg", 246 "SlowLoadDSubregister", "true", 247 "Loading into D subregs is slow">; 248 249def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp", 250 "UseWideStrideVFP", "true", 251 "Use a wide stride when allocating VFP registers">; 252 253// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. 254def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", 255 "DontWidenVMOVS", "true", 256 "Don't widen VMOVS to VMOVD">; 257 258// Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different 259// VFP register widths. 260def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon", 261 "SplatVFPToNeon", "true", 262 "Splat register from VFP to NEON", 263 [FeatureDontWidenVMOVS]>; 264 265// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions. 266def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", 267 "ExpandMLx", "true", 268 "Expand VFP/NEON MLA/MLS instructions">; 269 270// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS. 271def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards", 272 "true", "Has VMLx hazards">; 273 274// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from 275// VFP to NEON, as an execution domain optimization. 276def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", 277 "UseNEONForFPMovs", "true", 278 "Convert VMOVSR, VMOVRS, " 279 "VMOVS to NEON">; 280 281// Some processors benefit from using NEON instructions for scalar 282// single-precision FP operations. This affects instruction selection and should 283// only be enabled if the handling of denormals is not important. 284def FeatureNEONForFP : SubtargetFeature<"neonfp", 285 "UseNEONForSinglePrecisionFP", 286 "true", 287 "Use NEON for single precision FP">; 288 289// On some processors, VLDn instructions that access unaligned data take one 290// extra cycle. Take that into account when computing operand latencies. 291def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign", 292 "true", 293 "Check for VLDn unaligned access">; 294 295// Some processors have a nonpipelined VFP coprocessor. 296def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp", 297 "NonpipelinedVFP", "true", 298 "VFP instructions are not pipelined">; 299 300// Some processors have FP multiply-accumulate instructions that don't 301// play nicely with other VFP / NEON instructions, and it's generally better 302// to just not use them. 303def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 304 "Disable VFP / NEON MAC instructions">; 305 306// VFPv4 added VFMA instructions that can similar be fast or slow. 307def FeatureHasSlowFPVFMx : SubtargetFeature<"slowfpvfmx", "SlowFPVFMx", "true", 308 "Disable VFP / NEON FMA instructions">; 309 310// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 311def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 312 "HasVMLxForwarding", "true", 313 "Has multiplier accumulator forwarding">; 314 315// Disable 32-bit to 16-bit narrowing for experimentation. 316def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 317 "Prefer 32-bit Thumb instrs">; 318 319def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopLogAlignment","2", 320 "Prefer 32-bit alignment for loops">; 321 322def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "1", 323 "Model MVE instructions as a 1 beat per tick architecture">; 324 325def FeatureMVEVectorCostFactor2 : SubtargetFeature<"mve2beat", "MVEVectorCostFactor", "2", 326 "Model MVE instructions as a 2 beats per tick architecture">; 327 328def FeatureMVEVectorCostFactor4 : SubtargetFeature<"mve4beat", "MVEVectorCostFactor", "4", 329 "Model MVE instructions as a 4 beats per tick architecture">; 330 331/// Some instructions update CPSR partially, which can add false dependency for 332/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 333/// mapped to a separate physical register. Avoid partial CPSR update for these 334/// processors. 335def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 336 "AvoidCPSRPartialUpdate", "true", 337 "Avoid CPSR partial update for OOO execution">; 338 339/// Disable +1 predication cost for instructions updating CPSR. 340/// Enabled for Cortex-A57. 341def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr", 342 "CheapPredicableCPSRDef", 343 "true", 344 "Disable +1 predication cost for instructions updating CPSR">; 345 346def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 347 "AvoidMOVsShifterOperand", "true", 348 "Avoid movs instructions with " 349 "shifter operand">; 350 351// Some processors perform return stack prediction. CodeGen should avoid issue 352// "normal" call instructions to callees which do not return. 353def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", 354 "HasRetAddrStack", "true", 355 "Has return address stack">; 356 357// Some processors have no branch predictor, which changes the expected cost of 358// taking a branch which affects the choice of whether to use predicated 359// instructions. 360def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor", 361 "HasBranchPredictor", "false", 362 "Has no branch predictor">; 363 364/// DSP extension. 365def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", 366 "Supports DSP instructions in " 367 "ARM and/or Thumb2">; 368 369// Multiprocessing extension. 370def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 371 "Supports Multiprocessing extension">; 372 373// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 374def FeatureVirtualization : SubtargetFeature<"virtualization", 375 "HasVirtualization", "true", 376 "Supports Virtualization extension", 377 [FeatureHWDivThumb, FeatureHWDivARM]>; 378 379// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 380// See ARMInstrInfo.td for details. 381def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 382 "NaCl trap">; 383 384def FeatureStrictAlign : SubtargetFeature<"strict-align", 385 "StrictAlign", "true", 386 "Disallow all unaligned memory " 387 "access">; 388 389def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", 390 "Generate calls via indirect call " 391 "instructions">; 392 393def FeatureExecuteOnly : SubtargetFeature<"execute-only", 394 "GenExecuteOnly", "true", 395 "Enable the generation of " 396 "execute only code.">; 397 398def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", 399 "Reserve R9, making it unavailable" 400 " as GPR">; 401 402def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", 403 "Don't use movt/movw pairs for " 404 "32-bit imms">; 405 406def FeatureNoNegativeImmediates 407 : SubtargetFeature<"no-neg-immediates", 408 "NegativeImmediates", "false", 409 "Convert immediates and instructions " 410 "to their negated or complemented " 411 "equivalent when the immediate does " 412 "not fit in the encoding.">; 413 414// Use the MachineScheduler for instruction scheduling for the subtarget. 415def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true", 416 "Use the MachineScheduler">; 417 418def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler", 419 "DisablePostRAScheduler", "true", 420 "Don't schedule again after register allocation">; 421 422// Armv8.5-A extensions 423 424def FeatureSB : SubtargetFeature<"sb", "HasSB", "true", 425 "Enable v8.5a Speculation Barrier" >; 426 427// Armv8.6-A extensions 428def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", "true", 429 "Enable support for BFloat16 instructions", [FeatureNEON]>; 430 431def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8", 432 "true", "Enable Matrix Multiply Int8 Extension", [FeatureNEON]>; 433 434// Armv8.1-M extensions 435 436def FeatureLOB : SubtargetFeature<"lob", "HasLOB", "true", 437 "Enable Low Overhead Branch " 438 "extensions">; 439 440//===----------------------------------------------------------------------===// 441// ARM architecture class 442// 443 444// A-series ISA 445def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 446 "Is application profile ('A' series)">; 447 448// R-series ISA 449def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 450 "Is realtime profile ('R' series)">; 451 452// M-series ISA 453def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 454 "Is microcontroller profile ('M' series)">; 455 456 457def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 458 "Enable Thumb2 instructions">; 459 460def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 461 "Does not support ARM mode execution">; 462 463//===----------------------------------------------------------------------===// 464// ARM ISAa. 465// 466 467def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 468 "Support ARM v4T instructions">; 469 470def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 471 "Support ARM v5T instructions", 472 [HasV4TOps]>; 473 474def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 475 "Support ARM v5TE, v5TEj, and " 476 "v5TExp instructions", 477 [HasV5TOps]>; 478 479def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 480 "Support ARM v6 instructions", 481 [HasV5TEOps]>; 482 483def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 484 "Support ARM v6M instructions", 485 [HasV6Ops]>; 486 487def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", 488 "Support ARM v8M Baseline instructions", 489 [HasV6MOps]>; 490 491def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", 492 "Support ARM v6k instructions", 493 [HasV6Ops]>; 494 495def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 496 "Support ARM v6t2 instructions", 497 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; 498 499def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 500 "Support ARM v7 instructions", 501 [HasV6T2Ops, FeaturePerfMon, 502 FeatureV7Clrex]>; 503 504def HasV8MMainlineOps : 505 SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", 506 "Support ARM v8M Mainline instructions", 507 [HasV7Ops]>; 508 509def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 510 "Support ARM v8 instructions", 511 [HasV7Ops, FeatureAcquireRelease]>; 512 513def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 514 "Support ARM v8.1a instructions", 515 [HasV8Ops]>; 516 517def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 518 "Support ARM v8.2a instructions", 519 [HasV8_1aOps]>; 520 521def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 522 "Support ARM v8.3a instructions", 523 [HasV8_2aOps]>; 524 525def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 526 "Support ARM v8.4a instructions", 527 [HasV8_3aOps, FeatureDotProd]>; 528 529def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true", 530 "Support ARM v8.5a instructions", 531 [HasV8_4aOps, FeatureSB]>; 532 533def HasV8_6aOps : SubtargetFeature<"v8.6a", "HasV8_6aOps", "true", 534 "Support ARM v8.6a instructions", 535 [HasV8_5aOps, FeatureBF16, 536 FeatureMatMulInt8]>; 537 538def HasV8_1MMainlineOps : SubtargetFeature< 539 "v8.1m.main", "HasV8_1MMainlineOps", "true", 540 "Support ARM v8-1M Mainline instructions", 541 [HasV8MMainlineOps]>; 542def HasMVEIntegerOps : SubtargetFeature< 543 "mve", "HasMVEIntegerOps", "true", 544 "Support M-Class Vector Extension with integer ops", 545 [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>; 546def HasMVEFloatOps : SubtargetFeature< 547 "mve.fp", "HasMVEFloatOps", "true", 548 "Support M-Class Vector Extension with integer and floating ops", 549 [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>; 550 551def HasCDEOps : SubtargetFeature<"cde", "HasCDEOps", "true", 552 "Support CDE instructions", 553 [HasV8MMainlineOps]>; 554 555foreach i = {0-7} in 556 def FeatureCoprocCDE#i : SubtargetFeature<"cdecp"#i, 557 "CoprocCDE["#i#"]", "true", 558 "Coprocessor "#i#" ISA is CDEv1", 559 [HasCDEOps]>; 560 561//===----------------------------------------------------------------------===// 562// ARM Processor subtarget features. 563// 564 565def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 566 "Cortex-A5 ARM processors", []>; 567def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 568 "Cortex-A7 ARM processors", []>; 569def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 570 "Cortex-A8 ARM processors", []>; 571def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 572 "Cortex-A9 ARM processors", []>; 573def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 574 "Cortex-A12 ARM processors", []>; 575def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 576 "Cortex-A15 ARM processors", []>; 577def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", 578 "Cortex-A17 ARM processors", []>; 579def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", 580 "Cortex-A32 ARM processors", []>; 581def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 582 "Cortex-A35 ARM processors", []>; 583def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 584 "Cortex-A53 ARM processors", []>; 585def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 586 "Cortex-A55 ARM processors", []>; 587def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 588 "Cortex-A57 ARM processors", []>; 589def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 590 "Cortex-A72 ARM processors", []>; 591def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 592 "Cortex-A73 ARM processors", []>; 593def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 594 "Cortex-A75 ARM processors", []>; 595def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 596 "Cortex-A76 ARM processors", []>; 597def ProcA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", 598 "Cortex-A77 ARM processors", []>; 599def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily", "CortexA78", 600 "Cortex-A78 ARM processors", []>; 601def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", 602 "Cortex-X1 ARM processors", []>; 603 604def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 605 "Qualcomm Krait processors", []>; 606def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 607 "Qualcomm Kryo processors", []>; 608def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 609 "Swift ARM processors", []>; 610 611def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos", 612 "Samsung Exynos processors", 613 [FeatureZCZeroing, 614 FeatureUseWideStrideVFP, 615 FeatureSplatVFPToNeon, 616 FeatureSlowVGETLNi32, 617 FeatureSlowVDUP32, 618 FeatureSlowFPBrcc, 619 FeatureProfUnpredicate, 620 FeatureHWDivThumb, 621 FeatureHWDivARM, 622 FeatureHasSlowFPVMLx, 623 FeatureHasSlowFPVFMx, 624 FeatureHasRetAddrStack, 625 FeatureFuseLiterals, 626 FeatureFuseAES, 627 FeatureExpandMLx, 628 FeatureCrypto, 629 FeatureCRC]>; 630 631def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", 632 "Cortex-R4 ARM processors", []>; 633def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 634 "Cortex-R5 ARM processors", []>; 635def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", 636 "Cortex-R7 ARM processors", []>; 637def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", 638 "Cortex-R52 ARM processors", []>; 639 640def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", 641 "Cortex-M3 ARM processors", []>; 642 643 644//===----------------------------------------------------------------------===// 645// ARM Helper classes. 646// 647 648class Architecture<string fname, string aname, list<SubtargetFeature> features> 649 : SubtargetFeature<fname, "ARMArch", aname, 650 !strconcat(aname, " architecture"), features>; 651 652class ProcNoItin<string Name, list<SubtargetFeature> Features> 653 : Processor<Name, NoItineraries, Features>; 654 655 656//===----------------------------------------------------------------------===// 657// ARM architectures 658// 659 660def ARMv2 : Architecture<"armv2", "ARMv2", []>; 661 662def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; 663 664def ARMv3 : Architecture<"armv3", "ARMv3", []>; 665 666def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; 667 668def ARMv4 : Architecture<"armv4", "ARMv4", []>; 669 670def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; 671 672def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; 673 674def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; 675 676def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; 677 678def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops, 679 FeatureDSP]>; 680 681def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, 682 FeatureDSP]>; 683 684def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; 685 686def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, 687 FeatureTrustZone]>; 688 689def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, 690 FeatureNoARM, 691 ModeThumb, 692 FeatureDB, 693 FeatureMClass, 694 FeatureStrictAlign]>; 695 696def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, 697 FeatureNoARM, 698 ModeThumb, 699 FeatureDB, 700 FeatureMClass, 701 FeatureStrictAlign]>; 702 703def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, 704 FeatureNEON, 705 FeatureDB, 706 FeatureDSP, 707 FeatureAClass]>; 708 709def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops, 710 FeatureNEON, 711 FeatureDB, 712 FeatureDSP, 713 FeatureTrustZone, 714 FeatureMP, 715 FeatureVirtualization, 716 FeatureAClass]>; 717 718def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, 719 FeatureDB, 720 FeatureDSP, 721 FeatureHWDivThumb, 722 FeatureRClass]>; 723 724def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, 725 FeatureThumb2, 726 FeatureNoARM, 727 ModeThumb, 728 FeatureDB, 729 FeatureHWDivThumb, 730 FeatureMClass]>; 731 732def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, 733 FeatureThumb2, 734 FeatureNoARM, 735 ModeThumb, 736 FeatureDB, 737 FeatureHWDivThumb, 738 FeatureMClass, 739 FeatureDSP]>; 740 741def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, 742 FeatureAClass, 743 FeatureDB, 744 FeatureFPARMv8, 745 FeatureNEON, 746 FeatureDSP, 747 FeatureTrustZone, 748 FeatureMP, 749 FeatureVirtualization, 750 FeatureCrypto, 751 FeatureCRC]>; 752 753def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, 754 FeatureAClass, 755 FeatureDB, 756 FeatureFPARMv8, 757 FeatureNEON, 758 FeatureDSP, 759 FeatureTrustZone, 760 FeatureMP, 761 FeatureVirtualization, 762 FeatureCrypto, 763 FeatureCRC]>; 764 765def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, 766 FeatureAClass, 767 FeatureDB, 768 FeatureFPARMv8, 769 FeatureNEON, 770 FeatureDSP, 771 FeatureTrustZone, 772 FeatureMP, 773 FeatureVirtualization, 774 FeatureCrypto, 775 FeatureCRC, 776 FeatureRAS]>; 777 778def ARMv83a : Architecture<"armv8.3-a", "ARMv83a", [HasV8_3aOps, 779 FeatureAClass, 780 FeatureDB, 781 FeatureFPARMv8, 782 FeatureNEON, 783 FeatureDSP, 784 FeatureTrustZone, 785 FeatureMP, 786 FeatureVirtualization, 787 FeatureCrypto, 788 FeatureCRC, 789 FeatureRAS]>; 790 791def ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps, 792 FeatureAClass, 793 FeatureDB, 794 FeatureFPARMv8, 795 FeatureNEON, 796 FeatureDSP, 797 FeatureTrustZone, 798 FeatureMP, 799 FeatureVirtualization, 800 FeatureCrypto, 801 FeatureCRC, 802 FeatureRAS, 803 FeatureDotProd]>; 804 805def ARMv85a : Architecture<"armv8.5-a", "ARMv85a", [HasV8_5aOps, 806 FeatureAClass, 807 FeatureDB, 808 FeatureFPARMv8, 809 FeatureNEON, 810 FeatureDSP, 811 FeatureTrustZone, 812 FeatureMP, 813 FeatureVirtualization, 814 FeatureCrypto, 815 FeatureCRC, 816 FeatureRAS, 817 FeatureDotProd]>; 818def ARMv86a : Architecture<"armv8.6-a", "ARMv86a", [HasV8_6aOps, 819 FeatureAClass, 820 FeatureDB, 821 FeatureFPARMv8, 822 FeatureNEON, 823 FeatureDSP, 824 FeatureTrustZone, 825 FeatureMP, 826 FeatureVirtualization, 827 FeatureCrypto, 828 FeatureCRC, 829 FeatureRAS, 830 FeatureDotProd]>; 831 832def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, 833 FeatureRClass, 834 FeatureDB, 835 FeatureDFB, 836 FeatureDSP, 837 FeatureCRC, 838 FeatureMP, 839 FeatureVirtualization, 840 FeatureFPARMv8, 841 FeatureNEON]>; 842 843def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", 844 [HasV8MBaselineOps, 845 FeatureNoARM, 846 ModeThumb, 847 FeatureDB, 848 FeatureHWDivThumb, 849 FeatureV7Clrex, 850 Feature8MSecExt, 851 FeatureAcquireRelease, 852 FeatureMClass, 853 FeatureStrictAlign]>; 854 855def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", 856 [HasV8MMainlineOps, 857 FeatureNoARM, 858 ModeThumb, 859 FeatureDB, 860 FeatureHWDivThumb, 861 Feature8MSecExt, 862 FeatureAcquireRelease, 863 FeatureMClass]>; 864 865def ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline", 866 [HasV8_1MMainlineOps, 867 FeatureNoARM, 868 ModeThumb, 869 FeatureDB, 870 FeatureHWDivThumb, 871 Feature8MSecExt, 872 FeatureAcquireRelease, 873 FeatureMClass, 874 FeatureRAS, 875 FeatureLOB]>; 876 877// Aliases 878def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; 879def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; 880def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; 881def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; 882def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; 883def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; 884 885 886//===----------------------------------------------------------------------===// 887// ARM schedules. 888//===----------------------------------------------------------------------===// 889// 890include "ARMPredicates.td" 891include "ARMSchedule.td" 892 893//===----------------------------------------------------------------------===// 894// ARM processors 895// 896 897// Dummy CPU, used to target architectures 898def : ProcessorModel<"generic", CortexA8Model, []>; 899 900// FIXME: Several processors below are not using their own scheduler 901// model, but one of similar/previous processor. These should be fixed. 902 903def : ProcNoItin<"arm8", [ARMv4]>; 904def : ProcNoItin<"arm810", [ARMv4]>; 905def : ProcNoItin<"strongarm", [ARMv4]>; 906def : ProcNoItin<"strongarm110", [ARMv4]>; 907def : ProcNoItin<"strongarm1100", [ARMv4]>; 908def : ProcNoItin<"strongarm1110", [ARMv4]>; 909 910def : ProcNoItin<"arm7tdmi", [ARMv4t]>; 911def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; 912def : ProcNoItin<"arm710t", [ARMv4t]>; 913def : ProcNoItin<"arm720t", [ARMv4t]>; 914def : ProcNoItin<"arm9", [ARMv4t]>; 915def : ProcNoItin<"arm9tdmi", [ARMv4t]>; 916def : ProcNoItin<"arm920", [ARMv4t]>; 917def : ProcNoItin<"arm920t", [ARMv4t]>; 918def : ProcNoItin<"arm922t", [ARMv4t]>; 919def : ProcNoItin<"arm940t", [ARMv4t]>; 920def : ProcNoItin<"ep9312", [ARMv4t]>; 921 922def : ProcNoItin<"arm10tdmi", [ARMv5t]>; 923def : ProcNoItin<"arm1020t", [ARMv5t]>; 924 925def : ProcNoItin<"arm9e", [ARMv5te]>; 926def : ProcNoItin<"arm926ej-s", [ARMv5te]>; 927def : ProcNoItin<"arm946e-s", [ARMv5te]>; 928def : ProcNoItin<"arm966e-s", [ARMv5te]>; 929def : ProcNoItin<"arm968e-s", [ARMv5te]>; 930def : ProcNoItin<"arm10e", [ARMv5te]>; 931def : ProcNoItin<"arm1020e", [ARMv5te]>; 932def : ProcNoItin<"arm1022e", [ARMv5te]>; 933def : ProcNoItin<"xscale", [ARMv5te]>; 934def : ProcNoItin<"iwmmxt", [ARMv5te]>; 935 936def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; 937def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, 938 FeatureVFP2, 939 FeatureHasSlowFPVMLx]>; 940 941def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>; 942def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>; 943def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>; 944def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>; 945 946def : Processor<"arm1176j-s", ARMV6Itineraries, [ARMv6kz]>; 947def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; 948def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, 949 FeatureVFP2, 950 FeatureHasSlowFPVMLx]>; 951 952def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; 953def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, 954 FeatureVFP2, 955 FeatureHasSlowFPVMLx]>; 956 957def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; 958def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, 959 FeatureVFP2, 960 FeatureHasSlowFPVMLx]>; 961 962def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, 963 FeatureHasRetAddrStack, 964 FeatureTrustZone, 965 FeatureSlowFPBrcc, 966 FeatureHasSlowFPVMLx, 967 FeatureHasSlowFPVFMx, 968 FeatureVMLxForwarding, 969 FeatureMP, 970 FeatureVFP4]>; 971 972def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, 973 FeatureHasRetAddrStack, 974 FeatureTrustZone, 975 FeatureSlowFPBrcc, 976 FeatureHasVMLxHazards, 977 FeatureHasSlowFPVMLx, 978 FeatureHasSlowFPVFMx, 979 FeatureVMLxForwarding, 980 FeatureMP, 981 FeatureVFP4, 982 FeatureVirtualization]>; 983 984def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, 985 FeatureHasRetAddrStack, 986 FeatureNonpipelinedVFP, 987 FeatureTrustZone, 988 FeatureSlowFPBrcc, 989 FeatureHasVMLxHazards, 990 FeatureHasSlowFPVMLx, 991 FeatureHasSlowFPVFMx, 992 FeatureVMLxForwarding]>; 993 994def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, 995 FeatureHasRetAddrStack, 996 FeatureTrustZone, 997 FeatureHasVMLxHazards, 998 FeatureVMLxForwarding, 999 FeatureFP16, 1000 FeatureAvoidPartialCPSR, 1001 FeatureExpandMLx, 1002 FeaturePreferVMOVSR, 1003 FeatureMuxedUnits, 1004 FeatureNEONForFPMovs, 1005 FeatureCheckVLDnAlign, 1006 FeatureMP]>; 1007 1008def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, 1009 FeatureHasRetAddrStack, 1010 FeatureTrustZone, 1011 FeatureVMLxForwarding, 1012 FeatureVFP4, 1013 FeatureAvoidPartialCPSR, 1014 FeatureVirtualization, 1015 FeatureMP]>; 1016 1017def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, 1018 FeatureDontWidenVMOVS, 1019 FeatureSplatVFPToNeon, 1020 FeatureHasRetAddrStack, 1021 FeatureMuxedUnits, 1022 FeatureTrustZone, 1023 FeatureVFP4, 1024 FeatureMP, 1025 FeatureCheckVLDnAlign, 1026 FeatureAvoidPartialCPSR, 1027 FeatureVirtualization]>; 1028 1029def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, 1030 FeatureHasRetAddrStack, 1031 FeatureTrustZone, 1032 FeatureMP, 1033 FeatureVMLxForwarding, 1034 FeatureVFP4, 1035 FeatureAvoidPartialCPSR, 1036 FeatureVirtualization]>; 1037 1038// FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv 1039def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, 1040 FeatureHasRetAddrStack, 1041 FeatureMuxedUnits, 1042 FeatureCheckVLDnAlign, 1043 FeatureVMLxForwarding, 1044 FeatureFP16, 1045 FeatureAvoidPartialCPSR, 1046 FeatureVFP4, 1047 FeatureHWDivThumb, 1048 FeatureHWDivARM]>; 1049 1050def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, 1051 FeatureHasRetAddrStack, 1052 FeatureNEONForFP, 1053 FeatureVFP4, 1054 FeatureUseWideStrideVFP, 1055 FeatureMP, 1056 FeatureHWDivThumb, 1057 FeatureHWDivARM, 1058 FeatureAvoidPartialCPSR, 1059 FeatureAvoidMOVsShOp, 1060 FeatureHasSlowFPVMLx, 1061 FeatureHasSlowFPVFMx, 1062 FeatureHasVMLxHazards, 1063 FeatureProfUnpredicate, 1064 FeaturePrefISHSTBarrier, 1065 FeatureSlowOddRegister, 1066 FeatureSlowLoadDSubreg, 1067 FeatureSlowVGETLNi32, 1068 FeatureSlowVDUP32, 1069 FeatureUseMISched, 1070 FeatureNoPostRASched]>; 1071 1072def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, 1073 FeatureHasRetAddrStack, 1074 FeatureAvoidPartialCPSR]>; 1075 1076def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, 1077 FeatureHasRetAddrStack, 1078 FeatureSlowFPBrcc, 1079 FeatureHasSlowFPVMLx, 1080 FeatureHasSlowFPVFMx, 1081 FeatureVFP3_D16, 1082 FeatureAvoidPartialCPSR]>; 1083 1084def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, 1085 FeatureHasRetAddrStack, 1086 FeatureVFP3_D16, 1087 FeatureSlowFPBrcc, 1088 FeatureHWDivARM, 1089 FeatureHasSlowFPVMLx, 1090 FeatureHasSlowFPVFMx, 1091 FeatureAvoidPartialCPSR]>; 1092 1093def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, 1094 FeatureHasRetAddrStack, 1095 FeatureVFP3_D16, 1096 FeatureFP16, 1097 FeatureMP, 1098 FeatureSlowFPBrcc, 1099 FeatureHWDivARM, 1100 FeatureHasSlowFPVMLx, 1101 FeatureHasSlowFPVFMx, 1102 FeatureAvoidPartialCPSR]>; 1103 1104def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, 1105 FeatureHasRetAddrStack, 1106 FeatureVFP3_D16, 1107 FeatureFP16, 1108 FeatureMP, 1109 FeatureSlowFPBrcc, 1110 FeatureHWDivARM, 1111 FeatureHasSlowFPVMLx, 1112 FeatureHasSlowFPVFMx, 1113 FeatureAvoidPartialCPSR]>; 1114 1115def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m, 1116 ProcM3, 1117 FeaturePrefLoopAlign32, 1118 FeatureUseMISched, 1119 FeatureHasNoBranchPredictor]>; 1120 1121def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m, 1122 ProcM3, 1123 FeatureUseMISched, 1124 FeatureHasNoBranchPredictor]>; 1125 1126def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em, 1127 FeatureVFP4_D16_SP, 1128 FeaturePrefLoopAlign32, 1129 FeatureHasSlowFPVMLx, 1130 FeatureHasSlowFPVFMx, 1131 FeatureUseMISched, 1132 FeatureHasNoBranchPredictor]>; 1133 1134def : ProcNoItin<"cortex-m7", [ARMv7em, 1135 FeatureFPARMv8_D16]>; 1136 1137def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, 1138 FeatureNoMovt]>; 1139 1140def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline, 1141 FeatureDSP, 1142 FeatureFPARMv8_D16_SP, 1143 FeaturePrefLoopAlign32, 1144 FeatureHasSlowFPVMLx, 1145 FeatureHasSlowFPVFMx, 1146 FeatureUseMISched, 1147 FeatureHasNoBranchPredictor]>; 1148 1149def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline, 1150 FeatureDSP, 1151 FeatureFPARMv8_D16_SP, 1152 FeaturePrefLoopAlign32, 1153 FeatureHasSlowFPVMLx, 1154 FeatureHasSlowFPVFMx, 1155 FeatureUseMISched, 1156 FeatureHasNoBranchPredictor]>; 1157 1158def : ProcessorModel<"cortex-m55", CortexM4Model, [ARMv81mMainline, 1159 FeatureDSP, 1160 FeatureFPARMv8_D16, 1161 FeatureUseMISched, 1162 FeatureHasNoBranchPredictor, 1163 FeaturePrefLoopAlign32, 1164 FeatureHasSlowFPVMLx, 1165 HasMVEFloatOps]>; 1166 1167def : ProcNoItin<"cortex-a32", [ARMv8a, 1168 FeatureHWDivThumb, 1169 FeatureHWDivARM, 1170 FeatureCrypto, 1171 FeatureCRC]>; 1172 1173def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, 1174 FeatureHWDivThumb, 1175 FeatureHWDivARM, 1176 FeatureCrypto, 1177 FeatureCRC]>; 1178 1179def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, 1180 FeatureHWDivThumb, 1181 FeatureHWDivARM, 1182 FeatureCrypto, 1183 FeatureCRC, 1184 FeatureFPAO]>; 1185 1186def : ProcNoItin<"cortex-a55", [ARMv82a, ProcA55, 1187 FeatureHWDivThumb, 1188 FeatureHWDivARM, 1189 FeatureDotProd]>; 1190 1191def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57, 1192 FeatureHWDivThumb, 1193 FeatureHWDivARM, 1194 FeatureCrypto, 1195 FeatureCRC, 1196 FeatureFPAO, 1197 FeatureAvoidPartialCPSR, 1198 FeatureCheapPredicableCPSR]>; 1199 1200def : ProcessorModel<"cortex-a72", CortexA57Model, [ARMv8a, ProcA72, 1201 FeatureHWDivThumb, 1202 FeatureHWDivARM, 1203 FeatureCrypto, 1204 FeatureCRC]>; 1205 1206def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, 1207 FeatureHWDivThumb, 1208 FeatureHWDivARM, 1209 FeatureCrypto, 1210 FeatureCRC]>; 1211 1212def : ProcNoItin<"cortex-a75", [ARMv82a, ProcA75, 1213 FeatureHWDivThumb, 1214 FeatureHWDivARM, 1215 FeatureDotProd]>; 1216 1217def : ProcNoItin<"cortex-a76", [ARMv82a, ProcA76, 1218 FeatureHWDivThumb, 1219 FeatureHWDivARM, 1220 FeatureCrypto, 1221 FeatureCRC, 1222 FeatureFullFP16, 1223 FeatureDotProd]>; 1224 1225def : ProcNoItin<"cortex-a76ae", [ARMv82a, ProcA76, 1226 FeatureHWDivThumb, 1227 FeatureHWDivARM, 1228 FeatureCrypto, 1229 FeatureCRC, 1230 FeatureFullFP16, 1231 FeatureDotProd]>; 1232 1233def : ProcNoItin<"cortex-a77", [ARMv82a, ProcA77, 1234 FeatureHWDivThumb, 1235 FeatureHWDivARM, 1236 FeatureCrypto, 1237 FeatureCRC, 1238 FeatureFullFP16, 1239 FeatureDotProd]>; 1240 1241def : ProcNoItin<"cortex-a78", [ARMv82a, ProcA78, 1242 FeatureHWDivThumb, 1243 FeatureHWDivARM, 1244 FeatureCrypto, 1245 FeatureCRC, 1246 FeatureFullFP16, 1247 FeatureDotProd]>; 1248 1249def : ProcNoItin<"cortex-x1", [ARMv82a, ProcX1, 1250 FeatureHWDivThumb, 1251 FeatureHWDivARM, 1252 FeatureCrypto, 1253 FeatureCRC, 1254 FeatureFullFP16, 1255 FeatureDotProd]>; 1256 1257def : ProcNoItin<"neoverse-n1", [ARMv82a, 1258 FeatureHWDivThumb, 1259 FeatureHWDivARM, 1260 FeatureCrypto, 1261 FeatureCRC, 1262 FeatureDotProd]>; 1263 1264def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, 1265 FeatureHasRetAddrStack, 1266 FeatureNEONForFP, 1267 FeatureVFP4, 1268 FeatureMP, 1269 FeatureHWDivThumb, 1270 FeatureHWDivARM, 1271 FeatureAvoidPartialCPSR, 1272 FeatureAvoidMOVsShOp, 1273 FeatureHasSlowFPVMLx, 1274 FeatureHasSlowFPVFMx, 1275 FeatureCrypto, 1276 FeatureUseMISched, 1277 FeatureZCZeroing, 1278 FeatureNoPostRASched]>; 1279 1280def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynos]>; 1281def : ProcNoItin<"exynos-m4", [ARMv82a, ProcExynos, 1282 FeatureFullFP16, 1283 FeatureDotProd]>; 1284def : ProcNoItin<"exynos-m5", [ARMv82a, ProcExynos, 1285 FeatureFullFP16, 1286 FeatureDotProd]>; 1287 1288def : ProcNoItin<"kryo", [ARMv8a, ProcKryo, 1289 FeatureHWDivThumb, 1290 FeatureHWDivARM, 1291 FeatureCrypto, 1292 FeatureCRC]>; 1293 1294def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, 1295 FeatureUseMISched, 1296 FeatureFPAO]>; 1297 1298//===----------------------------------------------------------------------===// 1299// Register File Description 1300//===----------------------------------------------------------------------===// 1301 1302include "ARMRegisterInfo.td" 1303include "ARMRegisterBanks.td" 1304include "ARMCallingConv.td" 1305 1306//===----------------------------------------------------------------------===// 1307// Instruction Descriptions 1308//===----------------------------------------------------------------------===// 1309 1310include "ARMInstrInfo.td" 1311def ARMInstrInfo : InstrInfo; 1312 1313//===----------------------------------------------------------------------===// 1314// Declare the target which we are implementing 1315//===----------------------------------------------------------------------===// 1316 1317def ARMAsmWriter : AsmWriter { 1318 string AsmWriterClassName = "InstPrinter"; 1319 int PassSubtarget = 1; 1320 int Variant = 0; 1321 bit isMCAsmWriter = 1; 1322} 1323 1324def ARMAsmParser : AsmParser { 1325 bit ReportMultipleNearMisses = 1; 1326} 1327 1328def ARMAsmParserVariant : AsmParserVariant { 1329 int Variant = 0; 1330 string Name = "ARM"; 1331 string BreakCharacters = "."; 1332} 1333 1334def ARM : Target { 1335 // Pull in Instruction Info. 1336 let InstructionSet = ARMInstrInfo; 1337 let AssemblyWriters = [ARMAsmWriter]; 1338 let AssemblyParsers = [ARMAsmParser]; 1339 let AssemblyParserVariants = [ARMAsmParserVariant]; 1340 let AllowRegisterRenaming = 1; 1341} 1342