1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// ARM Subtarget state. 20// 21 22def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", 23 "true", "Thumb mode">; 24 25def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat", 26 "true", "Use software floating " 27 "point features.">; 28 29 30//===----------------------------------------------------------------------===// 31// ARM Subtarget features. 32// 33 34// Floating Point, HW Division and Neon Support 35 36// FP loads/stores/moves, shared between VFP and MVE (even in the integer-only 37// version). 38def FeatureFPRegs : SubtargetFeature<"fpregs", "HasFPRegs", "true", 39 "Enable FP registers">; 40 41// 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16 42// extension) and MVE (even in the integer-only version). 43def FeatureFPRegs16 : SubtargetFeature<"fpregs16", "HasFPRegs16", "true", 44 "Enable 16-bit FP registers", 45 [FeatureFPRegs]>; 46 47def FeatureFPRegs64 : SubtargetFeature<"fpregs64", "HasFPRegs64", "true", 48 "Enable 64-bit FP registers", 49 [FeatureFPRegs]>; 50 51def FeatureFP64 : SubtargetFeature<"fp64", "HasFP64", "true", 52 "Floating point unit supports " 53 "double precision", 54 [FeatureFPRegs64]>; 55 56def FeatureD32 : SubtargetFeature<"d32", "HasD32", "true", 57 "Extend FP to 32 double registers">; 58 59multiclass VFPver<string name, string query, string description, 60 list<SubtargetFeature> prev, 61 list<SubtargetFeature> otherimplies, 62 list<SubtargetFeature> vfp2prev = []> { 63 def _D16_SP: SubtargetFeature< 64 name#"d16sp", query#"D16SP", "true", 65 description#" with only 16 d-registers and no double precision", 66 !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) # 67 !foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) # 68 otherimplies>; 69 def _SP: SubtargetFeature< 70 name#"sp", query#"SP", "true", 71 description#" with no double precision", 72 !foreach(v, prev, !cast<SubtargetFeature>(v # "_SP")) # 73 otherimplies # [FeatureD32, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; 74 def _D16: SubtargetFeature< 75 name#"d16", query#"D16", "true", 76 description#" with only 16 d-registers", 77 !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) # 78 vfp2prev # 79 otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; 80 def "": SubtargetFeature< 81 name, query, "true", description, 82 prev # otherimplies # [ 83 !cast<SubtargetFeature>(NAME # "_D16"), 84 !cast<SubtargetFeature>(NAME # "_SP")]>; 85} 86 87def FeatureVFP2_D16_SP : SubtargetFeature<"vfp2d16sp", "HasVFPv2D16SP", "true", 88 "Enable VFP2 instructions with " 89 "no double precision", 90 [FeatureFPRegs]>; 91def FeatureVFP2_SP : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true", 92 "Enable VFP2 instructions with " 93 "no double precision", 94 [FeatureVFP2_D16_SP]>; 95def FeatureVFP2_D16 : SubtargetFeature<"vfp2d16", "HasVFPv2D16", "true", 96 "Enable VFP2 instructions", 97 [FeatureFP64, FeatureVFP2_D16_SP]>; 98def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 99 "Enable VFP2 instructions", 100 [FeatureVFP2_D16, FeatureVFP2_SP]>; 101 102defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions", 103 [], [], [FeatureVFP2]>; 104 105def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 106 "Enable NEON instructions", 107 [FeatureVFP3]>; 108 109def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 110 "Enable half-precision " 111 "floating point">; 112 113defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions", 114 [FeatureVFP3], [FeatureFP16]>; 115 116defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP", 117 [FeatureVFP4], []>; 118 119def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 120 "Enable full half-precision " 121 "floating point", 122 [FeatureFPARMv8_D16_SP, FeatureFPRegs16]>; 123 124def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 125 "Enable full half-precision " 126 "floating point fml instructions", 127 [FeatureFullFP16]>; 128 129def FeatureHWDivThumb : SubtargetFeature<"hwdiv", 130 "HasHardwareDivideInThumb", "true", 131 "Enable divide instructions in Thumb">; 132 133def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 134 "HasHardwareDivideInARM", "true", 135 "Enable divide instructions in ARM mode">; 136 137// Atomic Support 138def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 139 "Has data barrier (dmb/dsb) instructions">; 140 141def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", 142 "Has v7 clrex instruction">; 143 144def FeatureDFB : SubtargetFeature<"dfb", "HasFullDataBarrier", "true", 145 "Has full data barrier (dfb) instruction">; 146 147def FeatureAcquireRelease : SubtargetFeature<"acquire-release", 148 "HasAcquireRelease", "true", 149 "Has v8 acquire/release (lda/ldaex " 150 " etc) instructions">; 151 152 153def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 154 "FP compare + branch is slow">; 155 156def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 157 "Enable support for Performance " 158 "Monitor extensions">; 159 160 161// TrustZone Security Extensions 162def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 163 "Enable support for TrustZone " 164 "security extensions">; 165 166def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", 167 "Enable support for ARMv8-M " 168 "Security Extensions">; 169 170def FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true", 171 "Enable SHA1 and SHA256 support", [FeatureNEON]>; 172 173def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 174 "Enable AES support", [FeatureNEON]>; 175 176def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 177 "Enable support for " 178 "Cryptography extensions", 179 [FeatureNEON, FeatureSHA2, FeatureAES]>; 180 181def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 182 "Enable support for CRC instructions">; 183 184def FeatureDotProd : SubtargetFeature<"dotprod", "HasDotProd", "true", 185 "Enable support for dot product instructions", 186 [FeatureNEON]>; 187 188// Not to be confused with FeatureHasRetAddrStack (return address stack) 189def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 190 "Enable Reliability, Availability " 191 "and Serviceability extensions">; 192 193// Fast computation of non-negative address offsets 194def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true", 195 "Enable fast computation of " 196 "positive address offsets">; 197 198// Fast execution of AES crypto operations 199def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true", 200 "CPU fuses AES crypto operations">; 201 202// Fast execution of bottom and top halves of literal generation 203def FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true", 204 "CPU fuses literal generation operations">; 205 206// The way of reading thread pointer 207def FeatureReadTp : SubtargetFeature<"read-tp-hard", "ReadTPHard", "true", 208 "Reading thread pointer from register">; 209 210// Cyclone can zero VFP registers in 0 cycles. 211def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 212 "Has zero-cycle zeroing instructions">; 213 214// Whether it is profitable to unpredicate certain instructions during if-conversion 215def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr", 216 "IsProfitableToUnpredicate", "true", 217 "Is profitable to unpredicate">; 218 219// Some targets (e.g. Swift) have microcoded VGETLNi32. 220def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32", 221 "HasSlowVGETLNi32", "true", 222 "Has slow VGETLNi32 - prefer VMOV">; 223 224// Some targets (e.g. Swift) have microcoded VDUP32. 225def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", 226 "true", 227 "Has slow VDUP32 - prefer VMOV">; 228 229// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON 230// for scalar FP, as this allows more effective execution domain optimization. 231def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR", 232 "true", "Prefer VMOVSR">; 233 234// Swift has ISHST barriers compatible with Atomic Release semantics but weaker 235// than ISH 236def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST", 237 "true", "Prefer ISHST barriers">; 238 239// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU. 240def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", 241 "true", 242 "Has muxed AGU and NEON/FPU">; 243 244// Whether VLDM/VSTM starting with odd register number need more microops 245// than single VLDRS 246def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister", 247 "true", "VLDM/VSTM starting " 248 "with an odd register is slow">; 249 250// Some targets have a renaming dependency when loading into D subregisters. 251def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg", 252 "SlowLoadDSubregister", "true", 253 "Loading into D subregs is slow">; 254 255def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp", 256 "UseWideStrideVFP", "true", 257 "Use a wide stride when allocating VFP registers">; 258 259// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. 260def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", 261 "DontWidenVMOVS", "true", 262 "Don't widen VMOVS to VMOVD">; 263 264// Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different 265// VFP register widths. 266def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon", 267 "SplatVFPToNeon", "true", 268 "Splat register from VFP to NEON", 269 [FeatureDontWidenVMOVS]>; 270 271// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions. 272def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", 273 "ExpandMLx", "true", 274 "Expand VFP/NEON MLA/MLS instructions">; 275 276// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS. 277def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards", 278 "true", "Has VMLx hazards">; 279 280// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from 281// VFP to NEON, as an execution domain optimization. 282def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", 283 "UseNEONForFPMovs", "true", 284 "Convert VMOVSR, VMOVRS, " 285 "VMOVS to NEON">; 286 287// Some processors benefit from using NEON instructions for scalar 288// single-precision FP operations. This affects instruction selection and should 289// only be enabled if the handling of denormals is not important. 290def FeatureNEONForFP : SubtargetFeature<"neonfp", 291 "UseNEONForSinglePrecisionFP", 292 "true", 293 "Use NEON for single precision FP">; 294 295// On some processors, VLDn instructions that access unaligned data take one 296// extra cycle. Take that into account when computing operand latencies. 297def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign", 298 "true", 299 "Check for VLDn unaligned access">; 300 301// Some processors have a nonpipelined VFP coprocessor. 302def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp", 303 "NonpipelinedVFP", "true", 304 "VFP instructions are not pipelined">; 305 306// Some processors have FP multiply-accumulate instructions that don't 307// play nicely with other VFP / NEON instructions, and it's generally better 308// to just not use them. 309def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 310 "Disable VFP / NEON MAC instructions">; 311 312// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 313def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 314 "HasVMLxForwarding", "true", 315 "Has multiplier accumulator forwarding">; 316 317// Disable 32-bit to 16-bit narrowing for experimentation. 318def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 319 "Prefer 32-bit Thumb instrs">; 320 321def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopAlignment","2", 322 "Prefer 32-bit alignment for loops">; 323 324/// Some instructions update CPSR partially, which can add false dependency for 325/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 326/// mapped to a separate physical register. Avoid partial CPSR update for these 327/// processors. 328def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 329 "AvoidCPSRPartialUpdate", "true", 330 "Avoid CPSR partial update for OOO execution">; 331 332/// Disable +1 predication cost for instructions updating CPSR. 333/// Enabled for Cortex-A57. 334def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr", 335 "CheapPredicableCPSRDef", 336 "true", 337 "Disable +1 predication cost for instructions updating CPSR">; 338 339def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 340 "AvoidMOVsShifterOperand", "true", 341 "Avoid movs instructions with " 342 "shifter operand">; 343 344// Some processors perform return stack prediction. CodeGen should avoid issue 345// "normal" call instructions to callees which do not return. 346def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", 347 "HasRetAddrStack", "true", 348 "Has return address stack">; 349 350// Some processors have no branch predictor, which changes the expected cost of 351// taking a branch which affects the choice of whether to use predicated 352// instructions. 353def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor", 354 "HasBranchPredictor", "false", 355 "Has no branch predictor">; 356 357/// DSP extension. 358def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", 359 "Supports DSP instructions in " 360 "ARM and/or Thumb2">; 361 362// Multiprocessing extension. 363def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 364 "Supports Multiprocessing extension">; 365 366// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 367def FeatureVirtualization : SubtargetFeature<"virtualization", 368 "HasVirtualization", "true", 369 "Supports Virtualization extension", 370 [FeatureHWDivThumb, FeatureHWDivARM]>; 371 372// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 373// See ARMInstrInfo.td for details. 374def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 375 "NaCl trap">; 376 377def FeatureStrictAlign : SubtargetFeature<"strict-align", 378 "StrictAlign", "true", 379 "Disallow all unaligned memory " 380 "access">; 381 382def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", 383 "Generate calls via indirect call " 384 "instructions">; 385 386def FeatureExecuteOnly : SubtargetFeature<"execute-only", 387 "GenExecuteOnly", "true", 388 "Enable the generation of " 389 "execute only code.">; 390 391def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", 392 "Reserve R9, making it unavailable" 393 " as GPR">; 394 395def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", 396 "Don't use movt/movw pairs for " 397 "32-bit imms">; 398 399def FeatureNoNegativeImmediates 400 : SubtargetFeature<"no-neg-immediates", 401 "NegativeImmediates", "false", 402 "Convert immediates and instructions " 403 "to their negated or complemented " 404 "equivalent when the immediate does " 405 "not fit in the encoding.">; 406 407// Use the MachineScheduler for instruction scheduling for the subtarget. 408def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true", 409 "Use the MachineScheduler">; 410 411def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler", 412 "DisablePostRAScheduler", "true", 413 "Don't schedule again after register allocation">; 414 415// Enable use of alias analysis during code generation 416def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", 417 "Use alias analysis during codegen">; 418 419// Armv8.5-A extensions 420 421def FeatureSB : SubtargetFeature<"sb", "HasSB", "true", 422 "Enable v8.5a Speculation Barrier" >; 423 424// Armv8.1-M extensions 425 426def FeatureLOB : SubtargetFeature<"lob", "HasLOB", "true", 427 "Enable Low Overhead Branch " 428 "extensions">; 429 430//===----------------------------------------------------------------------===// 431// ARM architecture class 432// 433 434// A-series ISA 435def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 436 "Is application profile ('A' series)">; 437 438// R-series ISA 439def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 440 "Is realtime profile ('R' series)">; 441 442// M-series ISA 443def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 444 "Is microcontroller profile ('M' series)">; 445 446 447def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 448 "Enable Thumb2 instructions">; 449 450def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 451 "Does not support ARM mode execution">; 452 453//===----------------------------------------------------------------------===// 454// ARM ISAa. 455// 456 457def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 458 "Support ARM v4T instructions">; 459 460def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 461 "Support ARM v5T instructions", 462 [HasV4TOps]>; 463 464def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 465 "Support ARM v5TE, v5TEj, and " 466 "v5TExp instructions", 467 [HasV5TOps]>; 468 469def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 470 "Support ARM v6 instructions", 471 [HasV5TEOps]>; 472 473def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 474 "Support ARM v6M instructions", 475 [HasV6Ops]>; 476 477def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", 478 "Support ARM v8M Baseline instructions", 479 [HasV6MOps]>; 480 481def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", 482 "Support ARM v6k instructions", 483 [HasV6Ops]>; 484 485def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 486 "Support ARM v6t2 instructions", 487 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; 488 489def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 490 "Support ARM v7 instructions", 491 [HasV6T2Ops, FeaturePerfMon, 492 FeatureV7Clrex]>; 493 494def HasV8MMainlineOps : 495 SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", 496 "Support ARM v8M Mainline instructions", 497 [HasV7Ops]>; 498 499def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 500 "Support ARM v8 instructions", 501 [HasV7Ops, FeatureAcquireRelease]>; 502 503def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 504 "Support ARM v8.1a instructions", 505 [HasV8Ops]>; 506 507def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 508 "Support ARM v8.2a instructions", 509 [HasV8_1aOps]>; 510 511def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 512 "Support ARM v8.3a instructions", 513 [HasV8_2aOps]>; 514 515def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 516 "Support ARM v8.4a instructions", 517 [HasV8_3aOps, FeatureDotProd]>; 518 519def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true", 520 "Support ARM v8.5a instructions", 521 [HasV8_4aOps, FeatureSB]>; 522 523def HasV8_1MMainlineOps : SubtargetFeature< 524 "v8.1m.main", "HasV8_1MMainlineOps", "true", 525 "Support ARM v8-1M Mainline instructions", 526 [HasV8MMainlineOps]>; 527def HasMVEIntegerOps : SubtargetFeature< 528 "mve", "HasMVEIntegerOps", "true", 529 "Support M-Class Vector Extension with integer ops", 530 [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>; 531def HasMVEFloatOps : SubtargetFeature< 532 "mve.fp", "HasMVEFloatOps", "true", 533 "Support M-Class Vector Extension with integer and floating ops", 534 [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>; 535 536//===----------------------------------------------------------------------===// 537// ARM Processor subtarget features. 538// 539 540def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 541 "Cortex-A5 ARM processors", []>; 542def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 543 "Cortex-A7 ARM processors", []>; 544def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 545 "Cortex-A8 ARM processors", []>; 546def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 547 "Cortex-A9 ARM processors", []>; 548def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 549 "Cortex-A12 ARM processors", []>; 550def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 551 "Cortex-A15 ARM processors", []>; 552def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", 553 "Cortex-A17 ARM processors", []>; 554def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", 555 "Cortex-A32 ARM processors", []>; 556def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 557 "Cortex-A35 ARM processors", []>; 558def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 559 "Cortex-A53 ARM processors", []>; 560def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 561 "Cortex-A55 ARM processors", []>; 562def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 563 "Cortex-A57 ARM processors", []>; 564def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 565 "Cortex-A72 ARM processors", []>; 566def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 567 "Cortex-A73 ARM processors", []>; 568def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 569 "Cortex-A75 ARM processors", []>; 570def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 571 "Cortex-A76 ARM processors", []>; 572 573def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 574 "Qualcomm Krait processors", []>; 575def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 576 "Qualcomm Kryo processors", []>; 577def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 578 "Swift ARM processors", []>; 579 580def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos", 581 "Samsung Exynos processors", 582 [FeatureZCZeroing, 583 FeatureUseWideStrideVFP, 584 FeatureUseAA, 585 FeatureSplatVFPToNeon, 586 FeatureSlowVGETLNi32, 587 FeatureSlowVDUP32, 588 FeatureSlowFPBrcc, 589 FeatureProfUnpredicate, 590 FeatureHWDivThumb, 591 FeatureHWDivARM, 592 FeatureHasSlowFPVMLx, 593 FeatureHasRetAddrStack, 594 FeatureFuseLiterals, 595 FeatureFuseAES, 596 FeatureExpandMLx, 597 FeatureCrypto, 598 FeatureCRC]>; 599 600def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", 601 "Cortex-R4 ARM processors", []>; 602def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 603 "Cortex-R5 ARM processors", []>; 604def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", 605 "Cortex-R7 ARM processors", []>; 606def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", 607 "Cortex-R52 ARM processors", []>; 608 609def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", 610 "Cortex-M3 ARM processors", []>; 611 612 613//===----------------------------------------------------------------------===// 614// ARM Helper classes. 615// 616 617class Architecture<string fname, string aname, list<SubtargetFeature> features> 618 : SubtargetFeature<fname, "ARMArch", aname, 619 !strconcat(aname, " architecture"), features>; 620 621class ProcNoItin<string Name, list<SubtargetFeature> Features> 622 : Processor<Name, NoItineraries, Features>; 623 624 625//===----------------------------------------------------------------------===// 626// ARM architectures 627// 628 629def ARMv2 : Architecture<"armv2", "ARMv2", []>; 630 631def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; 632 633def ARMv3 : Architecture<"armv3", "ARMv3", []>; 634 635def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; 636 637def ARMv4 : Architecture<"armv4", "ARMv4", []>; 638 639def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; 640 641def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; 642 643def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; 644 645def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; 646 647def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops, 648 FeatureDSP]>; 649 650def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, 651 FeatureDSP]>; 652 653def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; 654 655def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, 656 FeatureTrustZone]>; 657 658def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, 659 FeatureNoARM, 660 ModeThumb, 661 FeatureDB, 662 FeatureMClass, 663 FeatureStrictAlign]>; 664 665def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, 666 FeatureNoARM, 667 ModeThumb, 668 FeatureDB, 669 FeatureMClass, 670 FeatureStrictAlign]>; 671 672def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, 673 FeatureNEON, 674 FeatureDB, 675 FeatureDSP, 676 FeatureAClass]>; 677 678def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops, 679 FeatureNEON, 680 FeatureDB, 681 FeatureDSP, 682 FeatureTrustZone, 683 FeatureMP, 684 FeatureVirtualization, 685 FeatureAClass]>; 686 687def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, 688 FeatureDB, 689 FeatureDSP, 690 FeatureHWDivThumb, 691 FeatureRClass]>; 692 693def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, 694 FeatureThumb2, 695 FeatureNoARM, 696 ModeThumb, 697 FeatureDB, 698 FeatureHWDivThumb, 699 FeatureMClass]>; 700 701def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, 702 FeatureThumb2, 703 FeatureNoARM, 704 ModeThumb, 705 FeatureDB, 706 FeatureHWDivThumb, 707 FeatureMClass, 708 FeatureDSP]>; 709 710def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, 711 FeatureAClass, 712 FeatureDB, 713 FeatureFPARMv8, 714 FeatureNEON, 715 FeatureDSP, 716 FeatureTrustZone, 717 FeatureMP, 718 FeatureVirtualization, 719 FeatureCrypto, 720 FeatureCRC]>; 721 722def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, 723 FeatureAClass, 724 FeatureDB, 725 FeatureFPARMv8, 726 FeatureNEON, 727 FeatureDSP, 728 FeatureTrustZone, 729 FeatureMP, 730 FeatureVirtualization, 731 FeatureCrypto, 732 FeatureCRC]>; 733 734def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, 735 FeatureAClass, 736 FeatureDB, 737 FeatureFPARMv8, 738 FeatureNEON, 739 FeatureDSP, 740 FeatureTrustZone, 741 FeatureMP, 742 FeatureVirtualization, 743 FeatureCrypto, 744 FeatureCRC, 745 FeatureRAS]>; 746 747def ARMv83a : Architecture<"armv8.3-a", "ARMv83a", [HasV8_3aOps, 748 FeatureAClass, 749 FeatureDB, 750 FeatureFPARMv8, 751 FeatureNEON, 752 FeatureDSP, 753 FeatureTrustZone, 754 FeatureMP, 755 FeatureVirtualization, 756 FeatureCrypto, 757 FeatureCRC, 758 FeatureRAS]>; 759 760def ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps, 761 FeatureAClass, 762 FeatureDB, 763 FeatureFPARMv8, 764 FeatureNEON, 765 FeatureDSP, 766 FeatureTrustZone, 767 FeatureMP, 768 FeatureVirtualization, 769 FeatureCrypto, 770 FeatureCRC, 771 FeatureRAS, 772 FeatureDotProd]>; 773 774def ARMv85a : Architecture<"armv8.5-a", "ARMv85a", [HasV8_5aOps, 775 FeatureAClass, 776 FeatureDB, 777 FeatureFPARMv8, 778 FeatureNEON, 779 FeatureDSP, 780 FeatureTrustZone, 781 FeatureMP, 782 FeatureVirtualization, 783 FeatureCrypto, 784 FeatureCRC, 785 FeatureRAS, 786 FeatureDotProd]>; 787 788def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, 789 FeatureRClass, 790 FeatureDB, 791 FeatureDFB, 792 FeatureDSP, 793 FeatureCRC, 794 FeatureMP, 795 FeatureVirtualization, 796 FeatureFPARMv8, 797 FeatureNEON]>; 798 799def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", 800 [HasV8MBaselineOps, 801 FeatureNoARM, 802 ModeThumb, 803 FeatureDB, 804 FeatureHWDivThumb, 805 FeatureV7Clrex, 806 Feature8MSecExt, 807 FeatureAcquireRelease, 808 FeatureMClass, 809 FeatureStrictAlign]>; 810 811def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", 812 [HasV8MMainlineOps, 813 FeatureNoARM, 814 ModeThumb, 815 FeatureDB, 816 FeatureHWDivThumb, 817 Feature8MSecExt, 818 FeatureAcquireRelease, 819 FeatureMClass]>; 820 821def ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline", 822 [HasV8_1MMainlineOps, 823 FeatureNoARM, 824 ModeThumb, 825 FeatureDB, 826 FeatureHWDivThumb, 827 Feature8MSecExt, 828 FeatureAcquireRelease, 829 FeatureMClass, 830 FeatureRAS, 831 FeatureLOB]>; 832 833// Aliases 834def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; 835def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; 836def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; 837def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; 838def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; 839def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; 840 841 842//===----------------------------------------------------------------------===// 843// ARM schedules. 844//===----------------------------------------------------------------------===// 845// 846include "ARMPredicates.td" 847include "ARMSchedule.td" 848 849//===----------------------------------------------------------------------===// 850// ARM processors 851// 852 853// Dummy CPU, used to target architectures 854def : ProcessorModel<"generic", CortexA8Model, []>; 855 856// FIXME: Several processors below are not using their own scheduler 857// model, but one of similar/previous processor. These should be fixed. 858 859def : ProcNoItin<"arm8", [ARMv4]>; 860def : ProcNoItin<"arm810", [ARMv4]>; 861def : ProcNoItin<"strongarm", [ARMv4]>; 862def : ProcNoItin<"strongarm110", [ARMv4]>; 863def : ProcNoItin<"strongarm1100", [ARMv4]>; 864def : ProcNoItin<"strongarm1110", [ARMv4]>; 865 866def : ProcNoItin<"arm7tdmi", [ARMv4t]>; 867def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; 868def : ProcNoItin<"arm710t", [ARMv4t]>; 869def : ProcNoItin<"arm720t", [ARMv4t]>; 870def : ProcNoItin<"arm9", [ARMv4t]>; 871def : ProcNoItin<"arm9tdmi", [ARMv4t]>; 872def : ProcNoItin<"arm920", [ARMv4t]>; 873def : ProcNoItin<"arm920t", [ARMv4t]>; 874def : ProcNoItin<"arm922t", [ARMv4t]>; 875def : ProcNoItin<"arm940t", [ARMv4t]>; 876def : ProcNoItin<"ep9312", [ARMv4t]>; 877 878def : ProcNoItin<"arm10tdmi", [ARMv5t]>; 879def : ProcNoItin<"arm1020t", [ARMv5t]>; 880 881def : ProcNoItin<"arm9e", [ARMv5te]>; 882def : ProcNoItin<"arm926ej-s", [ARMv5te]>; 883def : ProcNoItin<"arm946e-s", [ARMv5te]>; 884def : ProcNoItin<"arm966e-s", [ARMv5te]>; 885def : ProcNoItin<"arm968e-s", [ARMv5te]>; 886def : ProcNoItin<"arm10e", [ARMv5te]>; 887def : ProcNoItin<"arm1020e", [ARMv5te]>; 888def : ProcNoItin<"arm1022e", [ARMv5te]>; 889def : ProcNoItin<"xscale", [ARMv5te]>; 890def : ProcNoItin<"iwmmxt", [ARMv5te]>; 891 892def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; 893def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, 894 FeatureVFP2, 895 FeatureHasSlowFPVMLx]>; 896 897def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>; 898def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>; 899def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>; 900def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>; 901 902def : Processor<"arm1176j-s", ARMV6Itineraries, [ARMv6kz]>; 903def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; 904def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, 905 FeatureVFP2, 906 FeatureHasSlowFPVMLx]>; 907 908def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; 909def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, 910 FeatureVFP2, 911 FeatureHasSlowFPVMLx]>; 912 913def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; 914def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, 915 FeatureVFP2, 916 FeatureHasSlowFPVMLx]>; 917 918def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, 919 FeatureHasRetAddrStack, 920 FeatureTrustZone, 921 FeatureSlowFPBrcc, 922 FeatureHasSlowFPVMLx, 923 FeatureVMLxForwarding, 924 FeatureMP, 925 FeatureVFP4]>; 926 927def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, 928 FeatureHasRetAddrStack, 929 FeatureTrustZone, 930 FeatureSlowFPBrcc, 931 FeatureHasVMLxHazards, 932 FeatureHasSlowFPVMLx, 933 FeatureVMLxForwarding, 934 FeatureMP, 935 FeatureVFP4, 936 FeatureVirtualization]>; 937 938def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, 939 FeatureHasRetAddrStack, 940 FeatureNonpipelinedVFP, 941 FeatureTrustZone, 942 FeatureSlowFPBrcc, 943 FeatureHasVMLxHazards, 944 FeatureHasSlowFPVMLx, 945 FeatureVMLxForwarding]>; 946 947def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, 948 FeatureHasRetAddrStack, 949 FeatureTrustZone, 950 FeatureHasVMLxHazards, 951 FeatureVMLxForwarding, 952 FeatureFP16, 953 FeatureAvoidPartialCPSR, 954 FeatureExpandMLx, 955 FeaturePreferVMOVSR, 956 FeatureMuxedUnits, 957 FeatureNEONForFPMovs, 958 FeatureCheckVLDnAlign, 959 FeatureMP]>; 960 961def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, 962 FeatureHasRetAddrStack, 963 FeatureTrustZone, 964 FeatureVMLxForwarding, 965 FeatureVFP4, 966 FeatureAvoidPartialCPSR, 967 FeatureVirtualization, 968 FeatureMP]>; 969 970def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, 971 FeatureDontWidenVMOVS, 972 FeatureSplatVFPToNeon, 973 FeatureHasRetAddrStack, 974 FeatureMuxedUnits, 975 FeatureTrustZone, 976 FeatureVFP4, 977 FeatureMP, 978 FeatureCheckVLDnAlign, 979 FeatureAvoidPartialCPSR, 980 FeatureVirtualization]>; 981 982def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, 983 FeatureHasRetAddrStack, 984 FeatureTrustZone, 985 FeatureMP, 986 FeatureVMLxForwarding, 987 FeatureVFP4, 988 FeatureAvoidPartialCPSR, 989 FeatureVirtualization]>; 990 991// FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv 992def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, 993 FeatureHasRetAddrStack, 994 FeatureMuxedUnits, 995 FeatureCheckVLDnAlign, 996 FeatureVMLxForwarding, 997 FeatureFP16, 998 FeatureAvoidPartialCPSR, 999 FeatureVFP4, 1000 FeatureHWDivThumb, 1001 FeatureHWDivARM]>; 1002 1003def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, 1004 FeatureHasRetAddrStack, 1005 FeatureNEONForFP, 1006 FeatureVFP4, 1007 FeatureUseWideStrideVFP, 1008 FeatureMP, 1009 FeatureHWDivThumb, 1010 FeatureHWDivARM, 1011 FeatureAvoidPartialCPSR, 1012 FeatureAvoidMOVsShOp, 1013 FeatureHasSlowFPVMLx, 1014 FeatureHasVMLxHazards, 1015 FeatureProfUnpredicate, 1016 FeaturePrefISHSTBarrier, 1017 FeatureSlowOddRegister, 1018 FeatureSlowLoadDSubreg, 1019 FeatureSlowVGETLNi32, 1020 FeatureSlowVDUP32, 1021 FeatureUseMISched, 1022 FeatureNoPostRASched]>; 1023 1024def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, 1025 FeatureHasRetAddrStack, 1026 FeatureAvoidPartialCPSR]>; 1027 1028def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, 1029 FeatureHasRetAddrStack, 1030 FeatureSlowFPBrcc, 1031 FeatureHasSlowFPVMLx, 1032 FeatureVFP3_D16, 1033 FeatureAvoidPartialCPSR]>; 1034 1035def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, 1036 FeatureHasRetAddrStack, 1037 FeatureVFP3_D16, 1038 FeatureSlowFPBrcc, 1039 FeatureHWDivARM, 1040 FeatureHasSlowFPVMLx, 1041 FeatureAvoidPartialCPSR]>; 1042 1043def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, 1044 FeatureHasRetAddrStack, 1045 FeatureVFP3_D16, 1046 FeatureFP16, 1047 FeatureMP, 1048 FeatureSlowFPBrcc, 1049 FeatureHWDivARM, 1050 FeatureHasSlowFPVMLx, 1051 FeatureAvoidPartialCPSR]>; 1052 1053def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, 1054 FeatureHasRetAddrStack, 1055 FeatureVFP3_D16, 1056 FeatureFP16, 1057 FeatureMP, 1058 FeatureSlowFPBrcc, 1059 FeatureHWDivARM, 1060 FeatureHasSlowFPVMLx, 1061 FeatureAvoidPartialCPSR]>; 1062 1063def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m, 1064 ProcM3, 1065 FeaturePrefLoopAlign32, 1066 FeatureUseMISched, 1067 FeatureUseAA, 1068 FeatureHasNoBranchPredictor]>; 1069 1070def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m, 1071 ProcM3, 1072 FeatureUseMISched, 1073 FeatureUseAA, 1074 FeatureHasNoBranchPredictor]>; 1075 1076def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em, 1077 FeatureVFP4_D16_SP, 1078 FeaturePrefLoopAlign32, 1079 FeatureHasSlowFPVMLx, 1080 FeatureUseMISched, 1081 FeatureUseAA, 1082 FeatureHasNoBranchPredictor]>; 1083 1084def : ProcNoItin<"cortex-m7", [ARMv7em, 1085 FeatureFPARMv8_D16]>; 1086 1087def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, 1088 FeatureNoMovt]>; 1089 1090def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline, 1091 FeatureDSP, 1092 FeatureFPARMv8_D16_SP, 1093 FeaturePrefLoopAlign32, 1094 FeatureHasSlowFPVMLx, 1095 FeatureUseMISched, 1096 FeatureUseAA, 1097 FeatureHasNoBranchPredictor]>; 1098 1099def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline, 1100 FeatureDSP, 1101 FeatureFPARMv8_D16_SP, 1102 FeaturePrefLoopAlign32, 1103 FeatureHasSlowFPVMLx, 1104 FeatureUseMISched, 1105 FeatureUseAA, 1106 FeatureHasNoBranchPredictor]>; 1107 1108 1109def : ProcNoItin<"cortex-a32", [ARMv8a, 1110 FeatureHWDivThumb, 1111 FeatureHWDivARM, 1112 FeatureCrypto, 1113 FeatureCRC]>; 1114 1115def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, 1116 FeatureHWDivThumb, 1117 FeatureHWDivARM, 1118 FeatureCrypto, 1119 FeatureCRC]>; 1120 1121def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, 1122 FeatureHWDivThumb, 1123 FeatureHWDivARM, 1124 FeatureCrypto, 1125 FeatureCRC, 1126 FeatureFPAO]>; 1127 1128def : ProcNoItin<"cortex-a55", [ARMv82a, ProcA55, 1129 FeatureHWDivThumb, 1130 FeatureHWDivARM, 1131 FeatureDotProd]>; 1132 1133def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57, 1134 FeatureHWDivThumb, 1135 FeatureHWDivARM, 1136 FeatureCrypto, 1137 FeatureCRC, 1138 FeatureFPAO, 1139 FeatureAvoidPartialCPSR, 1140 FeatureCheapPredicableCPSR]>; 1141 1142def : ProcessorModel<"cortex-a72", CortexA57Model, [ARMv8a, ProcA72, 1143 FeatureHWDivThumb, 1144 FeatureHWDivARM, 1145 FeatureCrypto, 1146 FeatureCRC]>; 1147 1148def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, 1149 FeatureHWDivThumb, 1150 FeatureHWDivARM, 1151 FeatureCrypto, 1152 FeatureCRC]>; 1153 1154def : ProcNoItin<"cortex-a75", [ARMv82a, ProcA75, 1155 FeatureHWDivThumb, 1156 FeatureHWDivARM, 1157 FeatureDotProd]>; 1158 1159def : ProcNoItin<"cortex-a76", [ARMv82a, ProcA76, 1160 FeatureHWDivThumb, 1161 FeatureHWDivARM, 1162 FeatureCrypto, 1163 FeatureCRC, 1164 FeatureFullFP16, 1165 FeatureDotProd]>; 1166 1167def : ProcNoItin<"cortex-a76ae", [ARMv82a, ProcA76, 1168 FeatureHWDivThumb, 1169 FeatureHWDivARM, 1170 FeatureCrypto, 1171 FeatureCRC, 1172 FeatureFullFP16, 1173 FeatureDotProd]>; 1174 1175def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, 1176 FeatureHasRetAddrStack, 1177 FeatureNEONForFP, 1178 FeatureVFP4, 1179 FeatureMP, 1180 FeatureHWDivThumb, 1181 FeatureHWDivARM, 1182 FeatureAvoidPartialCPSR, 1183 FeatureAvoidMOVsShOp, 1184 FeatureHasSlowFPVMLx, 1185 FeatureCrypto, 1186 FeatureUseMISched, 1187 FeatureZCZeroing, 1188 FeatureNoPostRASched]>; 1189 1190def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynos]>; 1191def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynos]>; 1192def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynos]>; 1193def : ProcNoItin<"exynos-m4", [ARMv82a, ProcExynos, 1194 FeatureFullFP16, 1195 FeatureDotProd]>; 1196def : ProcNoItin<"exynos-m5", [ARMv82a, ProcExynos, 1197 FeatureFullFP16, 1198 FeatureDotProd]>; 1199 1200def : ProcNoItin<"kryo", [ARMv8a, ProcKryo, 1201 FeatureHWDivThumb, 1202 FeatureHWDivARM, 1203 FeatureCrypto, 1204 FeatureCRC]>; 1205 1206def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, 1207 FeatureUseMISched, 1208 FeatureFPAO, 1209 FeatureUseAA]>; 1210 1211//===----------------------------------------------------------------------===// 1212// Register File Description 1213//===----------------------------------------------------------------------===// 1214 1215include "ARMRegisterInfo.td" 1216include "ARMRegisterBanks.td" 1217include "ARMCallingConv.td" 1218 1219//===----------------------------------------------------------------------===// 1220// Instruction Descriptions 1221//===----------------------------------------------------------------------===// 1222 1223include "ARMInstrInfo.td" 1224def ARMInstrInfo : InstrInfo; 1225 1226//===----------------------------------------------------------------------===// 1227// Declare the target which we are implementing 1228//===----------------------------------------------------------------------===// 1229 1230def ARMAsmWriter : AsmWriter { 1231 string AsmWriterClassName = "InstPrinter"; 1232 int PassSubtarget = 1; 1233 int Variant = 0; 1234 bit isMCAsmWriter = 1; 1235} 1236 1237def ARMAsmParser : AsmParser { 1238 bit ReportMultipleNearMisses = 1; 1239} 1240 1241def ARMAsmParserVariant : AsmParserVariant { 1242 int Variant = 0; 1243 string Name = "ARM"; 1244 string BreakCharacters = "."; 1245} 1246 1247def ARM : Target { 1248 // Pull in Instruction Info. 1249 let InstructionSet = ARMInstrInfo; 1250 let AssemblyWriters = [ARMAsmWriter]; 1251 let AssemblyParsers = [ARMAsmParser]; 1252 let AssemblyParserVariants = [ARMAsmParserVariant]; 1253 let AllowRegisterRenaming = 1; 1254} 1255