1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// ARM Subtarget state. 20// 21 22def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", 23 "true", "Thumb mode">; 24 25def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat", 26 "true", "Use software floating " 27 "point features.">; 28 29 30//===----------------------------------------------------------------------===// 31// ARM Subtarget features. 32// 33 34// Floating Point, HW Division and Neon Support 35 36// FP loads/stores/moves, shared between VFP and MVE (even in the integer-only 37// version). 38def FeatureFPRegs : SubtargetFeature<"fpregs", "HasFPRegs", "true", 39 "Enable FP registers">; 40 41// 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16 42// extension) and MVE (even in the integer-only version). 43def FeatureFPRegs16 : SubtargetFeature<"fpregs16", "HasFPRegs16", "true", 44 "Enable 16-bit FP registers", 45 [FeatureFPRegs]>; 46 47def FeatureFPRegs64 : SubtargetFeature<"fpregs64", "HasFPRegs64", "true", 48 "Enable 64-bit FP registers", 49 [FeatureFPRegs]>; 50 51def FeatureFP64 : SubtargetFeature<"fp64", "HasFP64", "true", 52 "Floating point unit supports " 53 "double precision", 54 [FeatureFPRegs64]>; 55 56def FeatureD32 : SubtargetFeature<"d32", "HasD32", "true", 57 "Extend FP to 32 double registers">; 58 59multiclass VFPver<string name, string query, string description, 60 list<SubtargetFeature> prev, 61 list<SubtargetFeature> otherimplies, 62 list<SubtargetFeature> vfp2prev = []> { 63 def _D16_SP: SubtargetFeature< 64 name#"d16sp", query#"D16SP", "true", 65 description#" with only 16 d-registers and no double precision", 66 !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) # 67 !foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) # 68 otherimplies>; 69 def _SP: SubtargetFeature< 70 name#"sp", query#"SP", "true", 71 description#" with no double precision", 72 !foreach(v, prev, !cast<SubtargetFeature>(v # "_SP")) # 73 otherimplies # [FeatureD32, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; 74 def _D16: SubtargetFeature< 75 name#"d16", query#"D16", "true", 76 description#" with only 16 d-registers", 77 !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) # 78 vfp2prev # 79 otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; 80 def "": SubtargetFeature< 81 name, query, "true", description, 82 prev # otherimplies # [ 83 !cast<SubtargetFeature>(NAME # "_D16"), 84 !cast<SubtargetFeature>(NAME # "_SP")]>; 85} 86 87def FeatureVFP2_SP : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true", 88 "Enable VFP2 instructions with " 89 "no double precision", 90 [FeatureFPRegs]>; 91 92def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 93 "Enable VFP2 instructions", 94 [FeatureFP64, FeatureVFP2_SP]>; 95 96defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions", 97 [], [], [FeatureVFP2]>; 98 99def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 100 "Enable NEON instructions", 101 [FeatureVFP3]>; 102 103def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 104 "Enable half-precision " 105 "floating point">; 106 107defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions", 108 [FeatureVFP3], [FeatureFP16]>; 109 110defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP", 111 [FeatureVFP4], []>; 112 113def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 114 "Enable full half-precision " 115 "floating point", 116 [FeatureFPARMv8_D16_SP, FeatureFPRegs16]>; 117 118def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 119 "Enable full half-precision " 120 "floating point fml instructions", 121 [FeatureFullFP16]>; 122 123def FeatureHWDivThumb : SubtargetFeature<"hwdiv", 124 "HasHardwareDivideInThumb", "true", 125 "Enable divide instructions in Thumb">; 126 127def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 128 "HasHardwareDivideInARM", "true", 129 "Enable divide instructions in ARM mode">; 130 131// Atomic Support 132def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 133 "Has data barrier (dmb/dsb) instructions">; 134 135def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", 136 "Has v7 clrex instruction">; 137 138def FeatureDFB : SubtargetFeature<"dfb", "HasFullDataBarrier", "true", 139 "Has full data barrier (dfb) instruction">; 140 141def FeatureAcquireRelease : SubtargetFeature<"acquire-release", 142 "HasAcquireRelease", "true", 143 "Has v8 acquire/release (lda/ldaex " 144 " etc) instructions">; 145 146 147def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 148 "FP compare + branch is slow">; 149 150def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 151 "Enable support for Performance " 152 "Monitor extensions">; 153 154 155// TrustZone Security Extensions 156def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 157 "Enable support for TrustZone " 158 "security extensions">; 159 160def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", 161 "Enable support for ARMv8-M " 162 "Security Extensions">; 163 164def FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true", 165 "Enable SHA1 and SHA256 support", [FeatureNEON]>; 166 167def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 168 "Enable AES support", [FeatureNEON]>; 169 170def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 171 "Enable support for " 172 "Cryptography extensions", 173 [FeatureNEON, FeatureSHA2, FeatureAES]>; 174 175def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 176 "Enable support for CRC instructions">; 177 178def FeatureDotProd : SubtargetFeature<"dotprod", "HasDotProd", "true", 179 "Enable support for dot product instructions", 180 [FeatureNEON]>; 181 182// Not to be confused with FeatureHasRetAddrStack (return address stack) 183def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 184 "Enable Reliability, Availability " 185 "and Serviceability extensions">; 186 187// Fast computation of non-negative address offsets 188def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true", 189 "Enable fast computation of " 190 "positive address offsets">; 191 192// Fast execution of AES crypto operations 193def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true", 194 "CPU fuses AES crypto operations">; 195 196// Fast execution of bottom and top halves of literal generation 197def FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true", 198 "CPU fuses literal generation operations">; 199 200// The way of reading thread pointer 201def FeatureReadTp : SubtargetFeature<"read-tp-hard", "ReadTPHard", "true", 202 "Reading thread pointer from register">; 203 204// Cyclone can zero VFP registers in 0 cycles. 205def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 206 "Has zero-cycle zeroing instructions">; 207 208// Whether it is profitable to unpredicate certain instructions during if-conversion 209def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr", 210 "IsProfitableToUnpredicate", "true", 211 "Is profitable to unpredicate">; 212 213// Some targets (e.g. Swift) have microcoded VGETLNi32. 214def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32", 215 "HasSlowVGETLNi32", "true", 216 "Has slow VGETLNi32 - prefer VMOV">; 217 218// Some targets (e.g. Swift) have microcoded VDUP32. 219def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", 220 "true", 221 "Has slow VDUP32 - prefer VMOV">; 222 223// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON 224// for scalar FP, as this allows more effective execution domain optimization. 225def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR", 226 "true", "Prefer VMOVSR">; 227 228// Swift has ISHST barriers compatible with Atomic Release semantics but weaker 229// than ISH 230def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST", 231 "true", "Prefer ISHST barriers">; 232 233// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU. 234def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", 235 "true", 236 "Has muxed AGU and NEON/FPU">; 237 238// Whether VLDM/VSTM starting with odd register number need more microops 239// than single VLDRS 240def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister", 241 "true", "VLDM/VSTM starting " 242 "with an odd register is slow">; 243 244// Some targets have a renaming dependency when loading into D subregisters. 245def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg", 246 "SlowLoadDSubregister", "true", 247 "Loading into D subregs is slow">; 248 249def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp", 250 "UseWideStrideVFP", "true", 251 "Use a wide stride when allocating VFP registers">; 252 253// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. 254def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", 255 "DontWidenVMOVS", "true", 256 "Don't widen VMOVS to VMOVD">; 257 258// Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different 259// VFP register widths. 260def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon", 261 "SplatVFPToNeon", "true", 262 "Splat register from VFP to NEON", 263 [FeatureDontWidenVMOVS]>; 264 265// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions. 266def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", 267 "ExpandMLx", "true", 268 "Expand VFP/NEON MLA/MLS instructions">; 269 270// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS. 271def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards", 272 "true", "Has VMLx hazards">; 273 274// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from 275// VFP to NEON, as an execution domain optimization. 276def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", 277 "UseNEONForFPMovs", "true", 278 "Convert VMOVSR, VMOVRS, " 279 "VMOVS to NEON">; 280 281// Some processors benefit from using NEON instructions for scalar 282// single-precision FP operations. This affects instruction selection and should 283// only be enabled if the handling of denormals is not important. 284def FeatureNEONForFP : SubtargetFeature<"neonfp", 285 "UseNEONForSinglePrecisionFP", 286 "true", 287 "Use NEON for single precision FP">; 288 289// On some processors, VLDn instructions that access unaligned data take one 290// extra cycle. Take that into account when computing operand latencies. 291def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign", 292 "true", 293 "Check for VLDn unaligned access">; 294 295// Some processors have a nonpipelined VFP coprocessor. 296def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp", 297 "NonpipelinedVFP", "true", 298 "VFP instructions are not pipelined">; 299 300// Some processors have FP multiply-accumulate instructions that don't 301// play nicely with other VFP / NEON instructions, and it's generally better 302// to just not use them. 303def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 304 "Disable VFP / NEON MAC instructions">; 305 306// VFPv4 added VFMA instructions that can similar be fast or slow. 307def FeatureHasSlowFPVFMx : SubtargetFeature<"slowfpvfmx", "SlowFPVFMx", "true", 308 "Disable VFP / NEON FMA instructions">; 309 310// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 311def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 312 "HasVMLxForwarding", "true", 313 "Has multiplier accumulator forwarding">; 314 315// Disable 32-bit to 16-bit narrowing for experimentation. 316def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 317 "Prefer 32-bit Thumb instrs">; 318 319def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopLogAlignment","2", 320 "Prefer 32-bit alignment for loops">; 321 322def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "1", 323 "Model MVE instructions as a 1 beat per tick architecture">; 324 325def FeatureMVEVectorCostFactor2 : SubtargetFeature<"mve2beat", "MVEVectorCostFactor", "2", 326 "Model MVE instructions as a 2 beats per tick architecture">; 327 328def FeatureMVEVectorCostFactor4 : SubtargetFeature<"mve4beat", "MVEVectorCostFactor", "4", 329 "Model MVE instructions as a 4 beats per tick architecture">; 330 331/// Some instructions update CPSR partially, which can add false dependency for 332/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 333/// mapped to a separate physical register. Avoid partial CPSR update for these 334/// processors. 335def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 336 "AvoidCPSRPartialUpdate", "true", 337 "Avoid CPSR partial update for OOO execution">; 338 339/// Disable +1 predication cost for instructions updating CPSR. 340/// Enabled for Cortex-A57. 341def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr", 342 "CheapPredicableCPSRDef", 343 "true", 344 "Disable +1 predication cost for instructions updating CPSR">; 345 346def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 347 "AvoidMOVsShifterOperand", "true", 348 "Avoid movs instructions with " 349 "shifter operand">; 350 351// Some processors perform return stack prediction. CodeGen should avoid issue 352// "normal" call instructions to callees which do not return. 353def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", 354 "HasRetAddrStack", "true", 355 "Has return address stack">; 356 357// Some processors have no branch predictor, which changes the expected cost of 358// taking a branch which affects the choice of whether to use predicated 359// instructions. 360def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor", 361 "HasBranchPredictor", "false", 362 "Has no branch predictor">; 363 364/// DSP extension. 365def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", 366 "Supports DSP instructions in " 367 "ARM and/or Thumb2">; 368 369// Multiprocessing extension. 370def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 371 "Supports Multiprocessing extension">; 372 373// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 374def FeatureVirtualization : SubtargetFeature<"virtualization", 375 "HasVirtualization", "true", 376 "Supports Virtualization extension", 377 [FeatureHWDivThumb, FeatureHWDivARM]>; 378 379// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 380// See ARMInstrInfo.td for details. 381def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 382 "NaCl trap">; 383 384def FeatureStrictAlign : SubtargetFeature<"strict-align", 385 "StrictAlign", "true", 386 "Disallow all unaligned memory " 387 "access">; 388 389def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", 390 "Generate calls via indirect call " 391 "instructions">; 392 393def FeatureExecuteOnly : SubtargetFeature<"execute-only", 394 "GenExecuteOnly", "true", 395 "Enable the generation of " 396 "execute only code.">; 397 398def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", 399 "Reserve R9, making it unavailable" 400 " as GPR">; 401 402def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", 403 "Don't use movt/movw pairs for " 404 "32-bit imms">; 405 406def FeatureNoNegativeImmediates 407 : SubtargetFeature<"no-neg-immediates", 408 "NegativeImmediates", "false", 409 "Convert immediates and instructions " 410 "to their negated or complemented " 411 "equivalent when the immediate does " 412 "not fit in the encoding.">; 413 414// Use the MachineScheduler for instruction scheduling for the subtarget. 415def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true", 416 "Use the MachineScheduler">; 417 418def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler", 419 "DisablePostRAScheduler", "true", 420 "Don't schedule again after register allocation">; 421 422// Armv8.5-A extensions 423 424def FeatureSB : SubtargetFeature<"sb", "HasSB", "true", 425 "Enable v8.5a Speculation Barrier" >; 426 427// Armv8.6-A extensions 428def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", "true", 429 "Enable support for BFloat16 instructions", [FeatureNEON]>; 430 431def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8", 432 "true", "Enable Matrix Multiply Int8 Extension", [FeatureNEON]>; 433 434// Armv8.1-M extensions 435 436def FeatureLOB : SubtargetFeature<"lob", "HasLOB", "true", 437 "Enable Low Overhead Branch " 438 "extensions">; 439 440def FeatureFixCMSE_CVE_2021_35465 : SubtargetFeature<"fix-cmse-cve-2021-35465", 441 "FixCMSE_CVE_2021_35465", "true", 442 "Mitigate against the cve-2021-35465 " 443 "security vulnurability">; 444 445//===----------------------------------------------------------------------===// 446// ARM architecture class 447// 448 449// A-series ISA 450def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 451 "Is application profile ('A' series)">; 452 453// R-series ISA 454def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 455 "Is realtime profile ('R' series)">; 456 457// M-series ISA 458def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 459 "Is microcontroller profile ('M' series)">; 460 461 462def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 463 "Enable Thumb2 instructions">; 464 465def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 466 "Does not support ARM mode execution">; 467 468//===----------------------------------------------------------------------===// 469// ARM ISAa. 470// 471 472def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 473 "Support ARM v4T instructions">; 474 475def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 476 "Support ARM v5T instructions", 477 [HasV4TOps]>; 478 479def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 480 "Support ARM v5TE, v5TEj, and " 481 "v5TExp instructions", 482 [HasV5TOps]>; 483 484def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 485 "Support ARM v6 instructions", 486 [HasV5TEOps]>; 487 488def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 489 "Support ARM v6M instructions", 490 [HasV6Ops]>; 491 492def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", 493 "Support ARM v8M Baseline instructions", 494 [HasV6MOps]>; 495 496def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", 497 "Support ARM v6k instructions", 498 [HasV6Ops]>; 499 500def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 501 "Support ARM v6t2 instructions", 502 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; 503 504def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 505 "Support ARM v7 instructions", 506 [HasV6T2Ops, FeaturePerfMon, 507 FeatureV7Clrex]>; 508 509def HasV8MMainlineOps : 510 SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", 511 "Support ARM v8M Mainline instructions", 512 [HasV7Ops]>; 513 514def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 515 "Support ARM v8 instructions", 516 [HasV7Ops, FeatureAcquireRelease]>; 517 518def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 519 "Support ARM v8.1a instructions", 520 [HasV8Ops]>; 521 522def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 523 "Support ARM v8.2a instructions", 524 [HasV8_1aOps]>; 525 526def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 527 "Support ARM v8.3a instructions", 528 [HasV8_2aOps]>; 529 530def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 531 "Support ARM v8.4a instructions", 532 [HasV8_3aOps, FeatureDotProd]>; 533 534def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true", 535 "Support ARM v8.5a instructions", 536 [HasV8_4aOps, FeatureSB]>; 537 538def HasV8_6aOps : SubtargetFeature<"v8.6a", "HasV8_6aOps", "true", 539 "Support ARM v8.6a instructions", 540 [HasV8_5aOps, FeatureBF16, 541 FeatureMatMulInt8]>; 542 543def HasV8_7aOps : SubtargetFeature<"v8.7a", "HasV8_7aOps", "true", 544 "Support ARM v8.7a instructions", 545 [HasV8_6aOps]>; 546 547def HasV9_0aOps : SubtargetFeature<"v9a", "HasV9_0aOps", "true", 548 "Support ARM v9a instructions", 549 [HasV8_5aOps]>; 550 551def HasV9_1aOps : SubtargetFeature<"v9.1a", "HasV9_1aOps", "true", 552 "Support ARM v9.1a instructions", 553 [HasV8_6aOps, HasV9_0aOps]>; 554 555def HasV9_2aOps : SubtargetFeature<"v9.2a", "HasV9_2aOps", "true", 556 "Support ARM v9.2a instructions", 557 [HasV8_7aOps, HasV9_1aOps]>; 558 559def HasV8_1MMainlineOps : SubtargetFeature< 560 "v8.1m.main", "HasV8_1MMainlineOps", "true", 561 "Support ARM v8-1M Mainline instructions", 562 [HasV8MMainlineOps]>; 563def HasMVEIntegerOps : SubtargetFeature< 564 "mve", "HasMVEIntegerOps", "true", 565 "Support M-Class Vector Extension with integer ops", 566 [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>; 567def HasMVEFloatOps : SubtargetFeature< 568 "mve.fp", "HasMVEFloatOps", "true", 569 "Support M-Class Vector Extension with integer and floating ops", 570 [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>; 571 572def HasCDEOps : SubtargetFeature<"cde", "HasCDEOps", "true", 573 "Support CDE instructions", 574 [HasV8MMainlineOps]>; 575 576foreach i = {0-7} in 577 def FeatureCoprocCDE#i : SubtargetFeature<"cdecp"#i, 578 "CoprocCDE["#i#"]", "true", 579 "Coprocessor "#i#" ISA is CDEv1", 580 [HasCDEOps]>; 581 582//===----------------------------------------------------------------------===// 583// Control codegen mitigation against Straight Line Speculation vulnerability. 584//===----------------------------------------------------------------------===// 585 586def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr", 587 "HardenSlsRetBr", "true", 588 "Harden against straight line speculation across RETurn and BranchRegister " 589 "instructions">; 590def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr", 591 "HardenSlsBlr", "true", 592 "Harden against straight line speculation across indirect calls">; 593def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat", 594 "HardenSlsNoComdat", "true", 595 "Generate thunk code for SLS mitigation in the normal text section">; 596 597//===----------------------------------------------------------------------===// 598// ARM Processor subtarget features. 599// 600 601def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 602 "Cortex-A5 ARM processors", []>; 603def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 604 "Cortex-A7 ARM processors", []>; 605def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 606 "Cortex-A8 ARM processors", []>; 607def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 608 "Cortex-A9 ARM processors", []>; 609def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 610 "Cortex-A12 ARM processors", []>; 611def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 612 "Cortex-A15 ARM processors", []>; 613def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", 614 "Cortex-A17 ARM processors", []>; 615def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", 616 "Cortex-A32 ARM processors", []>; 617def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 618 "Cortex-A35 ARM processors", []>; 619def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 620 "Cortex-A53 ARM processors", []>; 621def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 622 "Cortex-A55 ARM processors", []>; 623def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 624 "Cortex-A57 ARM processors", []>; 625def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 626 "Cortex-A72 ARM processors", []>; 627def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 628 "Cortex-A73 ARM processors", []>; 629def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 630 "Cortex-A75 ARM processors", []>; 631def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 632 "Cortex-A76 ARM processors", []>; 633def ProcA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", 634 "Cortex-A77 ARM processors", []>; 635def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily", "CortexA78", 636 "Cortex-A78 ARM processors", []>; 637def ProcA78C : SubtargetFeature<"a78c", "ARMProcFamily", "CortexA78C", 638 "Cortex-A78C ARM processors", []>; 639def ProcA710 : SubtargetFeature<"cortex-a710", "ARMProcFamily", 640 "CortexA710", "Cortex-A710 ARM processors", []>; 641def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", 642 "Cortex-X1 ARM processors", []>; 643 644def ProcV1 : SubtargetFeature<"neoverse-v1", "ARMProcFamily", 645 "NeoverseV1", "Neoverse-V1 ARM processors", []>; 646 647def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 648 "Qualcomm Krait processors", []>; 649def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 650 "Qualcomm Kryo processors", []>; 651def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 652 "Swift ARM processors", []>; 653 654def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos", 655 "Samsung Exynos processors", 656 [FeatureZCZeroing, 657 FeatureUseWideStrideVFP, 658 FeatureSplatVFPToNeon, 659 FeatureSlowVGETLNi32, 660 FeatureSlowVDUP32, 661 FeatureSlowFPBrcc, 662 FeatureProfUnpredicate, 663 FeatureHWDivThumb, 664 FeatureHWDivARM, 665 FeatureHasSlowFPVMLx, 666 FeatureHasSlowFPVFMx, 667 FeatureHasRetAddrStack, 668 FeatureFuseLiterals, 669 FeatureFuseAES, 670 FeatureExpandMLx, 671 FeatureCrypto, 672 FeatureCRC]>; 673 674def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", 675 "Cortex-R4 ARM processors", []>; 676def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 677 "Cortex-R5 ARM processors", []>; 678def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", 679 "Cortex-R7 ARM processors", []>; 680def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", 681 "Cortex-R52 ARM processors", []>; 682 683def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", 684 "Cortex-M3 ARM processors", []>; 685def ProcM7 : SubtargetFeature<"m7", "ARMProcFamily", "CortexM7", 686 "Cortex-M7 ARM processors", []>; 687 688//===----------------------------------------------------------------------===// 689// ARM Helper classes. 690// 691 692class Architecture<string fname, string aname, list<SubtargetFeature> features> 693 : SubtargetFeature<fname, "ARMArch", aname, 694 !strconcat(aname, " architecture"), features>; 695 696class ProcNoItin<string Name, list<SubtargetFeature> Features> 697 : Processor<Name, NoItineraries, Features>; 698 699 700//===----------------------------------------------------------------------===// 701// ARM architectures 702// 703 704def ARMv2 : Architecture<"armv2", "ARMv2", []>; 705 706def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; 707 708def ARMv3 : Architecture<"armv3", "ARMv3", []>; 709 710def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; 711 712def ARMv4 : Architecture<"armv4", "ARMv4", []>; 713 714def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; 715 716def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; 717 718def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; 719 720def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; 721 722def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops, 723 FeatureDSP]>; 724 725def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, 726 FeatureDSP]>; 727 728def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; 729 730def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, 731 FeatureTrustZone]>; 732 733def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, 734 FeatureNoARM, 735 ModeThumb, 736 FeatureDB, 737 FeatureMClass, 738 FeatureStrictAlign]>; 739 740def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, 741 FeatureNoARM, 742 ModeThumb, 743 FeatureDB, 744 FeatureMClass, 745 FeatureStrictAlign]>; 746 747def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, 748 FeatureNEON, 749 FeatureDB, 750 FeatureDSP, 751 FeatureAClass]>; 752 753def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops, 754 FeatureNEON, 755 FeatureDB, 756 FeatureDSP, 757 FeatureTrustZone, 758 FeatureMP, 759 FeatureVirtualization, 760 FeatureAClass]>; 761 762def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, 763 FeatureDB, 764 FeatureDSP, 765 FeatureHWDivThumb, 766 FeatureRClass]>; 767 768def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, 769 FeatureThumb2, 770 FeatureNoARM, 771 ModeThumb, 772 FeatureDB, 773 FeatureHWDivThumb, 774 FeatureMClass]>; 775 776def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, 777 FeatureThumb2, 778 FeatureNoARM, 779 ModeThumb, 780 FeatureDB, 781 FeatureHWDivThumb, 782 FeatureMClass, 783 FeatureDSP]>; 784 785def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, 786 FeatureAClass, 787 FeatureDB, 788 FeatureFPARMv8, 789 FeatureNEON, 790 FeatureDSP, 791 FeatureTrustZone, 792 FeatureMP, 793 FeatureVirtualization, 794 FeatureCrypto, 795 FeatureCRC]>; 796 797def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, 798 FeatureAClass, 799 FeatureDB, 800 FeatureFPARMv8, 801 FeatureNEON, 802 FeatureDSP, 803 FeatureTrustZone, 804 FeatureMP, 805 FeatureVirtualization, 806 FeatureCrypto, 807 FeatureCRC]>; 808 809def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, 810 FeatureAClass, 811 FeatureDB, 812 FeatureFPARMv8, 813 FeatureNEON, 814 FeatureDSP, 815 FeatureTrustZone, 816 FeatureMP, 817 FeatureVirtualization, 818 FeatureCrypto, 819 FeatureCRC, 820 FeatureRAS]>; 821 822def ARMv83a : Architecture<"armv8.3-a", "ARMv83a", [HasV8_3aOps, 823 FeatureAClass, 824 FeatureDB, 825 FeatureFPARMv8, 826 FeatureNEON, 827 FeatureDSP, 828 FeatureTrustZone, 829 FeatureMP, 830 FeatureVirtualization, 831 FeatureCrypto, 832 FeatureCRC, 833 FeatureRAS]>; 834 835def ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps, 836 FeatureAClass, 837 FeatureDB, 838 FeatureFPARMv8, 839 FeatureNEON, 840 FeatureDSP, 841 FeatureTrustZone, 842 FeatureMP, 843 FeatureVirtualization, 844 FeatureCrypto, 845 FeatureCRC, 846 FeatureRAS, 847 FeatureDotProd]>; 848 849def ARMv85a : Architecture<"armv8.5-a", "ARMv85a", [HasV8_5aOps, 850 FeatureAClass, 851 FeatureDB, 852 FeatureFPARMv8, 853 FeatureNEON, 854 FeatureDSP, 855 FeatureTrustZone, 856 FeatureMP, 857 FeatureVirtualization, 858 FeatureCrypto, 859 FeatureCRC, 860 FeatureRAS, 861 FeatureDotProd]>; 862def ARMv86a : Architecture<"armv8.6-a", "ARMv86a", [HasV8_6aOps, 863 FeatureAClass, 864 FeatureDB, 865 FeatureFPARMv8, 866 FeatureNEON, 867 FeatureDSP, 868 FeatureTrustZone, 869 FeatureMP, 870 FeatureVirtualization, 871 FeatureCrypto, 872 FeatureCRC, 873 FeatureRAS, 874 FeatureDotProd]>; 875def ARMv87a : Architecture<"armv8.7-a", "ARMv87a", [HasV8_7aOps, 876 FeatureAClass, 877 FeatureDB, 878 FeatureFPARMv8, 879 FeatureNEON, 880 FeatureDSP, 881 FeatureTrustZone, 882 FeatureMP, 883 FeatureVirtualization, 884 FeatureCrypto, 885 FeatureCRC, 886 FeatureRAS, 887 FeatureDotProd]>; 888 889def ARMv9a : Architecture<"armv9-a", "ARMv9a", [HasV9_0aOps, 890 FeatureAClass, 891 FeatureDB, 892 FeatureFPARMv8, 893 FeatureNEON, 894 FeatureDSP, 895 FeatureTrustZone, 896 FeatureMP, 897 FeatureVirtualization, 898 FeatureCRC, 899 FeatureRAS, 900 FeatureDotProd]>; 901def ARMv91a : Architecture<"armv9.1-a", "ARMv91a", [HasV9_1aOps, 902 FeatureAClass, 903 FeatureDB, 904 FeatureFPARMv8, 905 FeatureNEON, 906 FeatureDSP, 907 FeatureTrustZone, 908 FeatureMP, 909 FeatureVirtualization, 910 FeatureCRC, 911 FeatureRAS, 912 FeatureDotProd]>; 913def ARMv92a : Architecture<"armv9.2-a", "ARMv92a", [HasV9_2aOps, 914 FeatureAClass, 915 FeatureDB, 916 FeatureFPARMv8, 917 FeatureNEON, 918 FeatureDSP, 919 FeatureTrustZone, 920 FeatureMP, 921 FeatureVirtualization, 922 FeatureCRC, 923 FeatureRAS, 924 FeatureDotProd]>; 925 926def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, 927 FeatureRClass, 928 FeatureDB, 929 FeatureDFB, 930 FeatureDSP, 931 FeatureCRC, 932 FeatureMP, 933 FeatureVirtualization, 934 FeatureFPARMv8, 935 FeatureNEON]>; 936 937def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", 938 [HasV8MBaselineOps, 939 FeatureNoARM, 940 ModeThumb, 941 FeatureDB, 942 FeatureHWDivThumb, 943 FeatureV7Clrex, 944 Feature8MSecExt, 945 FeatureAcquireRelease, 946 FeatureMClass, 947 FeatureStrictAlign]>; 948 949def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", 950 [HasV8MMainlineOps, 951 FeatureNoARM, 952 ModeThumb, 953 FeatureDB, 954 FeatureHWDivThumb, 955 Feature8MSecExt, 956 FeatureAcquireRelease, 957 FeatureMClass]>; 958 959def ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline", 960 [HasV8_1MMainlineOps, 961 FeatureNoARM, 962 ModeThumb, 963 FeatureDB, 964 FeatureHWDivThumb, 965 Feature8MSecExt, 966 FeatureAcquireRelease, 967 FeatureMClass, 968 FeatureRAS, 969 FeatureLOB]>; 970 971// Aliases 972def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; 973def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; 974def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; 975def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; 976def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; 977def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; 978 979//===----------------------------------------------------------------------===// 980// Register File Description 981//===----------------------------------------------------------------------===// 982 983include "ARMRegisterInfo.td" 984include "ARMRegisterBanks.td" 985include "ARMCallingConv.td" 986 987//===----------------------------------------------------------------------===// 988// ARM schedules. 989//===----------------------------------------------------------------------===// 990// 991include "ARMPredicates.td" 992include "ARMSchedule.td" 993 994//===----------------------------------------------------------------------===// 995// Instruction Descriptions 996//===----------------------------------------------------------------------===// 997 998include "ARMInstrInfo.td" 999def ARMInstrInfo : InstrInfo; 1000 1001//===----------------------------------------------------------------------===// 1002// ARM schedules 1003// 1004include "ARMScheduleV6.td" 1005include "ARMScheduleA8.td" 1006include "ARMScheduleA9.td" 1007include "ARMScheduleSwift.td" 1008include "ARMScheduleR52.td" 1009include "ARMScheduleA57.td" 1010include "ARMScheduleM4.td" 1011include "ARMScheduleM7.td" 1012 1013//===----------------------------------------------------------------------===// 1014// ARM processors 1015// 1016// Dummy CPU, used to target architectures 1017def : ProcessorModel<"generic", CortexA8Model, []>; 1018 1019// FIXME: Several processors below are not using their own scheduler 1020// model, but one of similar/previous processor. These should be fixed. 1021 1022def : ProcNoItin<"arm8", [ARMv4]>; 1023def : ProcNoItin<"arm810", [ARMv4]>; 1024def : ProcNoItin<"strongarm", [ARMv4]>; 1025def : ProcNoItin<"strongarm110", [ARMv4]>; 1026def : ProcNoItin<"strongarm1100", [ARMv4]>; 1027def : ProcNoItin<"strongarm1110", [ARMv4]>; 1028 1029def : ProcNoItin<"arm7tdmi", [ARMv4t]>; 1030def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; 1031def : ProcNoItin<"arm710t", [ARMv4t]>; 1032def : ProcNoItin<"arm720t", [ARMv4t]>; 1033def : ProcNoItin<"arm9", [ARMv4t]>; 1034def : ProcNoItin<"arm9tdmi", [ARMv4t]>; 1035def : ProcNoItin<"arm920", [ARMv4t]>; 1036def : ProcNoItin<"arm920t", [ARMv4t]>; 1037def : ProcNoItin<"arm922t", [ARMv4t]>; 1038def : ProcNoItin<"arm940t", [ARMv4t]>; 1039def : ProcNoItin<"ep9312", [ARMv4t]>; 1040 1041def : ProcNoItin<"arm10tdmi", [ARMv5t]>; 1042def : ProcNoItin<"arm1020t", [ARMv5t]>; 1043 1044def : ProcNoItin<"arm9e", [ARMv5te]>; 1045def : ProcNoItin<"arm926ej-s", [ARMv5te]>; 1046def : ProcNoItin<"arm946e-s", [ARMv5te]>; 1047def : ProcNoItin<"arm966e-s", [ARMv5te]>; 1048def : ProcNoItin<"arm968e-s", [ARMv5te]>; 1049def : ProcNoItin<"arm10e", [ARMv5te]>; 1050def : ProcNoItin<"arm1020e", [ARMv5te]>; 1051def : ProcNoItin<"arm1022e", [ARMv5te]>; 1052def : ProcNoItin<"xscale", [ARMv5te]>; 1053def : ProcNoItin<"iwmmxt", [ARMv5te]>; 1054 1055def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; 1056def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, 1057 FeatureVFP2, 1058 FeatureHasSlowFPVMLx]>; 1059 1060def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m, 1061 FeatureHasNoBranchPredictor]>; 1062def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m, 1063 FeatureHasNoBranchPredictor]>; 1064def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m, 1065 FeatureHasNoBranchPredictor]>; 1066def : Processor<"sc000", ARMV6Itineraries, [ARMv6m, 1067 FeatureHasNoBranchPredictor]>; 1068 1069def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; 1070def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, 1071 FeatureVFP2, 1072 FeatureHasSlowFPVMLx]>; 1073 1074def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; 1075def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, 1076 FeatureVFP2, 1077 FeatureHasSlowFPVMLx]>; 1078 1079def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; 1080def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, 1081 FeatureVFP2, 1082 FeatureHasSlowFPVMLx]>; 1083 1084def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, 1085 FeatureHasRetAddrStack, 1086 FeatureTrustZone, 1087 FeatureSlowFPBrcc, 1088 FeatureHasSlowFPVMLx, 1089 FeatureHasSlowFPVFMx, 1090 FeatureVMLxForwarding, 1091 FeatureMP, 1092 FeatureVFP4]>; 1093 1094def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, 1095 FeatureHasRetAddrStack, 1096 FeatureTrustZone, 1097 FeatureSlowFPBrcc, 1098 FeatureHasVMLxHazards, 1099 FeatureHasSlowFPVMLx, 1100 FeatureHasSlowFPVFMx, 1101 FeatureVMLxForwarding, 1102 FeatureMP, 1103 FeatureVFP4, 1104 FeatureVirtualization]>; 1105 1106def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, 1107 FeatureHasRetAddrStack, 1108 FeatureNonpipelinedVFP, 1109 FeatureTrustZone, 1110 FeatureSlowFPBrcc, 1111 FeatureHasVMLxHazards, 1112 FeatureHasSlowFPVMLx, 1113 FeatureHasSlowFPVFMx, 1114 FeatureVMLxForwarding]>; 1115 1116def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, 1117 FeatureHasRetAddrStack, 1118 FeatureTrustZone, 1119 FeatureHasVMLxHazards, 1120 FeatureVMLxForwarding, 1121 FeatureFP16, 1122 FeatureAvoidPartialCPSR, 1123 FeatureExpandMLx, 1124 FeaturePreferVMOVSR, 1125 FeatureMuxedUnits, 1126 FeatureNEONForFPMovs, 1127 FeatureCheckVLDnAlign, 1128 FeatureMP]>; 1129 1130def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, 1131 FeatureHasRetAddrStack, 1132 FeatureTrustZone, 1133 FeatureVMLxForwarding, 1134 FeatureVFP4, 1135 FeatureAvoidPartialCPSR, 1136 FeatureVirtualization, 1137 FeatureMP]>; 1138 1139def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, 1140 FeatureDontWidenVMOVS, 1141 FeatureSplatVFPToNeon, 1142 FeatureHasRetAddrStack, 1143 FeatureMuxedUnits, 1144 FeatureTrustZone, 1145 FeatureVFP4, 1146 FeatureMP, 1147 FeatureCheckVLDnAlign, 1148 FeatureAvoidPartialCPSR, 1149 FeatureVirtualization]>; 1150 1151def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, 1152 FeatureHasRetAddrStack, 1153 FeatureTrustZone, 1154 FeatureMP, 1155 FeatureVMLxForwarding, 1156 FeatureVFP4, 1157 FeatureAvoidPartialCPSR, 1158 FeatureVirtualization]>; 1159 1160// FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv 1161def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, 1162 FeatureHasRetAddrStack, 1163 FeatureMuxedUnits, 1164 FeatureCheckVLDnAlign, 1165 FeatureVMLxForwarding, 1166 FeatureFP16, 1167 FeatureAvoidPartialCPSR, 1168 FeatureVFP4, 1169 FeatureHWDivThumb, 1170 FeatureHWDivARM]>; 1171 1172def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, 1173 FeatureHasRetAddrStack, 1174 FeatureNEONForFP, 1175 FeatureVFP4, 1176 FeatureUseWideStrideVFP, 1177 FeatureMP, 1178 FeatureHWDivThumb, 1179 FeatureHWDivARM, 1180 FeatureAvoidPartialCPSR, 1181 FeatureAvoidMOVsShOp, 1182 FeatureHasSlowFPVMLx, 1183 FeatureHasSlowFPVFMx, 1184 FeatureHasVMLxHazards, 1185 FeatureProfUnpredicate, 1186 FeaturePrefISHSTBarrier, 1187 FeatureSlowOddRegister, 1188 FeatureSlowLoadDSubreg, 1189 FeatureSlowVGETLNi32, 1190 FeatureSlowVDUP32, 1191 FeatureUseMISched, 1192 FeatureNoPostRASched]>; 1193 1194def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, 1195 FeatureHasRetAddrStack, 1196 FeatureAvoidPartialCPSR]>; 1197 1198def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, 1199 FeatureHasRetAddrStack, 1200 FeatureSlowFPBrcc, 1201 FeatureHasSlowFPVMLx, 1202 FeatureHasSlowFPVFMx, 1203 FeatureVFP3_D16, 1204 FeatureAvoidPartialCPSR]>; 1205 1206def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, 1207 FeatureHasRetAddrStack, 1208 FeatureVFP3_D16, 1209 FeatureSlowFPBrcc, 1210 FeatureHWDivARM, 1211 FeatureHasSlowFPVMLx, 1212 FeatureHasSlowFPVFMx, 1213 FeatureAvoidPartialCPSR]>; 1214 1215def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, 1216 FeatureHasRetAddrStack, 1217 FeatureVFP3_D16, 1218 FeatureFP16, 1219 FeatureMP, 1220 FeatureSlowFPBrcc, 1221 FeatureHWDivARM, 1222 FeatureHasSlowFPVMLx, 1223 FeatureHasSlowFPVFMx, 1224 FeatureAvoidPartialCPSR]>; 1225 1226def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, 1227 FeatureHasRetAddrStack, 1228 FeatureVFP3_D16, 1229 FeatureFP16, 1230 FeatureMP, 1231 FeatureSlowFPBrcc, 1232 FeatureHWDivARM, 1233 FeatureHasSlowFPVMLx, 1234 FeatureHasSlowFPVFMx, 1235 FeatureAvoidPartialCPSR]>; 1236 1237def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m, 1238 ProcM3, 1239 FeaturePrefLoopAlign32, 1240 FeatureUseMISched, 1241 FeatureHasNoBranchPredictor]>; 1242 1243def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m, 1244 ProcM3, 1245 FeatureUseMISched, 1246 FeatureHasNoBranchPredictor]>; 1247 1248def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em, 1249 FeatureVFP4_D16_SP, 1250 FeaturePrefLoopAlign32, 1251 FeatureHasSlowFPVMLx, 1252 FeatureHasSlowFPVFMx, 1253 FeatureUseMISched, 1254 FeatureHasNoBranchPredictor]>; 1255 1256def : ProcessorModel<"cortex-m7", CortexM7Model, [ARMv7em, 1257 ProcM7, 1258 FeatureFPARMv8_D16, 1259 FeatureUseMISched]>; 1260 1261def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, 1262 FeatureNoMovt, 1263 FeatureHasNoBranchPredictor]>; 1264 1265def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline, 1266 FeatureDSP, 1267 FeatureFPARMv8_D16_SP, 1268 FeaturePrefLoopAlign32, 1269 FeatureHasSlowFPVMLx, 1270 FeatureHasSlowFPVFMx, 1271 FeatureUseMISched, 1272 FeatureHasNoBranchPredictor, 1273 FeatureFixCMSE_CVE_2021_35465]>; 1274 1275def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline, 1276 FeatureDSP, 1277 FeatureFPARMv8_D16_SP, 1278 FeaturePrefLoopAlign32, 1279 FeatureHasSlowFPVMLx, 1280 FeatureHasSlowFPVFMx, 1281 FeatureUseMISched, 1282 FeatureHasNoBranchPredictor, 1283 FeatureFixCMSE_CVE_2021_35465]>; 1284 1285def : ProcessorModel<"cortex-m55", CortexM4Model, [ARMv81mMainline, 1286 FeatureDSP, 1287 FeatureFPARMv8_D16, 1288 FeatureUseMISched, 1289 FeatureHasNoBranchPredictor, 1290 FeaturePrefLoopAlign32, 1291 FeatureHasSlowFPVMLx, 1292 HasMVEFloatOps, 1293 FeatureFixCMSE_CVE_2021_35465]>; 1294 1295def : ProcNoItin<"cortex-a32", [ARMv8a, 1296 FeatureHWDivThumb, 1297 FeatureHWDivARM, 1298 FeatureCrypto, 1299 FeatureCRC]>; 1300 1301def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, 1302 FeatureHWDivThumb, 1303 FeatureHWDivARM, 1304 FeatureCrypto, 1305 FeatureCRC]>; 1306 1307def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, 1308 FeatureHWDivThumb, 1309 FeatureHWDivARM, 1310 FeatureCrypto, 1311 FeatureCRC, 1312 FeatureFPAO]>; 1313 1314def : ProcNoItin<"cortex-a55", [ARMv82a, ProcA55, 1315 FeatureHWDivThumb, 1316 FeatureHWDivARM, 1317 FeatureDotProd]>; 1318 1319def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57, 1320 FeatureHWDivThumb, 1321 FeatureHWDivARM, 1322 FeatureCrypto, 1323 FeatureCRC, 1324 FeatureFPAO, 1325 FeatureAvoidPartialCPSR, 1326 FeatureCheapPredicableCPSR]>; 1327 1328def : ProcessorModel<"cortex-a72", CortexA57Model, [ARMv8a, ProcA72, 1329 FeatureHWDivThumb, 1330 FeatureHWDivARM, 1331 FeatureCrypto, 1332 FeatureCRC]>; 1333 1334def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, 1335 FeatureHWDivThumb, 1336 FeatureHWDivARM, 1337 FeatureCrypto, 1338 FeatureCRC]>; 1339 1340def : ProcNoItin<"cortex-a75", [ARMv82a, ProcA75, 1341 FeatureHWDivThumb, 1342 FeatureHWDivARM, 1343 FeatureDotProd]>; 1344 1345def : ProcNoItin<"cortex-a76", [ARMv82a, ProcA76, 1346 FeatureHWDivThumb, 1347 FeatureHWDivARM, 1348 FeatureCrypto, 1349 FeatureCRC, 1350 FeatureFullFP16, 1351 FeatureDotProd]>; 1352 1353def : ProcNoItin<"cortex-a76ae", [ARMv82a, ProcA76, 1354 FeatureHWDivThumb, 1355 FeatureHWDivARM, 1356 FeatureCrypto, 1357 FeatureCRC, 1358 FeatureFullFP16, 1359 FeatureDotProd]>; 1360 1361def : ProcNoItin<"cortex-a77", [ARMv82a, ProcA77, 1362 FeatureHWDivThumb, 1363 FeatureHWDivARM, 1364 FeatureCrypto, 1365 FeatureCRC, 1366 FeatureFullFP16, 1367 FeatureDotProd]>; 1368 1369def : ProcNoItin<"cortex-a78", [ARMv82a, ProcA78, 1370 FeatureHWDivThumb, 1371 FeatureHWDivARM, 1372 FeatureCrypto, 1373 FeatureCRC, 1374 FeatureFullFP16, 1375 FeatureDotProd]>; 1376 1377def : ProcNoItin<"cortex-a78c", [ARMv82a, ProcA78C, 1378 FeatureHWDivThumb, 1379 FeatureHWDivARM, 1380 FeatureCrypto, 1381 FeatureCRC, 1382 FeatureDotProd, 1383 FeatureFullFP16]>; 1384 1385def : ProcNoItin<"cortex-a710", [ARMv9a, ProcA710, 1386 FeatureHWDivThumb, 1387 FeatureHWDivARM, 1388 FeatureFP16FML, 1389 FeatureBF16, 1390 FeatureMatMulInt8, 1391 FeatureSB]>; 1392 1393def : ProcNoItin<"cortex-x1", [ARMv82a, ProcX1, 1394 FeatureHWDivThumb, 1395 FeatureHWDivARM, 1396 FeatureCrypto, 1397 FeatureCRC, 1398 FeatureFullFP16, 1399 FeatureDotProd]>; 1400 1401def : ProcNoItin<"neoverse-v1", [ARMv84a, 1402 FeatureHWDivThumb, 1403 FeatureHWDivARM, 1404 FeatureCrypto, 1405 FeatureCRC, 1406 FeatureFullFP16, 1407 FeatureBF16, 1408 FeatureMatMulInt8]>; 1409 1410def : ProcNoItin<"neoverse-n1", [ARMv82a, 1411 FeatureHWDivThumb, 1412 FeatureHWDivARM, 1413 FeatureCrypto, 1414 FeatureCRC, 1415 FeatureDotProd]>; 1416 1417def : ProcNoItin<"neoverse-n2", [ARMv85a, 1418 FeatureBF16, 1419 FeatureMatMulInt8, 1420 FeaturePerfMon]>; 1421 1422def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, 1423 FeatureHasRetAddrStack, 1424 FeatureNEONForFP, 1425 FeatureVFP4, 1426 FeatureMP, 1427 FeatureHWDivThumb, 1428 FeatureHWDivARM, 1429 FeatureAvoidPartialCPSR, 1430 FeatureAvoidMOVsShOp, 1431 FeatureHasSlowFPVMLx, 1432 FeatureHasSlowFPVFMx, 1433 FeatureCrypto, 1434 FeatureUseMISched, 1435 FeatureZCZeroing, 1436 FeatureNoPostRASched]>; 1437 1438def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynos]>; 1439def : ProcNoItin<"exynos-m4", [ARMv82a, ProcExynos, 1440 FeatureFullFP16, 1441 FeatureDotProd]>; 1442def : ProcNoItin<"exynos-m5", [ARMv82a, ProcExynos, 1443 FeatureFullFP16, 1444 FeatureDotProd]>; 1445 1446def : ProcNoItin<"kryo", [ARMv8a, ProcKryo, 1447 FeatureHWDivThumb, 1448 FeatureHWDivARM, 1449 FeatureCrypto, 1450 FeatureCRC]>; 1451 1452def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, 1453 FeatureUseMISched, 1454 FeatureFPAO]>; 1455 1456//===----------------------------------------------------------------------===// 1457// Declare the target which we are implementing 1458//===----------------------------------------------------------------------===// 1459 1460def ARMAsmWriter : AsmWriter { 1461 string AsmWriterClassName = "InstPrinter"; 1462 int PassSubtarget = 1; 1463 int Variant = 0; 1464 bit isMCAsmWriter = 1; 1465} 1466 1467def ARMAsmParser : AsmParser { 1468 bit ReportMultipleNearMisses = 1; 1469} 1470 1471def ARMAsmParserVariant : AsmParserVariant { 1472 int Variant = 0; 1473 string Name = "ARM"; 1474 string BreakCharacters = "."; 1475} 1476 1477def ARM : Target { 1478 // Pull in Instruction Info. 1479 let InstructionSet = ARMInstrInfo; 1480 let AssemblyWriters = [ARMAsmWriter]; 1481 let AssemblyParsers = [ARMAsmParser]; 1482 let AssemblyParserVariants = [ARMAsmParserVariant]; 1483 let AllowRegisterRenaming = 1; 1484} 1485