1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// ARM Subtarget state. 20// 21 22def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", 23 "true", "Thumb mode">; 24 25def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat", 26 "true", "Use software floating " 27 "point features.">; 28 29 30//===----------------------------------------------------------------------===// 31// ARM Subtarget features. 32// 33 34// Floating Point, HW Division and Neon Support 35 36// FP loads/stores/moves, shared between VFP and MVE (even in the integer-only 37// version). 38def FeatureFPRegs : SubtargetFeature<"fpregs", "HasFPRegs", "true", 39 "Enable FP registers">; 40 41// 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16 42// extension) and MVE (even in the integer-only version). 43def FeatureFPRegs16 : SubtargetFeature<"fpregs16", "HasFPRegs16", "true", 44 "Enable 16-bit FP registers", 45 [FeatureFPRegs]>; 46 47def FeatureFPRegs64 : SubtargetFeature<"fpregs64", "HasFPRegs64", "true", 48 "Enable 64-bit FP registers", 49 [FeatureFPRegs]>; 50 51def FeatureFP64 : SubtargetFeature<"fp64", "HasFP64", "true", 52 "Floating point unit supports " 53 "double precision", 54 [FeatureFPRegs64]>; 55 56def FeatureD32 : SubtargetFeature<"d32", "HasD32", "true", 57 "Extend FP to 32 double registers">; 58 59multiclass VFPver<string name, string query, string description, 60 list<SubtargetFeature> prev, 61 list<SubtargetFeature> otherimplies, 62 list<SubtargetFeature> vfp2prev = []> { 63 def _D16_SP: SubtargetFeature< 64 name#"d16sp", query#"D16SP", "true", 65 description#" with only 16 d-registers and no double precision", 66 !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) # 67 !foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) # 68 otherimplies>; 69 def _SP: SubtargetFeature< 70 name#"sp", query#"SP", "true", 71 description#" with no double precision", 72 !foreach(v, prev, !cast<SubtargetFeature>(v # "_SP")) # 73 otherimplies # [FeatureD32, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; 74 def _D16: SubtargetFeature< 75 name#"d16", query#"D16", "true", 76 description#" with only 16 d-registers", 77 !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) # 78 vfp2prev # 79 otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; 80 def "": SubtargetFeature< 81 name, query, "true", description, 82 prev # otherimplies # [ 83 !cast<SubtargetFeature>(NAME # "_D16"), 84 !cast<SubtargetFeature>(NAME # "_SP")]>; 85} 86 87def FeatureVFP2_SP : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true", 88 "Enable VFP2 instructions with " 89 "no double precision", 90 [FeatureFPRegs]>; 91 92def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 93 "Enable VFP2 instructions", 94 [FeatureFP64, FeatureVFP2_SP]>; 95 96defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions", 97 [], [], [FeatureVFP2]>; 98 99def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 100 "Enable NEON instructions", 101 [FeatureVFP3]>; 102 103def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 104 "Enable half-precision " 105 "floating point">; 106 107defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions", 108 [FeatureVFP3], [FeatureFP16]>; 109 110defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP", 111 [FeatureVFP4], []>; 112 113def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 114 "Enable full half-precision " 115 "floating point", 116 [FeatureFPARMv8_D16_SP, FeatureFPRegs16]>; 117 118def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 119 "Enable full half-precision " 120 "floating point fml instructions", 121 [FeatureFullFP16]>; 122 123def FeatureHWDivThumb : SubtargetFeature<"hwdiv", 124 "HasHardwareDivideInThumb", "true", 125 "Enable divide instructions in Thumb">; 126 127def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 128 "HasHardwareDivideInARM", "true", 129 "Enable divide instructions in ARM mode">; 130 131// Atomic Support 132def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 133 "Has data barrier (dmb/dsb) instructions">; 134 135def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", 136 "Has v7 clrex instruction">; 137 138def FeatureDFB : SubtargetFeature<"dfb", "HasFullDataBarrier", "true", 139 "Has full data barrier (dfb) instruction">; 140 141def FeatureAcquireRelease : SubtargetFeature<"acquire-release", 142 "HasAcquireRelease", "true", 143 "Has v8 acquire/release (lda/ldaex " 144 " etc) instructions">; 145 146 147def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 148 "FP compare + branch is slow">; 149 150def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 151 "Enable support for Performance " 152 "Monitor extensions">; 153 154 155// TrustZone Security Extensions 156def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 157 "Enable support for TrustZone " 158 "security extensions">; 159 160def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", 161 "Enable support for ARMv8-M " 162 "Security Extensions">; 163 164def FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true", 165 "Enable SHA1 and SHA256 support", [FeatureNEON]>; 166 167def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 168 "Enable AES support", [FeatureNEON]>; 169 170def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 171 "Enable support for " 172 "Cryptography extensions", 173 [FeatureNEON, FeatureSHA2, FeatureAES]>; 174 175def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 176 "Enable support for CRC instructions">; 177 178def FeatureDotProd : SubtargetFeature<"dotprod", "HasDotProd", "true", 179 "Enable support for dot product instructions", 180 [FeatureNEON]>; 181 182// Not to be confused with FeatureHasRetAddrStack (return address stack) 183def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 184 "Enable Reliability, Availability " 185 "and Serviceability extensions">; 186 187// Fast computation of non-negative address offsets 188def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true", 189 "Enable fast computation of " 190 "positive address offsets">; 191 192// Fast execution of AES crypto operations 193def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true", 194 "CPU fuses AES crypto operations">; 195 196// Fast execution of bottom and top halves of literal generation 197def FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true", 198 "CPU fuses literal generation operations">; 199 200// The way of reading thread pointer 201def FeatureReadTp : SubtargetFeature<"read-tp-hard", "ReadTPHard", "true", 202 "Reading thread pointer from register">; 203 204// Cyclone can zero VFP registers in 0 cycles. 205def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 206 "Has zero-cycle zeroing instructions">; 207 208// Whether it is profitable to unpredicate certain instructions during if-conversion 209def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr", 210 "IsProfitableToUnpredicate", "true", 211 "Is profitable to unpredicate">; 212 213// Some targets (e.g. Swift) have microcoded VGETLNi32. 214def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32", 215 "HasSlowVGETLNi32", "true", 216 "Has slow VGETLNi32 - prefer VMOV">; 217 218// Some targets (e.g. Swift) have microcoded VDUP32. 219def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", 220 "true", 221 "Has slow VDUP32 - prefer VMOV">; 222 223// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON 224// for scalar FP, as this allows more effective execution domain optimization. 225def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR", 226 "true", "Prefer VMOVSR">; 227 228// Swift has ISHST barriers compatible with Atomic Release semantics but weaker 229// than ISH 230def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST", 231 "true", "Prefer ISHST barriers">; 232 233// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU. 234def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", 235 "true", 236 "Has muxed AGU and NEON/FPU">; 237 238// Whether VLDM/VSTM starting with odd register number need more microops 239// than single VLDRS 240def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister", 241 "true", "VLDM/VSTM starting " 242 "with an odd register is slow">; 243 244// Some targets have a renaming dependency when loading into D subregisters. 245def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg", 246 "SlowLoadDSubregister", "true", 247 "Loading into D subregs is slow">; 248 249def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp", 250 "UseWideStrideVFP", "true", 251 "Use a wide stride when allocating VFP registers">; 252 253// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. 254def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", 255 "DontWidenVMOVS", "true", 256 "Don't widen VMOVS to VMOVD">; 257 258// Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different 259// VFP register widths. 260def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon", 261 "SplatVFPToNeon", "true", 262 "Splat register from VFP to NEON", 263 [FeatureDontWidenVMOVS]>; 264 265// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions. 266def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", 267 "ExpandMLx", "true", 268 "Expand VFP/NEON MLA/MLS instructions">; 269 270// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS. 271def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards", 272 "true", "Has VMLx hazards">; 273 274// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from 275// VFP to NEON, as an execution domain optimization. 276def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", 277 "UseNEONForFPMovs", "true", 278 "Convert VMOVSR, VMOVRS, " 279 "VMOVS to NEON">; 280 281// Some processors benefit from using NEON instructions for scalar 282// single-precision FP operations. This affects instruction selection and should 283// only be enabled if the handling of denormals is not important. 284def FeatureNEONForFP : SubtargetFeature<"neonfp", 285 "UseNEONForSinglePrecisionFP", 286 "true", 287 "Use NEON for single precision FP">; 288 289// On some processors, VLDn instructions that access unaligned data take one 290// extra cycle. Take that into account when computing operand latencies. 291def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign", 292 "true", 293 "Check for VLDn unaligned access">; 294 295// Some processors have a nonpipelined VFP coprocessor. 296def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp", 297 "NonpipelinedVFP", "true", 298 "VFP instructions are not pipelined">; 299 300// Some processors have FP multiply-accumulate instructions that don't 301// play nicely with other VFP / NEON instructions, and it's generally better 302// to just not use them. 303def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 304 "Disable VFP / NEON MAC instructions">; 305 306// VFPv4 added VFMA instructions that can similar be fast or slow. 307def FeatureHasSlowFPVFMx : SubtargetFeature<"slowfpvfmx", "SlowFPVFMx", "true", 308 "Disable VFP / NEON FMA instructions">; 309 310// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 311def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 312 "HasVMLxForwarding", "true", 313 "Has multiplier accumulator forwarding">; 314 315// Disable 32-bit to 16-bit narrowing for experimentation. 316def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 317 "Prefer 32-bit Thumb instrs">; 318 319def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopLogAlignment","2", 320 "Prefer 32-bit alignment for loops">; 321 322def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "1", 323 "Model MVE instructions as a 1 beat per tick architecture">; 324 325def FeatureMVEVectorCostFactor2 : SubtargetFeature<"mve2beat", "MVEVectorCostFactor", "2", 326 "Model MVE instructions as a 2 beats per tick architecture">; 327 328def FeatureMVEVectorCostFactor4 : SubtargetFeature<"mve4beat", "MVEVectorCostFactor", "4", 329 "Model MVE instructions as a 4 beats per tick architecture">; 330 331/// Some instructions update CPSR partially, which can add false dependency for 332/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 333/// mapped to a separate physical register. Avoid partial CPSR update for these 334/// processors. 335def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 336 "AvoidCPSRPartialUpdate", "true", 337 "Avoid CPSR partial update for OOO execution">; 338 339/// Disable +1 predication cost for instructions updating CPSR. 340/// Enabled for Cortex-A57. 341def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr", 342 "CheapPredicableCPSRDef", 343 "true", 344 "Disable +1 predication cost for instructions updating CPSR">; 345 346def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 347 "AvoidMOVsShifterOperand", "true", 348 "Avoid movs instructions with " 349 "shifter operand">; 350 351// Some processors perform return stack prediction. CodeGen should avoid issue 352// "normal" call instructions to callees which do not return. 353def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", 354 "HasRetAddrStack", "true", 355 "Has return address stack">; 356 357// Some processors have no branch predictor, which changes the expected cost of 358// taking a branch which affects the choice of whether to use predicated 359// instructions. 360def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor", 361 "HasBranchPredictor", "false", 362 "Has no branch predictor">; 363 364/// DSP extension. 365def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", 366 "Supports DSP instructions in " 367 "ARM and/or Thumb2">; 368 369// Multiprocessing extension. 370def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 371 "Supports Multiprocessing extension">; 372 373// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 374def FeatureVirtualization : SubtargetFeature<"virtualization", 375 "HasVirtualization", "true", 376 "Supports Virtualization extension", 377 [FeatureHWDivThumb, FeatureHWDivARM]>; 378 379// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 380// See ARMInstrInfo.td for details. 381def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 382 "NaCl trap">; 383 384def FeatureStrictAlign : SubtargetFeature<"strict-align", 385 "StrictAlign", "true", 386 "Disallow all unaligned memory " 387 "access">; 388 389def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", 390 "Generate calls via indirect call " 391 "instructions">; 392 393def FeatureExecuteOnly : SubtargetFeature<"execute-only", 394 "GenExecuteOnly", "true", 395 "Enable the generation of " 396 "execute only code.">; 397 398def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", 399 "Reserve R9, making it unavailable" 400 " as GPR">; 401 402def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", 403 "Don't use movt/movw pairs for " 404 "32-bit imms">; 405 406def FeatureNoNegativeImmediates 407 : SubtargetFeature<"no-neg-immediates", 408 "NegativeImmediates", "false", 409 "Convert immediates and instructions " 410 "to their negated or complemented " 411 "equivalent when the immediate does " 412 "not fit in the encoding.">; 413 414// Use the MachineScheduler for instruction scheduling for the subtarget. 415def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true", 416 "Use the MachineScheduler">; 417 418def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler", 419 "DisablePostRAScheduler", "true", 420 "Don't schedule again after register allocation">; 421 422// Armv8.5-A extensions 423 424def FeatureSB : SubtargetFeature<"sb", "HasSB", "true", 425 "Enable v8.5a Speculation Barrier" >; 426 427// Armv8.6-A extensions 428def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", "true", 429 "Enable support for BFloat16 instructions", [FeatureNEON]>; 430 431def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8", 432 "true", "Enable Matrix Multiply Int8 Extension", [FeatureNEON]>; 433 434// Armv8.1-M extensions 435 436def FeatureLOB : SubtargetFeature<"lob", "HasLOB", "true", 437 "Enable Low Overhead Branch " 438 "extensions">; 439 440def FeatureFixCMSE_CVE_2021_35465 : SubtargetFeature<"fix-cmse-cve-2021-35465", 441 "FixCMSE_CVE_2021_35465", "true", 442 "Mitigate against the cve-2021-35465 " 443 "security vulnurability">; 444 445def FeaturePACBTI : SubtargetFeature<"pacbti", "HasPACBTI", "true", 446 "Enable Pointer Authentication and Branch " 447 "Target Identification">; 448 449def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice", 450 "NoBTIAtReturnTwice", "true", 451 "Don't place a BTI instruction " 452 "after a return-twice">; 453 454//===----------------------------------------------------------------------===// 455// ARM architecture class 456// 457 458// A-series ISA 459def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 460 "Is application profile ('A' series)">; 461 462// R-series ISA 463def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 464 "Is realtime profile ('R' series)">; 465 466// M-series ISA 467def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 468 "Is microcontroller profile ('M' series)">; 469 470 471def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 472 "Enable Thumb2 instructions">; 473 474def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 475 "Does not support ARM mode execution">; 476 477//===----------------------------------------------------------------------===// 478// ARM ISAa. 479// 480 481def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 482 "Support ARM v4T instructions">; 483 484def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 485 "Support ARM v5T instructions", 486 [HasV4TOps]>; 487 488def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 489 "Support ARM v5TE, v5TEj, and " 490 "v5TExp instructions", 491 [HasV5TOps]>; 492 493def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 494 "Support ARM v6 instructions", 495 [HasV5TEOps]>; 496 497def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 498 "Support ARM v6M instructions", 499 [HasV6Ops]>; 500 501def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", 502 "Support ARM v8M Baseline instructions", 503 [HasV6MOps]>; 504 505def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", 506 "Support ARM v6k instructions", 507 [HasV6Ops]>; 508 509def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 510 "Support ARM v6t2 instructions", 511 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; 512 513def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 514 "Support ARM v7 instructions", 515 [HasV6T2Ops, FeatureV7Clrex]>; 516 517def HasV8MMainlineOps : 518 SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", 519 "Support ARM v8M Mainline instructions", 520 [HasV7Ops]>; 521 522def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 523 "Support ARM v8 instructions", 524 [HasV7Ops, FeaturePerfMon, FeatureAcquireRelease]>; 525 526def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 527 "Support ARM v8.1a instructions", 528 [HasV8Ops]>; 529 530def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 531 "Support ARM v8.2a instructions", 532 [HasV8_1aOps]>; 533 534def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 535 "Support ARM v8.3a instructions", 536 [HasV8_2aOps]>; 537 538def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 539 "Support ARM v8.4a instructions", 540 [HasV8_3aOps, FeatureDotProd]>; 541 542def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true", 543 "Support ARM v8.5a instructions", 544 [HasV8_4aOps, FeatureSB]>; 545 546def HasV8_6aOps : SubtargetFeature<"v8.6a", "HasV8_6aOps", "true", 547 "Support ARM v8.6a instructions", 548 [HasV8_5aOps, FeatureBF16, 549 FeatureMatMulInt8]>; 550 551def HasV8_7aOps : SubtargetFeature<"v8.7a", "HasV8_7aOps", "true", 552 "Support ARM v8.7a instructions", 553 [HasV8_6aOps]>; 554 555def HasV8_8aOps : SubtargetFeature<"v8.8a", "HasV8_8aOps", "true", 556 "Support ARM v8.8a instructions", 557 [HasV8_7aOps]>; 558 559def HasV9_0aOps : SubtargetFeature<"v9a", "HasV9_0aOps", "true", 560 "Support ARM v9a instructions", 561 [HasV8_5aOps]>; 562 563def HasV9_1aOps : SubtargetFeature<"v9.1a", "HasV9_1aOps", "true", 564 "Support ARM v9.1a instructions", 565 [HasV8_6aOps, HasV9_0aOps]>; 566 567def HasV9_2aOps : SubtargetFeature<"v9.2a", "HasV9_2aOps", "true", 568 "Support ARM v9.2a instructions", 569 [HasV8_7aOps, HasV9_1aOps]>; 570 571def HasV9_3aOps : SubtargetFeature<"v9.3a", "HasV9_3aOps", "true", 572 "Support ARM v9.3a instructions", 573 [HasV8_8aOps, HasV9_2aOps]>; 574 575def HasV8_1MMainlineOps : SubtargetFeature< 576 "v8.1m.main", "HasV8_1MMainlineOps", "true", 577 "Support ARM v8-1M Mainline instructions", 578 [HasV8MMainlineOps]>; 579def HasMVEIntegerOps : SubtargetFeature< 580 "mve", "HasMVEIntegerOps", "true", 581 "Support M-Class Vector Extension with integer ops", 582 [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>; 583def HasMVEFloatOps : SubtargetFeature< 584 "mve.fp", "HasMVEFloatOps", "true", 585 "Support M-Class Vector Extension with integer and floating ops", 586 [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>; 587 588def HasCDEOps : SubtargetFeature<"cde", "HasCDEOps", "true", 589 "Support CDE instructions", 590 [HasV8MMainlineOps]>; 591 592foreach i = {0-7} in 593 def FeatureCoprocCDE#i : SubtargetFeature<"cdecp"#i, 594 "CoprocCDE["#i#"]", "true", 595 "Coprocessor "#i#" ISA is CDEv1", 596 [HasCDEOps]>; 597 598//===----------------------------------------------------------------------===// 599// Control codegen mitigation against Straight Line Speculation vulnerability. 600//===----------------------------------------------------------------------===// 601 602def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr", 603 "HardenSlsRetBr", "true", 604 "Harden against straight line speculation across RETurn and BranchRegister " 605 "instructions">; 606def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr", 607 "HardenSlsBlr", "true", 608 "Harden against straight line speculation across indirect calls">; 609def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat", 610 "HardenSlsNoComdat", "true", 611 "Generate thunk code for SLS mitigation in the normal text section">; 612 613//===----------------------------------------------------------------------===// 614// ARM Processor subtarget features. 615// 616 617def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 618 "Cortex-A5 ARM processors", []>; 619def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 620 "Cortex-A7 ARM processors", []>; 621def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 622 "Cortex-A8 ARM processors", []>; 623def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 624 "Cortex-A9 ARM processors", []>; 625def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 626 "Cortex-A12 ARM processors", []>; 627def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 628 "Cortex-A15 ARM processors", []>; 629def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", 630 "Cortex-A17 ARM processors", []>; 631def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", 632 "Cortex-A32 ARM processors", []>; 633def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 634 "Cortex-A35 ARM processors", []>; 635def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 636 "Cortex-A53 ARM processors", []>; 637def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 638 "Cortex-A55 ARM processors", []>; 639def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 640 "Cortex-A57 ARM processors", []>; 641def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 642 "Cortex-A72 ARM processors", []>; 643def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 644 "Cortex-A73 ARM processors", []>; 645def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 646 "Cortex-A75 ARM processors", []>; 647def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 648 "Cortex-A76 ARM processors", []>; 649def ProcA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", 650 "Cortex-A77 ARM processors", []>; 651def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily", "CortexA78", 652 "Cortex-A78 ARM processors", []>; 653def ProcA78C : SubtargetFeature<"a78c", "ARMProcFamily", "CortexA78C", 654 "Cortex-A78C ARM processors", []>; 655def ProcA710 : SubtargetFeature<"cortex-a710", "ARMProcFamily", 656 "CortexA710", "Cortex-A710 ARM processors", []>; 657def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", 658 "Cortex-X1 ARM processors", []>; 659def ProcX1C : SubtargetFeature<"cortex-x1c", "ARMProcFamily", "CortexX1C", 660 "Cortex-X1C ARM processors", []>; 661 662def ProcV1 : SubtargetFeature<"neoverse-v1", "ARMProcFamily", 663 "NeoverseV1", "Neoverse-V1 ARM processors", []>; 664 665def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 666 "Qualcomm Krait processors", []>; 667def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 668 "Qualcomm Kryo processors", []>; 669def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 670 "Swift ARM processors", []>; 671 672def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos", 673 "Samsung Exynos processors", 674 [FeatureZCZeroing, 675 FeatureUseWideStrideVFP, 676 FeatureSplatVFPToNeon, 677 FeatureSlowVGETLNi32, 678 FeatureSlowVDUP32, 679 FeatureSlowFPBrcc, 680 FeatureProfUnpredicate, 681 FeatureHWDivThumb, 682 FeatureHWDivARM, 683 FeatureHasSlowFPVMLx, 684 FeatureHasSlowFPVFMx, 685 FeatureHasRetAddrStack, 686 FeatureFuseLiterals, 687 FeatureFuseAES, 688 FeatureExpandMLx, 689 FeatureCrypto, 690 FeatureCRC]>; 691 692def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", 693 "Cortex-R4 ARM processors", []>; 694def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 695 "Cortex-R5 ARM processors", []>; 696def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", 697 "Cortex-R7 ARM processors", []>; 698def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", 699 "Cortex-R52 ARM processors", []>; 700 701def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", 702 "Cortex-M3 ARM processors", []>; 703def ProcM7 : SubtargetFeature<"m7", "ARMProcFamily", "CortexM7", 704 "Cortex-M7 ARM processors", []>; 705 706//===----------------------------------------------------------------------===// 707// ARM Helper classes. 708// 709 710class Architecture<string fname, string aname, list<SubtargetFeature> features> 711 : SubtargetFeature<fname, "ARMArch", aname, 712 !strconcat(aname, " architecture"), features>; 713 714class ProcNoItin<string Name, list<SubtargetFeature> Features> 715 : Processor<Name, NoItineraries, Features>; 716 717 718//===----------------------------------------------------------------------===// 719// ARM architectures 720// 721 722def ARMv2 : Architecture<"armv2", "ARMv2", []>; 723 724def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; 725 726def ARMv3 : Architecture<"armv3", "ARMv3", []>; 727 728def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; 729 730def ARMv4 : Architecture<"armv4", "ARMv4", []>; 731 732def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; 733 734def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; 735 736def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; 737 738def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; 739 740def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops, 741 FeatureDSP]>; 742 743def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, 744 FeatureDSP]>; 745 746def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; 747 748def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, 749 FeatureTrustZone]>; 750 751def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, 752 FeatureNoARM, 753 ModeThumb, 754 FeatureDB, 755 FeatureMClass, 756 FeatureStrictAlign]>; 757 758def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, 759 FeatureNoARM, 760 ModeThumb, 761 FeatureDB, 762 FeatureMClass, 763 FeatureStrictAlign]>; 764 765def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, 766 FeatureNEON, 767 FeatureDB, 768 FeatureDSP, 769 FeatureAClass, 770 FeaturePerfMon]>; 771 772def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops, 773 FeatureNEON, 774 FeatureDB, 775 FeatureDSP, 776 FeatureTrustZone, 777 FeatureMP, 778 FeatureVirtualization, 779 FeatureAClass, 780 FeaturePerfMon]>; 781 782def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, 783 FeatureDB, 784 FeatureDSP, 785 FeatureHWDivThumb, 786 FeatureRClass, 787 FeaturePerfMon]>; 788 789def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, 790 FeatureThumb2, 791 FeatureNoARM, 792 ModeThumb, 793 FeatureDB, 794 FeatureHWDivThumb, 795 FeatureMClass]>; 796 797def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, 798 FeatureThumb2, 799 FeatureNoARM, 800 ModeThumb, 801 FeatureDB, 802 FeatureHWDivThumb, 803 FeatureMClass, 804 FeatureDSP]>; 805 806def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, 807 FeatureAClass, 808 FeatureDB, 809 FeatureFPARMv8, 810 FeatureNEON, 811 FeatureDSP, 812 FeatureTrustZone, 813 FeatureMP, 814 FeatureVirtualization, 815 FeatureCrypto, 816 FeatureCRC]>; 817 818def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, 819 FeatureAClass, 820 FeatureDB, 821 FeatureFPARMv8, 822 FeatureNEON, 823 FeatureDSP, 824 FeatureTrustZone, 825 FeatureMP, 826 FeatureVirtualization, 827 FeatureCrypto, 828 FeatureCRC]>; 829 830def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, 831 FeatureAClass, 832 FeatureDB, 833 FeatureFPARMv8, 834 FeatureNEON, 835 FeatureDSP, 836 FeatureTrustZone, 837 FeatureMP, 838 FeatureVirtualization, 839 FeatureCrypto, 840 FeatureCRC, 841 FeatureRAS]>; 842 843def ARMv83a : Architecture<"armv8.3-a", "ARMv83a", [HasV8_3aOps, 844 FeatureAClass, 845 FeatureDB, 846 FeatureFPARMv8, 847 FeatureNEON, 848 FeatureDSP, 849 FeatureTrustZone, 850 FeatureMP, 851 FeatureVirtualization, 852 FeatureCrypto, 853 FeatureCRC, 854 FeatureRAS]>; 855 856def ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps, 857 FeatureAClass, 858 FeatureDB, 859 FeatureFPARMv8, 860 FeatureNEON, 861 FeatureDSP, 862 FeatureTrustZone, 863 FeatureMP, 864 FeatureVirtualization, 865 FeatureCrypto, 866 FeatureCRC, 867 FeatureRAS, 868 FeatureDotProd]>; 869 870def ARMv85a : Architecture<"armv8.5-a", "ARMv85a", [HasV8_5aOps, 871 FeatureAClass, 872 FeatureDB, 873 FeatureFPARMv8, 874 FeatureNEON, 875 FeatureDSP, 876 FeatureTrustZone, 877 FeatureMP, 878 FeatureVirtualization, 879 FeatureCrypto, 880 FeatureCRC, 881 FeatureRAS, 882 FeatureDotProd]>; 883def ARMv86a : Architecture<"armv8.6-a", "ARMv86a", [HasV8_6aOps, 884 FeatureAClass, 885 FeatureDB, 886 FeatureFPARMv8, 887 FeatureNEON, 888 FeatureDSP, 889 FeatureTrustZone, 890 FeatureMP, 891 FeatureVirtualization, 892 FeatureCrypto, 893 FeatureCRC, 894 FeatureRAS, 895 FeatureDotProd]>; 896def ARMv87a : Architecture<"armv8.7-a", "ARMv87a", [HasV8_7aOps, 897 FeatureAClass, 898 FeatureDB, 899 FeatureFPARMv8, 900 FeatureNEON, 901 FeatureDSP, 902 FeatureTrustZone, 903 FeatureMP, 904 FeatureVirtualization, 905 FeatureCrypto, 906 FeatureCRC, 907 FeatureRAS, 908 FeatureDotProd]>; 909def ARMv88a : Architecture<"armv8.8-a", "ARMv88a", [HasV8_8aOps, 910 FeatureAClass, 911 FeatureDB, 912 FeatureFPARMv8, 913 FeatureNEON, 914 FeatureDSP, 915 FeatureTrustZone, 916 FeatureMP, 917 FeatureVirtualization, 918 FeatureCrypto, 919 FeatureCRC, 920 FeatureRAS, 921 FeatureDotProd]>; 922 923def ARMv9a : Architecture<"armv9-a", "ARMv9a", [HasV9_0aOps, 924 FeatureAClass, 925 FeatureDB, 926 FeatureFPARMv8, 927 FeatureNEON, 928 FeatureDSP, 929 FeatureTrustZone, 930 FeatureMP, 931 FeatureVirtualization, 932 FeatureCRC, 933 FeatureRAS, 934 FeatureDotProd]>; 935def ARMv91a : Architecture<"armv9.1-a", "ARMv91a", [HasV9_1aOps, 936 FeatureAClass, 937 FeatureDB, 938 FeatureFPARMv8, 939 FeatureNEON, 940 FeatureDSP, 941 FeatureTrustZone, 942 FeatureMP, 943 FeatureVirtualization, 944 FeatureCRC, 945 FeatureRAS, 946 FeatureDotProd]>; 947def ARMv92a : Architecture<"armv9.2-a", "ARMv92a", [HasV9_2aOps, 948 FeatureAClass, 949 FeatureDB, 950 FeatureFPARMv8, 951 FeatureNEON, 952 FeatureDSP, 953 FeatureTrustZone, 954 FeatureMP, 955 FeatureVirtualization, 956 FeatureCRC, 957 FeatureRAS, 958 FeatureDotProd]>; 959def ARMv93a : Architecture<"armv9.3-a", "ARMv93a", [HasV9_3aOps, 960 FeatureAClass, 961 FeatureDB, 962 FeatureFPARMv8, 963 FeatureNEON, 964 FeatureDSP, 965 FeatureTrustZone, 966 FeatureMP, 967 FeatureVirtualization, 968 FeatureCrypto, 969 FeatureCRC, 970 FeatureRAS, 971 FeatureDotProd]>; 972 973def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, 974 FeatureRClass, 975 FeatureDB, 976 FeatureDFB, 977 FeatureDSP, 978 FeatureCRC, 979 FeatureMP, 980 FeatureVirtualization, 981 FeatureFPARMv8, 982 FeatureNEON]>; 983 984def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", 985 [HasV8MBaselineOps, 986 FeatureNoARM, 987 ModeThumb, 988 FeatureDB, 989 FeatureHWDivThumb, 990 FeatureV7Clrex, 991 Feature8MSecExt, 992 FeatureAcquireRelease, 993 FeatureMClass, 994 FeatureStrictAlign]>; 995 996def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", 997 [HasV8MMainlineOps, 998 FeatureNoARM, 999 ModeThumb, 1000 FeatureDB, 1001 FeatureHWDivThumb, 1002 Feature8MSecExt, 1003 FeatureAcquireRelease, 1004 FeatureMClass]>; 1005 1006def ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline", 1007 [HasV8_1MMainlineOps, 1008 FeatureNoARM, 1009 ModeThumb, 1010 FeatureDB, 1011 FeatureHWDivThumb, 1012 Feature8MSecExt, 1013 FeatureAcquireRelease, 1014 FeatureMClass, 1015 FeatureRAS, 1016 FeatureLOB]>; 1017 1018// Aliases 1019def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; 1020def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; 1021def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; 1022def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; 1023def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; 1024def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; 1025 1026//===----------------------------------------------------------------------===// 1027// Register File Description 1028//===----------------------------------------------------------------------===// 1029 1030include "ARMRegisterInfo.td" 1031include "ARMRegisterBanks.td" 1032include "ARMCallingConv.td" 1033 1034//===----------------------------------------------------------------------===// 1035// ARM schedules. 1036//===----------------------------------------------------------------------===// 1037// 1038include "ARMPredicates.td" 1039include "ARMSchedule.td" 1040 1041//===----------------------------------------------------------------------===// 1042// Instruction Descriptions 1043//===----------------------------------------------------------------------===// 1044 1045include "ARMInstrInfo.td" 1046def ARMInstrInfo : InstrInfo; 1047 1048//===----------------------------------------------------------------------===// 1049// ARM schedules 1050// 1051include "ARMScheduleV6.td" 1052include "ARMScheduleA8.td" 1053include "ARMScheduleA9.td" 1054include "ARMScheduleSwift.td" 1055include "ARMScheduleR52.td" 1056include "ARMScheduleA57.td" 1057include "ARMScheduleM4.td" 1058include "ARMScheduleM7.td" 1059 1060//===----------------------------------------------------------------------===// 1061// ARM processors 1062// 1063// Dummy CPU, used to target architectures 1064def : ProcessorModel<"generic", CortexA8Model, []>; 1065 1066// FIXME: Several processors below are not using their own scheduler 1067// model, but one of similar/previous processor. These should be fixed. 1068 1069def : ProcNoItin<"arm8", [ARMv4]>; 1070def : ProcNoItin<"arm810", [ARMv4]>; 1071def : ProcNoItin<"strongarm", [ARMv4]>; 1072def : ProcNoItin<"strongarm110", [ARMv4]>; 1073def : ProcNoItin<"strongarm1100", [ARMv4]>; 1074def : ProcNoItin<"strongarm1110", [ARMv4]>; 1075 1076def : ProcNoItin<"arm7tdmi", [ARMv4t]>; 1077def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; 1078def : ProcNoItin<"arm710t", [ARMv4t]>; 1079def : ProcNoItin<"arm720t", [ARMv4t]>; 1080def : ProcNoItin<"arm9", [ARMv4t]>; 1081def : ProcNoItin<"arm9tdmi", [ARMv4t]>; 1082def : ProcNoItin<"arm920", [ARMv4t]>; 1083def : ProcNoItin<"arm920t", [ARMv4t]>; 1084def : ProcNoItin<"arm922t", [ARMv4t]>; 1085def : ProcNoItin<"arm940t", [ARMv4t]>; 1086def : ProcNoItin<"ep9312", [ARMv4t]>; 1087 1088def : ProcNoItin<"arm10tdmi", [ARMv5t]>; 1089def : ProcNoItin<"arm1020t", [ARMv5t]>; 1090 1091def : ProcNoItin<"arm9e", [ARMv5te]>; 1092def : ProcNoItin<"arm926ej-s", [ARMv5te]>; 1093def : ProcNoItin<"arm946e-s", [ARMv5te]>; 1094def : ProcNoItin<"arm966e-s", [ARMv5te]>; 1095def : ProcNoItin<"arm968e-s", [ARMv5te]>; 1096def : ProcNoItin<"arm10e", [ARMv5te]>; 1097def : ProcNoItin<"arm1020e", [ARMv5te]>; 1098def : ProcNoItin<"arm1022e", [ARMv5te]>; 1099def : ProcNoItin<"xscale", [ARMv5te]>; 1100def : ProcNoItin<"iwmmxt", [ARMv5te]>; 1101 1102def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; 1103def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, 1104 FeatureVFP2, 1105 FeatureHasSlowFPVMLx]>; 1106 1107def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m, 1108 FeatureHasNoBranchPredictor]>; 1109def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m, 1110 FeatureHasNoBranchPredictor]>; 1111def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m, 1112 FeatureHasNoBranchPredictor]>; 1113def : Processor<"sc000", ARMV6Itineraries, [ARMv6m, 1114 FeatureHasNoBranchPredictor]>; 1115 1116def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; 1117def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, 1118 FeatureVFP2, 1119 FeatureHasSlowFPVMLx]>; 1120 1121def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; 1122def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, 1123 FeatureVFP2, 1124 FeatureHasSlowFPVMLx]>; 1125 1126def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; 1127def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, 1128 FeatureVFP2, 1129 FeatureHasSlowFPVMLx]>; 1130 1131def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, 1132 FeatureHasRetAddrStack, 1133 FeatureTrustZone, 1134 FeatureSlowFPBrcc, 1135 FeatureHasSlowFPVMLx, 1136 FeatureHasSlowFPVFMx, 1137 FeatureVMLxForwarding, 1138 FeatureMP, 1139 FeatureVFP4]>; 1140 1141def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, 1142 FeatureHasRetAddrStack, 1143 FeatureTrustZone, 1144 FeatureSlowFPBrcc, 1145 FeatureHasVMLxHazards, 1146 FeatureHasSlowFPVMLx, 1147 FeatureHasSlowFPVFMx, 1148 FeatureVMLxForwarding, 1149 FeatureMP, 1150 FeatureVFP4, 1151 FeatureVirtualization]>; 1152 1153def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, 1154 FeatureHasRetAddrStack, 1155 FeatureNonpipelinedVFP, 1156 FeatureTrustZone, 1157 FeatureSlowFPBrcc, 1158 FeatureHasVMLxHazards, 1159 FeatureHasSlowFPVMLx, 1160 FeatureHasSlowFPVFMx, 1161 FeatureVMLxForwarding]>; 1162 1163def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, 1164 FeatureHasRetAddrStack, 1165 FeatureTrustZone, 1166 FeatureHasVMLxHazards, 1167 FeatureVMLxForwarding, 1168 FeatureFP16, 1169 FeatureAvoidPartialCPSR, 1170 FeatureExpandMLx, 1171 FeaturePreferVMOVSR, 1172 FeatureMuxedUnits, 1173 FeatureNEONForFPMovs, 1174 FeatureCheckVLDnAlign, 1175 FeatureMP]>; 1176 1177def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, 1178 FeatureHasRetAddrStack, 1179 FeatureTrustZone, 1180 FeatureVMLxForwarding, 1181 FeatureVFP4, 1182 FeatureAvoidPartialCPSR, 1183 FeatureVirtualization, 1184 FeatureMP]>; 1185 1186def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, 1187 FeatureDontWidenVMOVS, 1188 FeatureSplatVFPToNeon, 1189 FeatureHasRetAddrStack, 1190 FeatureMuxedUnits, 1191 FeatureTrustZone, 1192 FeatureVFP4, 1193 FeatureMP, 1194 FeatureCheckVLDnAlign, 1195 FeatureAvoidPartialCPSR, 1196 FeatureVirtualization]>; 1197 1198def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, 1199 FeatureHasRetAddrStack, 1200 FeatureTrustZone, 1201 FeatureMP, 1202 FeatureVMLxForwarding, 1203 FeatureVFP4, 1204 FeatureAvoidPartialCPSR, 1205 FeatureVirtualization]>; 1206 1207// FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv 1208def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, 1209 FeatureHasRetAddrStack, 1210 FeatureMuxedUnits, 1211 FeatureCheckVLDnAlign, 1212 FeatureVMLxForwarding, 1213 FeatureFP16, 1214 FeatureAvoidPartialCPSR, 1215 FeatureVFP4, 1216 FeatureHWDivThumb, 1217 FeatureHWDivARM]>; 1218 1219def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, 1220 FeatureHasRetAddrStack, 1221 FeatureNEONForFP, 1222 FeatureVFP4, 1223 FeatureUseWideStrideVFP, 1224 FeatureMP, 1225 FeatureHWDivThumb, 1226 FeatureHWDivARM, 1227 FeatureAvoidPartialCPSR, 1228 FeatureAvoidMOVsShOp, 1229 FeatureHasSlowFPVMLx, 1230 FeatureHasSlowFPVFMx, 1231 FeatureHasVMLxHazards, 1232 FeatureProfUnpredicate, 1233 FeaturePrefISHSTBarrier, 1234 FeatureSlowOddRegister, 1235 FeatureSlowLoadDSubreg, 1236 FeatureSlowVGETLNi32, 1237 FeatureSlowVDUP32, 1238 FeatureUseMISched, 1239 FeatureNoPostRASched]>; 1240 1241def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, 1242 FeatureHasRetAddrStack, 1243 FeatureAvoidPartialCPSR]>; 1244 1245def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, 1246 FeatureHasRetAddrStack, 1247 FeatureSlowFPBrcc, 1248 FeatureHasSlowFPVMLx, 1249 FeatureHasSlowFPVFMx, 1250 FeatureVFP3_D16, 1251 FeatureAvoidPartialCPSR]>; 1252 1253def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, 1254 FeatureHasRetAddrStack, 1255 FeatureVFP3_D16, 1256 FeatureSlowFPBrcc, 1257 FeatureHWDivARM, 1258 FeatureHasSlowFPVMLx, 1259 FeatureHasSlowFPVFMx, 1260 FeatureAvoidPartialCPSR]>; 1261 1262def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, 1263 FeatureHasRetAddrStack, 1264 FeatureVFP3_D16, 1265 FeatureFP16, 1266 FeatureMP, 1267 FeatureSlowFPBrcc, 1268 FeatureHWDivARM, 1269 FeatureHasSlowFPVMLx, 1270 FeatureHasSlowFPVFMx, 1271 FeatureAvoidPartialCPSR]>; 1272 1273def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, 1274 FeatureHasRetAddrStack, 1275 FeatureVFP3_D16, 1276 FeatureFP16, 1277 FeatureMP, 1278 FeatureSlowFPBrcc, 1279 FeatureHWDivARM, 1280 FeatureHasSlowFPVMLx, 1281 FeatureHasSlowFPVFMx, 1282 FeatureAvoidPartialCPSR]>; 1283 1284def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m, 1285 ProcM3, 1286 FeaturePrefLoopAlign32, 1287 FeatureUseMISched, 1288 FeatureHasNoBranchPredictor]>; 1289 1290def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m, 1291 ProcM3, 1292 FeatureUseMISched, 1293 FeatureHasNoBranchPredictor]>; 1294 1295def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em, 1296 FeatureVFP4_D16_SP, 1297 FeaturePrefLoopAlign32, 1298 FeatureHasSlowFPVMLx, 1299 FeatureHasSlowFPVFMx, 1300 FeatureUseMISched, 1301 FeatureHasNoBranchPredictor]>; 1302 1303def : ProcessorModel<"cortex-m7", CortexM7Model, [ARMv7em, 1304 ProcM7, 1305 FeatureFPARMv8_D16, 1306 FeatureUseMISched]>; 1307 1308def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, 1309 FeatureNoMovt, 1310 FeatureHasNoBranchPredictor]>; 1311 1312def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline, 1313 FeatureDSP, 1314 FeatureFPARMv8_D16_SP, 1315 FeaturePrefLoopAlign32, 1316 FeatureHasSlowFPVMLx, 1317 FeatureHasSlowFPVFMx, 1318 FeatureUseMISched, 1319 FeatureHasNoBranchPredictor, 1320 FeatureFixCMSE_CVE_2021_35465]>; 1321 1322def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline, 1323 FeatureDSP, 1324 FeatureFPARMv8_D16_SP, 1325 FeaturePrefLoopAlign32, 1326 FeatureHasSlowFPVMLx, 1327 FeatureHasSlowFPVFMx, 1328 FeatureUseMISched, 1329 FeatureHasNoBranchPredictor, 1330 FeatureFixCMSE_CVE_2021_35465]>; 1331 1332def : ProcessorModel<"cortex-m55", CortexM4Model, [ARMv81mMainline, 1333 FeatureDSP, 1334 FeatureFPARMv8_D16, 1335 FeatureUseMISched, 1336 FeatureHasNoBranchPredictor, 1337 FeaturePrefLoopAlign32, 1338 FeatureHasSlowFPVMLx, 1339 HasMVEFloatOps, 1340 FeatureFixCMSE_CVE_2021_35465]>; 1341 1342def : ProcNoItin<"cortex-a32", [ARMv8a, 1343 FeatureHWDivThumb, 1344 FeatureHWDivARM, 1345 FeatureCrypto, 1346 FeatureCRC]>; 1347 1348def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, 1349 FeatureHWDivThumb, 1350 FeatureHWDivARM, 1351 FeatureCrypto, 1352 FeatureCRC]>; 1353 1354def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, 1355 FeatureHWDivThumb, 1356 FeatureHWDivARM, 1357 FeatureCrypto, 1358 FeatureCRC, 1359 FeatureFPAO]>; 1360 1361def : ProcNoItin<"cortex-a55", [ARMv82a, ProcA55, 1362 FeatureHWDivThumb, 1363 FeatureHWDivARM, 1364 FeatureDotProd]>; 1365 1366def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57, 1367 FeatureHWDivThumb, 1368 FeatureHWDivARM, 1369 FeatureCrypto, 1370 FeatureCRC, 1371 FeatureFPAO, 1372 FeatureAvoidPartialCPSR, 1373 FeatureCheapPredicableCPSR]>; 1374 1375def : ProcessorModel<"cortex-a72", CortexA57Model, [ARMv8a, ProcA72, 1376 FeatureHWDivThumb, 1377 FeatureHWDivARM, 1378 FeatureCrypto, 1379 FeatureCRC]>; 1380 1381def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, 1382 FeatureHWDivThumb, 1383 FeatureHWDivARM, 1384 FeatureCrypto, 1385 FeatureCRC]>; 1386 1387def : ProcNoItin<"cortex-a75", [ARMv82a, ProcA75, 1388 FeatureHWDivThumb, 1389 FeatureHWDivARM, 1390 FeatureDotProd]>; 1391 1392def : ProcNoItin<"cortex-a76", [ARMv82a, ProcA76, 1393 FeatureHWDivThumb, 1394 FeatureHWDivARM, 1395 FeatureCrypto, 1396 FeatureCRC, 1397 FeatureFullFP16, 1398 FeatureDotProd]>; 1399 1400def : ProcNoItin<"cortex-a76ae", [ARMv82a, ProcA76, 1401 FeatureHWDivThumb, 1402 FeatureHWDivARM, 1403 FeatureCrypto, 1404 FeatureCRC, 1405 FeatureFullFP16, 1406 FeatureDotProd]>; 1407 1408def : ProcNoItin<"cortex-a77", [ARMv82a, ProcA77, 1409 FeatureHWDivThumb, 1410 FeatureHWDivARM, 1411 FeatureCrypto, 1412 FeatureCRC, 1413 FeatureFullFP16, 1414 FeatureDotProd]>; 1415 1416def : ProcNoItin<"cortex-a78", [ARMv82a, ProcA78, 1417 FeatureHWDivThumb, 1418 FeatureHWDivARM, 1419 FeatureCrypto, 1420 FeatureCRC, 1421 FeatureFullFP16, 1422 FeatureDotProd]>; 1423 1424def : ProcNoItin<"cortex-a78c", [ARMv82a, ProcA78C, 1425 FeatureHWDivThumb, 1426 FeatureHWDivARM, 1427 FeatureCrypto, 1428 FeatureCRC, 1429 FeatureDotProd, 1430 FeatureFullFP16]>; 1431 1432def : ProcNoItin<"cortex-a710", [ARMv9a, ProcA710, 1433 FeatureHWDivThumb, 1434 FeatureHWDivARM, 1435 FeatureFP16FML, 1436 FeatureBF16, 1437 FeatureMatMulInt8, 1438 FeatureSB]>; 1439 1440def : ProcNoItin<"cortex-x1", [ARMv82a, ProcX1, 1441 FeatureHWDivThumb, 1442 FeatureHWDivARM, 1443 FeatureCrypto, 1444 FeatureCRC, 1445 FeatureFullFP16, 1446 FeatureDotProd]>; 1447 1448def : ProcNoItin<"cortex-x1c", [ARMv82a, ProcX1C, 1449 FeatureHWDivThumb, 1450 FeatureHWDivARM, 1451 FeatureCrypto, 1452 FeatureCRC, 1453 FeatureFullFP16, 1454 FeatureDotProd]>; 1455 1456def : ProcNoItin<"neoverse-v1", [ARMv84a, 1457 FeatureHWDivThumb, 1458 FeatureHWDivARM, 1459 FeatureCrypto, 1460 FeatureCRC, 1461 FeatureFullFP16, 1462 FeatureBF16, 1463 FeatureMatMulInt8]>; 1464 1465def : ProcNoItin<"neoverse-n1", [ARMv82a, 1466 FeatureHWDivThumb, 1467 FeatureHWDivARM, 1468 FeatureCrypto, 1469 FeatureCRC, 1470 FeatureDotProd]>; 1471 1472def : ProcNoItin<"neoverse-n2", [ARMv85a, 1473 FeatureBF16, 1474 FeatureMatMulInt8]>; 1475 1476def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, 1477 FeatureHasRetAddrStack, 1478 FeatureNEONForFP, 1479 FeatureVFP4, 1480 FeatureMP, 1481 FeatureHWDivThumb, 1482 FeatureHWDivARM, 1483 FeatureAvoidPartialCPSR, 1484 FeatureAvoidMOVsShOp, 1485 FeatureHasSlowFPVMLx, 1486 FeatureHasSlowFPVFMx, 1487 FeatureCrypto, 1488 FeatureUseMISched, 1489 FeatureZCZeroing, 1490 FeatureNoPostRASched]>; 1491 1492def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynos]>; 1493def : ProcNoItin<"exynos-m4", [ARMv82a, ProcExynos, 1494 FeatureFullFP16, 1495 FeatureDotProd]>; 1496def : ProcNoItin<"exynos-m5", [ARMv82a, ProcExynos, 1497 FeatureFullFP16, 1498 FeatureDotProd]>; 1499 1500def : ProcNoItin<"kryo", [ARMv8a, ProcKryo, 1501 FeatureHWDivThumb, 1502 FeatureHWDivARM, 1503 FeatureCrypto, 1504 FeatureCRC]>; 1505 1506def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, 1507 FeatureUseMISched, 1508 FeatureFPAO]>; 1509 1510//===----------------------------------------------------------------------===// 1511// Declare the target which we are implementing 1512//===----------------------------------------------------------------------===// 1513 1514def ARMAsmWriter : AsmWriter { 1515 string AsmWriterClassName = "InstPrinter"; 1516 int PassSubtarget = 1; 1517 int Variant = 0; 1518 bit isMCAsmWriter = 1; 1519} 1520 1521def ARMAsmParser : AsmParser { 1522 bit ReportMultipleNearMisses = 1; 1523} 1524 1525def ARMAsmParserVariant : AsmParserVariant { 1526 int Variant = 0; 1527 string Name = "ARM"; 1528 string BreakCharacters = "."; 1529} 1530 1531def ARM : Target { 1532 // Pull in Instruction Info. 1533 let InstructionSet = ARMInstrInfo; 1534 let AssemblyWriters = [ARMAsmWriter]; 1535 let AssemblyParsers = [ARMAsmParser]; 1536 let AssemblyParserVariants = [ARMAsmParserVariant]; 1537 let AllowRegisterRenaming = 1; 1538} 1539