1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// ARM Subtarget state. 20// 21 22def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", 23 "true", "Thumb mode">; 24 25def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat", 26 "true", "Use software floating " 27 "point features.">; 28 29 30//===----------------------------------------------------------------------===// 31// ARM Subtarget features. 32// 33 34// Floating Point, HW Division and Neon Support 35 36// FP loads/stores/moves, shared between VFP and MVE (even in the integer-only 37// version). 38def FeatureFPRegs : SubtargetFeature<"fpregs", "HasFPRegs", "true", 39 "Enable FP registers">; 40 41// 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16 42// extension) and MVE (even in the integer-only version). 43def FeatureFPRegs16 : SubtargetFeature<"fpregs16", "HasFPRegs16", "true", 44 "Enable 16-bit FP registers", 45 [FeatureFPRegs]>; 46 47def FeatureFPRegs64 : SubtargetFeature<"fpregs64", "HasFPRegs64", "true", 48 "Enable 64-bit FP registers", 49 [FeatureFPRegs]>; 50 51def FeatureFP64 : SubtargetFeature<"fp64", "HasFP64", "true", 52 "Floating point unit supports " 53 "double precision", 54 [FeatureFPRegs64]>; 55 56def FeatureD32 : SubtargetFeature<"d32", "HasD32", "true", 57 "Extend FP to 32 double registers">; 58 59multiclass VFPver<string name, string query, string description, 60 list<SubtargetFeature> prev, 61 list<SubtargetFeature> otherimplies, 62 list<SubtargetFeature> vfp2prev = []> { 63 def _D16_SP: SubtargetFeature< 64 name#"d16sp", query#"D16SP", "true", 65 description#" with only 16 d-registers and no double precision", 66 !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) # 67 !foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) # 68 otherimplies>; 69 def _SP: SubtargetFeature< 70 name#"sp", query#"SP", "true", 71 description#" with no double precision", 72 !foreach(v, prev, !cast<SubtargetFeature>(v # "_SP")) # 73 otherimplies # [FeatureD32, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; 74 def _D16: SubtargetFeature< 75 name#"d16", query#"D16", "true", 76 description#" with only 16 d-registers", 77 !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) # 78 vfp2prev # 79 otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; 80 def "": SubtargetFeature< 81 name, query, "true", description, 82 prev # otherimplies # [ 83 !cast<SubtargetFeature>(NAME # "_D16"), 84 !cast<SubtargetFeature>(NAME # "_SP")]>; 85} 86 87def FeatureVFP2_SP : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true", 88 "Enable VFP2 instructions with " 89 "no double precision", 90 [FeatureFPRegs]>; 91 92def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 93 "Enable VFP2 instructions", 94 [FeatureFP64, FeatureVFP2_SP]>; 95 96defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions", 97 [], [], [FeatureVFP2]>; 98 99def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 100 "Enable NEON instructions", 101 [FeatureVFP3]>; 102 103def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 104 "Enable half-precision " 105 "floating point">; 106 107defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions", 108 [FeatureVFP3], [FeatureFP16]>; 109 110defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP", 111 [FeatureVFP4], []>; 112 113def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 114 "Enable full half-precision " 115 "floating point", 116 [FeatureFPARMv8_D16_SP, FeatureFPRegs16]>; 117 118def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 119 "Enable full half-precision " 120 "floating point fml instructions", 121 [FeatureFullFP16]>; 122 123def FeatureHWDivThumb : SubtargetFeature<"hwdiv", 124 "HasHardwareDivideInThumb", "true", 125 "Enable divide instructions in Thumb">; 126 127def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 128 "HasHardwareDivideInARM", "true", 129 "Enable divide instructions in ARM mode">; 130 131// Atomic Support 132def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 133 "Has data barrier (dmb/dsb) instructions">; 134 135def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", 136 "Has v7 clrex instruction">; 137 138def FeatureDFB : SubtargetFeature<"dfb", "HasFullDataBarrier", "true", 139 "Has full data barrier (dfb) instruction">; 140 141def FeatureAcquireRelease : SubtargetFeature<"acquire-release", 142 "HasAcquireRelease", "true", 143 "Has v8 acquire/release (lda/ldaex " 144 " etc) instructions">; 145 146 147def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 148 "FP compare + branch is slow">; 149 150def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 151 "Enable support for Performance " 152 "Monitor extensions">; 153 154 155// TrustZone Security Extensions 156def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 157 "Enable support for TrustZone " 158 "security extensions">; 159 160def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", 161 "Enable support for ARMv8-M " 162 "Security Extensions">; 163 164def FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true", 165 "Enable SHA1 and SHA256 support", [FeatureNEON]>; 166 167def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 168 "Enable AES support", [FeatureNEON]>; 169 170def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 171 "Enable support for " 172 "Cryptography extensions", 173 [FeatureNEON, FeatureSHA2, FeatureAES]>; 174 175def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 176 "Enable support for CRC instructions">; 177 178def FeatureDotProd : SubtargetFeature<"dotprod", "HasDotProd", "true", 179 "Enable support for dot product instructions", 180 [FeatureNEON]>; 181 182// Not to be confused with FeatureHasRetAddrStack (return address stack) 183def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 184 "Enable Reliability, Availability " 185 "and Serviceability extensions">; 186 187// Fast computation of non-negative address offsets 188def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true", 189 "Enable fast computation of " 190 "positive address offsets">; 191 192// Fast execution of AES crypto operations 193def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true", 194 "CPU fuses AES crypto operations">; 195 196// Fast execution of bottom and top halves of literal generation 197def FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true", 198 "CPU fuses literal generation operations">; 199 200// The way of reading thread pointer 201def FeatureReadTp : SubtargetFeature<"read-tp-hard", "ReadTPHard", "true", 202 "Reading thread pointer from register">; 203 204// Cyclone can zero VFP registers in 0 cycles. 205def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 206 "Has zero-cycle zeroing instructions">; 207 208// Whether it is profitable to unpredicate certain instructions during if-conversion 209def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr", 210 "IsProfitableToUnpredicate", "true", 211 "Is profitable to unpredicate">; 212 213// Some targets (e.g. Swift) have microcoded VGETLNi32. 214def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32", 215 "HasSlowVGETLNi32", "true", 216 "Has slow VGETLNi32 - prefer VMOV">; 217 218// Some targets (e.g. Swift) have microcoded VDUP32. 219def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", 220 "true", 221 "Has slow VDUP32 - prefer VMOV">; 222 223// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON 224// for scalar FP, as this allows more effective execution domain optimization. 225def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR", 226 "true", "Prefer VMOVSR">; 227 228// Swift has ISHST barriers compatible with Atomic Release semantics but weaker 229// than ISH 230def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST", 231 "true", "Prefer ISHST barriers">; 232 233// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU. 234def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", 235 "true", 236 "Has muxed AGU and NEON/FPU">; 237 238// Whether VLDM/VSTM starting with odd register number need more microops 239// than single VLDRS 240def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister", 241 "true", "VLDM/VSTM starting " 242 "with an odd register is slow">; 243 244// Some targets have a renaming dependency when loading into D subregisters. 245def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg", 246 "SlowLoadDSubregister", "true", 247 "Loading into D subregs is slow">; 248 249def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp", 250 "UseWideStrideVFP", "true", 251 "Use a wide stride when allocating VFP registers">; 252 253// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. 254def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", 255 "DontWidenVMOVS", "true", 256 "Don't widen VMOVS to VMOVD">; 257 258// Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different 259// VFP register widths. 260def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon", 261 "SplatVFPToNeon", "true", 262 "Splat register from VFP to NEON", 263 [FeatureDontWidenVMOVS]>; 264 265// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions. 266def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", 267 "ExpandMLx", "true", 268 "Expand VFP/NEON MLA/MLS instructions">; 269 270// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS. 271def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards", 272 "true", "Has VMLx hazards">; 273 274// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from 275// VFP to NEON, as an execution domain optimization. 276def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", 277 "UseNEONForFPMovs", "true", 278 "Convert VMOVSR, VMOVRS, " 279 "VMOVS to NEON">; 280 281// Some processors benefit from using NEON instructions for scalar 282// single-precision FP operations. This affects instruction selection and should 283// only be enabled if the handling of denormals is not important. 284def FeatureNEONForFP : SubtargetFeature<"neonfp", 285 "UseNEONForSinglePrecisionFP", 286 "true", 287 "Use NEON for single precision FP">; 288 289// On some processors, VLDn instructions that access unaligned data take one 290// extra cycle. Take that into account when computing operand latencies. 291def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign", 292 "true", 293 "Check for VLDn unaligned access">; 294 295// Some processors have a nonpipelined VFP coprocessor. 296def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp", 297 "NonpipelinedVFP", "true", 298 "VFP instructions are not pipelined">; 299 300// Some processors have FP multiply-accumulate instructions that don't 301// play nicely with other VFP / NEON instructions, and it's generally better 302// to just not use them. 303def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 304 "Disable VFP / NEON MAC instructions">; 305 306// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 307def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 308 "HasVMLxForwarding", "true", 309 "Has multiplier accumulator forwarding">; 310 311// Disable 32-bit to 16-bit narrowing for experimentation. 312def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 313 "Prefer 32-bit Thumb instrs">; 314 315def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopAlignment","2", 316 "Prefer 32-bit alignment for loops">; 317 318/// Some instructions update CPSR partially, which can add false dependency for 319/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 320/// mapped to a separate physical register. Avoid partial CPSR update for these 321/// processors. 322def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 323 "AvoidCPSRPartialUpdate", "true", 324 "Avoid CPSR partial update for OOO execution">; 325 326/// Disable +1 predication cost for instructions updating CPSR. 327/// Enabled for Cortex-A57. 328def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr", 329 "CheapPredicableCPSRDef", 330 "true", 331 "Disable +1 predication cost for instructions updating CPSR">; 332 333def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 334 "AvoidMOVsShifterOperand", "true", 335 "Avoid movs instructions with " 336 "shifter operand">; 337 338// Some processors perform return stack prediction. CodeGen should avoid issue 339// "normal" call instructions to callees which do not return. 340def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", 341 "HasRetAddrStack", "true", 342 "Has return address stack">; 343 344// Some processors have no branch predictor, which changes the expected cost of 345// taking a branch which affects the choice of whether to use predicated 346// instructions. 347def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor", 348 "HasBranchPredictor", "false", 349 "Has no branch predictor">; 350 351/// DSP extension. 352def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", 353 "Supports DSP instructions in " 354 "ARM and/or Thumb2">; 355 356// Multiprocessing extension. 357def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 358 "Supports Multiprocessing extension">; 359 360// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 361def FeatureVirtualization : SubtargetFeature<"virtualization", 362 "HasVirtualization", "true", 363 "Supports Virtualization extension", 364 [FeatureHWDivThumb, FeatureHWDivARM]>; 365 366// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 367// See ARMInstrInfo.td for details. 368def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 369 "NaCl trap">; 370 371def FeatureStrictAlign : SubtargetFeature<"strict-align", 372 "StrictAlign", "true", 373 "Disallow all unaligned memory " 374 "access">; 375 376def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", 377 "Generate calls via indirect call " 378 "instructions">; 379 380def FeatureExecuteOnly : SubtargetFeature<"execute-only", 381 "GenExecuteOnly", "true", 382 "Enable the generation of " 383 "execute only code.">; 384 385def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", 386 "Reserve R9, making it unavailable" 387 " as GPR">; 388 389def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", 390 "Don't use movt/movw pairs for " 391 "32-bit imms">; 392 393def FeatureNoNegativeImmediates 394 : SubtargetFeature<"no-neg-immediates", 395 "NegativeImmediates", "false", 396 "Convert immediates and instructions " 397 "to their negated or complemented " 398 "equivalent when the immediate does " 399 "not fit in the encoding.">; 400 401// Use the MachineScheduler for instruction scheduling for the subtarget. 402def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true", 403 "Use the MachineScheduler">; 404 405def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler", 406 "DisablePostRAScheduler", "true", 407 "Don't schedule again after register allocation">; 408 409// Enable use of alias analysis during code generation 410def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", 411 "Use alias analysis during codegen">; 412 413// Armv8.5-A extensions 414 415def FeatureSB : SubtargetFeature<"sb", "HasSB", "true", 416 "Enable v8.5a Speculation Barrier" >; 417 418// Armv8.1-M extensions 419 420def FeatureLOB : SubtargetFeature<"lob", "HasLOB", "true", 421 "Enable Low Overhead Branch " 422 "extensions">; 423 424//===----------------------------------------------------------------------===// 425// ARM architecture class 426// 427 428// A-series ISA 429def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 430 "Is application profile ('A' series)">; 431 432// R-series ISA 433def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 434 "Is realtime profile ('R' series)">; 435 436// M-series ISA 437def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 438 "Is microcontroller profile ('M' series)">; 439 440 441def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 442 "Enable Thumb2 instructions">; 443 444def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 445 "Does not support ARM mode execution">; 446 447//===----------------------------------------------------------------------===// 448// ARM ISAa. 449// 450 451def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 452 "Support ARM v4T instructions">; 453 454def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 455 "Support ARM v5T instructions", 456 [HasV4TOps]>; 457 458def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 459 "Support ARM v5TE, v5TEj, and " 460 "v5TExp instructions", 461 [HasV5TOps]>; 462 463def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 464 "Support ARM v6 instructions", 465 [HasV5TEOps]>; 466 467def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 468 "Support ARM v6M instructions", 469 [HasV6Ops]>; 470 471def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", 472 "Support ARM v8M Baseline instructions", 473 [HasV6MOps]>; 474 475def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", 476 "Support ARM v6k instructions", 477 [HasV6Ops]>; 478 479def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 480 "Support ARM v6t2 instructions", 481 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; 482 483def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 484 "Support ARM v7 instructions", 485 [HasV6T2Ops, FeaturePerfMon, 486 FeatureV7Clrex]>; 487 488def HasV8MMainlineOps : 489 SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", 490 "Support ARM v8M Mainline instructions", 491 [HasV7Ops]>; 492 493def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 494 "Support ARM v8 instructions", 495 [HasV7Ops, FeatureAcquireRelease]>; 496 497def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 498 "Support ARM v8.1a instructions", 499 [HasV8Ops]>; 500 501def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 502 "Support ARM v8.2a instructions", 503 [HasV8_1aOps]>; 504 505def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 506 "Support ARM v8.3a instructions", 507 [HasV8_2aOps]>; 508 509def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 510 "Support ARM v8.4a instructions", 511 [HasV8_3aOps, FeatureDotProd]>; 512 513def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true", 514 "Support ARM v8.5a instructions", 515 [HasV8_4aOps, FeatureSB]>; 516 517def HasV8_1MMainlineOps : SubtargetFeature< 518 "v8.1m.main", "HasV8_1MMainlineOps", "true", 519 "Support ARM v8-1M Mainline instructions", 520 [HasV8MMainlineOps]>; 521def HasMVEIntegerOps : SubtargetFeature< 522 "mve", "HasMVEIntegerOps", "true", 523 "Support M-Class Vector Extension with integer ops", 524 [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>; 525def HasMVEFloatOps : SubtargetFeature< 526 "mve.fp", "HasMVEFloatOps", "true", 527 "Support M-Class Vector Extension with integer and floating ops", 528 [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>; 529 530//===----------------------------------------------------------------------===// 531// ARM Processor subtarget features. 532// 533 534def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 535 "Cortex-A5 ARM processors", []>; 536def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 537 "Cortex-A7 ARM processors", []>; 538def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 539 "Cortex-A8 ARM processors", []>; 540def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 541 "Cortex-A9 ARM processors", []>; 542def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 543 "Cortex-A12 ARM processors", []>; 544def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 545 "Cortex-A15 ARM processors", []>; 546def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", 547 "Cortex-A17 ARM processors", []>; 548def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", 549 "Cortex-A32 ARM processors", []>; 550def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 551 "Cortex-A35 ARM processors", []>; 552def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 553 "Cortex-A53 ARM processors", []>; 554def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 555 "Cortex-A55 ARM processors", []>; 556def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 557 "Cortex-A57 ARM processors", []>; 558def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 559 "Cortex-A72 ARM processors", []>; 560def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 561 "Cortex-A73 ARM processors", []>; 562def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 563 "Cortex-A75 ARM processors", []>; 564def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 565 "Cortex-A76 ARM processors", []>; 566 567def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 568 "Qualcomm Krait processors", []>; 569def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 570 "Qualcomm Kryo processors", []>; 571def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 572 "Swift ARM processors", []>; 573 574def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos", 575 "Samsung Exynos processors", 576 [FeatureZCZeroing, 577 FeatureUseWideStrideVFP, 578 FeatureUseAA, 579 FeatureSplatVFPToNeon, 580 FeatureSlowVGETLNi32, 581 FeatureSlowVDUP32, 582 FeatureSlowFPBrcc, 583 FeatureProfUnpredicate, 584 FeatureHWDivThumb, 585 FeatureHWDivARM, 586 FeatureHasSlowFPVMLx, 587 FeatureHasRetAddrStack, 588 FeatureFuseLiterals, 589 FeatureFuseAES, 590 FeatureExpandMLx, 591 FeatureCrypto, 592 FeatureCRC]>; 593 594def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", 595 "Cortex-R4 ARM processors", []>; 596def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 597 "Cortex-R5 ARM processors", []>; 598def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", 599 "Cortex-R7 ARM processors", []>; 600def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", 601 "Cortex-R52 ARM processors", []>; 602 603def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", 604 "Cortex-M3 ARM processors", []>; 605 606 607//===----------------------------------------------------------------------===// 608// ARM Helper classes. 609// 610 611class Architecture<string fname, string aname, list<SubtargetFeature> features> 612 : SubtargetFeature<fname, "ARMArch", aname, 613 !strconcat(aname, " architecture"), features>; 614 615class ProcNoItin<string Name, list<SubtargetFeature> Features> 616 : Processor<Name, NoItineraries, Features>; 617 618 619//===----------------------------------------------------------------------===// 620// ARM architectures 621// 622 623def ARMv2 : Architecture<"armv2", "ARMv2", []>; 624 625def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; 626 627def ARMv3 : Architecture<"armv3", "ARMv3", []>; 628 629def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; 630 631def ARMv4 : Architecture<"armv4", "ARMv4", []>; 632 633def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; 634 635def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; 636 637def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; 638 639def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; 640 641def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops, 642 FeatureDSP]>; 643 644def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, 645 FeatureDSP]>; 646 647def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; 648 649def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, 650 FeatureTrustZone]>; 651 652def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, 653 FeatureNoARM, 654 ModeThumb, 655 FeatureDB, 656 FeatureMClass, 657 FeatureStrictAlign]>; 658 659def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, 660 FeatureNoARM, 661 ModeThumb, 662 FeatureDB, 663 FeatureMClass, 664 FeatureStrictAlign]>; 665 666def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, 667 FeatureNEON, 668 FeatureDB, 669 FeatureDSP, 670 FeatureAClass]>; 671 672def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops, 673 FeatureNEON, 674 FeatureDB, 675 FeatureDSP, 676 FeatureTrustZone, 677 FeatureMP, 678 FeatureVirtualization, 679 FeatureAClass]>; 680 681def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, 682 FeatureDB, 683 FeatureDSP, 684 FeatureHWDivThumb, 685 FeatureRClass]>; 686 687def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, 688 FeatureThumb2, 689 FeatureNoARM, 690 ModeThumb, 691 FeatureDB, 692 FeatureHWDivThumb, 693 FeatureMClass]>; 694 695def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, 696 FeatureThumb2, 697 FeatureNoARM, 698 ModeThumb, 699 FeatureDB, 700 FeatureHWDivThumb, 701 FeatureMClass, 702 FeatureDSP]>; 703 704def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, 705 FeatureAClass, 706 FeatureDB, 707 FeatureFPARMv8, 708 FeatureNEON, 709 FeatureDSP, 710 FeatureTrustZone, 711 FeatureMP, 712 FeatureVirtualization, 713 FeatureCrypto, 714 FeatureCRC]>; 715 716def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, 717 FeatureAClass, 718 FeatureDB, 719 FeatureFPARMv8, 720 FeatureNEON, 721 FeatureDSP, 722 FeatureTrustZone, 723 FeatureMP, 724 FeatureVirtualization, 725 FeatureCrypto, 726 FeatureCRC]>; 727 728def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, 729 FeatureAClass, 730 FeatureDB, 731 FeatureFPARMv8, 732 FeatureNEON, 733 FeatureDSP, 734 FeatureTrustZone, 735 FeatureMP, 736 FeatureVirtualization, 737 FeatureCrypto, 738 FeatureCRC, 739 FeatureRAS]>; 740 741def ARMv83a : Architecture<"armv8.3-a", "ARMv83a", [HasV8_3aOps, 742 FeatureAClass, 743 FeatureDB, 744 FeatureFPARMv8, 745 FeatureNEON, 746 FeatureDSP, 747 FeatureTrustZone, 748 FeatureMP, 749 FeatureVirtualization, 750 FeatureCrypto, 751 FeatureCRC, 752 FeatureRAS]>; 753 754def ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps, 755 FeatureAClass, 756 FeatureDB, 757 FeatureFPARMv8, 758 FeatureNEON, 759 FeatureDSP, 760 FeatureTrustZone, 761 FeatureMP, 762 FeatureVirtualization, 763 FeatureCrypto, 764 FeatureCRC, 765 FeatureRAS, 766 FeatureDotProd]>; 767 768def ARMv85a : Architecture<"armv8.5-a", "ARMv85a", [HasV8_5aOps, 769 FeatureAClass, 770 FeatureDB, 771 FeatureFPARMv8, 772 FeatureNEON, 773 FeatureDSP, 774 FeatureTrustZone, 775 FeatureMP, 776 FeatureVirtualization, 777 FeatureCrypto, 778 FeatureCRC, 779 FeatureRAS, 780 FeatureDotProd]>; 781 782def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, 783 FeatureRClass, 784 FeatureDB, 785 FeatureDFB, 786 FeatureDSP, 787 FeatureCRC, 788 FeatureMP, 789 FeatureVirtualization, 790 FeatureFPARMv8, 791 FeatureNEON]>; 792 793def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", 794 [HasV8MBaselineOps, 795 FeatureNoARM, 796 ModeThumb, 797 FeatureDB, 798 FeatureHWDivThumb, 799 FeatureV7Clrex, 800 Feature8MSecExt, 801 FeatureAcquireRelease, 802 FeatureMClass, 803 FeatureStrictAlign]>; 804 805def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", 806 [HasV8MMainlineOps, 807 FeatureNoARM, 808 ModeThumb, 809 FeatureDB, 810 FeatureHWDivThumb, 811 Feature8MSecExt, 812 FeatureAcquireRelease, 813 FeatureMClass]>; 814 815def ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline", 816 [HasV8_1MMainlineOps, 817 FeatureNoARM, 818 ModeThumb, 819 FeatureDB, 820 FeatureHWDivThumb, 821 Feature8MSecExt, 822 FeatureAcquireRelease, 823 FeatureMClass, 824 FeatureRAS, 825 FeatureLOB]>; 826 827// Aliases 828def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; 829def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; 830def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; 831def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; 832def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; 833def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; 834 835 836//===----------------------------------------------------------------------===// 837// ARM schedules. 838//===----------------------------------------------------------------------===// 839// 840include "ARMPredicates.td" 841include "ARMSchedule.td" 842 843//===----------------------------------------------------------------------===// 844// ARM processors 845// 846 847// Dummy CPU, used to target architectures 848def : ProcessorModel<"generic", CortexA8Model, []>; 849 850// FIXME: Several processors below are not using their own scheduler 851// model, but one of similar/previous processor. These should be fixed. 852 853def : ProcNoItin<"arm8", [ARMv4]>; 854def : ProcNoItin<"arm810", [ARMv4]>; 855def : ProcNoItin<"strongarm", [ARMv4]>; 856def : ProcNoItin<"strongarm110", [ARMv4]>; 857def : ProcNoItin<"strongarm1100", [ARMv4]>; 858def : ProcNoItin<"strongarm1110", [ARMv4]>; 859 860def : ProcNoItin<"arm7tdmi", [ARMv4t]>; 861def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; 862def : ProcNoItin<"arm710t", [ARMv4t]>; 863def : ProcNoItin<"arm720t", [ARMv4t]>; 864def : ProcNoItin<"arm9", [ARMv4t]>; 865def : ProcNoItin<"arm9tdmi", [ARMv4t]>; 866def : ProcNoItin<"arm920", [ARMv4t]>; 867def : ProcNoItin<"arm920t", [ARMv4t]>; 868def : ProcNoItin<"arm922t", [ARMv4t]>; 869def : ProcNoItin<"arm940t", [ARMv4t]>; 870def : ProcNoItin<"ep9312", [ARMv4t]>; 871 872def : ProcNoItin<"arm10tdmi", [ARMv5t]>; 873def : ProcNoItin<"arm1020t", [ARMv5t]>; 874 875def : ProcNoItin<"arm9e", [ARMv5te]>; 876def : ProcNoItin<"arm926ej-s", [ARMv5te]>; 877def : ProcNoItin<"arm946e-s", [ARMv5te]>; 878def : ProcNoItin<"arm966e-s", [ARMv5te]>; 879def : ProcNoItin<"arm968e-s", [ARMv5te]>; 880def : ProcNoItin<"arm10e", [ARMv5te]>; 881def : ProcNoItin<"arm1020e", [ARMv5te]>; 882def : ProcNoItin<"arm1022e", [ARMv5te]>; 883def : ProcNoItin<"xscale", [ARMv5te]>; 884def : ProcNoItin<"iwmmxt", [ARMv5te]>; 885 886def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; 887def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, 888 FeatureVFP2, 889 FeatureHasSlowFPVMLx]>; 890 891def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>; 892def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>; 893def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>; 894def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>; 895 896def : Processor<"arm1176j-s", ARMV6Itineraries, [ARMv6kz]>; 897def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; 898def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, 899 FeatureVFP2, 900 FeatureHasSlowFPVMLx]>; 901 902def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; 903def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, 904 FeatureVFP2, 905 FeatureHasSlowFPVMLx]>; 906 907def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; 908def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, 909 FeatureVFP2, 910 FeatureHasSlowFPVMLx]>; 911 912def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, 913 FeatureHasRetAddrStack, 914 FeatureTrustZone, 915 FeatureSlowFPBrcc, 916 FeatureHasSlowFPVMLx, 917 FeatureVMLxForwarding, 918 FeatureMP, 919 FeatureVFP4]>; 920 921def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, 922 FeatureHasRetAddrStack, 923 FeatureTrustZone, 924 FeatureSlowFPBrcc, 925 FeatureHasVMLxHazards, 926 FeatureHasSlowFPVMLx, 927 FeatureVMLxForwarding, 928 FeatureMP, 929 FeatureVFP4, 930 FeatureVirtualization]>; 931 932def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, 933 FeatureHasRetAddrStack, 934 FeatureNonpipelinedVFP, 935 FeatureTrustZone, 936 FeatureSlowFPBrcc, 937 FeatureHasVMLxHazards, 938 FeatureHasSlowFPVMLx, 939 FeatureVMLxForwarding]>; 940 941def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, 942 FeatureHasRetAddrStack, 943 FeatureTrustZone, 944 FeatureHasVMLxHazards, 945 FeatureVMLxForwarding, 946 FeatureFP16, 947 FeatureAvoidPartialCPSR, 948 FeatureExpandMLx, 949 FeaturePreferVMOVSR, 950 FeatureMuxedUnits, 951 FeatureNEONForFPMovs, 952 FeatureCheckVLDnAlign, 953 FeatureMP]>; 954 955def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, 956 FeatureHasRetAddrStack, 957 FeatureTrustZone, 958 FeatureVMLxForwarding, 959 FeatureVFP4, 960 FeatureAvoidPartialCPSR, 961 FeatureVirtualization, 962 FeatureMP]>; 963 964def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, 965 FeatureDontWidenVMOVS, 966 FeatureSplatVFPToNeon, 967 FeatureHasRetAddrStack, 968 FeatureMuxedUnits, 969 FeatureTrustZone, 970 FeatureVFP4, 971 FeatureMP, 972 FeatureCheckVLDnAlign, 973 FeatureAvoidPartialCPSR, 974 FeatureVirtualization]>; 975 976def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, 977 FeatureHasRetAddrStack, 978 FeatureTrustZone, 979 FeatureMP, 980 FeatureVMLxForwarding, 981 FeatureVFP4, 982 FeatureAvoidPartialCPSR, 983 FeatureVirtualization]>; 984 985// FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv 986def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, 987 FeatureHasRetAddrStack, 988 FeatureMuxedUnits, 989 FeatureCheckVLDnAlign, 990 FeatureVMLxForwarding, 991 FeatureFP16, 992 FeatureAvoidPartialCPSR, 993 FeatureVFP4, 994 FeatureHWDivThumb, 995 FeatureHWDivARM]>; 996 997def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, 998 FeatureHasRetAddrStack, 999 FeatureNEONForFP, 1000 FeatureVFP4, 1001 FeatureUseWideStrideVFP, 1002 FeatureMP, 1003 FeatureHWDivThumb, 1004 FeatureHWDivARM, 1005 FeatureAvoidPartialCPSR, 1006 FeatureAvoidMOVsShOp, 1007 FeatureHasSlowFPVMLx, 1008 FeatureHasVMLxHazards, 1009 FeatureProfUnpredicate, 1010 FeaturePrefISHSTBarrier, 1011 FeatureSlowOddRegister, 1012 FeatureSlowLoadDSubreg, 1013 FeatureSlowVGETLNi32, 1014 FeatureSlowVDUP32, 1015 FeatureUseMISched, 1016 FeatureNoPostRASched]>; 1017 1018def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, 1019 FeatureHasRetAddrStack, 1020 FeatureAvoidPartialCPSR]>; 1021 1022def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, 1023 FeatureHasRetAddrStack, 1024 FeatureSlowFPBrcc, 1025 FeatureHasSlowFPVMLx, 1026 FeatureVFP3_D16, 1027 FeatureAvoidPartialCPSR]>; 1028 1029def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, 1030 FeatureHasRetAddrStack, 1031 FeatureVFP3_D16, 1032 FeatureSlowFPBrcc, 1033 FeatureHWDivARM, 1034 FeatureHasSlowFPVMLx, 1035 FeatureAvoidPartialCPSR]>; 1036 1037def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, 1038 FeatureHasRetAddrStack, 1039 FeatureVFP3_D16, 1040 FeatureFP16, 1041 FeatureMP, 1042 FeatureSlowFPBrcc, 1043 FeatureHWDivARM, 1044 FeatureHasSlowFPVMLx, 1045 FeatureAvoidPartialCPSR]>; 1046 1047def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, 1048 FeatureHasRetAddrStack, 1049 FeatureVFP3_D16, 1050 FeatureFP16, 1051 FeatureMP, 1052 FeatureSlowFPBrcc, 1053 FeatureHWDivARM, 1054 FeatureHasSlowFPVMLx, 1055 FeatureAvoidPartialCPSR]>; 1056 1057def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m, 1058 ProcM3, 1059 FeaturePrefLoopAlign32, 1060 FeatureUseMISched, 1061 FeatureUseAA, 1062 FeatureHasNoBranchPredictor]>; 1063 1064def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m, 1065 ProcM3, 1066 FeatureUseMISched, 1067 FeatureUseAA, 1068 FeatureHasNoBranchPredictor]>; 1069 1070def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em, 1071 FeatureVFP4_D16_SP, 1072 FeaturePrefLoopAlign32, 1073 FeatureHasSlowFPVMLx, 1074 FeatureUseMISched, 1075 FeatureUseAA, 1076 FeatureHasNoBranchPredictor]>; 1077 1078def : ProcNoItin<"cortex-m7", [ARMv7em, 1079 FeatureFPARMv8_D16]>; 1080 1081def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, 1082 FeatureNoMovt]>; 1083 1084def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline, 1085 FeatureDSP, 1086 FeatureFPARMv8_D16_SP, 1087 FeaturePrefLoopAlign32, 1088 FeatureHasSlowFPVMLx, 1089 FeatureUseMISched, 1090 FeatureUseAA, 1091 FeatureHasNoBranchPredictor]>; 1092 1093def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline, 1094 FeatureDSP, 1095 FeatureFPARMv8_D16_SP, 1096 FeaturePrefLoopAlign32, 1097 FeatureHasSlowFPVMLx, 1098 FeatureUseMISched, 1099 FeatureUseAA, 1100 FeatureHasNoBranchPredictor]>; 1101 1102 1103def : ProcNoItin<"cortex-a32", [ARMv8a, 1104 FeatureHWDivThumb, 1105 FeatureHWDivARM, 1106 FeatureCrypto, 1107 FeatureCRC]>; 1108 1109def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, 1110 FeatureHWDivThumb, 1111 FeatureHWDivARM, 1112 FeatureCrypto, 1113 FeatureCRC]>; 1114 1115def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, 1116 FeatureHWDivThumb, 1117 FeatureHWDivARM, 1118 FeatureCrypto, 1119 FeatureCRC, 1120 FeatureFPAO]>; 1121 1122def : ProcNoItin<"cortex-a55", [ARMv82a, ProcA55, 1123 FeatureHWDivThumb, 1124 FeatureHWDivARM, 1125 FeatureDotProd]>; 1126 1127def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57, 1128 FeatureHWDivThumb, 1129 FeatureHWDivARM, 1130 FeatureCrypto, 1131 FeatureCRC, 1132 FeatureFPAO, 1133 FeatureAvoidPartialCPSR, 1134 FeatureCheapPredicableCPSR]>; 1135 1136def : ProcessorModel<"cortex-a72", CortexA57Model, [ARMv8a, ProcA72, 1137 FeatureHWDivThumb, 1138 FeatureHWDivARM, 1139 FeatureCrypto, 1140 FeatureCRC]>; 1141 1142def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, 1143 FeatureHWDivThumb, 1144 FeatureHWDivARM, 1145 FeatureCrypto, 1146 FeatureCRC]>; 1147 1148def : ProcNoItin<"cortex-a75", [ARMv82a, ProcA75, 1149 FeatureHWDivThumb, 1150 FeatureHWDivARM, 1151 FeatureDotProd]>; 1152 1153def : ProcNoItin<"cortex-a76", [ARMv82a, ProcA76, 1154 FeatureHWDivThumb, 1155 FeatureHWDivARM, 1156 FeatureCrypto, 1157 FeatureCRC, 1158 FeatureFullFP16, 1159 FeatureDotProd]>; 1160 1161def : ProcNoItin<"cortex-a76ae", [ARMv82a, ProcA76, 1162 FeatureHWDivThumb, 1163 FeatureHWDivARM, 1164 FeatureCrypto, 1165 FeatureCRC, 1166 FeatureFullFP16, 1167 FeatureDotProd]>; 1168 1169def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, 1170 FeatureHasRetAddrStack, 1171 FeatureNEONForFP, 1172 FeatureVFP4, 1173 FeatureMP, 1174 FeatureHWDivThumb, 1175 FeatureHWDivARM, 1176 FeatureAvoidPartialCPSR, 1177 FeatureAvoidMOVsShOp, 1178 FeatureHasSlowFPVMLx, 1179 FeatureCrypto, 1180 FeatureUseMISched, 1181 FeatureZCZeroing, 1182 FeatureNoPostRASched]>; 1183 1184def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynos]>; 1185def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynos]>; 1186def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynos]>; 1187def : ProcNoItin<"exynos-m4", [ARMv82a, ProcExynos, 1188 FeatureFullFP16, 1189 FeatureDotProd]>; 1190def : ProcNoItin<"exynos-m5", [ARMv82a, ProcExynos, 1191 FeatureFullFP16, 1192 FeatureDotProd]>; 1193 1194def : ProcNoItin<"kryo", [ARMv8a, ProcKryo, 1195 FeatureHWDivThumb, 1196 FeatureHWDivARM, 1197 FeatureCrypto, 1198 FeatureCRC]>; 1199 1200def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, 1201 FeatureUseMISched, 1202 FeatureFPAO, 1203 FeatureUseAA]>; 1204 1205//===----------------------------------------------------------------------===// 1206// Register File Description 1207//===----------------------------------------------------------------------===// 1208 1209include "ARMRegisterInfo.td" 1210include "ARMRegisterBanks.td" 1211include "ARMCallingConv.td" 1212 1213//===----------------------------------------------------------------------===// 1214// Instruction Descriptions 1215//===----------------------------------------------------------------------===// 1216 1217include "ARMInstrInfo.td" 1218def ARMInstrInfo : InstrInfo; 1219 1220//===----------------------------------------------------------------------===// 1221// Declare the target which we are implementing 1222//===----------------------------------------------------------------------===// 1223 1224def ARMAsmWriter : AsmWriter { 1225 string AsmWriterClassName = "InstPrinter"; 1226 int PassSubtarget = 1; 1227 int Variant = 0; 1228 bit isMCAsmWriter = 1; 1229} 1230 1231def ARMAsmParser : AsmParser { 1232 bit ReportMultipleNearMisses = 1; 1233} 1234 1235def ARMAsmParserVariant : AsmParserVariant { 1236 int Variant = 0; 1237 string Name = "ARM"; 1238 string BreakCharacters = "."; 1239} 1240 1241def ARM : Target { 1242 // Pull in Instruction Info. 1243 let InstructionSet = ARMInstrInfo; 1244 let AssemblyWriters = [ARMAsmWriter]; 1245 let AssemblyParsers = [ARMAsmParser]; 1246 let AssemblyParserVariants = [ARMAsmParserVariant]; 1247 let AllowRegisterRenaming = 1; 1248} 1249