10b57cec5SDimitry Andric//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// 100b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 110b57cec5SDimitry Andric 120b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric// Target-independent interfaces which we are implementing 140b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 150b57cec5SDimitry Andric 160b57cec5SDimitry Andricinclude "llvm/Target/Target.td" 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 190b57cec5SDimitry Andric// ARM Subtarget state. 200b57cec5SDimitry Andric// 210b57cec5SDimitry Andric 220b57cec5SDimitry Andricdef ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", 230b57cec5SDimitry Andric "true", "Thumb mode">; 240b57cec5SDimitry Andric 250b57cec5SDimitry Andricdef ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat", 260b57cec5SDimitry Andric "true", "Use software floating " 270b57cec5SDimitry Andric "point features.">; 280b57cec5SDimitry Andric 290b57cec5SDimitry Andric 300b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 310b57cec5SDimitry Andric// ARM Subtarget features. 320b57cec5SDimitry Andric// 330b57cec5SDimitry Andric 340b57cec5SDimitry Andric// Floating Point, HW Division and Neon Support 350b57cec5SDimitry Andric 360b57cec5SDimitry Andric// FP loads/stores/moves, shared between VFP and MVE (even in the integer-only 370b57cec5SDimitry Andric// version). 380b57cec5SDimitry Andricdef FeatureFPRegs : SubtargetFeature<"fpregs", "HasFPRegs", "true", 390b57cec5SDimitry Andric "Enable FP registers">; 400b57cec5SDimitry Andric 410b57cec5SDimitry Andric// 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16 420b57cec5SDimitry Andric// extension) and MVE (even in the integer-only version). 430b57cec5SDimitry Andricdef FeatureFPRegs16 : SubtargetFeature<"fpregs16", "HasFPRegs16", "true", 440b57cec5SDimitry Andric "Enable 16-bit FP registers", 450b57cec5SDimitry Andric [FeatureFPRegs]>; 460b57cec5SDimitry Andric 470b57cec5SDimitry Andricdef FeatureFPRegs64 : SubtargetFeature<"fpregs64", "HasFPRegs64", "true", 480b57cec5SDimitry Andric "Enable 64-bit FP registers", 490b57cec5SDimitry Andric [FeatureFPRegs]>; 500b57cec5SDimitry Andric 510b57cec5SDimitry Andricdef FeatureFP64 : SubtargetFeature<"fp64", "HasFP64", "true", 520b57cec5SDimitry Andric "Floating point unit supports " 530b57cec5SDimitry Andric "double precision", 540b57cec5SDimitry Andric [FeatureFPRegs64]>; 550b57cec5SDimitry Andric 560b57cec5SDimitry Andricdef FeatureD32 : SubtargetFeature<"d32", "HasD32", "true", 570b57cec5SDimitry Andric "Extend FP to 32 double registers">; 580b57cec5SDimitry Andric 590b57cec5SDimitry Andricmulticlass VFPver<string name, string query, string description, 600b57cec5SDimitry Andric list<SubtargetFeature> prev, 610b57cec5SDimitry Andric list<SubtargetFeature> otherimplies, 620b57cec5SDimitry Andric list<SubtargetFeature> vfp2prev = []> { 630b57cec5SDimitry Andric def _D16_SP: SubtargetFeature< 640b57cec5SDimitry Andric name#"d16sp", query#"D16SP", "true", 650b57cec5SDimitry Andric description#" with only 16 d-registers and no double precision", 660b57cec5SDimitry Andric !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) # 670b57cec5SDimitry Andric !foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) # 680b57cec5SDimitry Andric otherimplies>; 690b57cec5SDimitry Andric def _SP: SubtargetFeature< 700b57cec5SDimitry Andric name#"sp", query#"SP", "true", 710b57cec5SDimitry Andric description#" with no double precision", 720b57cec5SDimitry Andric !foreach(v, prev, !cast<SubtargetFeature>(v # "_SP")) # 730b57cec5SDimitry Andric otherimplies # [FeatureD32, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; 740b57cec5SDimitry Andric def _D16: SubtargetFeature< 750b57cec5SDimitry Andric name#"d16", query#"D16", "true", 760b57cec5SDimitry Andric description#" with only 16 d-registers", 770b57cec5SDimitry Andric !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) # 780b57cec5SDimitry Andric vfp2prev # 790b57cec5SDimitry Andric otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; 800b57cec5SDimitry Andric def "": SubtargetFeature< 810b57cec5SDimitry Andric name, query, "true", description, 820b57cec5SDimitry Andric prev # otherimplies # [ 830b57cec5SDimitry Andric !cast<SubtargetFeature>(NAME # "_D16"), 840b57cec5SDimitry Andric !cast<SubtargetFeature>(NAME # "_SP")]>; 850b57cec5SDimitry Andric} 860b57cec5SDimitry Andric 87c14a5a88SDimitry Andricdef FeatureVFP2_SP : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true", 88c14a5a88SDimitry Andric "Enable VFP2 instructions with " 89c14a5a88SDimitry Andric "no double precision", 908bcb0991SDimitry Andric [FeatureFPRegs]>; 918bcb0991SDimitry Andric 920b57cec5SDimitry Andricdef FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 930b57cec5SDimitry Andric "Enable VFP2 instructions", 948bcb0991SDimitry Andric [FeatureFP64, FeatureVFP2_SP]>; 950b57cec5SDimitry Andric 960b57cec5SDimitry Andricdefm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions", 970b57cec5SDimitry Andric [], [], [FeatureVFP2]>; 980b57cec5SDimitry Andric 990b57cec5SDimitry Andricdef FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 1000b57cec5SDimitry Andric "Enable NEON instructions", 1010b57cec5SDimitry Andric [FeatureVFP3]>; 1020b57cec5SDimitry Andric 1030b57cec5SDimitry Andricdef FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 1040b57cec5SDimitry Andric "Enable half-precision " 1050b57cec5SDimitry Andric "floating point">; 1060b57cec5SDimitry Andric 1070b57cec5SDimitry Andricdefm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions", 1080b57cec5SDimitry Andric [FeatureVFP3], [FeatureFP16]>; 1090b57cec5SDimitry Andric 1100b57cec5SDimitry Andricdefm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP", 1110b57cec5SDimitry Andric [FeatureVFP4], []>; 1120b57cec5SDimitry Andric 1130b57cec5SDimitry Andricdef FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 1140b57cec5SDimitry Andric "Enable full half-precision " 1150b57cec5SDimitry Andric "floating point", 1160b57cec5SDimitry Andric [FeatureFPARMv8_D16_SP, FeatureFPRegs16]>; 1170b57cec5SDimitry Andric 1180b57cec5SDimitry Andricdef FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 1190b57cec5SDimitry Andric "Enable full half-precision " 1200b57cec5SDimitry Andric "floating point fml instructions", 1210b57cec5SDimitry Andric [FeatureFullFP16]>; 1220b57cec5SDimitry Andric 1230b57cec5SDimitry Andricdef FeatureHWDivThumb : SubtargetFeature<"hwdiv", 1240b57cec5SDimitry Andric "HasHardwareDivideInThumb", "true", 1250b57cec5SDimitry Andric "Enable divide instructions in Thumb">; 1260b57cec5SDimitry Andric 1270b57cec5SDimitry Andricdef FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 1280b57cec5SDimitry Andric "HasHardwareDivideInARM", "true", 1290b57cec5SDimitry Andric "Enable divide instructions in ARM mode">; 1300b57cec5SDimitry Andric 1310b57cec5SDimitry Andric// Atomic Support 1320b57cec5SDimitry Andricdef FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 1330b57cec5SDimitry Andric "Has data barrier (dmb/dsb) instructions">; 1340b57cec5SDimitry Andric 1350b57cec5SDimitry Andricdef FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", 1360b57cec5SDimitry Andric "Has v7 clrex instruction">; 1370b57cec5SDimitry Andric 1380b57cec5SDimitry Andricdef FeatureDFB : SubtargetFeature<"dfb", "HasFullDataBarrier", "true", 1390b57cec5SDimitry Andric "Has full data barrier (dfb) instruction">; 1400b57cec5SDimitry Andric 1410b57cec5SDimitry Andricdef FeatureAcquireRelease : SubtargetFeature<"acquire-release", 1420b57cec5SDimitry Andric "HasAcquireRelease", "true", 1430b57cec5SDimitry Andric "Has v8 acquire/release (lda/ldaex " 1440b57cec5SDimitry Andric " etc) instructions">; 1450b57cec5SDimitry Andric 1460b57cec5SDimitry Andric 1470b57cec5SDimitry Andricdef FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 1480b57cec5SDimitry Andric "FP compare + branch is slow">; 1490b57cec5SDimitry Andric 1500b57cec5SDimitry Andricdef FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 1510b57cec5SDimitry Andric "Enable support for Performance " 1520b57cec5SDimitry Andric "Monitor extensions">; 1530b57cec5SDimitry Andric 1540b57cec5SDimitry Andric 1550b57cec5SDimitry Andric// TrustZone Security Extensions 1560b57cec5SDimitry Andricdef FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 1570b57cec5SDimitry Andric "Enable support for TrustZone " 1580b57cec5SDimitry Andric "security extensions">; 1590b57cec5SDimitry Andric 1600b57cec5SDimitry Andricdef Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", 1610b57cec5SDimitry Andric "Enable support for ARMv8-M " 1620b57cec5SDimitry Andric "Security Extensions">; 1630b57cec5SDimitry Andric 1640b57cec5SDimitry Andricdef FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true", 1650b57cec5SDimitry Andric "Enable SHA1 and SHA256 support", [FeatureNEON]>; 1660b57cec5SDimitry Andric 1670b57cec5SDimitry Andricdef FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 1680b57cec5SDimitry Andric "Enable AES support", [FeatureNEON]>; 1690b57cec5SDimitry Andric 1700b57cec5SDimitry Andricdef FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 1710b57cec5SDimitry Andric "Enable support for " 1720b57cec5SDimitry Andric "Cryptography extensions", 1730b57cec5SDimitry Andric [FeatureNEON, FeatureSHA2, FeatureAES]>; 1740b57cec5SDimitry Andric 1750b57cec5SDimitry Andricdef FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 1760b57cec5SDimitry Andric "Enable support for CRC instructions">; 1770b57cec5SDimitry Andric 1780b57cec5SDimitry Andricdef FeatureDotProd : SubtargetFeature<"dotprod", "HasDotProd", "true", 1790b57cec5SDimitry Andric "Enable support for dot product instructions", 1800b57cec5SDimitry Andric [FeatureNEON]>; 1810b57cec5SDimitry Andric 1820b57cec5SDimitry Andric// Not to be confused with FeatureHasRetAddrStack (return address stack) 1830b57cec5SDimitry Andricdef FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 1840b57cec5SDimitry Andric "Enable Reliability, Availability " 1850b57cec5SDimitry Andric "and Serviceability extensions">; 1860b57cec5SDimitry Andric 1870b57cec5SDimitry Andric// Fast computation of non-negative address offsets 1880b57cec5SDimitry Andricdef FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true", 1890b57cec5SDimitry Andric "Enable fast computation of " 1900b57cec5SDimitry Andric "positive address offsets">; 1910b57cec5SDimitry Andric 1920b57cec5SDimitry Andric// Fast execution of AES crypto operations 1930b57cec5SDimitry Andricdef FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true", 1940b57cec5SDimitry Andric "CPU fuses AES crypto operations">; 1950b57cec5SDimitry Andric 1960b57cec5SDimitry Andric// Fast execution of bottom and top halves of literal generation 1970b57cec5SDimitry Andricdef FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true", 1980b57cec5SDimitry Andric "CPU fuses literal generation operations">; 1990b57cec5SDimitry Andric 2000b57cec5SDimitry Andric// The way of reading thread pointer 2010b57cec5SDimitry Andricdef FeatureReadTp : SubtargetFeature<"read-tp-hard", "ReadTPHard", "true", 2020b57cec5SDimitry Andric "Reading thread pointer from register">; 2030b57cec5SDimitry Andric 2040b57cec5SDimitry Andric// Cyclone can zero VFP registers in 0 cycles. 2050b57cec5SDimitry Andricdef FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 2060b57cec5SDimitry Andric "Has zero-cycle zeroing instructions">; 2070b57cec5SDimitry Andric 2080b57cec5SDimitry Andric// Whether it is profitable to unpredicate certain instructions during if-conversion 2090b57cec5SDimitry Andricdef FeatureProfUnpredicate : SubtargetFeature<"prof-unpr", 2100b57cec5SDimitry Andric "IsProfitableToUnpredicate", "true", 2110b57cec5SDimitry Andric "Is profitable to unpredicate">; 2120b57cec5SDimitry Andric 2130b57cec5SDimitry Andric// Some targets (e.g. Swift) have microcoded VGETLNi32. 2140b57cec5SDimitry Andricdef FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32", 2150b57cec5SDimitry Andric "HasSlowVGETLNi32", "true", 2160b57cec5SDimitry Andric "Has slow VGETLNi32 - prefer VMOV">; 2170b57cec5SDimitry Andric 2180b57cec5SDimitry Andric// Some targets (e.g. Swift) have microcoded VDUP32. 2190b57cec5SDimitry Andricdef FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", 2200b57cec5SDimitry Andric "true", 2210b57cec5SDimitry Andric "Has slow VDUP32 - prefer VMOV">; 2220b57cec5SDimitry Andric 2230b57cec5SDimitry Andric// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON 2240b57cec5SDimitry Andric// for scalar FP, as this allows more effective execution domain optimization. 2250b57cec5SDimitry Andricdef FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR", 2260b57cec5SDimitry Andric "true", "Prefer VMOVSR">; 2270b57cec5SDimitry Andric 2280b57cec5SDimitry Andric// Swift has ISHST barriers compatible with Atomic Release semantics but weaker 2290b57cec5SDimitry Andric// than ISH 2300b57cec5SDimitry Andricdef FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST", 2310b57cec5SDimitry Andric "true", "Prefer ISHST barriers">; 2320b57cec5SDimitry Andric 2330b57cec5SDimitry Andric// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU. 2340b57cec5SDimitry Andricdef FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", 2350b57cec5SDimitry Andric "true", 2360b57cec5SDimitry Andric "Has muxed AGU and NEON/FPU">; 2370b57cec5SDimitry Andric 2380b57cec5SDimitry Andric// Whether VLDM/VSTM starting with odd register number need more microops 2390b57cec5SDimitry Andric// than single VLDRS 2400b57cec5SDimitry Andricdef FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister", 2410b57cec5SDimitry Andric "true", "VLDM/VSTM starting " 2420b57cec5SDimitry Andric "with an odd register is slow">; 2430b57cec5SDimitry Andric 2440b57cec5SDimitry Andric// Some targets have a renaming dependency when loading into D subregisters. 2450b57cec5SDimitry Andricdef FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg", 2460b57cec5SDimitry Andric "SlowLoadDSubregister", "true", 2470b57cec5SDimitry Andric "Loading into D subregs is slow">; 2480b57cec5SDimitry Andric 2490b57cec5SDimitry Andricdef FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp", 2500b57cec5SDimitry Andric "UseWideStrideVFP", "true", 2510b57cec5SDimitry Andric "Use a wide stride when allocating VFP registers">; 2520b57cec5SDimitry Andric 2530b57cec5SDimitry Andric// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. 2540b57cec5SDimitry Andricdef FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", 2550b57cec5SDimitry Andric "DontWidenVMOVS", "true", 2560b57cec5SDimitry Andric "Don't widen VMOVS to VMOVD">; 2570b57cec5SDimitry Andric 2580b57cec5SDimitry Andric// Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different 2590b57cec5SDimitry Andric// VFP register widths. 2600b57cec5SDimitry Andricdef FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon", 2610b57cec5SDimitry Andric "SplatVFPToNeon", "true", 2620b57cec5SDimitry Andric "Splat register from VFP to NEON", 2630b57cec5SDimitry Andric [FeatureDontWidenVMOVS]>; 2640b57cec5SDimitry Andric 2650b57cec5SDimitry Andric// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions. 2660b57cec5SDimitry Andricdef FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", 2670b57cec5SDimitry Andric "ExpandMLx", "true", 2680b57cec5SDimitry Andric "Expand VFP/NEON MLA/MLS instructions">; 2690b57cec5SDimitry Andric 2700b57cec5SDimitry Andric// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS. 2710b57cec5SDimitry Andricdef FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards", 2720b57cec5SDimitry Andric "true", "Has VMLx hazards">; 2730b57cec5SDimitry Andric 2740b57cec5SDimitry Andric// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from 2750b57cec5SDimitry Andric// VFP to NEON, as an execution domain optimization. 2760b57cec5SDimitry Andricdef FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", 2770b57cec5SDimitry Andric "UseNEONForFPMovs", "true", 2780b57cec5SDimitry Andric "Convert VMOVSR, VMOVRS, " 2790b57cec5SDimitry Andric "VMOVS to NEON">; 2800b57cec5SDimitry Andric 2810b57cec5SDimitry Andric// Some processors benefit from using NEON instructions for scalar 2820b57cec5SDimitry Andric// single-precision FP operations. This affects instruction selection and should 2830b57cec5SDimitry Andric// only be enabled if the handling of denormals is not important. 2840b57cec5SDimitry Andricdef FeatureNEONForFP : SubtargetFeature<"neonfp", 2850b57cec5SDimitry Andric "UseNEONForSinglePrecisionFP", 2860b57cec5SDimitry Andric "true", 2870b57cec5SDimitry Andric "Use NEON for single precision FP">; 2880b57cec5SDimitry Andric 2890b57cec5SDimitry Andric// On some processors, VLDn instructions that access unaligned data take one 2900b57cec5SDimitry Andric// extra cycle. Take that into account when computing operand latencies. 2910b57cec5SDimitry Andricdef FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign", 2920b57cec5SDimitry Andric "true", 2930b57cec5SDimitry Andric "Check for VLDn unaligned access">; 2940b57cec5SDimitry Andric 2950b57cec5SDimitry Andric// Some processors have a nonpipelined VFP coprocessor. 2960b57cec5SDimitry Andricdef FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp", 2970b57cec5SDimitry Andric "NonpipelinedVFP", "true", 2980b57cec5SDimitry Andric "VFP instructions are not pipelined">; 2990b57cec5SDimitry Andric 3000b57cec5SDimitry Andric// Some processors have FP multiply-accumulate instructions that don't 3010b57cec5SDimitry Andric// play nicely with other VFP / NEON instructions, and it's generally better 3020b57cec5SDimitry Andric// to just not use them. 3030b57cec5SDimitry Andricdef FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 3040b57cec5SDimitry Andric "Disable VFP / NEON MAC instructions">; 3050b57cec5SDimitry Andric 306480093f4SDimitry Andric// VFPv4 added VFMA instructions that can similar be fast or slow. 307480093f4SDimitry Andricdef FeatureHasSlowFPVFMx : SubtargetFeature<"slowfpvfmx", "SlowFPVFMx", "true", 308480093f4SDimitry Andric "Disable VFP / NEON FMA instructions">; 309480093f4SDimitry Andric 3100b57cec5SDimitry Andric// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 3110b57cec5SDimitry Andricdef FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 3120b57cec5SDimitry Andric "HasVMLxForwarding", "true", 3130b57cec5SDimitry Andric "Has multiplier accumulator forwarding">; 3140b57cec5SDimitry Andric 3150b57cec5SDimitry Andric// Disable 32-bit to 16-bit narrowing for experimentation. 3160b57cec5SDimitry Andricdef FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 3170b57cec5SDimitry Andric "Prefer 32-bit Thumb instrs">; 3180b57cec5SDimitry Andric 3198bcb0991SDimitry Andricdef FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopLogAlignment","2", 3200b57cec5SDimitry Andric "Prefer 32-bit alignment for loops">; 3210b57cec5SDimitry Andric 3228bcb0991SDimitry Andricdef FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "1", 3238bcb0991SDimitry Andric "Model MVE instructions as a 1 beat per tick architecture">; 3248bcb0991SDimitry Andric 3258bcb0991SDimitry Andricdef FeatureMVEVectorCostFactor2 : SubtargetFeature<"mve2beat", "MVEVectorCostFactor", "2", 3268bcb0991SDimitry Andric "Model MVE instructions as a 2 beats per tick architecture">; 3278bcb0991SDimitry Andric 3288bcb0991SDimitry Andricdef FeatureMVEVectorCostFactor4 : SubtargetFeature<"mve4beat", "MVEVectorCostFactor", "4", 3298bcb0991SDimitry Andric "Model MVE instructions as a 4 beats per tick architecture">; 3308bcb0991SDimitry Andric 3310b57cec5SDimitry Andric/// Some instructions update CPSR partially, which can add false dependency for 3320b57cec5SDimitry Andric/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 3330b57cec5SDimitry Andric/// mapped to a separate physical register. Avoid partial CPSR update for these 3340b57cec5SDimitry Andric/// processors. 3350b57cec5SDimitry Andricdef FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 3360b57cec5SDimitry Andric "AvoidCPSRPartialUpdate", "true", 3370b57cec5SDimitry Andric "Avoid CPSR partial update for OOO execution">; 3380b57cec5SDimitry Andric 3390b57cec5SDimitry Andric/// Disable +1 predication cost for instructions updating CPSR. 3400b57cec5SDimitry Andric/// Enabled for Cortex-A57. 3410b57cec5SDimitry Andricdef FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr", 3420b57cec5SDimitry Andric "CheapPredicableCPSRDef", 3430b57cec5SDimitry Andric "true", 3440b57cec5SDimitry Andric "Disable +1 predication cost for instructions updating CPSR">; 3450b57cec5SDimitry Andric 3460b57cec5SDimitry Andricdef FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 3470b57cec5SDimitry Andric "AvoidMOVsShifterOperand", "true", 3480b57cec5SDimitry Andric "Avoid movs instructions with " 3490b57cec5SDimitry Andric "shifter operand">; 3500b57cec5SDimitry Andric 3510b57cec5SDimitry Andric// Some processors perform return stack prediction. CodeGen should avoid issue 3520b57cec5SDimitry Andric// "normal" call instructions to callees which do not return. 3530b57cec5SDimitry Andricdef FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", 3540b57cec5SDimitry Andric "HasRetAddrStack", "true", 3550b57cec5SDimitry Andric "Has return address stack">; 3560b57cec5SDimitry Andric 3570b57cec5SDimitry Andric// Some processors have no branch predictor, which changes the expected cost of 3580b57cec5SDimitry Andric// taking a branch which affects the choice of whether to use predicated 3590b57cec5SDimitry Andric// instructions. 3600b57cec5SDimitry Andricdef FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor", 3610b57cec5SDimitry Andric "HasBranchPredictor", "false", 3620b57cec5SDimitry Andric "Has no branch predictor">; 3630b57cec5SDimitry Andric 3640b57cec5SDimitry Andric/// DSP extension. 3650b57cec5SDimitry Andricdef FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", 3660b57cec5SDimitry Andric "Supports DSP instructions in " 3670b57cec5SDimitry Andric "ARM and/or Thumb2">; 3680b57cec5SDimitry Andric 3690b57cec5SDimitry Andric// Multiprocessing extension. 3700b57cec5SDimitry Andricdef FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 3710b57cec5SDimitry Andric "Supports Multiprocessing extension">; 3720b57cec5SDimitry Andric 3730b57cec5SDimitry Andric// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 3740b57cec5SDimitry Andricdef FeatureVirtualization : SubtargetFeature<"virtualization", 3750b57cec5SDimitry Andric "HasVirtualization", "true", 3760b57cec5SDimitry Andric "Supports Virtualization extension", 3770b57cec5SDimitry Andric [FeatureHWDivThumb, FeatureHWDivARM]>; 3780b57cec5SDimitry Andric 3790b57cec5SDimitry Andric// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 3800b57cec5SDimitry Andric// See ARMInstrInfo.td for details. 3810b57cec5SDimitry Andricdef FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 3820b57cec5SDimitry Andric "NaCl trap">; 3830b57cec5SDimitry Andric 3840b57cec5SDimitry Andricdef FeatureStrictAlign : SubtargetFeature<"strict-align", 3850b57cec5SDimitry Andric "StrictAlign", "true", 3860b57cec5SDimitry Andric "Disallow all unaligned memory " 3870b57cec5SDimitry Andric "access">; 3880b57cec5SDimitry Andric 3890b57cec5SDimitry Andricdef FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", 3900b57cec5SDimitry Andric "Generate calls via indirect call " 3910b57cec5SDimitry Andric "instructions">; 3920b57cec5SDimitry Andric 3930b57cec5SDimitry Andricdef FeatureExecuteOnly : SubtargetFeature<"execute-only", 3940b57cec5SDimitry Andric "GenExecuteOnly", "true", 3950b57cec5SDimitry Andric "Enable the generation of " 3960b57cec5SDimitry Andric "execute only code.">; 3970b57cec5SDimitry Andric 3980b57cec5SDimitry Andricdef FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", 3990b57cec5SDimitry Andric "Reserve R9, making it unavailable" 4000b57cec5SDimitry Andric " as GPR">; 4010b57cec5SDimitry Andric 4020b57cec5SDimitry Andricdef FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", 4030b57cec5SDimitry Andric "Don't use movt/movw pairs for " 4040b57cec5SDimitry Andric "32-bit imms">; 4050b57cec5SDimitry Andric 4060b57cec5SDimitry Andricdef FeatureNoNegativeImmediates 4070b57cec5SDimitry Andric : SubtargetFeature<"no-neg-immediates", 4080b57cec5SDimitry Andric "NegativeImmediates", "false", 4090b57cec5SDimitry Andric "Convert immediates and instructions " 4100b57cec5SDimitry Andric "to their negated or complemented " 4110b57cec5SDimitry Andric "equivalent when the immediate does " 4120b57cec5SDimitry Andric "not fit in the encoding.">; 4130b57cec5SDimitry Andric 4140b57cec5SDimitry Andric// Use the MachineScheduler for instruction scheduling for the subtarget. 4150b57cec5SDimitry Andricdef FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true", 4160b57cec5SDimitry Andric "Use the MachineScheduler">; 4170b57cec5SDimitry Andric 4180b57cec5SDimitry Andricdef FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler", 4190b57cec5SDimitry Andric "DisablePostRAScheduler", "true", 4200b57cec5SDimitry Andric "Don't schedule again after register allocation">; 4210b57cec5SDimitry Andric 4220b57cec5SDimitry Andric// Armv8.5-A extensions 4230b57cec5SDimitry Andric 4240b57cec5SDimitry Andricdef FeatureSB : SubtargetFeature<"sb", "HasSB", "true", 4250b57cec5SDimitry Andric "Enable v8.5a Speculation Barrier" >; 4260b57cec5SDimitry Andric 4275ffd83dbSDimitry Andric// Armv8.6-A extensions 4285ffd83dbSDimitry Andricdef FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", "true", 4295ffd83dbSDimitry Andric "Enable support for BFloat16 instructions", [FeatureNEON]>; 4305ffd83dbSDimitry Andric 4315ffd83dbSDimitry Andricdef FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8", 4325ffd83dbSDimitry Andric "true", "Enable Matrix Multiply Int8 Extension", [FeatureNEON]>; 4335ffd83dbSDimitry Andric 4340b57cec5SDimitry Andric// Armv8.1-M extensions 4350b57cec5SDimitry Andric 4360b57cec5SDimitry Andricdef FeatureLOB : SubtargetFeature<"lob", "HasLOB", "true", 4370b57cec5SDimitry Andric "Enable Low Overhead Branch " 4380b57cec5SDimitry Andric "extensions">; 4390b57cec5SDimitry Andric 4400b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 4410b57cec5SDimitry Andric// ARM architecture class 4420b57cec5SDimitry Andric// 4430b57cec5SDimitry Andric 4440b57cec5SDimitry Andric// A-series ISA 4450b57cec5SDimitry Andricdef FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 4460b57cec5SDimitry Andric "Is application profile ('A' series)">; 4470b57cec5SDimitry Andric 4480b57cec5SDimitry Andric// R-series ISA 4490b57cec5SDimitry Andricdef FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 4500b57cec5SDimitry Andric "Is realtime profile ('R' series)">; 4510b57cec5SDimitry Andric 4520b57cec5SDimitry Andric// M-series ISA 4530b57cec5SDimitry Andricdef FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 4540b57cec5SDimitry Andric "Is microcontroller profile ('M' series)">; 4550b57cec5SDimitry Andric 4560b57cec5SDimitry Andric 4570b57cec5SDimitry Andricdef FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 4580b57cec5SDimitry Andric "Enable Thumb2 instructions">; 4590b57cec5SDimitry Andric 4600b57cec5SDimitry Andricdef FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 4610b57cec5SDimitry Andric "Does not support ARM mode execution">; 4620b57cec5SDimitry Andric 4630b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 4640b57cec5SDimitry Andric// ARM ISAa. 4650b57cec5SDimitry Andric// 4660b57cec5SDimitry Andric 4670b57cec5SDimitry Andricdef HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 4680b57cec5SDimitry Andric "Support ARM v4T instructions">; 4690b57cec5SDimitry Andric 4700b57cec5SDimitry Andricdef HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 4710b57cec5SDimitry Andric "Support ARM v5T instructions", 4720b57cec5SDimitry Andric [HasV4TOps]>; 4730b57cec5SDimitry Andric 4740b57cec5SDimitry Andricdef HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 4750b57cec5SDimitry Andric "Support ARM v5TE, v5TEj, and " 4760b57cec5SDimitry Andric "v5TExp instructions", 4770b57cec5SDimitry Andric [HasV5TOps]>; 4780b57cec5SDimitry Andric 4790b57cec5SDimitry Andricdef HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 4800b57cec5SDimitry Andric "Support ARM v6 instructions", 4810b57cec5SDimitry Andric [HasV5TEOps]>; 4820b57cec5SDimitry Andric 4830b57cec5SDimitry Andricdef HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 4840b57cec5SDimitry Andric "Support ARM v6M instructions", 4850b57cec5SDimitry Andric [HasV6Ops]>; 4860b57cec5SDimitry Andric 4870b57cec5SDimitry Andricdef HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", 4880b57cec5SDimitry Andric "Support ARM v8M Baseline instructions", 4890b57cec5SDimitry Andric [HasV6MOps]>; 4900b57cec5SDimitry Andric 4910b57cec5SDimitry Andricdef HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", 4920b57cec5SDimitry Andric "Support ARM v6k instructions", 4930b57cec5SDimitry Andric [HasV6Ops]>; 4940b57cec5SDimitry Andric 4950b57cec5SDimitry Andricdef HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 4960b57cec5SDimitry Andric "Support ARM v6t2 instructions", 4970b57cec5SDimitry Andric [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; 4980b57cec5SDimitry Andric 4990b57cec5SDimitry Andricdef HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 5000b57cec5SDimitry Andric "Support ARM v7 instructions", 5010b57cec5SDimitry Andric [HasV6T2Ops, FeaturePerfMon, 5020b57cec5SDimitry Andric FeatureV7Clrex]>; 5030b57cec5SDimitry Andric 5040b57cec5SDimitry Andricdef HasV8MMainlineOps : 5050b57cec5SDimitry Andric SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", 5060b57cec5SDimitry Andric "Support ARM v8M Mainline instructions", 5070b57cec5SDimitry Andric [HasV7Ops]>; 5080b57cec5SDimitry Andric 5090b57cec5SDimitry Andricdef HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 5100b57cec5SDimitry Andric "Support ARM v8 instructions", 5110b57cec5SDimitry Andric [HasV7Ops, FeatureAcquireRelease]>; 5120b57cec5SDimitry Andric 5130b57cec5SDimitry Andricdef HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 5140b57cec5SDimitry Andric "Support ARM v8.1a instructions", 5150b57cec5SDimitry Andric [HasV8Ops]>; 5160b57cec5SDimitry Andric 5170b57cec5SDimitry Andricdef HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 5180b57cec5SDimitry Andric "Support ARM v8.2a instructions", 5190b57cec5SDimitry Andric [HasV8_1aOps]>; 5200b57cec5SDimitry Andric 5210b57cec5SDimitry Andricdef HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 5220b57cec5SDimitry Andric "Support ARM v8.3a instructions", 5230b57cec5SDimitry Andric [HasV8_2aOps]>; 5240b57cec5SDimitry Andric 5250b57cec5SDimitry Andricdef HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 5260b57cec5SDimitry Andric "Support ARM v8.4a instructions", 5270b57cec5SDimitry Andric [HasV8_3aOps, FeatureDotProd]>; 5280b57cec5SDimitry Andric 5290b57cec5SDimitry Andricdef HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true", 5300b57cec5SDimitry Andric "Support ARM v8.5a instructions", 5310b57cec5SDimitry Andric [HasV8_4aOps, FeatureSB]>; 5320b57cec5SDimitry Andric 5335ffd83dbSDimitry Andricdef HasV8_6aOps : SubtargetFeature<"v8.6a", "HasV8_6aOps", "true", 5345ffd83dbSDimitry Andric "Support ARM v8.6a instructions", 5355ffd83dbSDimitry Andric [HasV8_5aOps, FeatureBF16, 5365ffd83dbSDimitry Andric FeatureMatMulInt8]>; 5375ffd83dbSDimitry Andric 538e8d8bef9SDimitry Andricdef HasV8_7aOps : SubtargetFeature<"v8.7a", "HasV8_7aOps", "true", 539e8d8bef9SDimitry Andric "Support ARM v8.7a instructions", 540e8d8bef9SDimitry Andric [HasV8_6aOps]>; 541e8d8bef9SDimitry Andric 5420b57cec5SDimitry Andricdef HasV8_1MMainlineOps : SubtargetFeature< 5430b57cec5SDimitry Andric "v8.1m.main", "HasV8_1MMainlineOps", "true", 5440b57cec5SDimitry Andric "Support ARM v8-1M Mainline instructions", 5450b57cec5SDimitry Andric [HasV8MMainlineOps]>; 5460b57cec5SDimitry Andricdef HasMVEIntegerOps : SubtargetFeature< 5470b57cec5SDimitry Andric "mve", "HasMVEIntegerOps", "true", 5480b57cec5SDimitry Andric "Support M-Class Vector Extension with integer ops", 5490b57cec5SDimitry Andric [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>; 5500b57cec5SDimitry Andricdef HasMVEFloatOps : SubtargetFeature< 5510b57cec5SDimitry Andric "mve.fp", "HasMVEFloatOps", "true", 5520b57cec5SDimitry Andric "Support M-Class Vector Extension with integer and floating ops", 5530b57cec5SDimitry Andric [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>; 5540b57cec5SDimitry Andric 5555ffd83dbSDimitry Andricdef HasCDEOps : SubtargetFeature<"cde", "HasCDEOps", "true", 5565ffd83dbSDimitry Andric "Support CDE instructions", 5575ffd83dbSDimitry Andric [HasV8MMainlineOps]>; 5585ffd83dbSDimitry Andric 5595ffd83dbSDimitry Andricforeach i = {0-7} in 5605ffd83dbSDimitry Andric def FeatureCoprocCDE#i : SubtargetFeature<"cdecp"#i, 5615ffd83dbSDimitry Andric "CoprocCDE["#i#"]", "true", 5625ffd83dbSDimitry Andric "Coprocessor "#i#" ISA is CDEv1", 5635ffd83dbSDimitry Andric [HasCDEOps]>; 5645ffd83dbSDimitry Andric 5650b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 566e8d8bef9SDimitry Andric// Control codegen mitigation against Straight Line Speculation vulnerability. 567e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 568e8d8bef9SDimitry Andric 569e8d8bef9SDimitry Andricdef FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr", 570e8d8bef9SDimitry Andric "HardenSlsRetBr", "true", 571e8d8bef9SDimitry Andric "Harden against straight line speculation across RETurn and BranchRegister " 572e8d8bef9SDimitry Andric "instructions">; 573e8d8bef9SDimitry Andricdef FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr", 574e8d8bef9SDimitry Andric "HardenSlsBlr", "true", 575e8d8bef9SDimitry Andric "Harden against straight line speculation across indirect calls">; 576*fe6060f1SDimitry Andricdef FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat", 577*fe6060f1SDimitry Andric "HardenSlsNoComdat", "true", 578*fe6060f1SDimitry Andric "Generate thunk code for SLS mitigation in the normal text section">; 579e8d8bef9SDimitry Andric 580e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 5810b57cec5SDimitry Andric// ARM Processor subtarget features. 5820b57cec5SDimitry Andric// 5830b57cec5SDimitry Andric 5840b57cec5SDimitry Andricdef ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 5850b57cec5SDimitry Andric "Cortex-A5 ARM processors", []>; 5860b57cec5SDimitry Andricdef ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 5870b57cec5SDimitry Andric "Cortex-A7 ARM processors", []>; 5880b57cec5SDimitry Andricdef ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 5890b57cec5SDimitry Andric "Cortex-A8 ARM processors", []>; 5900b57cec5SDimitry Andricdef ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 5910b57cec5SDimitry Andric "Cortex-A9 ARM processors", []>; 5920b57cec5SDimitry Andricdef ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 5930b57cec5SDimitry Andric "Cortex-A12 ARM processors", []>; 5940b57cec5SDimitry Andricdef ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 5950b57cec5SDimitry Andric "Cortex-A15 ARM processors", []>; 5960b57cec5SDimitry Andricdef ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", 5970b57cec5SDimitry Andric "Cortex-A17 ARM processors", []>; 5980b57cec5SDimitry Andricdef ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", 5990b57cec5SDimitry Andric "Cortex-A32 ARM processors", []>; 6000b57cec5SDimitry Andricdef ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 6010b57cec5SDimitry Andric "Cortex-A35 ARM processors", []>; 6020b57cec5SDimitry Andricdef ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 6030b57cec5SDimitry Andric "Cortex-A53 ARM processors", []>; 6040b57cec5SDimitry Andricdef ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 6050b57cec5SDimitry Andric "Cortex-A55 ARM processors", []>; 6060b57cec5SDimitry Andricdef ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 6070b57cec5SDimitry Andric "Cortex-A57 ARM processors", []>; 6080b57cec5SDimitry Andricdef ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 6090b57cec5SDimitry Andric "Cortex-A72 ARM processors", []>; 6100b57cec5SDimitry Andricdef ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 6110b57cec5SDimitry Andric "Cortex-A73 ARM processors", []>; 6120b57cec5SDimitry Andricdef ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 6130b57cec5SDimitry Andric "Cortex-A75 ARM processors", []>; 6140b57cec5SDimitry Andricdef ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 6150b57cec5SDimitry Andric "Cortex-A76 ARM processors", []>; 6165ffd83dbSDimitry Andricdef ProcA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", 6175ffd83dbSDimitry Andric "Cortex-A77 ARM processors", []>; 6185ffd83dbSDimitry Andricdef ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily", "CortexA78", 6195ffd83dbSDimitry Andric "Cortex-A78 ARM processors", []>; 620e8d8bef9SDimitry Andricdef ProcA78C : SubtargetFeature<"a78c", "ARMProcFamily", "CortexA78C", 621e8d8bef9SDimitry Andric "Cortex-A78C ARM processors", []>; 6225ffd83dbSDimitry Andricdef ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", 6235ffd83dbSDimitry Andric "Cortex-X1 ARM processors", []>; 6240b57cec5SDimitry Andric 625e8d8bef9SDimitry Andricdef ProcV1 : SubtargetFeature<"neoverse-v1", "ARMProcFamily", 626e8d8bef9SDimitry Andric "NeoverseV1", "Neoverse-V1 ARM processors", []>; 627e8d8bef9SDimitry Andric 6280b57cec5SDimitry Andricdef ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 6290b57cec5SDimitry Andric "Qualcomm Krait processors", []>; 6300b57cec5SDimitry Andricdef ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 6310b57cec5SDimitry Andric "Qualcomm Kryo processors", []>; 6320b57cec5SDimitry Andricdef ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 6330b57cec5SDimitry Andric "Swift ARM processors", []>; 6340b57cec5SDimitry Andric 6350b57cec5SDimitry Andricdef ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos", 6360b57cec5SDimitry Andric "Samsung Exynos processors", 6370b57cec5SDimitry Andric [FeatureZCZeroing, 6380b57cec5SDimitry Andric FeatureUseWideStrideVFP, 6390b57cec5SDimitry Andric FeatureSplatVFPToNeon, 6400b57cec5SDimitry Andric FeatureSlowVGETLNi32, 6410b57cec5SDimitry Andric FeatureSlowVDUP32, 6420b57cec5SDimitry Andric FeatureSlowFPBrcc, 6430b57cec5SDimitry Andric FeatureProfUnpredicate, 6440b57cec5SDimitry Andric FeatureHWDivThumb, 6450b57cec5SDimitry Andric FeatureHWDivARM, 6460b57cec5SDimitry Andric FeatureHasSlowFPVMLx, 647480093f4SDimitry Andric FeatureHasSlowFPVFMx, 6480b57cec5SDimitry Andric FeatureHasRetAddrStack, 6490b57cec5SDimitry Andric FeatureFuseLiterals, 6500b57cec5SDimitry Andric FeatureFuseAES, 6510b57cec5SDimitry Andric FeatureExpandMLx, 6520b57cec5SDimitry Andric FeatureCrypto, 6530b57cec5SDimitry Andric FeatureCRC]>; 6540b57cec5SDimitry Andric 6550b57cec5SDimitry Andricdef ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", 6560b57cec5SDimitry Andric "Cortex-R4 ARM processors", []>; 6570b57cec5SDimitry Andricdef ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 6580b57cec5SDimitry Andric "Cortex-R5 ARM processors", []>; 6590b57cec5SDimitry Andricdef ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", 6600b57cec5SDimitry Andric "Cortex-R7 ARM processors", []>; 6610b57cec5SDimitry Andricdef ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", 6620b57cec5SDimitry Andric "Cortex-R52 ARM processors", []>; 6630b57cec5SDimitry Andric 6640b57cec5SDimitry Andricdef ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", 6650b57cec5SDimitry Andric "Cortex-M3 ARM processors", []>; 666e8d8bef9SDimitry Andricdef ProcM7 : SubtargetFeature<"m7", "ARMProcFamily", "CortexM7", 667e8d8bef9SDimitry Andric "Cortex-M7 ARM processors", []>; 6680b57cec5SDimitry Andric 6690b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 6700b57cec5SDimitry Andric// ARM Helper classes. 6710b57cec5SDimitry Andric// 6720b57cec5SDimitry Andric 6730b57cec5SDimitry Andricclass Architecture<string fname, string aname, list<SubtargetFeature> features> 6740b57cec5SDimitry Andric : SubtargetFeature<fname, "ARMArch", aname, 6750b57cec5SDimitry Andric !strconcat(aname, " architecture"), features>; 6760b57cec5SDimitry Andric 6770b57cec5SDimitry Andricclass ProcNoItin<string Name, list<SubtargetFeature> Features> 6780b57cec5SDimitry Andric : Processor<Name, NoItineraries, Features>; 6790b57cec5SDimitry Andric 6800b57cec5SDimitry Andric 6810b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 6820b57cec5SDimitry Andric// ARM architectures 6830b57cec5SDimitry Andric// 6840b57cec5SDimitry Andric 6850b57cec5SDimitry Andricdef ARMv2 : Architecture<"armv2", "ARMv2", []>; 6860b57cec5SDimitry Andric 6870b57cec5SDimitry Andricdef ARMv2a : Architecture<"armv2a", "ARMv2a", []>; 6880b57cec5SDimitry Andric 6890b57cec5SDimitry Andricdef ARMv3 : Architecture<"armv3", "ARMv3", []>; 6900b57cec5SDimitry Andric 6910b57cec5SDimitry Andricdef ARMv3m : Architecture<"armv3m", "ARMv3m", []>; 6920b57cec5SDimitry Andric 6930b57cec5SDimitry Andricdef ARMv4 : Architecture<"armv4", "ARMv4", []>; 6940b57cec5SDimitry Andric 6950b57cec5SDimitry Andricdef ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; 6960b57cec5SDimitry Andric 6970b57cec5SDimitry Andricdef ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; 6980b57cec5SDimitry Andric 6990b57cec5SDimitry Andricdef ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; 7000b57cec5SDimitry Andric 7010b57cec5SDimitry Andricdef ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; 7020b57cec5SDimitry Andric 7030b57cec5SDimitry Andricdef ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops, 7040b57cec5SDimitry Andric FeatureDSP]>; 7050b57cec5SDimitry Andric 7060b57cec5SDimitry Andricdef ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, 7070b57cec5SDimitry Andric FeatureDSP]>; 7080b57cec5SDimitry Andric 7090b57cec5SDimitry Andricdef ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; 7100b57cec5SDimitry Andric 7110b57cec5SDimitry Andricdef ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, 7120b57cec5SDimitry Andric FeatureTrustZone]>; 7130b57cec5SDimitry Andric 7140b57cec5SDimitry Andricdef ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, 7150b57cec5SDimitry Andric FeatureNoARM, 7160b57cec5SDimitry Andric ModeThumb, 7170b57cec5SDimitry Andric FeatureDB, 7180b57cec5SDimitry Andric FeatureMClass, 7190b57cec5SDimitry Andric FeatureStrictAlign]>; 7200b57cec5SDimitry Andric 7210b57cec5SDimitry Andricdef ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, 7220b57cec5SDimitry Andric FeatureNoARM, 7230b57cec5SDimitry Andric ModeThumb, 7240b57cec5SDimitry Andric FeatureDB, 7250b57cec5SDimitry Andric FeatureMClass, 7260b57cec5SDimitry Andric FeatureStrictAlign]>; 7270b57cec5SDimitry Andric 7280b57cec5SDimitry Andricdef ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, 7290b57cec5SDimitry Andric FeatureNEON, 7300b57cec5SDimitry Andric FeatureDB, 7310b57cec5SDimitry Andric FeatureDSP, 7320b57cec5SDimitry Andric FeatureAClass]>; 7330b57cec5SDimitry Andric 7340b57cec5SDimitry Andricdef ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops, 7350b57cec5SDimitry Andric FeatureNEON, 7360b57cec5SDimitry Andric FeatureDB, 7370b57cec5SDimitry Andric FeatureDSP, 7380b57cec5SDimitry Andric FeatureTrustZone, 7390b57cec5SDimitry Andric FeatureMP, 7400b57cec5SDimitry Andric FeatureVirtualization, 7410b57cec5SDimitry Andric FeatureAClass]>; 7420b57cec5SDimitry Andric 7430b57cec5SDimitry Andricdef ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, 7440b57cec5SDimitry Andric FeatureDB, 7450b57cec5SDimitry Andric FeatureDSP, 7460b57cec5SDimitry Andric FeatureHWDivThumb, 7470b57cec5SDimitry Andric FeatureRClass]>; 7480b57cec5SDimitry Andric 7490b57cec5SDimitry Andricdef ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, 7500b57cec5SDimitry Andric FeatureThumb2, 7510b57cec5SDimitry Andric FeatureNoARM, 7520b57cec5SDimitry Andric ModeThumb, 7530b57cec5SDimitry Andric FeatureDB, 7540b57cec5SDimitry Andric FeatureHWDivThumb, 7550b57cec5SDimitry Andric FeatureMClass]>; 7560b57cec5SDimitry Andric 7570b57cec5SDimitry Andricdef ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, 7580b57cec5SDimitry Andric FeatureThumb2, 7590b57cec5SDimitry Andric FeatureNoARM, 7600b57cec5SDimitry Andric ModeThumb, 7610b57cec5SDimitry Andric FeatureDB, 7620b57cec5SDimitry Andric FeatureHWDivThumb, 7630b57cec5SDimitry Andric FeatureMClass, 7640b57cec5SDimitry Andric FeatureDSP]>; 7650b57cec5SDimitry Andric 7660b57cec5SDimitry Andricdef ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, 7670b57cec5SDimitry Andric FeatureAClass, 7680b57cec5SDimitry Andric FeatureDB, 7690b57cec5SDimitry Andric FeatureFPARMv8, 7700b57cec5SDimitry Andric FeatureNEON, 7710b57cec5SDimitry Andric FeatureDSP, 7720b57cec5SDimitry Andric FeatureTrustZone, 7730b57cec5SDimitry Andric FeatureMP, 7740b57cec5SDimitry Andric FeatureVirtualization, 7750b57cec5SDimitry Andric FeatureCrypto, 7760b57cec5SDimitry Andric FeatureCRC]>; 7770b57cec5SDimitry Andric 7780b57cec5SDimitry Andricdef ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, 7790b57cec5SDimitry Andric FeatureAClass, 7800b57cec5SDimitry Andric FeatureDB, 7810b57cec5SDimitry Andric FeatureFPARMv8, 7820b57cec5SDimitry Andric FeatureNEON, 7830b57cec5SDimitry Andric FeatureDSP, 7840b57cec5SDimitry Andric FeatureTrustZone, 7850b57cec5SDimitry Andric FeatureMP, 7860b57cec5SDimitry Andric FeatureVirtualization, 7870b57cec5SDimitry Andric FeatureCrypto, 7880b57cec5SDimitry Andric FeatureCRC]>; 7890b57cec5SDimitry Andric 7900b57cec5SDimitry Andricdef ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, 7910b57cec5SDimitry Andric FeatureAClass, 7920b57cec5SDimitry Andric FeatureDB, 7930b57cec5SDimitry Andric FeatureFPARMv8, 7940b57cec5SDimitry Andric FeatureNEON, 7950b57cec5SDimitry Andric FeatureDSP, 7960b57cec5SDimitry Andric FeatureTrustZone, 7970b57cec5SDimitry Andric FeatureMP, 7980b57cec5SDimitry Andric FeatureVirtualization, 7990b57cec5SDimitry Andric FeatureCrypto, 8000b57cec5SDimitry Andric FeatureCRC, 8010b57cec5SDimitry Andric FeatureRAS]>; 8020b57cec5SDimitry Andric 8030b57cec5SDimitry Andricdef ARMv83a : Architecture<"armv8.3-a", "ARMv83a", [HasV8_3aOps, 8040b57cec5SDimitry Andric FeatureAClass, 8050b57cec5SDimitry Andric FeatureDB, 8060b57cec5SDimitry Andric FeatureFPARMv8, 8070b57cec5SDimitry Andric FeatureNEON, 8080b57cec5SDimitry Andric FeatureDSP, 8090b57cec5SDimitry Andric FeatureTrustZone, 8100b57cec5SDimitry Andric FeatureMP, 8110b57cec5SDimitry Andric FeatureVirtualization, 8120b57cec5SDimitry Andric FeatureCrypto, 8130b57cec5SDimitry Andric FeatureCRC, 8140b57cec5SDimitry Andric FeatureRAS]>; 8150b57cec5SDimitry Andric 8160b57cec5SDimitry Andricdef ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps, 8170b57cec5SDimitry Andric FeatureAClass, 8180b57cec5SDimitry Andric FeatureDB, 8190b57cec5SDimitry Andric FeatureFPARMv8, 8200b57cec5SDimitry Andric FeatureNEON, 8210b57cec5SDimitry Andric FeatureDSP, 8220b57cec5SDimitry Andric FeatureTrustZone, 8230b57cec5SDimitry Andric FeatureMP, 8240b57cec5SDimitry Andric FeatureVirtualization, 8250b57cec5SDimitry Andric FeatureCrypto, 8260b57cec5SDimitry Andric FeatureCRC, 8270b57cec5SDimitry Andric FeatureRAS, 8280b57cec5SDimitry Andric FeatureDotProd]>; 8290b57cec5SDimitry Andric 8300b57cec5SDimitry Andricdef ARMv85a : Architecture<"armv8.5-a", "ARMv85a", [HasV8_5aOps, 8310b57cec5SDimitry Andric FeatureAClass, 8320b57cec5SDimitry Andric FeatureDB, 8330b57cec5SDimitry Andric FeatureFPARMv8, 8340b57cec5SDimitry Andric FeatureNEON, 8350b57cec5SDimitry Andric FeatureDSP, 8360b57cec5SDimitry Andric FeatureTrustZone, 8370b57cec5SDimitry Andric FeatureMP, 8380b57cec5SDimitry Andric FeatureVirtualization, 8390b57cec5SDimitry Andric FeatureCrypto, 8400b57cec5SDimitry Andric FeatureCRC, 8410b57cec5SDimitry Andric FeatureRAS, 8420b57cec5SDimitry Andric FeatureDotProd]>; 8435ffd83dbSDimitry Andricdef ARMv86a : Architecture<"armv8.6-a", "ARMv86a", [HasV8_6aOps, 8445ffd83dbSDimitry Andric FeatureAClass, 8455ffd83dbSDimitry Andric FeatureDB, 8465ffd83dbSDimitry Andric FeatureFPARMv8, 8475ffd83dbSDimitry Andric FeatureNEON, 8485ffd83dbSDimitry Andric FeatureDSP, 8495ffd83dbSDimitry Andric FeatureTrustZone, 8505ffd83dbSDimitry Andric FeatureMP, 8515ffd83dbSDimitry Andric FeatureVirtualization, 8525ffd83dbSDimitry Andric FeatureCrypto, 8535ffd83dbSDimitry Andric FeatureCRC, 8545ffd83dbSDimitry Andric FeatureRAS, 8555ffd83dbSDimitry Andric FeatureDotProd]>; 856*fe6060f1SDimitry Andricdef ARMv87a : Architecture<"armv8.7-a", "ARMv87a", [HasV8_7aOps, 857e8d8bef9SDimitry Andric FeatureAClass, 858e8d8bef9SDimitry Andric FeatureDB, 859e8d8bef9SDimitry Andric FeatureFPARMv8, 860e8d8bef9SDimitry Andric FeatureNEON, 861e8d8bef9SDimitry Andric FeatureDSP, 862e8d8bef9SDimitry Andric FeatureTrustZone, 863e8d8bef9SDimitry Andric FeatureMP, 864e8d8bef9SDimitry Andric FeatureVirtualization, 865e8d8bef9SDimitry Andric FeatureCrypto, 866e8d8bef9SDimitry Andric FeatureCRC, 867e8d8bef9SDimitry Andric FeatureRAS, 868e8d8bef9SDimitry Andric FeatureDotProd]>; 8690b57cec5SDimitry Andric 8700b57cec5SDimitry Andricdef ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, 8710b57cec5SDimitry Andric FeatureRClass, 8720b57cec5SDimitry Andric FeatureDB, 8730b57cec5SDimitry Andric FeatureDFB, 8740b57cec5SDimitry Andric FeatureDSP, 8750b57cec5SDimitry Andric FeatureCRC, 8760b57cec5SDimitry Andric FeatureMP, 8770b57cec5SDimitry Andric FeatureVirtualization, 8780b57cec5SDimitry Andric FeatureFPARMv8, 8790b57cec5SDimitry Andric FeatureNEON]>; 8800b57cec5SDimitry Andric 8810b57cec5SDimitry Andricdef ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", 8820b57cec5SDimitry Andric [HasV8MBaselineOps, 8830b57cec5SDimitry Andric FeatureNoARM, 8840b57cec5SDimitry Andric ModeThumb, 8850b57cec5SDimitry Andric FeatureDB, 8860b57cec5SDimitry Andric FeatureHWDivThumb, 8870b57cec5SDimitry Andric FeatureV7Clrex, 8880b57cec5SDimitry Andric Feature8MSecExt, 8890b57cec5SDimitry Andric FeatureAcquireRelease, 8900b57cec5SDimitry Andric FeatureMClass, 8910b57cec5SDimitry Andric FeatureStrictAlign]>; 8920b57cec5SDimitry Andric 8930b57cec5SDimitry Andricdef ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", 8940b57cec5SDimitry Andric [HasV8MMainlineOps, 8950b57cec5SDimitry Andric FeatureNoARM, 8960b57cec5SDimitry Andric ModeThumb, 8970b57cec5SDimitry Andric FeatureDB, 8980b57cec5SDimitry Andric FeatureHWDivThumb, 8990b57cec5SDimitry Andric Feature8MSecExt, 9000b57cec5SDimitry Andric FeatureAcquireRelease, 9010b57cec5SDimitry Andric FeatureMClass]>; 9020b57cec5SDimitry Andric 9030b57cec5SDimitry Andricdef ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline", 9040b57cec5SDimitry Andric [HasV8_1MMainlineOps, 9050b57cec5SDimitry Andric FeatureNoARM, 9060b57cec5SDimitry Andric ModeThumb, 9070b57cec5SDimitry Andric FeatureDB, 9080b57cec5SDimitry Andric FeatureHWDivThumb, 9090b57cec5SDimitry Andric Feature8MSecExt, 9100b57cec5SDimitry Andric FeatureAcquireRelease, 9110b57cec5SDimitry Andric FeatureMClass, 9120b57cec5SDimitry Andric FeatureRAS, 9130b57cec5SDimitry Andric FeatureLOB]>; 9140b57cec5SDimitry Andric 9150b57cec5SDimitry Andric// Aliases 9160b57cec5SDimitry Andricdef IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; 9170b57cec5SDimitry Andricdef IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; 9180b57cec5SDimitry Andricdef XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; 9190b57cec5SDimitry Andricdef ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; 9200b57cec5SDimitry Andricdef ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; 9210b57cec5SDimitry Andricdef ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; 9220b57cec5SDimitry Andric 923e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 924e8d8bef9SDimitry Andric// Register File Description 925e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 926e8d8bef9SDimitry Andric 927e8d8bef9SDimitry Andricinclude "ARMRegisterInfo.td" 928e8d8bef9SDimitry Andricinclude "ARMRegisterBanks.td" 929e8d8bef9SDimitry Andricinclude "ARMCallingConv.td" 9300b57cec5SDimitry Andric 9310b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 9320b57cec5SDimitry Andric// ARM schedules. 9330b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 9340b57cec5SDimitry Andric// 9350b57cec5SDimitry Andricinclude "ARMPredicates.td" 9360b57cec5SDimitry Andricinclude "ARMSchedule.td" 9370b57cec5SDimitry Andric 9380b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 939e8d8bef9SDimitry Andric// Instruction Descriptions 940e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 941e8d8bef9SDimitry Andric 942e8d8bef9SDimitry Andricinclude "ARMInstrInfo.td" 943e8d8bef9SDimitry Andricdef ARMInstrInfo : InstrInfo; 944e8d8bef9SDimitry Andric 945e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 946e8d8bef9SDimitry Andric// ARM schedules 947e8d8bef9SDimitry Andric// 948e8d8bef9SDimitry Andricinclude "ARMScheduleV6.td" 949e8d8bef9SDimitry Andricinclude "ARMScheduleA8.td" 950e8d8bef9SDimitry Andricinclude "ARMScheduleA9.td" 951e8d8bef9SDimitry Andricinclude "ARMScheduleSwift.td" 952e8d8bef9SDimitry Andricinclude "ARMScheduleR52.td" 953e8d8bef9SDimitry Andricinclude "ARMScheduleA57.td" 954e8d8bef9SDimitry Andricinclude "ARMScheduleM4.td" 955e8d8bef9SDimitry Andricinclude "ARMScheduleM7.td" 956e8d8bef9SDimitry Andric 957e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 9580b57cec5SDimitry Andric// ARM processors 9590b57cec5SDimitry Andric// 9600b57cec5SDimitry Andric// Dummy CPU, used to target architectures 9610b57cec5SDimitry Andricdef : ProcessorModel<"generic", CortexA8Model, []>; 9620b57cec5SDimitry Andric 9630b57cec5SDimitry Andric// FIXME: Several processors below are not using their own scheduler 9640b57cec5SDimitry Andric// model, but one of similar/previous processor. These should be fixed. 9650b57cec5SDimitry Andric 9660b57cec5SDimitry Andricdef : ProcNoItin<"arm8", [ARMv4]>; 9670b57cec5SDimitry Andricdef : ProcNoItin<"arm810", [ARMv4]>; 9680b57cec5SDimitry Andricdef : ProcNoItin<"strongarm", [ARMv4]>; 9690b57cec5SDimitry Andricdef : ProcNoItin<"strongarm110", [ARMv4]>; 9700b57cec5SDimitry Andricdef : ProcNoItin<"strongarm1100", [ARMv4]>; 9710b57cec5SDimitry Andricdef : ProcNoItin<"strongarm1110", [ARMv4]>; 9720b57cec5SDimitry Andric 9730b57cec5SDimitry Andricdef : ProcNoItin<"arm7tdmi", [ARMv4t]>; 9740b57cec5SDimitry Andricdef : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; 9750b57cec5SDimitry Andricdef : ProcNoItin<"arm710t", [ARMv4t]>; 9760b57cec5SDimitry Andricdef : ProcNoItin<"arm720t", [ARMv4t]>; 9770b57cec5SDimitry Andricdef : ProcNoItin<"arm9", [ARMv4t]>; 9780b57cec5SDimitry Andricdef : ProcNoItin<"arm9tdmi", [ARMv4t]>; 9790b57cec5SDimitry Andricdef : ProcNoItin<"arm920", [ARMv4t]>; 9800b57cec5SDimitry Andricdef : ProcNoItin<"arm920t", [ARMv4t]>; 9810b57cec5SDimitry Andricdef : ProcNoItin<"arm922t", [ARMv4t]>; 9820b57cec5SDimitry Andricdef : ProcNoItin<"arm940t", [ARMv4t]>; 9830b57cec5SDimitry Andricdef : ProcNoItin<"ep9312", [ARMv4t]>; 9840b57cec5SDimitry Andric 9850b57cec5SDimitry Andricdef : ProcNoItin<"arm10tdmi", [ARMv5t]>; 9860b57cec5SDimitry Andricdef : ProcNoItin<"arm1020t", [ARMv5t]>; 9870b57cec5SDimitry Andric 9880b57cec5SDimitry Andricdef : ProcNoItin<"arm9e", [ARMv5te]>; 9890b57cec5SDimitry Andricdef : ProcNoItin<"arm926ej-s", [ARMv5te]>; 9900b57cec5SDimitry Andricdef : ProcNoItin<"arm946e-s", [ARMv5te]>; 9910b57cec5SDimitry Andricdef : ProcNoItin<"arm966e-s", [ARMv5te]>; 9920b57cec5SDimitry Andricdef : ProcNoItin<"arm968e-s", [ARMv5te]>; 9930b57cec5SDimitry Andricdef : ProcNoItin<"arm10e", [ARMv5te]>; 9940b57cec5SDimitry Andricdef : ProcNoItin<"arm1020e", [ARMv5te]>; 9950b57cec5SDimitry Andricdef : ProcNoItin<"arm1022e", [ARMv5te]>; 9960b57cec5SDimitry Andricdef : ProcNoItin<"xscale", [ARMv5te]>; 9970b57cec5SDimitry Andricdef : ProcNoItin<"iwmmxt", [ARMv5te]>; 9980b57cec5SDimitry Andric 9990b57cec5SDimitry Andricdef : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; 10000b57cec5SDimitry Andricdef : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, 10010b57cec5SDimitry Andric FeatureVFP2, 10020b57cec5SDimitry Andric FeatureHasSlowFPVMLx]>; 10030b57cec5SDimitry Andric 1004*fe6060f1SDimitry Andricdef : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m, 1005*fe6060f1SDimitry Andric FeatureHasNoBranchPredictor]>; 1006*fe6060f1SDimitry Andricdef : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m, 1007*fe6060f1SDimitry Andric FeatureHasNoBranchPredictor]>; 1008*fe6060f1SDimitry Andricdef : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m, 1009*fe6060f1SDimitry Andric FeatureHasNoBranchPredictor]>; 1010*fe6060f1SDimitry Andricdef : Processor<"sc000", ARMV6Itineraries, [ARMv6m, 1011*fe6060f1SDimitry Andric FeatureHasNoBranchPredictor]>; 10120b57cec5SDimitry Andric 10130b57cec5SDimitry Andricdef : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; 10140b57cec5SDimitry Andricdef : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, 10150b57cec5SDimitry Andric FeatureVFP2, 10160b57cec5SDimitry Andric FeatureHasSlowFPVMLx]>; 10170b57cec5SDimitry Andric 10180b57cec5SDimitry Andricdef : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; 10190b57cec5SDimitry Andricdef : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, 10200b57cec5SDimitry Andric FeatureVFP2, 10210b57cec5SDimitry Andric FeatureHasSlowFPVMLx]>; 10220b57cec5SDimitry Andric 10230b57cec5SDimitry Andricdef : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; 10240b57cec5SDimitry Andricdef : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, 10250b57cec5SDimitry Andric FeatureVFP2, 10260b57cec5SDimitry Andric FeatureHasSlowFPVMLx]>; 10270b57cec5SDimitry Andric 10280b57cec5SDimitry Andricdef : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, 10290b57cec5SDimitry Andric FeatureHasRetAddrStack, 10300b57cec5SDimitry Andric FeatureTrustZone, 10310b57cec5SDimitry Andric FeatureSlowFPBrcc, 10320b57cec5SDimitry Andric FeatureHasSlowFPVMLx, 1033480093f4SDimitry Andric FeatureHasSlowFPVFMx, 10340b57cec5SDimitry Andric FeatureVMLxForwarding, 10350b57cec5SDimitry Andric FeatureMP, 10360b57cec5SDimitry Andric FeatureVFP4]>; 10370b57cec5SDimitry Andric 10380b57cec5SDimitry Andricdef : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, 10390b57cec5SDimitry Andric FeatureHasRetAddrStack, 10400b57cec5SDimitry Andric FeatureTrustZone, 10410b57cec5SDimitry Andric FeatureSlowFPBrcc, 10420b57cec5SDimitry Andric FeatureHasVMLxHazards, 10430b57cec5SDimitry Andric FeatureHasSlowFPVMLx, 1044480093f4SDimitry Andric FeatureHasSlowFPVFMx, 10450b57cec5SDimitry Andric FeatureVMLxForwarding, 10460b57cec5SDimitry Andric FeatureMP, 10470b57cec5SDimitry Andric FeatureVFP4, 10480b57cec5SDimitry Andric FeatureVirtualization]>; 10490b57cec5SDimitry Andric 10500b57cec5SDimitry Andricdef : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, 10510b57cec5SDimitry Andric FeatureHasRetAddrStack, 10520b57cec5SDimitry Andric FeatureNonpipelinedVFP, 10530b57cec5SDimitry Andric FeatureTrustZone, 10540b57cec5SDimitry Andric FeatureSlowFPBrcc, 10550b57cec5SDimitry Andric FeatureHasVMLxHazards, 10560b57cec5SDimitry Andric FeatureHasSlowFPVMLx, 1057480093f4SDimitry Andric FeatureHasSlowFPVFMx, 10580b57cec5SDimitry Andric FeatureVMLxForwarding]>; 10590b57cec5SDimitry Andric 10600b57cec5SDimitry Andricdef : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, 10610b57cec5SDimitry Andric FeatureHasRetAddrStack, 10620b57cec5SDimitry Andric FeatureTrustZone, 10630b57cec5SDimitry Andric FeatureHasVMLxHazards, 10640b57cec5SDimitry Andric FeatureVMLxForwarding, 10650b57cec5SDimitry Andric FeatureFP16, 10660b57cec5SDimitry Andric FeatureAvoidPartialCPSR, 10670b57cec5SDimitry Andric FeatureExpandMLx, 10680b57cec5SDimitry Andric FeaturePreferVMOVSR, 10690b57cec5SDimitry Andric FeatureMuxedUnits, 10700b57cec5SDimitry Andric FeatureNEONForFPMovs, 10710b57cec5SDimitry Andric FeatureCheckVLDnAlign, 10720b57cec5SDimitry Andric FeatureMP]>; 10730b57cec5SDimitry Andric 10740b57cec5SDimitry Andricdef : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, 10750b57cec5SDimitry Andric FeatureHasRetAddrStack, 10760b57cec5SDimitry Andric FeatureTrustZone, 10770b57cec5SDimitry Andric FeatureVMLxForwarding, 10780b57cec5SDimitry Andric FeatureVFP4, 10790b57cec5SDimitry Andric FeatureAvoidPartialCPSR, 10800b57cec5SDimitry Andric FeatureVirtualization, 10810b57cec5SDimitry Andric FeatureMP]>; 10820b57cec5SDimitry Andric 10830b57cec5SDimitry Andricdef : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, 10840b57cec5SDimitry Andric FeatureDontWidenVMOVS, 10850b57cec5SDimitry Andric FeatureSplatVFPToNeon, 10860b57cec5SDimitry Andric FeatureHasRetAddrStack, 10870b57cec5SDimitry Andric FeatureMuxedUnits, 10880b57cec5SDimitry Andric FeatureTrustZone, 10890b57cec5SDimitry Andric FeatureVFP4, 10900b57cec5SDimitry Andric FeatureMP, 10910b57cec5SDimitry Andric FeatureCheckVLDnAlign, 10920b57cec5SDimitry Andric FeatureAvoidPartialCPSR, 10930b57cec5SDimitry Andric FeatureVirtualization]>; 10940b57cec5SDimitry Andric 10950b57cec5SDimitry Andricdef : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, 10960b57cec5SDimitry Andric FeatureHasRetAddrStack, 10970b57cec5SDimitry Andric FeatureTrustZone, 10980b57cec5SDimitry Andric FeatureMP, 10990b57cec5SDimitry Andric FeatureVMLxForwarding, 11000b57cec5SDimitry Andric FeatureVFP4, 11010b57cec5SDimitry Andric FeatureAvoidPartialCPSR, 11020b57cec5SDimitry Andric FeatureVirtualization]>; 11030b57cec5SDimitry Andric 11040b57cec5SDimitry Andric// FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv 11050b57cec5SDimitry Andricdef : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, 11060b57cec5SDimitry Andric FeatureHasRetAddrStack, 11070b57cec5SDimitry Andric FeatureMuxedUnits, 11080b57cec5SDimitry Andric FeatureCheckVLDnAlign, 11090b57cec5SDimitry Andric FeatureVMLxForwarding, 11100b57cec5SDimitry Andric FeatureFP16, 11110b57cec5SDimitry Andric FeatureAvoidPartialCPSR, 11120b57cec5SDimitry Andric FeatureVFP4, 11130b57cec5SDimitry Andric FeatureHWDivThumb, 11140b57cec5SDimitry Andric FeatureHWDivARM]>; 11150b57cec5SDimitry Andric 11160b57cec5SDimitry Andricdef : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, 11170b57cec5SDimitry Andric FeatureHasRetAddrStack, 11180b57cec5SDimitry Andric FeatureNEONForFP, 11190b57cec5SDimitry Andric FeatureVFP4, 11200b57cec5SDimitry Andric FeatureUseWideStrideVFP, 11210b57cec5SDimitry Andric FeatureMP, 11220b57cec5SDimitry Andric FeatureHWDivThumb, 11230b57cec5SDimitry Andric FeatureHWDivARM, 11240b57cec5SDimitry Andric FeatureAvoidPartialCPSR, 11250b57cec5SDimitry Andric FeatureAvoidMOVsShOp, 11260b57cec5SDimitry Andric FeatureHasSlowFPVMLx, 1127480093f4SDimitry Andric FeatureHasSlowFPVFMx, 11280b57cec5SDimitry Andric FeatureHasVMLxHazards, 11290b57cec5SDimitry Andric FeatureProfUnpredicate, 11300b57cec5SDimitry Andric FeaturePrefISHSTBarrier, 11310b57cec5SDimitry Andric FeatureSlowOddRegister, 11320b57cec5SDimitry Andric FeatureSlowLoadDSubreg, 11330b57cec5SDimitry Andric FeatureSlowVGETLNi32, 11340b57cec5SDimitry Andric FeatureSlowVDUP32, 11350b57cec5SDimitry Andric FeatureUseMISched, 11360b57cec5SDimitry Andric FeatureNoPostRASched]>; 11370b57cec5SDimitry Andric 11380b57cec5SDimitry Andricdef : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, 11390b57cec5SDimitry Andric FeatureHasRetAddrStack, 11400b57cec5SDimitry Andric FeatureAvoidPartialCPSR]>; 11410b57cec5SDimitry Andric 11420b57cec5SDimitry Andricdef : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, 11430b57cec5SDimitry Andric FeatureHasRetAddrStack, 11440b57cec5SDimitry Andric FeatureSlowFPBrcc, 11450b57cec5SDimitry Andric FeatureHasSlowFPVMLx, 1146480093f4SDimitry Andric FeatureHasSlowFPVFMx, 11470b57cec5SDimitry Andric FeatureVFP3_D16, 11480b57cec5SDimitry Andric FeatureAvoidPartialCPSR]>; 11490b57cec5SDimitry Andric 11500b57cec5SDimitry Andricdef : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, 11510b57cec5SDimitry Andric FeatureHasRetAddrStack, 11520b57cec5SDimitry Andric FeatureVFP3_D16, 11530b57cec5SDimitry Andric FeatureSlowFPBrcc, 11540b57cec5SDimitry Andric FeatureHWDivARM, 11550b57cec5SDimitry Andric FeatureHasSlowFPVMLx, 1156480093f4SDimitry Andric FeatureHasSlowFPVFMx, 11570b57cec5SDimitry Andric FeatureAvoidPartialCPSR]>; 11580b57cec5SDimitry Andric 11590b57cec5SDimitry Andricdef : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, 11600b57cec5SDimitry Andric FeatureHasRetAddrStack, 11610b57cec5SDimitry Andric FeatureVFP3_D16, 11620b57cec5SDimitry Andric FeatureFP16, 11630b57cec5SDimitry Andric FeatureMP, 11640b57cec5SDimitry Andric FeatureSlowFPBrcc, 11650b57cec5SDimitry Andric FeatureHWDivARM, 11660b57cec5SDimitry Andric FeatureHasSlowFPVMLx, 1167480093f4SDimitry Andric FeatureHasSlowFPVFMx, 11680b57cec5SDimitry Andric FeatureAvoidPartialCPSR]>; 11690b57cec5SDimitry Andric 11700b57cec5SDimitry Andricdef : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, 11710b57cec5SDimitry Andric FeatureHasRetAddrStack, 11720b57cec5SDimitry Andric FeatureVFP3_D16, 11730b57cec5SDimitry Andric FeatureFP16, 11740b57cec5SDimitry Andric FeatureMP, 11750b57cec5SDimitry Andric FeatureSlowFPBrcc, 11760b57cec5SDimitry Andric FeatureHWDivARM, 11770b57cec5SDimitry Andric FeatureHasSlowFPVMLx, 1178480093f4SDimitry Andric FeatureHasSlowFPVFMx, 11790b57cec5SDimitry Andric FeatureAvoidPartialCPSR]>; 11800b57cec5SDimitry Andric 11810b57cec5SDimitry Andricdef : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m, 11820b57cec5SDimitry Andric ProcM3, 11830b57cec5SDimitry Andric FeaturePrefLoopAlign32, 11840b57cec5SDimitry Andric FeatureUseMISched, 11850b57cec5SDimitry Andric FeatureHasNoBranchPredictor]>; 11860b57cec5SDimitry Andric 11870b57cec5SDimitry Andricdef : ProcessorModel<"sc300", CortexM4Model, [ARMv7m, 11880b57cec5SDimitry Andric ProcM3, 11890b57cec5SDimitry Andric FeatureUseMISched, 11900b57cec5SDimitry Andric FeatureHasNoBranchPredictor]>; 11910b57cec5SDimitry Andric 11920b57cec5SDimitry Andricdef : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em, 11930b57cec5SDimitry Andric FeatureVFP4_D16_SP, 11940b57cec5SDimitry Andric FeaturePrefLoopAlign32, 11950b57cec5SDimitry Andric FeatureHasSlowFPVMLx, 1196480093f4SDimitry Andric FeatureHasSlowFPVFMx, 11970b57cec5SDimitry Andric FeatureUseMISched, 11980b57cec5SDimitry Andric FeatureHasNoBranchPredictor]>; 11990b57cec5SDimitry Andric 1200e8d8bef9SDimitry Andricdef : ProcessorModel<"cortex-m7", CortexM7Model, [ARMv7em, 1201e8d8bef9SDimitry Andric ProcM7, 1202e8d8bef9SDimitry Andric FeatureFPARMv8_D16, 1203e8d8bef9SDimitry Andric FeatureUseMISched]>; 12040b57cec5SDimitry Andric 12050b57cec5SDimitry Andricdef : ProcNoItin<"cortex-m23", [ARMv8mBaseline, 1206*fe6060f1SDimitry Andric FeatureNoMovt, 1207*fe6060f1SDimitry Andric FeatureHasNoBranchPredictor]>; 12080b57cec5SDimitry Andric 12090b57cec5SDimitry Andricdef : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline, 12100b57cec5SDimitry Andric FeatureDSP, 12110b57cec5SDimitry Andric FeatureFPARMv8_D16_SP, 12120b57cec5SDimitry Andric FeaturePrefLoopAlign32, 12130b57cec5SDimitry Andric FeatureHasSlowFPVMLx, 1214480093f4SDimitry Andric FeatureHasSlowFPVFMx, 12150b57cec5SDimitry Andric FeatureUseMISched, 12160b57cec5SDimitry Andric FeatureHasNoBranchPredictor]>; 12170b57cec5SDimitry Andric 12180b57cec5SDimitry Andricdef : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline, 12190b57cec5SDimitry Andric FeatureDSP, 12200b57cec5SDimitry Andric FeatureFPARMv8_D16_SP, 12210b57cec5SDimitry Andric FeaturePrefLoopAlign32, 12220b57cec5SDimitry Andric FeatureHasSlowFPVMLx, 1223480093f4SDimitry Andric FeatureHasSlowFPVFMx, 12240b57cec5SDimitry Andric FeatureUseMISched, 12250b57cec5SDimitry Andric FeatureHasNoBranchPredictor]>; 12260b57cec5SDimitry Andric 12275ffd83dbSDimitry Andricdef : ProcessorModel<"cortex-m55", CortexM4Model, [ARMv81mMainline, 12285ffd83dbSDimitry Andric FeatureDSP, 12295ffd83dbSDimitry Andric FeatureFPARMv8_D16, 12305ffd83dbSDimitry Andric FeatureUseMISched, 12315ffd83dbSDimitry Andric FeatureHasNoBranchPredictor, 12325ffd83dbSDimitry Andric FeaturePrefLoopAlign32, 12335ffd83dbSDimitry Andric FeatureHasSlowFPVMLx, 12345ffd83dbSDimitry Andric HasMVEFloatOps]>; 12350b57cec5SDimitry Andric 12360b57cec5SDimitry Andricdef : ProcNoItin<"cortex-a32", [ARMv8a, 12370b57cec5SDimitry Andric FeatureHWDivThumb, 12380b57cec5SDimitry Andric FeatureHWDivARM, 12390b57cec5SDimitry Andric FeatureCrypto, 12400b57cec5SDimitry Andric FeatureCRC]>; 12410b57cec5SDimitry Andric 12420b57cec5SDimitry Andricdef : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, 12430b57cec5SDimitry Andric FeatureHWDivThumb, 12440b57cec5SDimitry Andric FeatureHWDivARM, 12450b57cec5SDimitry Andric FeatureCrypto, 12460b57cec5SDimitry Andric FeatureCRC]>; 12470b57cec5SDimitry Andric 12480b57cec5SDimitry Andricdef : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, 12490b57cec5SDimitry Andric FeatureHWDivThumb, 12500b57cec5SDimitry Andric FeatureHWDivARM, 12510b57cec5SDimitry Andric FeatureCrypto, 12520b57cec5SDimitry Andric FeatureCRC, 12530b57cec5SDimitry Andric FeatureFPAO]>; 12540b57cec5SDimitry Andric 12550b57cec5SDimitry Andricdef : ProcNoItin<"cortex-a55", [ARMv82a, ProcA55, 12560b57cec5SDimitry Andric FeatureHWDivThumb, 12570b57cec5SDimitry Andric FeatureHWDivARM, 12580b57cec5SDimitry Andric FeatureDotProd]>; 12590b57cec5SDimitry Andric 12600b57cec5SDimitry Andricdef : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57, 12610b57cec5SDimitry Andric FeatureHWDivThumb, 12620b57cec5SDimitry Andric FeatureHWDivARM, 12630b57cec5SDimitry Andric FeatureCrypto, 12640b57cec5SDimitry Andric FeatureCRC, 12650b57cec5SDimitry Andric FeatureFPAO, 12660b57cec5SDimitry Andric FeatureAvoidPartialCPSR, 12670b57cec5SDimitry Andric FeatureCheapPredicableCPSR]>; 12680b57cec5SDimitry Andric 12690b57cec5SDimitry Andricdef : ProcessorModel<"cortex-a72", CortexA57Model, [ARMv8a, ProcA72, 12700b57cec5SDimitry Andric FeatureHWDivThumb, 12710b57cec5SDimitry Andric FeatureHWDivARM, 12720b57cec5SDimitry Andric FeatureCrypto, 12730b57cec5SDimitry Andric FeatureCRC]>; 12740b57cec5SDimitry Andric 12750b57cec5SDimitry Andricdef : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, 12760b57cec5SDimitry Andric FeatureHWDivThumb, 12770b57cec5SDimitry Andric FeatureHWDivARM, 12780b57cec5SDimitry Andric FeatureCrypto, 12790b57cec5SDimitry Andric FeatureCRC]>; 12800b57cec5SDimitry Andric 12810b57cec5SDimitry Andricdef : ProcNoItin<"cortex-a75", [ARMv82a, ProcA75, 12820b57cec5SDimitry Andric FeatureHWDivThumb, 12830b57cec5SDimitry Andric FeatureHWDivARM, 12840b57cec5SDimitry Andric FeatureDotProd]>; 12850b57cec5SDimitry Andric 12860b57cec5SDimitry Andricdef : ProcNoItin<"cortex-a76", [ARMv82a, ProcA76, 12870b57cec5SDimitry Andric FeatureHWDivThumb, 12880b57cec5SDimitry Andric FeatureHWDivARM, 12890b57cec5SDimitry Andric FeatureCrypto, 12900b57cec5SDimitry Andric FeatureCRC, 12910b57cec5SDimitry Andric FeatureFullFP16, 12920b57cec5SDimitry Andric FeatureDotProd]>; 12930b57cec5SDimitry Andric 12940b57cec5SDimitry Andricdef : ProcNoItin<"cortex-a76ae", [ARMv82a, ProcA76, 12950b57cec5SDimitry Andric FeatureHWDivThumb, 12960b57cec5SDimitry Andric FeatureHWDivARM, 12970b57cec5SDimitry Andric FeatureCrypto, 12980b57cec5SDimitry Andric FeatureCRC, 12990b57cec5SDimitry Andric FeatureFullFP16, 13000b57cec5SDimitry Andric FeatureDotProd]>; 13010b57cec5SDimitry Andric 13025ffd83dbSDimitry Andricdef : ProcNoItin<"cortex-a77", [ARMv82a, ProcA77, 13035ffd83dbSDimitry Andric FeatureHWDivThumb, 13045ffd83dbSDimitry Andric FeatureHWDivARM, 13055ffd83dbSDimitry Andric FeatureCrypto, 13065ffd83dbSDimitry Andric FeatureCRC, 13075ffd83dbSDimitry Andric FeatureFullFP16, 13085ffd83dbSDimitry Andric FeatureDotProd]>; 13095ffd83dbSDimitry Andric 13105ffd83dbSDimitry Andricdef : ProcNoItin<"cortex-a78", [ARMv82a, ProcA78, 13115ffd83dbSDimitry Andric FeatureHWDivThumb, 13125ffd83dbSDimitry Andric FeatureHWDivARM, 13135ffd83dbSDimitry Andric FeatureCrypto, 13145ffd83dbSDimitry Andric FeatureCRC, 13155ffd83dbSDimitry Andric FeatureFullFP16, 13165ffd83dbSDimitry Andric FeatureDotProd]>; 13175ffd83dbSDimitry Andric 1318e8d8bef9SDimitry Andricdef : ProcNoItin<"cortex-a78c", [ARMv82a, ProcA78C, 1319e8d8bef9SDimitry Andric FeatureHWDivThumb, 1320e8d8bef9SDimitry Andric FeatureHWDivARM, 1321e8d8bef9SDimitry Andric FeatureCrypto, 1322e8d8bef9SDimitry Andric FeatureCRC, 1323e8d8bef9SDimitry Andric FeatureDotProd, 1324e8d8bef9SDimitry Andric FeatureFullFP16]>; 1325e8d8bef9SDimitry Andric 13265ffd83dbSDimitry Andricdef : ProcNoItin<"cortex-x1", [ARMv82a, ProcX1, 13275ffd83dbSDimitry Andric FeatureHWDivThumb, 13285ffd83dbSDimitry Andric FeatureHWDivARM, 13295ffd83dbSDimitry Andric FeatureCrypto, 13305ffd83dbSDimitry Andric FeatureCRC, 13315ffd83dbSDimitry Andric FeatureFullFP16, 13325ffd83dbSDimitry Andric FeatureDotProd]>; 13335ffd83dbSDimitry Andric 1334e8d8bef9SDimitry Andricdef : ProcNoItin<"neoverse-v1", [ARMv84a, 1335e8d8bef9SDimitry Andric FeatureHWDivThumb, 1336e8d8bef9SDimitry Andric FeatureHWDivARM, 1337e8d8bef9SDimitry Andric FeatureCrypto, 1338e8d8bef9SDimitry Andric FeatureCRC, 1339e8d8bef9SDimitry Andric FeatureFullFP16, 1340e8d8bef9SDimitry Andric FeatureBF16, 1341e8d8bef9SDimitry Andric FeatureMatMulInt8]>; 1342e8d8bef9SDimitry Andric 13438bcb0991SDimitry Andricdef : ProcNoItin<"neoverse-n1", [ARMv82a, 13448bcb0991SDimitry Andric FeatureHWDivThumb, 13458bcb0991SDimitry Andric FeatureHWDivARM, 13468bcb0991SDimitry Andric FeatureCrypto, 13478bcb0991SDimitry Andric FeatureCRC, 13488bcb0991SDimitry Andric FeatureDotProd]>; 13498bcb0991SDimitry Andric 1350e8d8bef9SDimitry Andricdef : ProcNoItin<"neoverse-n2", [ARMv85a, 1351e8d8bef9SDimitry Andric FeatureBF16, 1352e8d8bef9SDimitry Andric FeatureMatMulInt8, 1353e8d8bef9SDimitry Andric FeaturePerfMon]>; 1354e8d8bef9SDimitry Andric 13550b57cec5SDimitry Andricdef : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, 13560b57cec5SDimitry Andric FeatureHasRetAddrStack, 13570b57cec5SDimitry Andric FeatureNEONForFP, 13580b57cec5SDimitry Andric FeatureVFP4, 13590b57cec5SDimitry Andric FeatureMP, 13600b57cec5SDimitry Andric FeatureHWDivThumb, 13610b57cec5SDimitry Andric FeatureHWDivARM, 13620b57cec5SDimitry Andric FeatureAvoidPartialCPSR, 13630b57cec5SDimitry Andric FeatureAvoidMOVsShOp, 13640b57cec5SDimitry Andric FeatureHasSlowFPVMLx, 1365480093f4SDimitry Andric FeatureHasSlowFPVFMx, 13660b57cec5SDimitry Andric FeatureCrypto, 13670b57cec5SDimitry Andric FeatureUseMISched, 13680b57cec5SDimitry Andric FeatureZCZeroing, 13690b57cec5SDimitry Andric FeatureNoPostRASched]>; 13700b57cec5SDimitry Andric 13710b57cec5SDimitry Andricdef : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynos]>; 13720b57cec5SDimitry Andricdef : ProcNoItin<"exynos-m4", [ARMv82a, ProcExynos, 13730b57cec5SDimitry Andric FeatureFullFP16, 13740b57cec5SDimitry Andric FeatureDotProd]>; 13750b57cec5SDimitry Andricdef : ProcNoItin<"exynos-m5", [ARMv82a, ProcExynos, 13760b57cec5SDimitry Andric FeatureFullFP16, 13770b57cec5SDimitry Andric FeatureDotProd]>; 13780b57cec5SDimitry Andric 13790b57cec5SDimitry Andricdef : ProcNoItin<"kryo", [ARMv8a, ProcKryo, 13800b57cec5SDimitry Andric FeatureHWDivThumb, 13810b57cec5SDimitry Andric FeatureHWDivARM, 13820b57cec5SDimitry Andric FeatureCrypto, 13830b57cec5SDimitry Andric FeatureCRC]>; 13840b57cec5SDimitry Andric 13850b57cec5SDimitry Andricdef : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, 13860b57cec5SDimitry Andric FeatureUseMISched, 1387480093f4SDimitry Andric FeatureFPAO]>; 13880b57cec5SDimitry Andric 13890b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 13900b57cec5SDimitry Andric// Declare the target which we are implementing 13910b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 13920b57cec5SDimitry Andric 13930b57cec5SDimitry Andricdef ARMAsmWriter : AsmWriter { 13940b57cec5SDimitry Andric string AsmWriterClassName = "InstPrinter"; 13950b57cec5SDimitry Andric int PassSubtarget = 1; 13960b57cec5SDimitry Andric int Variant = 0; 13970b57cec5SDimitry Andric bit isMCAsmWriter = 1; 13980b57cec5SDimitry Andric} 13990b57cec5SDimitry Andric 14000b57cec5SDimitry Andricdef ARMAsmParser : AsmParser { 14010b57cec5SDimitry Andric bit ReportMultipleNearMisses = 1; 14020b57cec5SDimitry Andric} 14030b57cec5SDimitry Andric 14040b57cec5SDimitry Andricdef ARMAsmParserVariant : AsmParserVariant { 14050b57cec5SDimitry Andric int Variant = 0; 14060b57cec5SDimitry Andric string Name = "ARM"; 14070b57cec5SDimitry Andric string BreakCharacters = "."; 14080b57cec5SDimitry Andric} 14090b57cec5SDimitry Andric 14100b57cec5SDimitry Andricdef ARM : Target { 14110b57cec5SDimitry Andric // Pull in Instruction Info. 14120b57cec5SDimitry Andric let InstructionSet = ARMInstrInfo; 14130b57cec5SDimitry Andric let AssemblyWriters = [ARMAsmWriter]; 14140b57cec5SDimitry Andric let AssemblyParsers = [ARMAsmParser]; 14150b57cec5SDimitry Andric let AssemblyParserVariants = [ARMAsmParserVariant]; 14160b57cec5SDimitry Andric let AllowRegisterRenaming = 1; 14170b57cec5SDimitry Andric} 1418