10b57cec5SDimitry Andric //===-- ARM.h - Top-level interface for ARM representation ------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file contains the entry points for global functions defined in the LLVM 100b57cec5SDimitry Andric // ARM back-end. 110b57cec5SDimitry Andric // 120b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_ARM_ARM_H 150b57cec5SDimitry Andric #define LLVM_LIB_TARGET_ARM_ARM_H 160b57cec5SDimitry Andric 170b57cec5SDimitry Andric #include "llvm/IR/LegacyPassManager.h" 180b57cec5SDimitry Andric #include "llvm/Support/CodeGen.h" 190b57cec5SDimitry Andric #include <functional> 200b57cec5SDimitry Andric #include <vector> 210b57cec5SDimitry Andric 220b57cec5SDimitry Andric namespace llvm { 230b57cec5SDimitry Andric 240b57cec5SDimitry Andric class ARMAsmPrinter; 250b57cec5SDimitry Andric class ARMBaseTargetMachine; 260b57cec5SDimitry Andric class ARMRegisterBankInfo; 270b57cec5SDimitry Andric class ARMSubtarget; 280b57cec5SDimitry Andric struct BasicBlockInfo; 290b57cec5SDimitry Andric class Function; 300b57cec5SDimitry Andric class FunctionPass; 310b57cec5SDimitry Andric class InstructionSelector; 320b57cec5SDimitry Andric class MachineBasicBlock; 330b57cec5SDimitry Andric class MachineFunction; 340b57cec5SDimitry Andric class MachineInstr; 350b57cec5SDimitry Andric class MCInst; 360b57cec5SDimitry Andric class PassRegistry; 370b57cec5SDimitry Andric 388bcb0991SDimitry Andric Pass *createMVETailPredicationPass(); 390b57cec5SDimitry Andric FunctionPass *createARMLowOverheadLoopsPass(); 40*e8d8bef9SDimitry Andric FunctionPass *createARMBlockPlacementPass(); 410b57cec5SDimitry Andric Pass *createARMParallelDSPPass(); 420b57cec5SDimitry Andric FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM, 430b57cec5SDimitry Andric CodeGenOpt::Level OptLevel); 440b57cec5SDimitry Andric FunctionPass *createA15SDOptimizerPass(); 450b57cec5SDimitry Andric FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false); 460b57cec5SDimitry Andric FunctionPass *createARMExpandPseudoPass(); 470b57cec5SDimitry Andric FunctionPass *createARMConstantIslandPass(); 480b57cec5SDimitry Andric FunctionPass *createMLxExpansionPass(); 490b57cec5SDimitry Andric FunctionPass *createThumb2ITBlockPass(); 500b57cec5SDimitry Andric FunctionPass *createMVEVPTBlockPass(); 515ffd83dbSDimitry Andric FunctionPass *createMVEVPTOptimisationsPass(); 520b57cec5SDimitry Andric FunctionPass *createARMOptimizeBarriersPass(); 530b57cec5SDimitry Andric FunctionPass *createThumb2SizeReductionPass( 540b57cec5SDimitry Andric std::function<bool(const Function &)> Ftor = nullptr); 550b57cec5SDimitry Andric InstructionSelector * 560b57cec5SDimitry Andric createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, 570b57cec5SDimitry Andric const ARMRegisterBankInfo &RBI); 58480093f4SDimitry Andric Pass *createMVEGatherScatterLoweringPass(); 59*e8d8bef9SDimitry Andric FunctionPass *createARMSLSHardeningPass(); 60*e8d8bef9SDimitry Andric FunctionPass *createARMIndirectThunks(); 610b57cec5SDimitry Andric 620b57cec5SDimitry Andric void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, 630b57cec5SDimitry Andric ARMAsmPrinter &AP); 640b57cec5SDimitry Andric 650b57cec5SDimitry Andric void initializeARMParallelDSPPass(PassRegistry &); 660b57cec5SDimitry Andric void initializeARMLoadStoreOptPass(PassRegistry &); 670b57cec5SDimitry Andric void initializeARMPreAllocLoadStoreOptPass(PassRegistry &); 680b57cec5SDimitry Andric void initializeARMConstantIslandsPass(PassRegistry &); 690b57cec5SDimitry Andric void initializeARMExpandPseudoPass(PassRegistry &); 700b57cec5SDimitry Andric void initializeThumb2SizeReducePass(PassRegistry &); 710b57cec5SDimitry Andric void initializeThumb2ITBlockPass(PassRegistry &); 720b57cec5SDimitry Andric void initializeMVEVPTBlockPass(PassRegistry &); 735ffd83dbSDimitry Andric void initializeMVEVPTOptimisationsPass(PassRegistry &); 740b57cec5SDimitry Andric void initializeARMLowOverheadLoopsPass(PassRegistry &); 75*e8d8bef9SDimitry Andric void initializeARMBlockPlacementPass(PassRegistry &); 768bcb0991SDimitry Andric void initializeMVETailPredicationPass(PassRegistry &); 77480093f4SDimitry Andric void initializeMVEGatherScatterLoweringPass(PassRegistry &); 78*e8d8bef9SDimitry Andric void initializeARMSLSHardeningPass(PassRegistry &); 790b57cec5SDimitry Andric 800b57cec5SDimitry Andric } // end namespace llvm 810b57cec5SDimitry Andric 820b57cec5SDimitry Andric #endif // LLVM_LIB_TARGET_ARM_ARM_H 83