1*0b57cec5SDimitry Andric //===-- ARM.h - Top-level interface for ARM representation ------*- C++ -*-===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric // 9*0b57cec5SDimitry Andric // This file contains the entry points for global functions defined in the LLVM 10*0b57cec5SDimitry Andric // ARM back-end. 11*0b57cec5SDimitry Andric // 12*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 13*0b57cec5SDimitry Andric 14*0b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_ARM_ARM_H 15*0b57cec5SDimitry Andric #define LLVM_LIB_TARGET_ARM_ARM_H 16*0b57cec5SDimitry Andric 17*0b57cec5SDimitry Andric #include "llvm/IR/LegacyPassManager.h" 18*0b57cec5SDimitry Andric #include "llvm/Support/CodeGen.h" 19*0b57cec5SDimitry Andric #include <functional> 20*0b57cec5SDimitry Andric #include <vector> 21*0b57cec5SDimitry Andric 22*0b57cec5SDimitry Andric namespace llvm { 23*0b57cec5SDimitry Andric 24*0b57cec5SDimitry Andric class ARMAsmPrinter; 25*0b57cec5SDimitry Andric class ARMBaseTargetMachine; 26*0b57cec5SDimitry Andric class ARMRegisterBankInfo; 27*0b57cec5SDimitry Andric class ARMSubtarget; 28*0b57cec5SDimitry Andric struct BasicBlockInfo; 29*0b57cec5SDimitry Andric class Function; 30*0b57cec5SDimitry Andric class FunctionPass; 31*0b57cec5SDimitry Andric class InstructionSelector; 32*0b57cec5SDimitry Andric class MachineBasicBlock; 33*0b57cec5SDimitry Andric class MachineFunction; 34*0b57cec5SDimitry Andric class MachineInstr; 35*0b57cec5SDimitry Andric class MCInst; 36*0b57cec5SDimitry Andric class PassRegistry; 37*0b57cec5SDimitry Andric 38*0b57cec5SDimitry Andric FunctionPass *createARMLowOverheadLoopsPass(); 39*0b57cec5SDimitry Andric Pass *createARMParallelDSPPass(); 40*0b57cec5SDimitry Andric FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM, 41*0b57cec5SDimitry Andric CodeGenOpt::Level OptLevel); 42*0b57cec5SDimitry Andric FunctionPass *createA15SDOptimizerPass(); 43*0b57cec5SDimitry Andric FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false); 44*0b57cec5SDimitry Andric FunctionPass *createARMExpandPseudoPass(); 45*0b57cec5SDimitry Andric FunctionPass *createARMCodeGenPreparePass(); 46*0b57cec5SDimitry Andric FunctionPass *createARMConstantIslandPass(); 47*0b57cec5SDimitry Andric FunctionPass *createMLxExpansionPass(); 48*0b57cec5SDimitry Andric FunctionPass *createThumb2ITBlockPass(); 49*0b57cec5SDimitry Andric FunctionPass *createMVEVPTBlockPass(); 50*0b57cec5SDimitry Andric FunctionPass *createARMOptimizeBarriersPass(); 51*0b57cec5SDimitry Andric FunctionPass *createThumb2SizeReductionPass( 52*0b57cec5SDimitry Andric std::function<bool(const Function &)> Ftor = nullptr); 53*0b57cec5SDimitry Andric InstructionSelector * 54*0b57cec5SDimitry Andric createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, 55*0b57cec5SDimitry Andric const ARMRegisterBankInfo &RBI); 56*0b57cec5SDimitry Andric 57*0b57cec5SDimitry Andric void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, 58*0b57cec5SDimitry Andric ARMAsmPrinter &AP); 59*0b57cec5SDimitry Andric 60*0b57cec5SDimitry Andric void initializeARMParallelDSPPass(PassRegistry &); 61*0b57cec5SDimitry Andric void initializeARMLoadStoreOptPass(PassRegistry &); 62*0b57cec5SDimitry Andric void initializeARMPreAllocLoadStoreOptPass(PassRegistry &); 63*0b57cec5SDimitry Andric void initializeARMCodeGenPreparePass(PassRegistry &); 64*0b57cec5SDimitry Andric void initializeARMConstantIslandsPass(PassRegistry &); 65*0b57cec5SDimitry Andric void initializeARMExpandPseudoPass(PassRegistry &); 66*0b57cec5SDimitry Andric void initializeThumb2SizeReducePass(PassRegistry &); 67*0b57cec5SDimitry Andric void initializeThumb2ITBlockPass(PassRegistry &); 68*0b57cec5SDimitry Andric void initializeMVEVPTBlockPass(PassRegistry &); 69*0b57cec5SDimitry Andric void initializeARMLowOverheadLoopsPass(PassRegistry &); 70*0b57cec5SDimitry Andric 71*0b57cec5SDimitry Andric } // end namespace llvm 72*0b57cec5SDimitry Andric 73*0b57cec5SDimitry Andric #endif // LLVM_LIB_TARGET_ARM_ARM_H 74