1//===- ARC.td - Describe the ARC Target Machine ------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/Target/Target.td" 10 11//===----------------------------------------------------------------------===// 12// ARC Subtarget features 13//===----------------------------------------------------------------------===// 14 15def FeatureNORM 16 : SubtargetFeature<"norm", "Xnorm", "true", 17 "Enable support for norm instruction.">; 18 19//===----------------------------------------------------------------------===// 20// Registers, calling conventions, instruction descriptions 21//===----------------------------------------------------------------------===// 22 23include "ARCRegisterInfo.td" 24include "ARCInstrInfo.td" 25include "ARCCallingConv.td" 26 27def ARCInstrInfo : InstrInfo; 28 29class Proc<string Name, list<SubtargetFeature> Features> 30 : Processor<Name, NoItineraries, Features>; 31 32def : Proc<"generic", []>; 33 34def ARC : Target { 35 let InstructionSet = ARCInstrInfo; 36} 37