1*0b57cec5SDimitry Andric//===- ARC.td - Describe the ARC Target Machine ------------*- tablegen -*-===// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric 9*0b57cec5SDimitry Andricinclude "llvm/Target/Target.td" 10*0b57cec5SDimitry Andric 11*0b57cec5SDimitry Andricinclude "ARCRegisterInfo.td" 12*0b57cec5SDimitry Andricinclude "ARCInstrInfo.td" 13*0b57cec5SDimitry Andricinclude "ARCCallingConv.td" 14*0b57cec5SDimitry Andric 15*0b57cec5SDimitry Andricdef ARCInstrInfo : InstrInfo; 16*0b57cec5SDimitry Andric 17*0b57cec5SDimitry Andricclass Proc<string Name, list<SubtargetFeature> Features> 18*0b57cec5SDimitry Andric : Processor<Name, NoItineraries, Features>; 19*0b57cec5SDimitry Andric 20*0b57cec5SDimitry Andricdef : Proc<"generic", []>; 21*0b57cec5SDimitry Andric 22*0b57cec5SDimitry Andricdef ARC : Target { 23*0b57cec5SDimitry Andric let InstructionSet = ARCInstrInfo; 24*0b57cec5SDimitry Andric} 25