xref: /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ARC.td (revision fe6060f10f634930ff71b7c50291ddc610da2475)
10b57cec5SDimitry Andric//===- ARC.td - Describe the ARC Target Machine ------------*- tablegen -*-===//
20b57cec5SDimitry Andric//
30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric//
70b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric
90b57cec5SDimitry Andricinclude "llvm/Target/Target.td"
100b57cec5SDimitry Andric
11*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===//
12*fe6060f1SDimitry Andric// ARC Subtarget features
13*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===//
14*fe6060f1SDimitry Andric
15*fe6060f1SDimitry Andricdef FeatureNORM
16*fe6060f1SDimitry Andric    : SubtargetFeature<"norm", "Xnorm", "true",
17*fe6060f1SDimitry Andric                       "Enable support for norm instruction.">;
18*fe6060f1SDimitry Andric
19*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===//
20*fe6060f1SDimitry Andric// Registers, calling conventions, instruction descriptions
21*fe6060f1SDimitry Andric//===----------------------------------------------------------------------===//
22*fe6060f1SDimitry Andric
230b57cec5SDimitry Andricinclude "ARCRegisterInfo.td"
240b57cec5SDimitry Andricinclude "ARCInstrInfo.td"
250b57cec5SDimitry Andricinclude "ARCCallingConv.td"
260b57cec5SDimitry Andric
270b57cec5SDimitry Andricdef ARCInstrInfo : InstrInfo;
280b57cec5SDimitry Andric
290b57cec5SDimitry Andricclass Proc<string Name, list<SubtargetFeature> Features>
300b57cec5SDimitry Andric : Processor<Name, NoItineraries, Features>;
310b57cec5SDimitry Andric
320b57cec5SDimitry Andricdef : Proc<"generic", []>;
330b57cec5SDimitry Andric
340b57cec5SDimitry Andricdef ARC : Target {
350b57cec5SDimitry Andric  let InstructionSet = ARCInstrInfo;
360b57cec5SDimitry Andric}
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