1//===-- VOPInstructions.td - Vector Instruction Definitions ---------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// dummies for outer let 10class LetDummies { 11 bit TRANS; 12 bit ReadsModeReg; 13 bit mayRaiseFPException; 14 bit isCommutable; 15 bit isConvertibleToThreeAddress; 16 bit isMoveImm; 17 bit isReMaterializable; 18 bit isAsCheapAsAMove; 19 bit VOPAsmPrefer32Bit; 20 bit FPDPRounding; 21 Predicate SubtargetPredicate; 22 string Constraints; 23 string DisableEncoding; 24 list<SchedReadWrite> SchedRW; 25 list<Register> Uses; 26 list<Register> Defs; 27} 28 29class VOP <string opName> { 30 string OpName = opName; 31} 32 33class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> : 34 InstSI <outs, ins, asm, pattern> { 35 36 let mayLoad = 0; 37 let mayStore = 0; 38 let hasSideEffects = 0; 39 let UseNamedOperandTable = 1; 40 let VALU = 1; 41 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 42} 43 44class VOP_Pseudo <string opName, string suffix, VOPProfile P, dag outs, dag ins, 45 string asm, list<dag> pattern> : 46 InstSI <outs, ins, asm, pattern>, 47 VOP <opName>, 48 SIMCInstr <opName#suffix, SIEncodingFamily.NONE> { 49 let isPseudo = 1; 50 let isCodeGenOnly = 1; 51 let UseNamedOperandTable = 1; 52 53 string Mnemonic = opName; 54 VOPProfile Pfl = P; 55 56 string AsmOperands; 57} 58 59class VOP3Common <dag outs, dag ins, string asm = "", 60 list<dag> pattern = [], bit HasMods = 0> : 61 VOPAnyCommon <outs, ins, asm, pattern> { 62 63 // Using complex patterns gives VOP3 patterns a very high complexity rating, 64 // but standalone patterns are almost always preferred, so we need to adjust the 65 // priority lower. The goal is to use a high number to reduce complexity to 66 // zero (or less than zero). 67 let AddedComplexity = -1000; 68 69 let VOP3 = 1; 70 71 let AsmVariantName = AMDGPUAsmVariants.VOP3; 72 let AsmMatchConverter = !if(HasMods, "cvtVOP3", ""); 73 74 let isCodeGenOnly = 0; 75 76 int Size = 8; 77 78 // Because SGPRs may be allowed if there are multiple operands, we 79 // need a post-isel hook to insert copies in order to avoid 80 // violating constant bus requirements. 81 let hasPostISelHook = 1; 82} 83 84class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [], 85 bit isVOP3P = 0, bit isVop3OpSel = 0> : 86 VOP_Pseudo <opName, "_e64", P, P.Outs64, 87 !if(isVop3OpSel, 88 P.InsVOP3OpSel, 89 !if(!and(isVOP3P, P.IsPacked), P.InsVOP3P, P.Ins64)), 90 "", pattern> { 91 92 let VOP3_OPSEL = isVop3OpSel; 93 let IsPacked = P.IsPacked; 94 let IsMAI = P.IsMAI; 95 96 let AsmOperands = !if(isVop3OpSel, 97 P.AsmVOP3OpSel, 98 !if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64)); 99 100 let Size = 8; 101 let mayLoad = 0; 102 let mayStore = 0; 103 let hasSideEffects = 0; 104 105 // Because SGPRs may be allowed if there are multiple operands, we 106 // need a post-isel hook to insert copies in order to avoid 107 // violating constant bus requirements. 108 let hasPostISelHook = 1; 109 110 // Using complex patterns gives VOP3 patterns a very high complexity rating, 111 // but standalone patterns are almost always preferred, so we need to adjust the 112 // priority lower. The goal is to use a high number to reduce complexity to 113 // zero (or less than zero). 114 let AddedComplexity = -1000; 115 116 let VOP3 = 1; 117 let VALU = 1; 118 let FPClamp = P.HasFPClamp; 119 let IntClamp = P.HasIntClamp; 120 let ClampLo = P.HasClampLo; 121 let ClampHi = P.HasClampHi; 122 123 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 124 125 let mayRaiseFPException = ReadsModeReg; 126 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 127 128 let AsmVariantName = AMDGPUAsmVariants.VOP3; 129 let AsmMatchConverter = 130 !if(isVOP3P, 131 "cvtVOP3P", 132 !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), 133 "cvtVOP3", 134 "")); 135} 136 137class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> : 138 VOP3_Pseudo<opName, P, pattern, 1> { 139 let VOP3P = 1; 140} 141 142class VOP_Real<VOP_Pseudo ps> { 143 Instruction Opcode = !cast<Instruction>(NAME); 144 bit IsSingle = ps.Pfl.IsSingle; 145} 146 147class VOP3_Real <VOP_Pseudo ps, int EncodingFamily> : 148 VOP_Real <ps>, 149 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 150 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 151 152 let VALU = 1; 153 let VOP3 = 1; 154 let isPseudo = 0; 155 let isCodeGenOnly = 0; 156 let UseNamedOperandTable = 1; 157 158 let Constraints = ps.Constraints; 159 let DisableEncoding = ps.DisableEncoding; 160 161 // copy relevant pseudo op flags 162 let SubtargetPredicate = ps.SubtargetPredicate; 163 let OtherPredicates = ps.OtherPredicates; 164 let AsmMatchConverter = ps.AsmMatchConverter; 165 let AsmVariantName = ps.AsmVariantName; 166 let Constraints = ps.Constraints; 167 let DisableEncoding = ps.DisableEncoding; 168 let TSFlags = ps.TSFlags; 169 let UseNamedOperandTable = ps.UseNamedOperandTable; 170 let Uses = ps.Uses; 171 let Defs = ps.Defs; 172 let SchedRW = ps.SchedRW; 173 let mayLoad = ps.mayLoad; 174 let mayStore = ps.mayStore; 175 let TRANS = ps.TRANS; 176 177 VOPProfile Pfl = ps.Pfl; 178} 179 180// XXX - Is there any reason to distinguish this from regular VOP3 181// here? 182class VOP3P_Real<VOP_Pseudo ps, int EncodingFamily> : 183 VOP3_Real<ps, EncodingFamily>; 184 185class VOP3a<VOPProfile P> : Enc64 { 186 bits<4> src0_modifiers; 187 bits<9> src0; 188 bits<3> src1_modifiers; 189 bits<9> src1; 190 bits<3> src2_modifiers; 191 bits<9> src2; 192 bits<1> clamp; 193 bits<2> omod; 194 195 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 196 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); 197 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); 198 199 let Inst{31-26} = 0x34; //encoding 200 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 201 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 202 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 203 let Inst{60-59} = !if(P.HasOMod, omod, 0); 204 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 205 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 206 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 207} 208 209class VOP3a_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a<p> { 210 let Inst{11} = !if(p.HasClamp, clamp{0}, 0); 211 let Inst{25-17} = op; 212} 213 214class VOP3a_gfx10<bits<10> op, VOPProfile p> : VOP3a<p> { 215 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 216 let Inst{25-16} = op; 217 let Inst{31-26} = 0x35; 218} 219 220class VOP3a_vi <bits<10> op, VOPProfile P> : VOP3a<P> { 221 let Inst{25-16} = op; 222 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 223} 224 225class VOP3e_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a_gfx6_gfx7<op, p> { 226 bits<8> vdst; 227 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 228} 229 230class VOP3e_gfx10<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p> { 231 bits<8> vdst; 232 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 233} 234 235class VOP3e_vi <bits<10> op, VOPProfile P> : VOP3a_vi <op, P> { 236 bits<8> vdst; 237 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0); 238} 239 240class VOP3OpSel_gfx9 <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 241 let Inst{11} = !if(P.HasSrc0, src0_modifiers{2}, 0); 242 let Inst{12} = !if(P.HasSrc1, src1_modifiers{2}, 0); 243 let Inst{13} = !if(P.HasSrc2, src2_modifiers{2}, 0); 244 let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0); 245} 246 247class VOP3OpSel_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 248 let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0); 249 let Inst{12} = !if(p.HasSrc1, src1_modifiers{2}, 0); 250 let Inst{13} = !if(p.HasSrc2, src2_modifiers{2}, 0); 251 let Inst{14} = !if(p.HasDst, src0_modifiers{3}, 0); 252} 253 254// NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa 255class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 256 bits<2> attrchan; 257 bits<6> attr; 258 bits<1> high; 259 260 let Inst{8} = 0; // No modifiers for src0 261 let Inst{61} = 0; 262 263 let Inst{9} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 264 let Inst{62} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 265 266 let Inst{37-32} = attr; 267 let Inst{39-38} = attrchan; 268 let Inst{40} = !if(P.HasHigh, high, 0); 269 270 let Inst{49-41} = src0; 271} 272 273class VOP3Interp_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 274 bits<6> attr; 275 bits<2> attrchan; 276 bits<1> high; 277 278 let Inst{8} = 0; 279 let Inst{9} = !if(p.HasSrc0Mods, src0_modifiers{1}, 0); 280 let Inst{37-32} = attr; 281 let Inst{39-38} = attrchan; 282 let Inst{40} = !if(p.HasHigh, high, 0); 283 let Inst{49-41} = src0; 284 let Inst{61} = 0; 285 let Inst{62} = !if(p.HasSrc0Mods, src0_modifiers{0}, 0); 286} 287 288class VOP3be <VOPProfile P> : Enc64 { 289 bits<8> vdst; 290 bits<2> src0_modifiers; 291 bits<9> src0; 292 bits<2> src1_modifiers; 293 bits<9> src1; 294 bits<2> src2_modifiers; 295 bits<9> src2; 296 bits<7> sdst; 297 bits<2> omod; 298 299 let Inst{7-0} = vdst; 300 let Inst{14-8} = sdst; 301 let Inst{31-26} = 0x34; //encoding 302 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 303 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 304 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 305 let Inst{60-59} = !if(P.HasOMod, omod, 0); 306 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 307 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 308 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 309} 310 311class VOP3Pe <bits<7> op, VOPProfile P> : Enc64 { 312 bits<8> vdst; 313 // neg, neg_hi, op_sel put in srcN_modifiers 314 bits<4> src0_modifiers; 315 bits<9> src0; 316 bits<4> src1_modifiers; 317 bits<9> src1; 318 bits<4> src2_modifiers; 319 bits<9> src2; 320 bits<1> clamp; 321 322 let Inst{7-0} = vdst; 323 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0 324 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1 325 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2 326 327 let Inst{11} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{2}, 0); // op_sel(0) 328 let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1) 329 let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2) 330 331 let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, ?); // op_sel_hi(2) 332 333 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 334 335 let Inst{22-16} = op; 336 let Inst{31-23} = 0x1a7; //encoding 337 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 338 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 339 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 340 let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, ?); // op_sel_hi(0) 341 let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, ?); // op_sel_hi(1) 342 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo) 343 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo) 344 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo) 345} 346 347class VOP3Pe_MAI <bits<7> op, VOPProfile P, bit acc_cd = 0> : Enc64 { 348 bits<8> vdst; 349 bits<10> src0; 350 bits<10> src1; 351 bits<9> src2; 352 bits<3> blgp; 353 bits<3> cbsz; 354 bits<4> abid; 355 356 let Inst{7-0} = vdst; 357 358 let Inst{10-8} = !if(P.HasSrc1, cbsz, 0); 359 let Inst{14-11} = !if(P.HasSrc1, abid, 0); 360 361 let Inst{15} = acc_cd; 362 363 let Inst{22-16} = op; 364 let Inst{31-23} = 0x1a7; //encoding 365 let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0); 366 let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0); 367 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 368 369 let Inst{59} = !if(P.HasSrc0, src0{9}, 0); // acc(0) 370 let Inst{60} = !if(P.HasSrc1, src1{9}, 0); // acc(1) 371 372 let Inst{63-61} = !if(P.HasSrc1, blgp, 0); 373} 374 375 376class VOP3Pe_gfx10 <bits<7> op, VOPProfile P> : VOP3Pe<op, P> { 377 let Inst{31-23} = 0x198; //encoding 378} 379 380class VOP3be_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3be<p> { 381 let Inst{25-17} = op; 382} 383 384class VOP3be_gfx10<bits<10> op, VOPProfile p> : VOP3be<p> { 385 bits<1> clamp; 386 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 387 let Inst{25-16} = op; 388 let Inst{31-26} = 0x35; 389} 390 391class VOP3be_vi <bits<10> op, VOPProfile P> : VOP3be<P> { 392 bits<1> clamp; 393 let Inst{25-16} = op; 394 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 395} 396 397def SDWA { 398 // sdwa_sel 399 int BYTE_0 = 0; 400 int BYTE_1 = 1; 401 int BYTE_2 = 2; 402 int BYTE_3 = 3; 403 int WORD_0 = 4; 404 int WORD_1 = 5; 405 int DWORD = 6; 406 407 // dst_unused 408 int UNUSED_PAD = 0; 409 int UNUSED_SEXT = 1; 410 int UNUSED_PRESERVE = 2; 411} 412 413class VOP_SDWAe<VOPProfile P> : Enc64 { 414 bits<8> src0; 415 bits<3> src0_sel; 416 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 417 bits<3> src1_sel; 418 bits<2> src1_modifiers; 419 bits<3> dst_sel; 420 bits<2> dst_unused; 421 bits<1> clamp; 422 423 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 424 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?); 425 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?); 426 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 427 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 428 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 429 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 430 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 431 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 432 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 433} 434 435// GFX9 adds two features to SDWA: 436// 1. Add 3 fields to the SDWA microcode word: S0, S1 and OMOD. 437// a. S0 and S1 indicate that source 0 and 1 respectively are SGPRs rather 438// than VGPRs (at most 1 can be an SGPR); 439// b. OMOD is the standard output modifier (result *2, *4, /2) 440// 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This 441// replaces OMOD and the dest fields with SD and SDST (SGPR destination) 442// field. 443// a. When SD=1, the SDST is used as the destination for the compare result; 444// b. When SD=0, VCC is used. 445// 446// In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA 447 448// gfx9 SDWA basic encoding 449class VOP_SDWA9e<VOPProfile P> : Enc64 { 450 bits<9> src0; // {src0_sgpr{0}, src0{7-0}} 451 bits<3> src0_sel; 452 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 453 bits<3> src1_sel; 454 bits<2> src1_modifiers; 455 bits<1> src1_sgpr; 456 457 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 458 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 459 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 460 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 461 let Inst{55} = !if(P.HasSrc0, src0{8}, 0); 462 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 463 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 464 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 465 let Inst{63} = 0; // src1_sgpr - should be specified in subclass 466} 467 468// gfx9 SDWA-A 469class VOP_SDWA9Ae<VOPProfile P> : VOP_SDWA9e<P> { 470 bits<3> dst_sel; 471 bits<2> dst_unused; 472 bits<1> clamp; 473 bits<2> omod; 474 475 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?); 476 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?); 477 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 478 let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0); 479} 480 481// gfx9 SDWA-B 482class VOP_SDWA9Be<VOPProfile P> : VOP_SDWA9e<P> { 483 bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}} 484 485 let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, ?); 486 let Inst{47} = !if(P.EmitDst, sdst{7}, 0); 487} 488 489class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> : 490 InstSI <P.OutsSDWA, P.InsSDWA, "", pattern>, 491 VOP <opName>, 492 SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE> { 493 494 let isPseudo = 1; 495 let isCodeGenOnly = 1; 496 let UseNamedOperandTable = 1; 497 498 string Mnemonic = opName; 499 string AsmOperands = P.AsmSDWA; 500 string AsmOperands9 = P.AsmSDWA9; 501 502 let Size = 8; 503 let mayLoad = 0; 504 let mayStore = 0; 505 let hasSideEffects = 0; 506 507 let VALU = 1; 508 let SDWA = 1; 509 510 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 511 512 let mayRaiseFPException = ReadsModeReg; 513 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 514 515 let SubtargetPredicate = HasSDWA; 516 let AssemblerPredicate = HasSDWA; 517 let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA, 518 AMDGPUAsmVariants.Disable); 519 let DecoderNamespace = "SDWA"; 520 521 VOPProfile Pfl = P; 522} 523 524class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> : 525 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 526 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> { 527 528 let VALU = 1; 529 let SDWA = 1; 530 let isPseudo = 0; 531 let isCodeGenOnly = 0; 532 533 let Defs = ps.Defs; 534 let Uses = ps.Uses; 535 let hasSideEffects = ps.hasSideEffects; 536 537 let Constraints = ps.Constraints; 538 let DisableEncoding = ps.DisableEncoding; 539 540 // Copy relevant pseudo op flags 541 let SubtargetPredicate = ps.SubtargetPredicate; 542 let AssemblerPredicate = ps.AssemblerPredicate; 543 let AsmMatchConverter = ps.AsmMatchConverter; 544 let AsmVariantName = ps.AsmVariantName; 545 let UseNamedOperandTable = ps.UseNamedOperandTable; 546 let DecoderNamespace = ps.DecoderNamespace; 547 let Constraints = ps.Constraints; 548 let DisableEncoding = ps.DisableEncoding; 549 let TSFlags = ps.TSFlags; 550 let SchedRW = ps.SchedRW; 551 let mayLoad = ps.mayLoad; 552 let mayStore = ps.mayStore; 553 let TRANS = ps.TRANS; 554} 555 556class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 557 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands9, []> { 558 559 let VALU = 1; 560 let SDWA = 1; 561 let isPseudo = 0; 562 let isCodeGenOnly = 0; 563 564 let Defs = ps.Defs; 565 let Uses = ps.Uses; 566 let hasSideEffects = ps.hasSideEffects; 567 568 let Constraints = ps.Constraints; 569 let DisableEncoding = ps.DisableEncoding; 570 571 let SubtargetPredicate = HasSDWA9; 572 let AssemblerPredicate = HasSDWA9; 573 let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9, 574 AMDGPUAsmVariants.Disable); 575 let DecoderNamespace = "SDWA9"; 576 577 // Copy relevant pseudo op flags 578 let AsmMatchConverter = ps.AsmMatchConverter; 579 let UseNamedOperandTable = ps.UseNamedOperandTable; 580 let Constraints = ps.Constraints; 581 let DisableEncoding = ps.DisableEncoding; 582 let TSFlags = ps.TSFlags; 583 let SchedRW = ps.SchedRW; 584 let mayLoad = ps.mayLoad; 585 let mayStore = ps.mayStore; 586 let TRANS = ps.TRANS; 587} 588 589class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 590 Base_VOP_SDWA9_Real <ps >, 591 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>; 592 593class Base_VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : Base_VOP_SDWA9_Real<ps> { 594 let SubtargetPredicate = HasSDWA10; 595 let AssemblerPredicate = HasSDWA10; 596 let DecoderNamespace = "SDWA10"; 597} 598 599class VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : 600 Base_VOP_SDWA10_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SDWA10>; 601 602class VOP_DPPe<VOPProfile P, bit IsDPP16=0> : Enc64 { 603 bits<2> src0_modifiers; 604 bits<8> src0; 605 bits<2> src1_modifiers; 606 bits<9> dpp_ctrl; 607 bits<1> bound_ctrl; 608 bits<4> bank_mask; 609 bits<4> row_mask; 610 bit fi; 611 612 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 613 let Inst{48-40} = dpp_ctrl; 614 let Inst{50} = !if(IsDPP16, fi, ?); 615 let Inst{51} = bound_ctrl; 616 let Inst{52} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg 617 let Inst{53} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs 618 let Inst{54} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg 619 let Inst{55} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs 620 let Inst{59-56} = bank_mask; 621 let Inst{63-60} = row_mask; 622} 623 624class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 625 InstSI <P.OutsDPP, P.InsDPP, OpName#P.AsmDPP, pattern>, 626 VOP <OpName>, 627 SIMCInstr <OpName#"_dpp", SIEncodingFamily.NONE> { 628 629 let isPseudo = 1; 630 let isCodeGenOnly = 1; 631 632 let mayLoad = 0; 633 let mayStore = 0; 634 let hasSideEffects = 0; 635 let UseNamedOperandTable = 1; 636 637 let VALU = 1; 638 let DPP = 1; 639 let Size = 8; 640 641 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 642 643 let mayRaiseFPException = ReadsModeReg; 644 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 645 let isConvergent = 1; 646 647 string Mnemonic = OpName; 648 string AsmOperands = P.AsmDPP; 649 650 let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); 651 let SubtargetPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 652 let AssemblerPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 653 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 654 AMDGPUAsmVariants.Disable); 655 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 656 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 657 let DecoderNamespace = "DPP"; 658 659 VOPProfile Pfl = P; 660} 661 662class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> : 663 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 664 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 665 666 let VALU = 1; 667 let DPP = 1; 668 let isPseudo = 0; 669 let isCodeGenOnly = 0; 670 671 let Defs = ps.Defs; 672 let Uses = ps.Uses; 673 let hasSideEffects = ps.hasSideEffects; 674 675 let Constraints = ps.Constraints; 676 let DisableEncoding = ps.DisableEncoding; 677 678 // Copy relevant pseudo op flags 679 let isConvergent = ps.isConvergent; 680 let SubtargetPredicate = ps.SubtargetPredicate; 681 let AssemblerPredicate = ps.AssemblerPredicate; 682 let AsmMatchConverter = ps.AsmMatchConverter; 683 let AsmVariantName = ps.AsmVariantName; 684 let UseNamedOperandTable = ps.UseNamedOperandTable; 685 let DecoderNamespace = ps.DecoderNamespace; 686 let Constraints = ps.Constraints; 687 let DisableEncoding = ps.DisableEncoding; 688 let TSFlags = ps.TSFlags; 689 let SchedRW = ps.SchedRW; 690 let mayLoad = ps.mayLoad; 691 let mayStore = ps.mayStore; 692 let TRANS = ps.TRANS; 693} 694 695class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16, 696 dag InsDPP = !if(IsDPP16, P.InsDPP16, P.InsDPP), 697 string AsmDPP = !if(IsDPP16, P.AsmDPP16, P.AsmDPP)> : 698 InstSI <P.OutsDPP, InsDPP, OpName#AsmDPP, []>, 699 VOP_DPPe<P, IsDPP16> { 700 701 let mayLoad = 0; 702 let mayStore = 0; 703 let hasSideEffects = 0; 704 let UseNamedOperandTable = 1; 705 706 let VALU = 1; 707 let DPP = 1; 708 let Size = 8; 709 710 let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); 711 let SubtargetPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 712 let AssemblerPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 713 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 714 AMDGPUAsmVariants.Disable); 715 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 716 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 717 let DecoderNamespace = "DPP"; 718} 719 720class VOP_DPP8e<VOPProfile P> : Enc64 { 721 bits<8> src0; 722 bits<24> dpp8; 723 bits<9> fi; 724 725 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 726 let Inst{63-40} = dpp8{23-0}; 727} 728 729class VOP_DPP8<string OpName, VOPProfile P> : 730 InstSI<P.OutsDPP8, P.InsDPP8, OpName#P.AsmDPP8, []>, 731 VOP_DPP8e<P> { 732 733 let mayLoad = 0; 734 let mayStore = 0; 735 let hasSideEffects = 0; 736 let UseNamedOperandTable = 1; 737 738 let VALU = 1; 739 let DPP = 1; 740 let Size = 8; 741 742 let AsmMatchConverter = "cvtDPP8"; 743 let SubtargetPredicate = HasDPP8; 744 let AssemblerPredicate = HasDPP8; 745 let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.DPP, 746 AMDGPUAsmVariants.Disable); 747 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 748 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 749} 750 751def DPP8Mode { 752 int FI_0 = 0xE9; 753 int FI_1 = 0xEA; 754} 755 756class getNumNodeArgs<SDPatternOperator Op> { 757 SDNode N = !cast<SDNode>(Op); 758 SDTypeProfile TP = N.TypeProfile; 759 int ret = TP.NumOperands; 760} 761 762class getDivergentFrag<SDPatternOperator Op> { 763 assert !or(!isa<SDNode>(Op), !isa<PatFrags>(Op)), "Expected SDNode or PatFrags"; 764 765 int NumSrcArgs = !if(!isa<SDNode>(Op), getNumNodeArgs<Op>.ret, 766 !size(!cast<PatFrags>(Op).Operands)); 767 PatFrag ret = PatFrag < 768 !if(!eq(NumSrcArgs, 1), 769 (ops node:$src0), 770 !if(!eq(NumSrcArgs, 2), 771 (ops node:$src0, node:$src1), 772 (ops node:$src0, node:$src1, node:$src2))), 773 !if(!eq(NumSrcArgs, 1), 774 (Op $src0), 775 !if(!eq(NumSrcArgs, 2), 776 (Op $src0, $src1), 777 (Op $src0, $src1, $src2))), 778 [{ return N->isDivergent(); }] 779 >; 780} 781 782class VOPPatGen<SDPatternOperator Op, VOPProfile P> { 783 784 PatFrag Operator = getDivergentFrag < Op >.ret; 785 786 dag Ins = !foreach(tmp, P.Ins32, !subst(ins, Operator, 787 !subst(P.Src0RC32, P.Src0VT, 788 !subst(P.Src1RC32, P.Src1VT, tmp)))); 789 790 791 dag Outs = !foreach(tmp, P.Outs32, !subst(outs, set, 792 !subst(P.DstRC, P.DstVT, tmp))); 793 794 list<dag> ret = [!con(Outs, (set Ins))]; 795} 796 797class DivergentUnaryFrag<SDPatternOperator Op> : PatFrag < 798 (ops node:$src0), 799 (Op $src0), 800 [{ return N->isDivergent(); }]> { 801 // This check is unnecessary as it's captured by the result register 802 // bank constraint. 803 // 804 // FIXME: Should add a way for the emitter to recognize this is a 805 // trivially true predicate to eliminate the check. 806 let GISelPredicateCode = [{return true;}]; 807} 808 809class VOPPatOrNull<SDPatternOperator Op, VOPProfile P> { 810 list<dag> ret = !if(!ne(P.NeedPatGen,PatGenMode.NoPattern), VOPPatGen<Op, P>.ret, []); 811} 812 813class DivergentFragOrOp<SDPatternOperator Op, VOPProfile P> { 814 SDPatternOperator ret = !if(!eq(P.NeedPatGen,PatGenMode.Pattern), 815 !if(!isa<SDNode>(Op), getDivergentFrag<Op>.ret, Op), Op); 816} 817 818class getVSrcOp<ValueType vt> { 819 RegisterOperand ret = !if(!eq(vt.Size, 32), VSrc_b32, VSrc_b16); 820} 821 822// Class for binary integer operations with the clamp bit set for saturation 823// TODO: Add sub with negated inline constant pattern. 824class VOPBinOpClampPat<SDPatternOperator node, Instruction inst, ValueType vt> : 825 GCNPat<(node vt:$src0, vt:$src1), 826 (inst getVSrcOp<vt>.ret:$src0, getVSrcOp<vt>.ret:$src1, 827 DSTCLAMP.ENABLE) 828>; 829 830 831include "VOPCInstructions.td" 832include "VOP1Instructions.td" 833include "VOP2Instructions.td" 834include "VOP3Instructions.td" 835include "VOP3PInstructions.td" 836 837 838class VOPInfoTable <string Format> : GenericTable { 839 let FilterClass = Format # "_Real"; 840 let CppTypeName = "VOPInfo"; 841 let Fields = ["Opcode", "IsSingle"]; 842 843 let PrimaryKey = ["Opcode"]; 844 let PrimaryKeyName = "get" # Format # "OpcodeHelper"; 845} 846 847def VOP1InfoTable : VOPInfoTable<"VOP1">; 848def VOP2InfoTable : VOPInfoTable<"VOP2">; 849def VOP3InfoTable : VOPInfoTable<"VOP3">; 850