xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/VOPInstructions.td (revision 6966ac055c3b7a39266fb982493330df7a097997)
1//===-- VOPInstructions.td - Vector Instruction Defintions ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9// dummies for outer let
10class LetDummies {
11  bit isCommutable;
12  bit isConvertibleToThreeAddress;
13  bit isMoveImm;
14  bit isReMaterializable;
15  bit isAsCheapAsAMove;
16  bit VOPAsmPrefer32Bit;
17  Predicate SubtargetPredicate;
18  string Constraints;
19  string DisableEncoding;
20  list<SchedReadWrite> SchedRW;
21  list<Register> Uses;
22  list<Register> Defs;
23}
24
25class VOP <string opName> {
26  string OpName = opName;
27}
28
29class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
30    InstSI <outs, ins, asm, pattern> {
31
32  let mayLoad = 0;
33  let mayStore = 0;
34  let hasSideEffects = 0;
35  let UseNamedOperandTable = 1;
36  let VALU = 1;
37  let Uses = [EXEC];
38}
39
40class VOP_Pseudo <string opName, string suffix, VOPProfile P, dag outs, dag ins,
41                  string asm, list<dag> pattern> :
42  InstSI <outs, ins, asm, pattern>,
43  VOP <opName>,
44  SIMCInstr <opName#suffix, SIEncodingFamily.NONE>,
45  MnemonicAlias<opName#suffix, opName> {
46
47  let isPseudo = 1;
48  let isCodeGenOnly = 1;
49  let UseNamedOperandTable = 1;
50
51  string Mnemonic = opName;
52  VOPProfile Pfl = P;
53
54  string AsmOperands;
55}
56
57class VOP3Common <dag outs, dag ins, string asm = "",
58                  list<dag> pattern = [], bit HasMods = 0,
59                  bit VOP3Only = 0> :
60  VOPAnyCommon <outs, ins, asm, pattern> {
61
62  // Using complex patterns gives VOP3 patterns a very high complexity rating,
63  // but standalone patterns are almost always preferred, so we need to adjust the
64  // priority lower.  The goal is to use a high number to reduce complexity to
65  // zero (or less than zero).
66  let AddedComplexity = -1000;
67
68  let VOP3 = 1;
69
70  let AsmVariantName = AMDGPUAsmVariants.VOP3;
71  let AsmMatchConverter = !if(!eq(HasMods,1), "cvtVOP3", "");
72
73  let isCodeGenOnly = 0;
74
75  int Size = 8;
76
77  // Because SGPRs may be allowed if there are multiple operands, we
78  // need a post-isel hook to insert copies in order to avoid
79  // violating constant bus requirements.
80  let hasPostISelHook = 1;
81}
82
83class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
84                   bit VOP3Only = 0, bit isVOP3P = 0, bit isVop3OpSel = 0> :
85  VOP_Pseudo <opName, "_e64", P, P.Outs64,
86              !if(isVop3OpSel,
87                  P.InsVOP3OpSel,
88                  !if(!and(isVOP3P, P.IsPacked), P.InsVOP3P, P.Ins64)),
89              "", pattern> {
90
91  let VOP3_OPSEL = isVop3OpSel;
92  let IsPacked = P.IsPacked;
93  let IsMAI = P.IsMAI;
94
95  let AsmOperands = !if(isVop3OpSel,
96                        P.AsmVOP3OpSel,
97                        !if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64));
98
99  let Size = 8;
100  let mayLoad = 0;
101  let mayStore = 0;
102  let hasSideEffects = 0;
103
104  // Because SGPRs may be allowed if there are multiple operands, we
105  // need a post-isel hook to insert copies in order to avoid
106  // violating constant bus requirements.
107  let hasPostISelHook = 1;
108
109  // Using complex patterns gives VOP3 patterns a very high complexity rating,
110  // but standalone patterns are almost always preferred, so we need to adjust the
111  // priority lower.  The goal is to use a high number to reduce complexity to
112  // zero (or less than zero).
113  let AddedComplexity = -1000;
114
115  let VOP3 = 1;
116  let VALU = 1;
117  let FPClamp = P.HasFPClamp;
118  let IntClamp = P.HasIntClamp;
119  let ClampLo = P.HasClampLo;
120  let ClampHi = P.HasClampHi;
121
122  let Uses = [EXEC];
123
124  let AsmVariantName = AMDGPUAsmVariants.VOP3;
125  let AsmMatchConverter =
126    !if(isVOP3P,
127        "cvtVOP3P",
128        !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),
129            "cvtVOP3",
130            ""));
131}
132
133class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> :
134  VOP3_Pseudo<opName, P, pattern, 1, 1> {
135  let VOP3P = 1;
136}
137
138class VOP3_Real <VOP_Pseudo ps, int EncodingFamily> :
139  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
140  SIMCInstr <ps.PseudoInstr, EncodingFamily> {
141
142  let isPseudo = 0;
143  let isCodeGenOnly = 0;
144  let UseNamedOperandTable = 1;
145
146  let Constraints     = ps.Constraints;
147  let DisableEncoding = ps.DisableEncoding;
148
149  // copy relevant pseudo op flags
150  let SubtargetPredicate = ps.SubtargetPredicate;
151  let AsmMatchConverter  = ps.AsmMatchConverter;
152  let AsmVariantName     = ps.AsmVariantName;
153  let Constraints        = ps.Constraints;
154  let DisableEncoding    = ps.DisableEncoding;
155  let TSFlags            = ps.TSFlags;
156  let UseNamedOperandTable = ps.UseNamedOperandTable;
157  let Uses                 = ps.Uses;
158  let Defs                 = ps.Defs;
159
160  VOPProfile Pfl = ps.Pfl;
161}
162
163// XXX - Is there any reason to distingusih this from regular VOP3
164// here?
165class VOP3P_Real<VOP_Pseudo ps, int EncodingFamily> :
166  VOP3_Real<ps, EncodingFamily>;
167
168class VOP3a<VOPProfile P> : Enc64 {
169  bits<4> src0_modifiers;
170  bits<9> src0;
171  bits<3> src1_modifiers;
172  bits<9> src1;
173  bits<3> src2_modifiers;
174  bits<9> src2;
175  bits<1> clamp;
176  bits<2> omod;
177
178  let Inst{8}     = !if(P.HasSrc0Mods, src0_modifiers{1}, 0);
179  let Inst{9}     = !if(P.HasSrc1Mods, src1_modifiers{1}, 0);
180  let Inst{10}    = !if(P.HasSrc2Mods, src2_modifiers{1}, 0);
181
182  let Inst{31-26} = 0x34; //encoding
183  let Inst{40-32} = !if(P.HasSrc0, src0, 0);
184  let Inst{49-41} = !if(P.HasSrc1, src1, 0);
185  let Inst{58-50} = !if(P.HasSrc2, src2, 0);
186  let Inst{60-59} = !if(P.HasOMod, omod, 0);
187  let Inst{61}    = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
188  let Inst{62}    = !if(P.HasSrc1Mods, src1_modifiers{0}, 0);
189  let Inst{63}    = !if(P.HasSrc2Mods, src2_modifiers{0}, 0);
190}
191
192class VOP3a_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a<p> {
193  let Inst{11}    = !if(p.HasClamp, clamp{0}, 0);
194  let Inst{25-17} = op;
195}
196
197class VOP3a_gfx10<bits<10> op, VOPProfile p> : VOP3a<p> {
198  let Inst{15}    = !if(p.HasClamp, clamp{0}, 0);
199  let Inst{25-16} = op;
200  let Inst{31-26} = 0x35;
201}
202
203class VOP3a_vi <bits<10> op, VOPProfile P> : VOP3a<P> {
204  let Inst{25-16} = op;
205  let Inst{15}    = !if(P.HasClamp, clamp{0}, 0);
206}
207
208class VOP3e_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a_gfx6_gfx7<op, p> {
209  bits<8> vdst;
210  let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0);
211}
212
213class VOP3e_gfx10<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p> {
214  bits<8> vdst;
215  let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0);
216}
217
218class VOP3e_vi <bits<10> op, VOPProfile P> : VOP3a_vi <op, P> {
219  bits<8> vdst;
220  let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0);
221}
222
223class VOP3OpSel_gfx9 <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> {
224  let Inst{11} = !if(P.HasSrc0, src0_modifiers{2}, 0);
225  let Inst{12} = !if(P.HasSrc1, src1_modifiers{2}, 0);
226  let Inst{13} = !if(P.HasSrc2, src2_modifiers{2}, 0);
227  let Inst{14} = !if(P.HasDst,  src0_modifiers{3}, 0);
228}
229
230class VOP3OpSel_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> {
231  let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0);
232  let Inst{12} = !if(p.HasSrc1, src1_modifiers{2}, 0);
233  let Inst{13} = !if(p.HasSrc2, src2_modifiers{2}, 0);
234  let Inst{14} = !if(p.HasDst,  src0_modifiers{3}, 0);
235}
236
237// NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa
238class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> {
239  bits<2> attrchan;
240  bits<6> attr;
241  bits<1> high;
242
243  let Inst{8}     = 0; // No modifiers for src0
244  let Inst{61}    = 0;
245
246  let Inst{9}     = !if(P.HasSrc0Mods, src0_modifiers{1}, 0);
247  let Inst{62}    = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
248
249  let Inst{37-32} = attr;
250  let Inst{39-38} = attrchan;
251  let Inst{40}    = !if(P.HasHigh, high, 0);
252
253  let Inst{49-41} = src0;
254}
255
256class VOP3Interp_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> {
257  bits<6> attr;
258  bits<2> attrchan;
259  bits<1> high;
260
261  let Inst{8}     = 0;
262  let Inst{9}     = !if(p.HasSrc0Mods, src0_modifiers{1}, 0);
263  let Inst{37-32} = attr;
264  let Inst{39-38} = attrchan;
265  let Inst{40}    = !if(p.HasHigh, high, 0);
266  let Inst{49-41} = src0;
267  let Inst{61}    = 0;
268  let Inst{62}    = !if(p.HasSrc0Mods, src0_modifiers{0}, 0);
269}
270
271class VOP3be <VOPProfile P> : Enc64 {
272  bits<8> vdst;
273  bits<2> src0_modifiers;
274  bits<9> src0;
275  bits<2> src1_modifiers;
276  bits<9> src1;
277  bits<2> src2_modifiers;
278  bits<9> src2;
279  bits<7> sdst;
280  bits<2> omod;
281
282  let Inst{7-0}   = vdst;
283  let Inst{14-8}  = sdst;
284  let Inst{31-26} = 0x34; //encoding
285  let Inst{40-32} = !if(P.HasSrc0, src0, 0);
286  let Inst{49-41} = !if(P.HasSrc1, src1, 0);
287  let Inst{58-50} = !if(P.HasSrc2, src2, 0);
288  let Inst{60-59} = !if(P.HasOMod, omod, 0);
289  let Inst{61}    = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
290  let Inst{62}    = !if(P.HasSrc1Mods, src1_modifiers{0}, 0);
291  let Inst{63}    = !if(P.HasSrc2Mods, src2_modifiers{0}, 0);
292}
293
294class VOP3Pe <bits<10> op, VOPProfile P> : Enc64 {
295  bits<8> vdst;
296  // neg, neg_hi, op_sel put in srcN_modifiers
297  bits<4> src0_modifiers;
298  bits<9> src0;
299  bits<4> src1_modifiers;
300  bits<9> src1;
301  bits<4> src2_modifiers;
302  bits<9> src2;
303  bits<1> clamp;
304
305  let Inst{7-0} = vdst;
306  let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0
307  let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1
308  let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2
309
310  let Inst{11} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{2}, 0); // op_sel(0)
311  let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1)
312  let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2)
313
314  let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, 0); // op_sel_hi(2)
315
316  let Inst{15} = !if(P.HasClamp, clamp{0}, 0);
317
318  let Inst{25-16} = op;
319  let Inst{31-26} = 0x34; //encoding
320  let Inst{40-32} = !if(P.HasSrc0, src0, 0);
321  let Inst{49-41} = !if(P.HasSrc1, src1, 0);
322  let Inst{58-50} = !if(P.HasSrc2, src2, 0);
323  let Inst{59}    = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, 0); // op_sel_hi(0)
324  let Inst{60}    = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, 0); // op_sel_hi(1)
325  let Inst{61}    = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo)
326  let Inst{62}    = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo)
327  let Inst{63}    = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo)
328}
329
330class VOP3Pe_MAI <bits<10> op, VOPProfile P> : Enc64 {
331  bits<8> vdst;
332  bits<10> src0;
333  bits<10> src1;
334  bits<9> src2;
335  bits<3> blgp;
336  bits<3> cbsz;
337  bits<4> abid;
338  bits<1> clamp;
339
340  let Inst{7-0} = vdst;
341
342  let Inst{10-8}  = !if(P.HasSrc1, cbsz, 0);
343  let Inst{14-11} = !if(P.HasSrc1, abid, 0);
344
345  let Inst{15} = !if(P.HasClamp, clamp{0}, 0);
346
347  let Inst{25-16} = op;
348  let Inst{31-26} = 0x34; //encoding
349  let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0);
350  let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0);
351  let Inst{58-50} = !if(P.HasSrc2, src2, 0);
352
353  let Inst{59}    = !if(P.HasSrc0, src0{9}, 0); // acc(0)
354  let Inst{60}    = !if(P.HasSrc1, src1{9}, 0); // acc(1)
355
356  let Inst{63-61} = !if(P.HasSrc1, blgp, 0);
357}
358
359
360class VOP3Pe_gfx10 <bits<10> op, VOPProfile P> : VOP3Pe<op, P> {
361  let Inst{31-26} = 0x33; //encoding
362}
363
364class VOP3be_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3be<p> {
365  let Inst{25-17} = op;
366}
367
368class VOP3be_gfx10<bits<10> op, VOPProfile p> : VOP3be<p> {
369  bits<1> clamp;
370  let Inst{15}    = !if(p.HasClamp, clamp{0}, 0);
371  let Inst{25-16} = op;
372  let Inst{31-26} = 0x35;
373}
374
375class VOP3be_vi <bits<10> op, VOPProfile P> : VOP3be<P> {
376  bits<1> clamp;
377  let Inst{25-16} = op;
378  let Inst{15}    = !if(P.HasClamp, clamp{0}, 0);
379}
380
381def SDWA {
382  // sdwa_sel
383  int BYTE_0 = 0;
384  int BYTE_1 = 1;
385  int BYTE_2 = 2;
386  int BYTE_3 = 3;
387  int WORD_0 = 4;
388  int WORD_1 = 5;
389  int DWORD = 6;
390
391  // dst_unused
392  int UNUSED_PAD = 0;
393  int UNUSED_SEXT = 1;
394  int UNUSED_PRESERVE = 2;
395}
396
397class VOP_SDWAe<VOPProfile P> : Enc64 {
398  bits<8> src0;
399  bits<3> src0_sel;
400  bits<2> src0_modifiers; // float: {abs,neg}, int {sext}
401  bits<3> src1_sel;
402  bits<2> src1_modifiers;
403  bits<3> dst_sel;
404  bits<2> dst_unused;
405  bits<1> clamp;
406
407  let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
408  let Inst{42-40} = !if(P.EmitDst, dst_sel{2-0}, 0);
409  let Inst{44-43} = !if(P.EmitDst, dst_unused{1-0}, 0);
410  let Inst{45}    = !if(P.HasSDWAClamp, clamp{0}, 0);
411  let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0);
412  let Inst{51}    = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0);
413  let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0);
414  let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0);
415  let Inst{59}    = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0);
416  let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0);
417}
418
419// GFX9 adds two features to SDWA:
420// 1.	Add 3 fields to the SDWA microcode word: S0, S1 and OMOD.
421//    a. S0 and S1 indicate that source 0 and 1 respectively are SGPRs rather
422//       than VGPRs (at most 1 can be an SGPR);
423//    b. OMOD is the standard output modifier (result *2, *4, /2)
424// 2.	Add a new version of the SDWA microcode word for VOPC: SDWAB. This
425//    replaces OMOD and the dest fields with SD and SDST (SGPR destination)
426//    field.
427//    a. When SD=1, the SDST is used as the destination for the compare result;
428//    b. When SD=0, VCC is used.
429//
430// In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA
431
432// gfx9 SDWA basic encoding
433class VOP_SDWA9e<VOPProfile P> : Enc64 {
434  bits<9> src0; // {src0_sgpr{0}, src0{7-0}}
435  bits<3> src0_sel;
436  bits<2> src0_modifiers; // float: {abs,neg}, int {sext}
437  bits<3> src1_sel;
438  bits<2> src1_modifiers;
439  bits<1> src1_sgpr;
440
441  let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
442  let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0);
443  let Inst{51}    = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0);
444  let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0);
445  let Inst{55}    = !if(P.HasSrc0, src0{8}, 0);
446  let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0);
447  let Inst{59}    = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0);
448  let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0);
449  let Inst{63}    = 0; // src1_sgpr - should be specified in subclass
450}
451
452// gfx9 SDWA-A
453class VOP_SDWA9Ae<VOPProfile P> : VOP_SDWA9e<P> {
454  bits<3> dst_sel;
455  bits<2> dst_unused;
456  bits<1> clamp;
457  bits<2> omod;
458
459  let Inst{42-40} = !if(P.EmitDst, dst_sel{2-0}, 0);
460  let Inst{44-43} = !if(P.EmitDst, dst_unused{1-0}, 0);
461  let Inst{45}    = !if(P.HasSDWAClamp, clamp{0}, 0);
462  let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0);
463}
464
465// gfx9 SDWA-B
466class VOP_SDWA9Be<VOPProfile P> : VOP_SDWA9e<P> {
467  bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}}
468
469  let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, ?);
470  let Inst{47} = !if(P.EmitDst, sdst{7}, 0);
471}
472
473class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> :
474  InstSI <P.OutsSDWA, P.InsSDWA, "", pattern>,
475  VOP <opName>,
476  SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE>,
477  MnemonicAlias <opName#"_sdwa", opName> {
478
479  let isPseudo = 1;
480  let isCodeGenOnly = 1;
481  let UseNamedOperandTable = 1;
482
483  string Mnemonic = opName;
484  string AsmOperands = P.AsmSDWA;
485  string AsmOperands9 = P.AsmSDWA9;
486
487  let Size = 8;
488  let mayLoad = 0;
489  let mayStore = 0;
490  let hasSideEffects = 0;
491
492  let VALU = 1;
493  let SDWA = 1;
494  let Uses = [EXEC];
495
496  let SubtargetPredicate = !if(P.HasExtSDWA, HasSDWA, DisableInst);
497  let AssemblerPredicate = !if(P.HasExtSDWA, HasSDWA, DisableInst);
498  let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA,
499                                         AMDGPUAsmVariants.Disable);
500  let DecoderNamespace = "SDWA";
501
502  VOPProfile Pfl = P;
503}
504
505class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> :
506  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
507  SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> {
508
509  let isPseudo = 0;
510  let isCodeGenOnly = 0;
511
512  let Defs = ps.Defs;
513  let Uses = ps.Uses;
514  let SchedRW = ps.SchedRW;
515  let hasSideEffects = ps.hasSideEffects;
516
517  let Constraints     = ps.Constraints;
518  let DisableEncoding = ps.DisableEncoding;
519
520  // Copy relevant pseudo op flags
521  let SubtargetPredicate   = ps.SubtargetPredicate;
522  let AssemblerPredicate   = ps.AssemblerPredicate;
523  let AsmMatchConverter    = ps.AsmMatchConverter;
524  let AsmVariantName       = ps.AsmVariantName;
525  let UseNamedOperandTable = ps.UseNamedOperandTable;
526  let DecoderNamespace     = ps.DecoderNamespace;
527  let Constraints          = ps.Constraints;
528  let DisableEncoding      = ps.DisableEncoding;
529  let TSFlags              = ps.TSFlags;
530}
531
532class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
533  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands9, []> {
534
535  let isPseudo = 0;
536  let isCodeGenOnly = 0;
537
538  let Defs = ps.Defs;
539  let Uses = ps.Uses;
540  let SchedRW = ps.SchedRW;
541  let hasSideEffects = ps.hasSideEffects;
542
543  let Constraints     = ps.Constraints;
544  let DisableEncoding = ps.DisableEncoding;
545
546  let SubtargetPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA9, DisableInst);
547  let AssemblerPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA9, DisableInst);
548  let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9,
549                                               AMDGPUAsmVariants.Disable);
550  let DecoderNamespace = "SDWA9";
551
552  // Copy relevant pseudo op flags
553  let AsmMatchConverter    = ps.AsmMatchConverter;
554  let UseNamedOperandTable = ps.UseNamedOperandTable;
555  let Constraints          = ps.Constraints;
556  let DisableEncoding      = ps.DisableEncoding;
557  let TSFlags              = ps.TSFlags;
558}
559
560class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
561  Base_VOP_SDWA9_Real <ps >,
562  SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>;
563
564class Base_VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : Base_VOP_SDWA9_Real<ps> {
565  let SubtargetPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA10, DisableInst);
566  let AssemblerPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA10, DisableInst);
567  let DecoderNamespace = "SDWA10";
568}
569
570class VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> :
571  Base_VOP_SDWA10_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SDWA10>;
572
573class VOP_DPPe<VOPProfile P, bit IsDPP16=0> : Enc64 {
574  bits<2> src0_modifiers;
575  bits<8> src0;
576  bits<2> src1_modifiers;
577  bits<9> dpp_ctrl;
578  bits<1> bound_ctrl;
579  bits<4> bank_mask;
580  bits<4> row_mask;
581  bit     fi;
582
583  let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
584  let Inst{48-40} = dpp_ctrl;
585  let Inst{50}    = !if(IsDPP16, fi, ?);
586  let Inst{51}    = bound_ctrl;
587  let Inst{52}    = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg
588  let Inst{53}    = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs
589  let Inst{54}    = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg
590  let Inst{55}    = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs
591  let Inst{59-56} = bank_mask;
592  let Inst{63-60} = row_mask;
593}
594
595class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
596  InstSI <P.OutsDPP, P.InsDPP, OpName#P.AsmDPP, pattern>,
597  VOP <OpName>,
598  SIMCInstr <OpName#"_dpp", SIEncodingFamily.NONE>,
599  MnemonicAlias <OpName#"_dpp", OpName> {
600
601  let isPseudo = 1;
602  let isCodeGenOnly = 1;
603
604  let mayLoad = 0;
605  let mayStore = 0;
606  let hasSideEffects = 0;
607  let UseNamedOperandTable = 1;
608
609  let VALU = 1;
610  let DPP = 1;
611  let Size = 8;
612  let Uses = [EXEC];
613  let isConvergent = 1;
614
615  string Mnemonic = OpName;
616  string AsmOperands = P.AsmDPP;
617
618  let AsmMatchConverter = !if(!eq(P.HasModifiers,1), "cvtDPP", "");
619  let SubtargetPredicate = HasDPP;
620  let AssemblerPredicate = !if(P.HasExtDPP, HasDPP, DisableInst);
621  let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
622                                        AMDGPUAsmVariants.Disable);
623  let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", "");
624  let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, "");
625  let DecoderNamespace = "DPP";
626
627  VOPProfile Pfl = P;
628}
629
630class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> :
631  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
632  SIMCInstr <ps.PseudoInstr, EncodingFamily> {
633
634  let isPseudo = 0;
635  let isCodeGenOnly = 0;
636
637  let Defs = ps.Defs;
638  let Uses = ps.Uses;
639  let SchedRW = ps.SchedRW;
640  let hasSideEffects = ps.hasSideEffects;
641
642  let Constraints     = ps.Constraints;
643  let DisableEncoding = ps.DisableEncoding;
644
645  // Copy relevant pseudo op flags
646  let isConvergent         = ps.isConvergent;
647  let SubtargetPredicate   = ps.SubtargetPredicate;
648  let AssemblerPredicate   = ps.AssemblerPredicate;
649  let AsmMatchConverter    = ps.AsmMatchConverter;
650  let AsmVariantName       = ps.AsmVariantName;
651  let UseNamedOperandTable = ps.UseNamedOperandTable;
652  let DecoderNamespace     = ps.DecoderNamespace;
653  let Constraints          = ps.Constraints;
654  let DisableEncoding      = ps.DisableEncoding;
655  let TSFlags              = ps.TSFlags;
656}
657
658class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16,
659               dag InsDPP = !if(IsDPP16, P.InsDPP16, P.InsDPP),
660               string AsmDPP = !if(IsDPP16, P.AsmDPP16, P.AsmDPP)> :
661  InstSI <P.OutsDPP, InsDPP, OpName#AsmDPP, []>,
662  VOP_DPPe<P, IsDPP16> {
663
664  let mayLoad = 0;
665  let mayStore = 0;
666  let hasSideEffects = 0;
667  let UseNamedOperandTable = 1;
668
669  let VALU = 1;
670  let DPP = 1;
671  let Size = 8;
672
673  let AsmMatchConverter = !if(!eq(P.HasModifiers,1), "cvtDPP", "");
674  let SubtargetPredicate = HasDPP;
675  let AssemblerPredicate = !if(P.HasExtDPP, HasDPP, DisableInst);
676  let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
677                                        AMDGPUAsmVariants.Disable);
678  let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", "");
679  let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, "");
680  let DecoderNamespace = "DPP";
681}
682
683class VOP_DPP8e<VOPProfile P> : Enc64 {
684  bits<8> src0;
685  bits<24> dpp8;
686  bits<9> fi;
687
688  let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
689  let Inst{63-40} = dpp8{23-0};
690}
691
692class VOP_DPP8<string OpName, VOPProfile P> :
693  InstSI<P.OutsDPP8, P.InsDPP8, OpName#P.AsmDPP8, []>,
694  VOP_DPP8e<P> {
695
696  let mayLoad = 0;
697  let mayStore = 0;
698  let hasSideEffects = 0;
699  let UseNamedOperandTable = 1;
700
701  let VALU = 1;
702  let DPP = 1;
703  let Size = 8;
704
705  let AsmMatchConverter = "cvtDPP8";
706  let SubtargetPredicate = HasDPP8;
707  let AssemblerPredicate = !if(P.HasExt, HasDPP8, DisableInst);
708  let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.DPP,
709                                     AMDGPUAsmVariants.Disable);
710  let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", "");
711  let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, "");
712}
713
714def DPP8Mode {
715  int FI_0 = 0xE9;
716  int FI_1 = 0xEA;
717}
718
719class getNumNodeArgs<SDPatternOperator Op> {
720  SDNode N = !cast<SDNode>(Op);
721  SDTypeProfile TP = N.TypeProfile;
722  int ret = TP.NumOperands;
723}
724
725
726class getDivergentFrag<SDPatternOperator Op> {
727
728  int NumSrcArgs = getNumNodeArgs<Op>.ret;
729  PatFrag ret = PatFrag <
730    !if(!eq(NumSrcArgs, 1),
731             (ops node:$src0),
732             !if(!eq(NumSrcArgs, 2),
733               (ops node:$src0, node:$src1),
734               (ops node:$src0, node:$src1, node:$src2))),
735    !if(!eq(NumSrcArgs, 1),
736             (Op $src0),
737             !if(!eq(NumSrcArgs, 2),
738               (Op $src0, $src1),
739               (Op $src0, $src1, $src2))),
740    [{ return N->isDivergent(); }]
741  >;
742}
743
744class VOPPatGen<SDPatternOperator Op, VOPProfile P> {
745
746  PatFrag Operator = getDivergentFrag < Op >.ret;
747
748  dag Ins = !foreach(tmp, P.Ins32, !subst(ins, Operator,
749                                         !subst(P.Src0RC32, P.Src0VT,
750                                               !subst(P.Src1RC32, P.Src1VT, tmp))));
751
752
753  dag Outs = !foreach(tmp, P.Outs32, !subst(outs, set,
754                                           !subst(P.DstRC, P.DstVT, tmp)));
755
756  list<dag> ret =  [!con(Outs, (set Ins))];
757}
758
759class VOPPatOrNull<SDPatternOperator Op, VOPProfile P> {
760  list<dag> ret = !if(!ne(P.NeedPatGen,PatGenMode.NoPattern), VOPPatGen<Op, P>.ret, []);
761}
762
763class DivergentFragOrOp<SDPatternOperator Op, VOPProfile P> {
764  SDPatternOperator ret = !if(!eq(P.NeedPatGen,PatGenMode.Pattern),
765   !if(!isa<SDNode>(Op), getDivergentFrag<Op>.ret, Op), Op);
766}
767
768include "VOPCInstructions.td"
769include "VOP1Instructions.td"
770include "VOP2Instructions.td"
771include "VOP3Instructions.td"
772include "VOP3PInstructions.td"
773