1//===-- VOPInstructions.td - Vector Instruction Defintions ----------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// dummies for outer let 10class LetDummies { 11 bit isCommutable; 12 bit isConvertibleToThreeAddress; 13 bit isMoveImm; 14 bit isReMaterializable; 15 bit isAsCheapAsAMove; 16 bit VOPAsmPrefer32Bit; 17 bit FPDPRounding; 18 Predicate SubtargetPredicate; 19 string Constraints; 20 string DisableEncoding; 21 list<SchedReadWrite> SchedRW; 22 list<Register> Uses; 23 list<Register> Defs; 24} 25 26class VOP <string opName> { 27 string OpName = opName; 28} 29 30class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> : 31 InstSI <outs, ins, asm, pattern> { 32 33 let mayLoad = 0; 34 let mayStore = 0; 35 let hasSideEffects = 0; 36 let UseNamedOperandTable = 1; 37 let VALU = 1; 38 let Uses = [EXEC]; 39} 40 41class VOP_Pseudo <string opName, string suffix, VOPProfile P, dag outs, dag ins, 42 string asm, list<dag> pattern> : 43 InstSI <outs, ins, asm, pattern>, 44 VOP <opName>, 45 SIMCInstr <opName#suffix, SIEncodingFamily.NONE> { 46 let isPseudo = 1; 47 let isCodeGenOnly = 1; 48 let UseNamedOperandTable = 1; 49 50 string Mnemonic = opName; 51 VOPProfile Pfl = P; 52 53 string AsmOperands; 54} 55 56class VOP3Common <dag outs, dag ins, string asm = "", 57 list<dag> pattern = [], bit HasMods = 0, 58 bit VOP3Only = 0> : 59 VOPAnyCommon <outs, ins, asm, pattern> { 60 61 // Using complex patterns gives VOP3 patterns a very high complexity rating, 62 // but standalone patterns are almost always preferred, so we need to adjust the 63 // priority lower. The goal is to use a high number to reduce complexity to 64 // zero (or less than zero). 65 let AddedComplexity = -1000; 66 67 let VOP3 = 1; 68 69 let AsmVariantName = AMDGPUAsmVariants.VOP3; 70 let AsmMatchConverter = !if(!eq(HasMods,1), "cvtVOP3", ""); 71 72 let isCodeGenOnly = 0; 73 74 int Size = 8; 75 76 // Because SGPRs may be allowed if there are multiple operands, we 77 // need a post-isel hook to insert copies in order to avoid 78 // violating constant bus requirements. 79 let hasPostISelHook = 1; 80} 81 82class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [], 83 bit VOP3Only = 0, bit isVOP3P = 0, bit isVop3OpSel = 0> : 84 VOP_Pseudo <opName, "_e64", P, P.Outs64, 85 !if(isVop3OpSel, 86 P.InsVOP3OpSel, 87 !if(!and(isVOP3P, P.IsPacked), P.InsVOP3P, P.Ins64)), 88 "", pattern> { 89 90 let VOP3_OPSEL = isVop3OpSel; 91 let IsPacked = P.IsPacked; 92 let IsMAI = P.IsMAI; 93 94 let AsmOperands = !if(isVop3OpSel, 95 P.AsmVOP3OpSel, 96 !if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64)); 97 98 let Size = 8; 99 let mayLoad = 0; 100 let mayStore = 0; 101 let hasSideEffects = 0; 102 103 // Because SGPRs may be allowed if there are multiple operands, we 104 // need a post-isel hook to insert copies in order to avoid 105 // violating constant bus requirements. 106 let hasPostISelHook = 1; 107 108 // Using complex patterns gives VOP3 patterns a very high complexity rating, 109 // but standalone patterns are almost always preferred, so we need to adjust the 110 // priority lower. The goal is to use a high number to reduce complexity to 111 // zero (or less than zero). 112 let AddedComplexity = -1000; 113 114 let VOP3 = 1; 115 let VALU = 1; 116 let FPClamp = P.HasFPClamp; 117 let IntClamp = P.HasIntClamp; 118 let ClampLo = P.HasClampLo; 119 let ClampHi = P.HasClampHi; 120 121 let Uses = [EXEC]; 122 123 let AsmVariantName = AMDGPUAsmVariants.VOP3; 124 let AsmMatchConverter = 125 !if(isVOP3P, 126 "cvtVOP3P", 127 !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)), 128 "cvtVOP3", 129 "")); 130} 131 132class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> : 133 VOP3_Pseudo<opName, P, pattern, 1, 1> { 134 let VOP3P = 1; 135} 136 137class VOP3_Real <VOP_Pseudo ps, int EncodingFamily> : 138 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 139 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 140 141 let isPseudo = 0; 142 let isCodeGenOnly = 0; 143 let UseNamedOperandTable = 1; 144 145 let Constraints = ps.Constraints; 146 let DisableEncoding = ps.DisableEncoding; 147 148 // copy relevant pseudo op flags 149 let SubtargetPredicate = ps.SubtargetPredicate; 150 let OtherPredicates = ps.OtherPredicates; 151 let AsmMatchConverter = ps.AsmMatchConverter; 152 let AsmVariantName = ps.AsmVariantName; 153 let Constraints = ps.Constraints; 154 let DisableEncoding = ps.DisableEncoding; 155 let TSFlags = ps.TSFlags; 156 let UseNamedOperandTable = ps.UseNamedOperandTable; 157 let Uses = ps.Uses; 158 let Defs = ps.Defs; 159 160 VOPProfile Pfl = ps.Pfl; 161} 162 163// XXX - Is there any reason to distingusih this from regular VOP3 164// here? 165class VOP3P_Real<VOP_Pseudo ps, int EncodingFamily> : 166 VOP3_Real<ps, EncodingFamily>; 167 168class VOP3a<VOPProfile P> : Enc64 { 169 bits<4> src0_modifiers; 170 bits<9> src0; 171 bits<3> src1_modifiers; 172 bits<9> src1; 173 bits<3> src2_modifiers; 174 bits<9> src2; 175 bits<1> clamp; 176 bits<2> omod; 177 178 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 179 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); 180 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); 181 182 let Inst{31-26} = 0x34; //encoding 183 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 184 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 185 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 186 let Inst{60-59} = !if(P.HasOMod, omod, 0); 187 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 188 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 189 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 190} 191 192class VOP3a_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a<p> { 193 let Inst{11} = !if(p.HasClamp, clamp{0}, 0); 194 let Inst{25-17} = op; 195} 196 197class VOP3a_gfx10<bits<10> op, VOPProfile p> : VOP3a<p> { 198 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 199 let Inst{25-16} = op; 200 let Inst{31-26} = 0x35; 201} 202 203class VOP3a_vi <bits<10> op, VOPProfile P> : VOP3a<P> { 204 let Inst{25-16} = op; 205 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 206} 207 208class VOP3e_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a_gfx6_gfx7<op, p> { 209 bits<8> vdst; 210 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 211} 212 213class VOP3e_gfx10<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p> { 214 bits<8> vdst; 215 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 216} 217 218class VOP3e_vi <bits<10> op, VOPProfile P> : VOP3a_vi <op, P> { 219 bits<8> vdst; 220 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0); 221} 222 223class VOP3OpSel_gfx9 <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 224 let Inst{11} = !if(P.HasSrc0, src0_modifiers{2}, 0); 225 let Inst{12} = !if(P.HasSrc1, src1_modifiers{2}, 0); 226 let Inst{13} = !if(P.HasSrc2, src2_modifiers{2}, 0); 227 let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0); 228} 229 230class VOP3OpSel_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 231 let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0); 232 let Inst{12} = !if(p.HasSrc1, src1_modifiers{2}, 0); 233 let Inst{13} = !if(p.HasSrc2, src2_modifiers{2}, 0); 234 let Inst{14} = !if(p.HasDst, src0_modifiers{3}, 0); 235} 236 237// NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa 238class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 239 bits<2> attrchan; 240 bits<6> attr; 241 bits<1> high; 242 243 let Inst{8} = 0; // No modifiers for src0 244 let Inst{61} = 0; 245 246 let Inst{9} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 247 let Inst{62} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 248 249 let Inst{37-32} = attr; 250 let Inst{39-38} = attrchan; 251 let Inst{40} = !if(P.HasHigh, high, 0); 252 253 let Inst{49-41} = src0; 254} 255 256class VOP3Interp_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 257 bits<6> attr; 258 bits<2> attrchan; 259 bits<1> high; 260 261 let Inst{8} = 0; 262 let Inst{9} = !if(p.HasSrc0Mods, src0_modifiers{1}, 0); 263 let Inst{37-32} = attr; 264 let Inst{39-38} = attrchan; 265 let Inst{40} = !if(p.HasHigh, high, 0); 266 let Inst{49-41} = src0; 267 let Inst{61} = 0; 268 let Inst{62} = !if(p.HasSrc0Mods, src0_modifiers{0}, 0); 269} 270 271class VOP3be <VOPProfile P> : Enc64 { 272 bits<8> vdst; 273 bits<2> src0_modifiers; 274 bits<9> src0; 275 bits<2> src1_modifiers; 276 bits<9> src1; 277 bits<2> src2_modifiers; 278 bits<9> src2; 279 bits<7> sdst; 280 bits<2> omod; 281 282 let Inst{7-0} = vdst; 283 let Inst{14-8} = sdst; 284 let Inst{31-26} = 0x34; //encoding 285 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 286 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 287 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 288 let Inst{60-59} = !if(P.HasOMod, omod, 0); 289 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 290 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 291 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 292} 293 294class VOP3Pe <bits<10> op, VOPProfile P> : Enc64 { 295 bits<8> vdst; 296 // neg, neg_hi, op_sel put in srcN_modifiers 297 bits<4> src0_modifiers; 298 bits<9> src0; 299 bits<4> src1_modifiers; 300 bits<9> src1; 301 bits<4> src2_modifiers; 302 bits<9> src2; 303 bits<1> clamp; 304 305 let Inst{7-0} = vdst; 306 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0 307 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1 308 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2 309 310 let Inst{11} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{2}, 0); // op_sel(0) 311 let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1) 312 let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2) 313 314 let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, 0); // op_sel_hi(2) 315 316 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 317 318 let Inst{25-16} = op; 319 let Inst{31-26} = 0x34; //encoding 320 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 321 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 322 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 323 let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, 0); // op_sel_hi(0) 324 let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, 0); // op_sel_hi(1) 325 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo) 326 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo) 327 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo) 328} 329 330class VOP3Pe_MAI <bits<10> op, VOPProfile P> : Enc64 { 331 bits<8> vdst; 332 bits<10> src0; 333 bits<10> src1; 334 bits<9> src2; 335 bits<3> blgp; 336 bits<3> cbsz; 337 bits<4> abid; 338 bits<1> clamp; 339 340 let Inst{7-0} = vdst; 341 342 let Inst{10-8} = !if(P.HasSrc1, cbsz, 0); 343 let Inst{14-11} = !if(P.HasSrc1, abid, 0); 344 345 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 346 347 let Inst{25-16} = op; 348 let Inst{31-26} = 0x34; //encoding 349 let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0); 350 let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0); 351 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 352 353 let Inst{59} = !if(P.HasSrc0, src0{9}, 0); // acc(0) 354 let Inst{60} = !if(P.HasSrc1, src1{9}, 0); // acc(1) 355 356 let Inst{63-61} = !if(P.HasSrc1, blgp, 0); 357} 358 359 360class VOP3Pe_gfx10 <bits<10> op, VOPProfile P> : VOP3Pe<op, P> { 361 let Inst{31-26} = 0x33; //encoding 362} 363 364class VOP3be_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3be<p> { 365 let Inst{25-17} = op; 366} 367 368class VOP3be_gfx10<bits<10> op, VOPProfile p> : VOP3be<p> { 369 bits<1> clamp; 370 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 371 let Inst{25-16} = op; 372 let Inst{31-26} = 0x35; 373} 374 375class VOP3be_vi <bits<10> op, VOPProfile P> : VOP3be<P> { 376 bits<1> clamp; 377 let Inst{25-16} = op; 378 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 379} 380 381def SDWA { 382 // sdwa_sel 383 int BYTE_0 = 0; 384 int BYTE_1 = 1; 385 int BYTE_2 = 2; 386 int BYTE_3 = 3; 387 int WORD_0 = 4; 388 int WORD_1 = 5; 389 int DWORD = 6; 390 391 // dst_unused 392 int UNUSED_PAD = 0; 393 int UNUSED_SEXT = 1; 394 int UNUSED_PRESERVE = 2; 395} 396 397class VOP_SDWAe<VOPProfile P> : Enc64 { 398 bits<8> src0; 399 bits<3> src0_sel; 400 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 401 bits<3> src1_sel; 402 bits<2> src1_modifiers; 403 bits<3> dst_sel; 404 bits<2> dst_unused; 405 bits<1> clamp; 406 407 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 408 let Inst{42-40} = !if(P.EmitDst, dst_sel{2-0}, 0); 409 let Inst{44-43} = !if(P.EmitDst, dst_unused{1-0}, 0); 410 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 411 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 412 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 413 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 414 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 415 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 416 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 417} 418 419// GFX9 adds two features to SDWA: 420// 1. Add 3 fields to the SDWA microcode word: S0, S1 and OMOD. 421// a. S0 and S1 indicate that source 0 and 1 respectively are SGPRs rather 422// than VGPRs (at most 1 can be an SGPR); 423// b. OMOD is the standard output modifier (result *2, *4, /2) 424// 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This 425// replaces OMOD and the dest fields with SD and SDST (SGPR destination) 426// field. 427// a. When SD=1, the SDST is used as the destination for the compare result; 428// b. When SD=0, VCC is used. 429// 430// In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA 431 432// gfx9 SDWA basic encoding 433class VOP_SDWA9e<VOPProfile P> : Enc64 { 434 bits<9> src0; // {src0_sgpr{0}, src0{7-0}} 435 bits<3> src0_sel; 436 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 437 bits<3> src1_sel; 438 bits<2> src1_modifiers; 439 bits<1> src1_sgpr; 440 441 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 442 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 443 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 444 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 445 let Inst{55} = !if(P.HasSrc0, src0{8}, 0); 446 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 447 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 448 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 449 let Inst{63} = 0; // src1_sgpr - should be specified in subclass 450} 451 452// gfx9 SDWA-A 453class VOP_SDWA9Ae<VOPProfile P> : VOP_SDWA9e<P> { 454 bits<3> dst_sel; 455 bits<2> dst_unused; 456 bits<1> clamp; 457 bits<2> omod; 458 459 let Inst{42-40} = !if(P.EmitDst, dst_sel{2-0}, 0); 460 let Inst{44-43} = !if(P.EmitDst, dst_unused{1-0}, 0); 461 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 462 let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0); 463} 464 465// gfx9 SDWA-B 466class VOP_SDWA9Be<VOPProfile P> : VOP_SDWA9e<P> { 467 bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}} 468 469 let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, ?); 470 let Inst{47} = !if(P.EmitDst, sdst{7}, 0); 471} 472 473class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> : 474 InstSI <P.OutsSDWA, P.InsSDWA, "", pattern>, 475 VOP <opName>, 476 SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE> { 477 478 let isPseudo = 1; 479 let isCodeGenOnly = 1; 480 let UseNamedOperandTable = 1; 481 482 string Mnemonic = opName; 483 string AsmOperands = P.AsmSDWA; 484 string AsmOperands9 = P.AsmSDWA9; 485 486 let Size = 8; 487 let mayLoad = 0; 488 let mayStore = 0; 489 let hasSideEffects = 0; 490 491 let VALU = 1; 492 let SDWA = 1; 493 let Uses = [EXEC]; 494 495 let SubtargetPredicate = !if(P.HasExtSDWA, HasSDWA, DisableInst); 496 let AssemblerPredicate = !if(P.HasExtSDWA, HasSDWA, DisableInst); 497 let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA, 498 AMDGPUAsmVariants.Disable); 499 let DecoderNamespace = "SDWA"; 500 501 VOPProfile Pfl = P; 502} 503 504class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> : 505 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 506 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> { 507 508 let isPseudo = 0; 509 let isCodeGenOnly = 0; 510 511 let Defs = ps.Defs; 512 let Uses = ps.Uses; 513 let SchedRW = ps.SchedRW; 514 let hasSideEffects = ps.hasSideEffects; 515 516 let Constraints = ps.Constraints; 517 let DisableEncoding = ps.DisableEncoding; 518 519 // Copy relevant pseudo op flags 520 let SubtargetPredicate = ps.SubtargetPredicate; 521 let AssemblerPredicate = ps.AssemblerPredicate; 522 let AsmMatchConverter = ps.AsmMatchConverter; 523 let AsmVariantName = ps.AsmVariantName; 524 let UseNamedOperandTable = ps.UseNamedOperandTable; 525 let DecoderNamespace = ps.DecoderNamespace; 526 let Constraints = ps.Constraints; 527 let DisableEncoding = ps.DisableEncoding; 528 let TSFlags = ps.TSFlags; 529} 530 531class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 532 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands9, []> { 533 534 let isPseudo = 0; 535 let isCodeGenOnly = 0; 536 537 let Defs = ps.Defs; 538 let Uses = ps.Uses; 539 let SchedRW = ps.SchedRW; 540 let hasSideEffects = ps.hasSideEffects; 541 542 let Constraints = ps.Constraints; 543 let DisableEncoding = ps.DisableEncoding; 544 545 let SubtargetPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA9, DisableInst); 546 let AssemblerPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA9, DisableInst); 547 let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9, 548 AMDGPUAsmVariants.Disable); 549 let DecoderNamespace = "SDWA9"; 550 551 // Copy relevant pseudo op flags 552 let AsmMatchConverter = ps.AsmMatchConverter; 553 let UseNamedOperandTable = ps.UseNamedOperandTable; 554 let Constraints = ps.Constraints; 555 let DisableEncoding = ps.DisableEncoding; 556 let TSFlags = ps.TSFlags; 557} 558 559class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 560 Base_VOP_SDWA9_Real <ps >, 561 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>; 562 563class Base_VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : Base_VOP_SDWA9_Real<ps> { 564 let SubtargetPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA10, DisableInst); 565 let AssemblerPredicate = !if(ps.Pfl.HasExtSDWA9, HasSDWA10, DisableInst); 566 let DecoderNamespace = "SDWA10"; 567} 568 569class VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : 570 Base_VOP_SDWA10_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SDWA10>; 571 572class VOP_DPPe<VOPProfile P, bit IsDPP16=0> : Enc64 { 573 bits<2> src0_modifiers; 574 bits<8> src0; 575 bits<2> src1_modifiers; 576 bits<9> dpp_ctrl; 577 bits<1> bound_ctrl; 578 bits<4> bank_mask; 579 bits<4> row_mask; 580 bit fi; 581 582 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 583 let Inst{48-40} = dpp_ctrl; 584 let Inst{50} = !if(IsDPP16, fi, ?); 585 let Inst{51} = bound_ctrl; 586 let Inst{52} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg 587 let Inst{53} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs 588 let Inst{54} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg 589 let Inst{55} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs 590 let Inst{59-56} = bank_mask; 591 let Inst{63-60} = row_mask; 592} 593 594class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 595 InstSI <P.OutsDPP, P.InsDPP, OpName#P.AsmDPP, pattern>, 596 VOP <OpName>, 597 SIMCInstr <OpName#"_dpp", SIEncodingFamily.NONE> { 598 599 let isPseudo = 1; 600 let isCodeGenOnly = 1; 601 602 let mayLoad = 0; 603 let mayStore = 0; 604 let hasSideEffects = 0; 605 let UseNamedOperandTable = 1; 606 607 let VALU = 1; 608 let DPP = 1; 609 let Size = 8; 610 let Uses = [EXEC]; 611 let isConvergent = 1; 612 613 string Mnemonic = OpName; 614 string AsmOperands = P.AsmDPP; 615 616 let AsmMatchConverter = !if(!eq(P.HasModifiers,1), "cvtDPP", ""); 617 let SubtargetPredicate = HasDPP; 618 let AssemblerPredicate = !if(P.HasExtDPP, HasDPP, DisableInst); 619 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 620 AMDGPUAsmVariants.Disable); 621 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 622 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 623 let DecoderNamespace = "DPP"; 624 625 VOPProfile Pfl = P; 626} 627 628class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> : 629 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 630 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 631 632 let isPseudo = 0; 633 let isCodeGenOnly = 0; 634 635 let Defs = ps.Defs; 636 let Uses = ps.Uses; 637 let SchedRW = ps.SchedRW; 638 let hasSideEffects = ps.hasSideEffects; 639 640 let Constraints = ps.Constraints; 641 let DisableEncoding = ps.DisableEncoding; 642 643 // Copy relevant pseudo op flags 644 let isConvergent = ps.isConvergent; 645 let SubtargetPredicate = ps.SubtargetPredicate; 646 let AssemblerPredicate = ps.AssemblerPredicate; 647 let AsmMatchConverter = ps.AsmMatchConverter; 648 let AsmVariantName = ps.AsmVariantName; 649 let UseNamedOperandTable = ps.UseNamedOperandTable; 650 let DecoderNamespace = ps.DecoderNamespace; 651 let Constraints = ps.Constraints; 652 let DisableEncoding = ps.DisableEncoding; 653 let TSFlags = ps.TSFlags; 654} 655 656class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16, 657 dag InsDPP = !if(IsDPP16, P.InsDPP16, P.InsDPP), 658 string AsmDPP = !if(IsDPP16, P.AsmDPP16, P.AsmDPP)> : 659 InstSI <P.OutsDPP, InsDPP, OpName#AsmDPP, []>, 660 VOP_DPPe<P, IsDPP16> { 661 662 let mayLoad = 0; 663 let mayStore = 0; 664 let hasSideEffects = 0; 665 let UseNamedOperandTable = 1; 666 667 let VALU = 1; 668 let DPP = 1; 669 let Size = 8; 670 671 let AsmMatchConverter = !if(!eq(P.HasModifiers,1), "cvtDPP", ""); 672 let SubtargetPredicate = HasDPP; 673 let AssemblerPredicate = !if(P.HasExtDPP, HasDPP, DisableInst); 674 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 675 AMDGPUAsmVariants.Disable); 676 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 677 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 678 let DecoderNamespace = "DPP"; 679} 680 681class VOP_DPP8e<VOPProfile P> : Enc64 { 682 bits<8> src0; 683 bits<24> dpp8; 684 bits<9> fi; 685 686 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 687 let Inst{63-40} = dpp8{23-0}; 688} 689 690class VOP_DPP8<string OpName, VOPProfile P> : 691 InstSI<P.OutsDPP8, P.InsDPP8, OpName#P.AsmDPP8, []>, 692 VOP_DPP8e<P> { 693 694 let mayLoad = 0; 695 let mayStore = 0; 696 let hasSideEffects = 0; 697 let UseNamedOperandTable = 1; 698 699 let VALU = 1; 700 let DPP = 1; 701 let Size = 8; 702 703 let AsmMatchConverter = "cvtDPP8"; 704 let SubtargetPredicate = HasDPP8; 705 let AssemblerPredicate = !if(P.HasExt, HasDPP8, DisableInst); 706 let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.DPP, 707 AMDGPUAsmVariants.Disable); 708 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 709 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 710} 711 712def DPP8Mode { 713 int FI_0 = 0xE9; 714 int FI_1 = 0xEA; 715} 716 717class getNumNodeArgs<SDPatternOperator Op> { 718 SDNode N = !cast<SDNode>(Op); 719 SDTypeProfile TP = N.TypeProfile; 720 int ret = TP.NumOperands; 721} 722 723 724class getDivergentFrag<SDPatternOperator Op> { 725 726 int NumSrcArgs = getNumNodeArgs<Op>.ret; 727 PatFrag ret = PatFrag < 728 !if(!eq(NumSrcArgs, 1), 729 (ops node:$src0), 730 !if(!eq(NumSrcArgs, 2), 731 (ops node:$src0, node:$src1), 732 (ops node:$src0, node:$src1, node:$src2))), 733 !if(!eq(NumSrcArgs, 1), 734 (Op $src0), 735 !if(!eq(NumSrcArgs, 2), 736 (Op $src0, $src1), 737 (Op $src0, $src1, $src2))), 738 [{ return N->isDivergent(); }] 739 >; 740} 741 742class VOPPatGen<SDPatternOperator Op, VOPProfile P> { 743 744 PatFrag Operator = getDivergentFrag < Op >.ret; 745 746 dag Ins = !foreach(tmp, P.Ins32, !subst(ins, Operator, 747 !subst(P.Src0RC32, P.Src0VT, 748 !subst(P.Src1RC32, P.Src1VT, tmp)))); 749 750 751 dag Outs = !foreach(tmp, P.Outs32, !subst(outs, set, 752 !subst(P.DstRC, P.DstVT, tmp))); 753 754 list<dag> ret = [!con(Outs, (set Ins))]; 755} 756 757class VOPPatOrNull<SDPatternOperator Op, VOPProfile P> { 758 list<dag> ret = !if(!ne(P.NeedPatGen,PatGenMode.NoPattern), VOPPatGen<Op, P>.ret, []); 759} 760 761class DivergentFragOrOp<SDPatternOperator Op, VOPProfile P> { 762 SDPatternOperator ret = !if(!eq(P.NeedPatGen,PatGenMode.Pattern), 763 !if(!isa<SDNode>(Op), getDivergentFrag<Op>.ret, Op), Op); 764} 765 766include "VOPCInstructions.td" 767include "VOP1Instructions.td" 768include "VOP2Instructions.td" 769include "VOP3Instructions.td" 770include "VOP3PInstructions.td" 771