1//===-- VOPInstructions.td - Vector Instruction Definitions ---------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// dummies for outer let 10class LetDummies { 11 bit TRANS; 12 bit ReadsModeReg; 13 bit mayRaiseFPException; 14 bit isCommutable; 15 bit isConvertibleToThreeAddress; 16 bit isMoveImm; 17 bit isReMaterializable; 18 bit isAsCheapAsAMove; 19 bit VOPAsmPrefer32Bit; 20 bit FPDPRounding; 21 Predicate SubtargetPredicate; 22 string Constraints; 23 string DisableEncoding; 24 list<SchedReadWrite> SchedRW; 25 list<Register> Uses; 26 list<Register> Defs; 27 list<Predicate> OtherPredicates; 28 Predicate AssemblerPredicate; 29 string DecoderNamespace; 30} 31 32class VOP <string opName> { 33 string OpName = opName; 34} 35 36// First 13 insts from VOPDY are also VOPDX. DOT2ACC_F32_BF16 is omitted 37defvar VOPDX_Max_Index = 12; 38 39class VOPD_Component<bits<5> OpIn, string vOPDName> { 40 Instruction BaseVOP = !cast<Instruction>(NAME); 41 string VOPDName = "v_dual_" # !substr(vOPDName, 2); 42 bits<5> VOPDOp = OpIn; 43 bit CanBeVOPDX = !le(VOPDOp, VOPDX_Max_Index); 44} 45 46class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> : 47 InstSI <outs, ins, asm, pattern> { 48 49 let mayLoad = 0; 50 let mayStore = 0; 51 let hasSideEffects = 0; 52 let UseNamedOperandTable = 1; 53 let VALU = 1; 54 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 55} 56 57class VOP_Pseudo <string opName, string suffix, VOPProfile P, dag outs, dag ins, 58 string asm, list<dag> pattern> : 59 InstSI <outs, ins, asm, pattern>, 60 VOP <opName>, 61 SIMCInstr <opName#suffix, SIEncodingFamily.NONE> { 62 let isPseudo = 1; 63 let isCodeGenOnly = 1; 64 let UseNamedOperandTable = 1; 65 66 string Mnemonic = opName; 67 Instruction Opcode = !cast<Instruction>(NAME); 68 bit IsTrue16 = P.IsTrue16; 69 VOPProfile Pfl = P; 70 71 string AsmOperands; 72} 73 74class VOP3Common <dag outs, dag ins, string asm = "", 75 list<dag> pattern = [], bit HasMods = 0> : 76 VOPAnyCommon <outs, ins, asm, pattern> { 77 78 // Using complex patterns gives VOP3 patterns a very high complexity rating, 79 // but standalone patterns are almost always preferred, so we need to adjust the 80 // priority lower. The goal is to use a high number to reduce complexity to 81 // zero (or less than zero). 82 let AddedComplexity = -1000; 83 84 let VOP3 = 1; 85 86 let AsmVariantName = AMDGPUAsmVariants.VOP3; 87 let AsmMatchConverter = !if(HasMods, "cvtVOP3", ""); 88 89 let isCodeGenOnly = 0; 90 91 int Size = 8; 92 93 // Because SGPRs may be allowed if there are multiple operands, we 94 // need a post-isel hook to insert copies in order to avoid 95 // violating constant bus requirements. 96 let hasPostISelHook = 1; 97} 98 99class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [], 100 bit isVOP3P = 0, bit isVop3OpSel = 0> : 101 VOP_Pseudo <opName, "_e64", P, P.Outs64, 102 !if(isVop3OpSel, 103 P.InsVOP3OpSel, 104 !if(!and(isVOP3P, P.IsPacked), P.InsVOP3P, P.Ins64)), 105 "", pattern> { 106 107 let VOP3_OPSEL = isVop3OpSel; 108 let IsPacked = P.IsPacked; 109 let IsMAI = P.IsMAI; 110 let IsWMMA = P.IsWMMA; 111 112 let AsmOperands = !if(isVop3OpSel, 113 P.AsmVOP3OpSel, 114 !if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64)); 115 116 let Size = 8; 117 let mayLoad = 0; 118 let mayStore = 0; 119 let hasSideEffects = 0; 120 121 // Because SGPRs may be allowed if there are multiple operands, we 122 // need a post-isel hook to insert copies in order to avoid 123 // violating constant bus requirements. 124 let hasPostISelHook = 1; 125 126 // Using complex patterns gives VOP3 patterns a very high complexity rating, 127 // but standalone patterns are almost always preferred, so we need to adjust the 128 // priority lower. The goal is to use a high number to reduce complexity to 129 // zero (or less than zero). 130 let AddedComplexity = -1000; 131 132 let VOP3 = 1; 133 let VALU = 1; 134 let FPClamp = P.HasFPClamp; 135 let IntClamp = P.HasIntClamp; 136 let ClampLo = P.HasClampLo; 137 let ClampHi = P.HasClampHi; 138 139 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 140 141 let mayRaiseFPException = ReadsModeReg; 142 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 143 144 let AsmVariantName = AMDGPUAsmVariants.VOP3; 145 let AsmMatchConverter = 146 !if(isVOP3P, 147 "cvtVOP3P", 148 !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), 149 "cvtVOP3", 150 "")); 151} 152 153class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> : 154 VOP3_Pseudo<opName, P, pattern, 1> { 155 let VOP3P = 1; 156} 157 158class VOP_Real<VOP_Pseudo ps> { 159 Instruction Opcode = !cast<Instruction>(NAME); 160 bit IsSingle = ps.Pfl.IsSingle; 161} 162 163class VOP3_Real <VOP_Pseudo ps, int EncodingFamily, string asm_name = ps.Mnemonic> : 164 VOP_Real <ps>, 165 InstSI <ps.OutOperandList, ps.InOperandList, asm_name # ps.AsmOperands, []>, 166 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 167 168 let VALU = 1; 169 let VOP3 = 1; 170 let isPseudo = 0; 171 let isCodeGenOnly = 0; 172 let UseNamedOperandTable = 1; 173 174 // copy relevant pseudo op flags 175 let SubtargetPredicate = ps.SubtargetPredicate; 176 let OtherPredicates = ps.OtherPredicates; 177 let AsmMatchConverter = ps.AsmMatchConverter; 178 let AsmVariantName = ps.AsmVariantName; 179 let Constraints = ps.Constraints; 180 let DisableEncoding = ps.DisableEncoding; 181 let TSFlags = ps.TSFlags; 182 let UseNamedOperandTable = ps.UseNamedOperandTable; 183 let Uses = ps.Uses; 184 let Defs = ps.Defs; 185 let SchedRW = ps.SchedRW; 186 let mayLoad = ps.mayLoad; 187 let mayStore = ps.mayStore; 188 let TRANS = ps.TRANS; 189 190 VOPProfile Pfl = ps.Pfl; 191} 192 193// XXX - Is there any reason to distinguish this from regular VOP3 194// here? 195class VOP3P_Real<VOP_Pseudo ps, int EncodingFamily, string asm_name = ps.Mnemonic> : 196 VOP3_Real<ps, EncodingFamily, asm_name> { 197 198 // The v_wmma pseudos have extra constraints that we do not want to impose on the real instruction. 199 let Constraints = !if(!eq(!substr(ps.Mnemonic,0,6), "v_wmma"), "", ps.Constraints); 200} 201 202class VOP3a<VOPProfile P> : Enc64 { 203 bits<4> src0_modifiers; 204 bits<9> src0; 205 bits<3> src1_modifiers; 206 bits<9> src1; 207 bits<3> src2_modifiers; 208 bits<9> src2; 209 bits<1> clamp; 210 bits<2> omod; 211 212 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 213 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); 214 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); 215 216 let Inst{31-26} = 0x34; //encoding 217 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 218 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 219 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 220 let Inst{60-59} = !if(P.HasOMod, omod, 0); 221 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 222 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 223 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 224} 225 226class VOP3a_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a<p> { 227 let Inst{11} = !if(p.HasClamp, clamp{0}, 0); 228 let Inst{25-17} = op; 229} 230 231class VOP3a_gfx10<bits<10> op, VOPProfile p> : VOP3a<p> { 232 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 233 let Inst{25-16} = op; 234 let Inst{31-26} = 0x35; 235} 236 237class VOP3a_gfx11<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p>; 238 239class VOP3a_vi <bits<10> op, VOPProfile P> : VOP3a<P> { 240 let Inst{25-16} = op; 241 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 242} 243 244class VOP3e_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a_gfx6_gfx7<op, p> { 245 bits<8> vdst; 246 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 247} 248 249class VOP3e_gfx10<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p> { 250 bits<8> vdst; 251 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 252} 253 254class VOP3e_gfx11<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p>; 255 256class VOP3e_vi <bits<10> op, VOPProfile P> : VOP3a_vi <op, P> { 257 bits<8> vdst; 258 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0); 259} 260 261class VOP3OpSel_gfx9 <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 262 let Inst{11} = !if(P.HasSrc0, src0_modifiers{2}, 0); 263 let Inst{12} = !if(P.HasSrc1, src1_modifiers{2}, 0); 264 let Inst{13} = !if(P.HasSrc2, src2_modifiers{2}, 0); 265 let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0); 266} 267 268class VOP3OpSel_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 269 let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0); 270 let Inst{12} = !if(p.HasSrc1, src1_modifiers{2}, 0); 271 let Inst{13} = !if(p.HasSrc2, src2_modifiers{2}, 0); 272 let Inst{14} = !if(p.HasDst, src0_modifiers{3}, 0); 273} 274 275class VOP3OpSel_gfx11<bits<10> op, VOPProfile p> : VOP3OpSel_gfx10<op, p>; 276 277class VOP3DotOpSel_gfx11<bits<10> op, VOPProfile p> : VOP3OpSel_gfx11<op, p>{ 278 let Inst{11} = ?; 279 let Inst{12} = ?; 280} 281 282// NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa 283class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 284 bits<2> attrchan; 285 bits<6> attr; 286 bits<1> high; 287 288 let Inst{8} = 0; // No modifiers for src0 289 let Inst{61} = 0; 290 291 let Inst{9} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 292 let Inst{62} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 293 294 let Inst{37-32} = attr; 295 let Inst{39-38} = attrchan; 296 let Inst{40} = !if(P.HasHigh, high, 0); 297 298 let Inst{49-41} = src0; 299} 300 301class VOP3Interp_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 302 bits<6> attr; 303 bits<2> attrchan; 304 bits<1> high; 305 306 let Inst{8} = 0; 307 let Inst{9} = !if(p.HasSrc0Mods, src0_modifiers{1}, 0); 308 let Inst{37-32} = attr; 309 let Inst{39-38} = attrchan; 310 let Inst{40} = !if(p.HasHigh, high, 0); 311 let Inst{49-41} = src0; 312 let Inst{61} = 0; 313 let Inst{62} = !if(p.HasSrc0Mods, src0_modifiers{0}, 0); 314} 315 316class VOP3Interp_gfx11<bits<10> op, VOPProfile p> : VOP3Interp_gfx10<op, p>; 317 318class VOP3be <VOPProfile P> : Enc64 { 319 bits<8> vdst; 320 bits<2> src0_modifiers; 321 bits<9> src0; 322 bits<2> src1_modifiers; 323 bits<9> src1; 324 bits<2> src2_modifiers; 325 bits<9> src2; 326 bits<7> sdst; 327 bits<2> omod; 328 329 let Inst{7-0} = vdst; 330 let Inst{14-8} = sdst; 331 let Inst{31-26} = 0x34; //encoding 332 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 333 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 334 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 335 let Inst{60-59} = !if(P.HasOMod, omod, 0); 336 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 337 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 338 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 339} 340 341class VOP3Pe <bits<7> op, VOPProfile P> : Enc64 { 342 bits<8> vdst; 343 bits<4> src0_modifiers; 344 bits<9> src0; 345 bits<4> src1_modifiers; 346 bits<9> src1; 347 bits<4> src2_modifiers; 348 bits<9> src2; 349 bits<1> clamp; 350 351 let Inst{7-0} = vdst; 352 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0 353 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1 354 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2 355 356 let Inst{11} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{2}, 0); // op_sel(0) 357 let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1) 358 let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2) 359 360 let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, ?); // op_sel_hi(2) 361 362 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 363 364 let Inst{22-16} = op; 365 let Inst{31-23} = 0x1a7; //encoding 366 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 367 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 368 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 369 let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, ?); // op_sel_hi(0) 370 let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, ?); // op_sel_hi(1) 371 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo) 372 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo) 373 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo) 374} 375 376class VOP3Pe_MAI <bits<7> op, VOPProfile P, bit acc_cd = 0> : Enc64 { 377 bits<8> vdst; 378 bits<10> src0; 379 bits<10> src1; 380 bits<9> src2; 381 bits<3> blgp; 382 bits<3> cbsz; 383 bits<4> abid; 384 385 let Inst{7-0} = vdst; 386 387 let Inst{10-8} = !if(P.HasSrc1, cbsz, 0); 388 let Inst{14-11} = !if(P.HasSrc1, abid, 0); 389 390 let Inst{15} = acc_cd; 391 392 let Inst{22-16} = op; 393 let Inst{31-23} = 0x1a7; //encoding 394 let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0); 395 let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0); 396 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 397 398 let Inst{59} = !if(P.HasSrc0, src0{9}, 0); // acc(0) 399 let Inst{60} = !if(P.HasSrc1, src1{9}, 0); // acc(1) 400 401 let Inst{63-61} = !if(P.HasSrc1, blgp, 0); 402} 403 404class VOP3Pe_SMFMAC <bits<7> op> : Enc64 { 405 bits<10> vdst; // VGPR or AGPR, but not SGPR. vdst{8} is not encoded in the instruction. 406 bits<10> src0; 407 bits<10> src1; 408 bits<9> idx; 409 bits<3> blgp; 410 bits<3> cbsz; 411 bits<4> abid; 412 413 let blgp = 0; 414 415 let Inst{7-0} = vdst{7-0}; 416 417 let Inst{10-8} = cbsz; 418 let Inst{14-11} = abid; 419 420 let Inst{15} = vdst{9}; // acc(vdst) 421 422 let Inst{22-16} = op; 423 let Inst{31-23} = 0x1a7; // encoding 424 let Inst{40-32} = src0{8-0}; 425 let Inst{49-41} = src1{8-0}; 426 let Inst{58-50} = idx; 427 428 let Inst{59} = src0{9}; // acc(0) 429 let Inst{60} = src1{9}; // acc(1) 430 431 let Inst{63-61} = blgp; 432} 433 434class VOP3Pe_gfx10 <bits<7> op, VOPProfile P> : VOP3Pe<op, P> { 435 let Inst{31-23} = 0x198; //encoding 436} 437 438class VOP3Pe_gfx11<bits<7> op, VOPProfile P> : VOP3Pe_gfx10<op, P>; 439 440class VOP3be_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3be<p> { 441 let Inst{25-17} = op; 442} 443 444class VOP3be_gfx10<bits<10> op, VOPProfile p> : VOP3be<p> { 445 bits<1> clamp; 446 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 447 let Inst{25-16} = op; 448 let Inst{31-26} = 0x35; 449} 450 451class VOP3be_gfx11<bits<10> op, VOPProfile p> : VOP3be_gfx10<op, p>; 452 453class VOP3be_vi <bits<10> op, VOPProfile P> : VOP3be<P> { 454 bits<1> clamp; 455 let Inst{25-16} = op; 456 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 457} 458 459def SDWA { 460 // sdwa_sel 461 int BYTE_0 = 0; 462 int BYTE_1 = 1; 463 int BYTE_2 = 2; 464 int BYTE_3 = 3; 465 int WORD_0 = 4; 466 int WORD_1 = 5; 467 int DWORD = 6; 468 469 // dst_unused 470 int UNUSED_PAD = 0; 471 int UNUSED_SEXT = 1; 472 int UNUSED_PRESERVE = 2; 473} 474 475class VOP_SDWAe<VOPProfile P> : Enc64 { 476 bits<8> src0; 477 bits<3> src0_sel; 478 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 479 bits<3> src1_sel; 480 bits<2> src1_modifiers; 481 bits<3> dst_sel; 482 bits<2> dst_unused; 483 bits<1> clamp; 484 485 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 486 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?); 487 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?); 488 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 489 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 490 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 491 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 492 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 493 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 494 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 495} 496 497// GFX9 adds two features to SDWA: 498// 1. Add 3 fields to the SDWA microcode word: S0, S1 and OMOD. 499// a. S0 and S1 indicate that source 0 and 1 respectively are SGPRs rather 500// than VGPRs (at most 1 can be an SGPR); 501// b. OMOD is the standard output modifier (result *2, *4, /2) 502// 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This 503// replaces OMOD and the dest fields with SD and SDST (SGPR destination) 504// field. 505// a. When SD=1, the SDST is used as the destination for the compare result; 506// b. When SD=0, VCC is used. 507// 508// In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA 509 510// gfx9 SDWA basic encoding 511class VOP_SDWA9e<VOPProfile P> : Enc64 { 512 bits<9> src0; // {src0_sgpr{0}, src0{7-0}} 513 bits<3> src0_sel; 514 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 515 bits<3> src1_sel; 516 bits<2> src1_modifiers; 517 bits<1> src1_sgpr; 518 519 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 520 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 521 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 522 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 523 let Inst{55} = !if(P.HasSrc0, src0{8}, 0); 524 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 525 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 526 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 527 let Inst{63} = 0; // src1_sgpr - should be specified in subclass 528} 529 530// gfx9 SDWA-A 531class VOP_SDWA9Ae<VOPProfile P> : VOP_SDWA9e<P> { 532 bits<3> dst_sel; 533 bits<2> dst_unused; 534 bits<1> clamp; 535 bits<2> omod; 536 537 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?); 538 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?); 539 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 540 let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0); 541} 542 543// gfx9 SDWA-B 544class VOP_SDWA9Be<VOPProfile P> : VOP_SDWA9e<P> { 545 bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}} 546 547 let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, ?); 548 let Inst{47} = !if(P.EmitDst, sdst{7}, 0); 549} 550 551class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> : 552 InstSI <P.OutsSDWA, P.InsSDWA, "", pattern>, 553 VOP <opName>, 554 SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE> { 555 556 let isPseudo = 1; 557 let isCodeGenOnly = 1; 558 let UseNamedOperandTable = 1; 559 560 string Mnemonic = opName; 561 string AsmOperands = P.AsmSDWA; 562 string AsmOperands9 = P.AsmSDWA9; 563 564 let Size = 8; 565 let mayLoad = 0; 566 let mayStore = 0; 567 let hasSideEffects = 0; 568 569 let VALU = 1; 570 let SDWA = 1; 571 572 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 573 574 let mayRaiseFPException = ReadsModeReg; 575 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 576 577 let SubtargetPredicate = HasSDWA; 578 let AssemblerPredicate = HasSDWA; 579 let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA, 580 AMDGPUAsmVariants.Disable); 581 let DecoderNamespace = "SDWA"; 582 583 VOPProfile Pfl = P; 584} 585 586class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> : 587 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 588 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> { 589 590 let VALU = 1; 591 let SDWA = 1; 592 let isPseudo = 0; 593 let isCodeGenOnly = 0; 594 595 let Defs = ps.Defs; 596 let Uses = ps.Uses; 597 let hasSideEffects = ps.hasSideEffects; 598 599 let Constraints = ps.Constraints; 600 let DisableEncoding = ps.DisableEncoding; 601 602 // Copy relevant pseudo op flags 603 let SubtargetPredicate = ps.SubtargetPredicate; 604 let AssemblerPredicate = ps.AssemblerPredicate; 605 let AsmMatchConverter = ps.AsmMatchConverter; 606 let AsmVariantName = ps.AsmVariantName; 607 let UseNamedOperandTable = ps.UseNamedOperandTable; 608 let DecoderNamespace = ps.DecoderNamespace; 609 let Constraints = ps.Constraints; 610 let DisableEncoding = ps.DisableEncoding; 611 let TSFlags = ps.TSFlags; 612 let SchedRW = ps.SchedRW; 613 let mayLoad = ps.mayLoad; 614 let mayStore = ps.mayStore; 615 let TRANS = ps.TRANS; 616} 617 618class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 619 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands9, []> { 620 621 let VALU = 1; 622 let SDWA = 1; 623 let isPseudo = 0; 624 let isCodeGenOnly = 0; 625 626 let Defs = ps.Defs; 627 let Uses = ps.Uses; 628 let hasSideEffects = ps.hasSideEffects; 629 630 let Constraints = ps.Constraints; 631 let DisableEncoding = ps.DisableEncoding; 632 633 let SubtargetPredicate = HasSDWA9; 634 let AssemblerPredicate = HasSDWA9; 635 let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9, 636 AMDGPUAsmVariants.Disable); 637 let DecoderNamespace = "SDWA9"; 638 639 // Copy relevant pseudo op flags 640 let AsmMatchConverter = ps.AsmMatchConverter; 641 let UseNamedOperandTable = ps.UseNamedOperandTable; 642 let Constraints = ps.Constraints; 643 let DisableEncoding = ps.DisableEncoding; 644 let TSFlags = ps.TSFlags; 645 let SchedRW = ps.SchedRW; 646 let mayLoad = ps.mayLoad; 647 let mayStore = ps.mayStore; 648 let TRANS = ps.TRANS; 649} 650 651class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 652 Base_VOP_SDWA9_Real <ps >, 653 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>; 654 655class Base_VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : Base_VOP_SDWA9_Real<ps> { 656 let SubtargetPredicate = HasSDWA10; 657 let AssemblerPredicate = HasSDWA10; 658 let DecoderNamespace = "SDWA10"; 659} 660 661class VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : 662 Base_VOP_SDWA10_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SDWA10>; 663 664class VOP_DPPe<VOPProfile P, bit IsDPP16=0> : Enc64 { 665 bits<2> src0_modifiers; 666 bits<8> src0; 667 bits<2> src1_modifiers; 668 bits<9> dpp_ctrl; 669 bits<1> bound_ctrl; 670 bits<4> bank_mask; 671 bits<4> row_mask; 672 bit fi; 673 674 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 675 let Inst{48-40} = dpp_ctrl; 676 let Inst{50} = !if(IsDPP16, fi, ?); 677 let Inst{51} = bound_ctrl; 678 let Inst{52} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg 679 let Inst{53} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs 680 let Inst{54} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg 681 let Inst{55} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs 682 let Inst{59-56} = bank_mask; 683 let Inst{63-60} = row_mask; 684} 685 686class VOP3_DPPe_Fields_Base { 687 bits<9> dpp_ctrl; 688 bits<1> bound_ctrl; 689 bits<4> bank_mask; 690 bits<4> row_mask; 691 bit fi; 692} 693class VOP3_DPPe_Fields : VOP3_DPPe_Fields_Base { 694 bits<8> src0; 695} 696 697// Common refers to common between DPP and DPP8 698class VOP3_DPPe_Common_Base<bits<10> op, VOPProfile P> : Enc96 { 699 bits<4> src0_modifiers; 700 bits<3> src1_modifiers; 701 bits<3> src2_modifiers; 702 bits<1> clamp; 703 bits<2> omod; 704 705 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 706 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); 707 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); 708 // OPSEL must be set such that the low result only uses low inputs, and the high result only uses high inputs. 709 let Inst{11} = !if(P.HasOpSel,!if(P.HasSrc0Mods, src0_modifiers{2}, 0),?); 710 let Inst{12} = !if(P.HasOpSel,!if(P.HasSrc1Mods, src1_modifiers{2}, 0),?); 711 let Inst{13} = !if(P.HasOpSel,!if(P.HasSrc2Mods, src2_modifiers{2}, 0),?); 712 let Inst{14} = !if(P.HasOpSel,!if(P.HasSrc0Mods, src0_modifiers{3}, 0),?); 713 let Inst{15} = !if(P.HasClamp, clamp, 0); 714 let Inst{25-16} = op; 715 let Inst{31-26} = 0x35; 716 717 let Inst{60-59} = !if(P.HasOMod, omod, 0); 718 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 719 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 720 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 721} 722 723class VOP3_DPPe_Common<bits<10> op, VOPProfile P> : VOP3_DPPe_Common_Base<op, P> { 724 bits<8> vdst; 725 bits<9> src1; 726 bits<9> src2; 727 728 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0); 729 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 730 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 731} 732 733class VOP3P_DPPe_Common_Base<bits<7> op, VOPProfile P> : Enc96 { 734 bits<4> src0_modifiers; 735 bits<4> src1_modifiers; 736 bits<4> src2_modifiers; 737 bits<1> clamp; 738 739 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0 740 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1 741 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2 742 let Inst{11} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{2}, 0); // op_sel(0) 743 let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1) 744 let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2) 745 let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, ?); // op_sel_hi(2) 746 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 747 let Inst{22-16} = op; 748 let Inst{31-23} = 0x198; // encoding 749 let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, ?); // op_sel_hi(0) 750 let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, ?); // op_sel_hi(1) 751 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo) 752 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo) 753 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo) 754} 755 756class VOP3P_DPPe_Common<bits<7> op, VOPProfile P> : VOP3P_DPPe_Common_Base<op, P> { 757 bits<8> vdst; 758 bits<9> src1; 759 bits<9> src2; 760 761 let Inst{7-0} = vdst; 762 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 763 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 764} 765 766class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[], 767 dag Ins = P.InsDPP, string asmOps = P.AsmDPP> : 768 InstSI <P.OutsDPP, Ins, OpName#asmOps, pattern>, 769 VOP <OpName>, 770 SIMCInstr <OpName#"_dpp", SIEncodingFamily.NONE> { 771 772 let isPseudo = 1; 773 let isCodeGenOnly = 1; 774 775 let mayLoad = 0; 776 let mayStore = 0; 777 let hasSideEffects = 0; 778 let UseNamedOperandTable = 1; 779 780 let VALU = 1; 781 let DPP = 1; 782 let Size = 8; 783 784 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 785 786 let mayRaiseFPException = ReadsModeReg; 787 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 788 let isConvergent = 1; 789 790 string Mnemonic = OpName; 791 string AsmOperands = asmOps; 792 793 let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); 794 let SubtargetPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 795 let AssemblerPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 796 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 797 AMDGPUAsmVariants.Disable); 798 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 799 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 800 let DecoderNamespace = "DPP"; 801 802 VOPProfile Pfl = P; 803} 804 805class VOP3_DPP_Pseudo <string OpName, VOPProfile P> : 806 VOP_DPP_Pseudo <OpName, P, [], P.InsVOP3DPP, P.AsmVOP3DPP> { 807 let PseudoInstr = OpName#"_e64"#"_dpp"; 808 let OutOperandList = P.OutsVOP3DPP; 809 let Size = 12; 810 let VOP3 = 1; 811 let AsmMatchConverter = "cvtVOP3DPP"; 812 let AsmVariantName = !if(P.HasExtVOP3DPP, AMDGPUAsmVariants.VOP3_DPP, 813 AMDGPUAsmVariants.Disable); 814} 815 816class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> : 817 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 818 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 819 820 let VALU = 1; 821 let DPP = 1; 822 let isPseudo = 0; 823 let isCodeGenOnly = 0; 824 825 let Defs = ps.Defs; 826 let Uses = ps.Uses; 827 let hasSideEffects = ps.hasSideEffects; 828 829 let Constraints = ps.Constraints; 830 let DisableEncoding = ps.DisableEncoding; 831 832 // Copy relevant pseudo op flags 833 let isConvergent = ps.isConvergent; 834 let SubtargetPredicate = ps.SubtargetPredicate; 835 let AssemblerPredicate = ps.AssemblerPredicate; 836 let OtherPredicates = ps.OtherPredicates; 837 let AsmMatchConverter = ps.AsmMatchConverter; 838 let AsmVariantName = ps.AsmVariantName; 839 let UseNamedOperandTable = ps.UseNamedOperandTable; 840 let DecoderNamespace = ps.DecoderNamespace; 841 let Constraints = ps.Constraints; 842 let DisableEncoding = ps.DisableEncoding; 843 let TSFlags = ps.TSFlags; 844 let SchedRW = ps.SchedRW; 845 let mayLoad = ps.mayLoad; 846 let mayStore = ps.mayStore; 847 let TRANS = ps.TRANS; 848} 849 850class VOP_DPP_Base <string OpName, VOPProfile P, 851 dag InsDPP, 852 string AsmDPP > : 853 InstSI <P.OutsDPP, InsDPP, OpName#AsmDPP, []> { 854 855 let mayLoad = 0; 856 let mayStore = 0; 857 let hasSideEffects = 0; 858 let UseNamedOperandTable = 1; 859 860 let VALU = 1; 861 let DPP = 1; 862 let Size = 8; 863 864 let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); 865 let SubtargetPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 866 let AssemblerPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 867 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 868 AMDGPUAsmVariants.Disable); 869 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 870 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 871 let DecoderNamespace = "DPP"; 872} 873 874class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16, 875 dag InsDPP = !if(IsDPP16, P.InsDPP16, P.InsDPP), 876 string AsmDPP = !if(IsDPP16, P.AsmDPP16, P.AsmDPP)> : 877 VOP_DPP_Base<OpName, P, InsDPP, AsmDPP>, VOP_DPPe<P, IsDPP16>; 878 879class VOP3_DPP_Base <string OpName, VOPProfile P, bit IsDPP16, 880 dag InsDPP = !if(IsDPP16, P.InsVOP3DPP16, P.InsVOP3DPP), 881 string AsmDPP = !if(IsDPP16, P.AsmVOP3DPP16, P.AsmVOP3DPP)> : 882 VOP_DPP_Base<OpName, P, InsDPP, AsmDPP> { 883 let OutOperandList = P.OutsVOP3DPP; 884 let AsmMatchConverter = "cvtVOP3DPP"; 885 let VOP3 = 1; 886 let AsmVariantName = !if(P.HasExtVOP3DPP, AMDGPUAsmVariants.VOP3_DPP, 887 AMDGPUAsmVariants.Disable); 888 let Size = 12; 889} 890 891class VOP3_DPP <bits<10> op, string OpName, VOPProfile P, bit IsDPP16, 892 dag InsDPP = !if(IsDPP16, P.InsVOP3DPP16, P.InsVOP3DPP), 893 string AsmDPP = !if(IsDPP16, P.AsmVOP3DPP16, P.AsmVOP3DPP)> : 894 VOP3_DPP_Base<OpName, P, IsDPP16, InsDPP, AsmDPP>, VOP3_DPPe_Common<op, P>, 895 VOP3_DPPe_Fields { 896 897 let Inst{40-32} = 0xfa; 898 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 899 let Inst{80-72} = dpp_ctrl; 900 let Inst{82} = !if(IsDPP16, fi, ?); 901 let Inst{83} = bound_ctrl; 902 903 // Inst{87-84} ignored by hw 904 let Inst{91-88} = bank_mask; 905 let Inst{95-92} = row_mask; 906} 907 908class VOP3P_DPP <bits<7> op, string OpName, VOPProfile P, bit IsDPP16, 909 dag InsDPP = !if(IsDPP16, P.InsVOP3DPP16, P.InsVOP3DPP), 910 string AsmDPP = !if(IsDPP16, P.AsmVOP3DPP16, P.AsmVOP3DPP)> : 911 VOP3_DPP_Base<OpName, P, IsDPP16, InsDPP, AsmDPP>, VOP3P_DPPe_Common<op, P>, 912 VOP3_DPPe_Fields { 913 914 let VOP3P = 1; 915 916 let Inst{40-32} = 0xfa; 917 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 918 let Inst{80-72} = dpp_ctrl; 919 let Inst{82} = !if(IsDPP16, fi, ?); 920 let Inst{83} = bound_ctrl; 921 922 // Inst{87-84} ignored by hw 923 let Inst{91-88} = bank_mask; 924 let Inst{95-92} = row_mask; 925} 926 927class VOP_DPP8e<VOPProfile P> : Enc64 { 928 bits<8> src0; 929 bits<24> dpp8; 930 bits<9> fi; 931 932 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 933 let Inst{63-40} = dpp8{23-0}; 934} 935 936class VOP3_DPP8e_Fields { 937 bits<8> src0; 938 bits<24> dpp8; 939 bits<9> fi; 940} 941 942class VOP_DPP8_Base<string OpName, VOPProfile P, dag InsDPP8 = P.InsDPP8, string AsmDPP8 = P.AsmDPP8> : 943 InstSI<P.OutsDPP8, InsDPP8, OpName#AsmDPP8, []> { 944 945 let mayLoad = 0; 946 let mayStore = 0; 947 let hasSideEffects = 0; 948 let UseNamedOperandTable = 1; 949 950 let VALU = 1; 951 let DPP = 1; 952 let Size = 8; 953 954 let AsmMatchConverter = "cvtDPP8"; 955 let SubtargetPredicate = HasDPP8; 956 let AssemblerPredicate = HasDPP8; 957 let AsmVariantName = AMDGPUAsmVariants.DPP; 958 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 959 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 960} 961 962class VOP_DPP8<string OpName, VOPProfile P> : 963 VOP_DPP8_Base<OpName, P>, VOP_DPP8e<P>; 964 965class VOP3_DPP8_Base<string OpName, VOPProfile P> : 966 VOP_DPP8_Base<OpName, P, P.InsVOP3DPP8, P.AsmVOP3DPP8> { 967 let OutOperandList = P.OutsVOP3DPP8; 968 let AsmMatchConverter = "cvtVOP3DPP8"; 969 let AsmVariantName = !if(P.HasExtVOP3DPP, AMDGPUAsmVariants.VOP3_DPP, 970 AMDGPUAsmVariants.Disable); 971 let VOP3 = 1; 972 let Size = 12; 973} 974 975 976class VOP3_DPP8<bits<10> op, string OpName, VOPProfile P> : 977 VOP3_DPP8_Base<OpName, P>, VOP3_DPPe_Common<op, P>, 978 VOP3_DPP8e_Fields { 979 980 let Inst{40-32} = fi; 981 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 982 let Inst{95-72} = dpp8{23-0}; 983} 984 985class VOP3P_DPP8<bits<7> op, string OpName, VOPProfile P> : 986 VOP3_DPP8_Base<OpName, P>, VOP3P_DPPe_Common<op, P>, 987 VOP3_DPP8e_Fields { 988 989 let VOP3P = 1; 990 let Inst{40-32} = fi; 991 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 992 let Inst{95-72} = dpp8{23-0}; 993} 994 995def DPP8Mode { 996 int FI_0 = 0xE9; 997 int FI_1 = 0xEA; 998} 999 1000class getNumNodeArgs<SDPatternOperator Op> { 1001 SDNode N = !cast<SDNode>(Op); 1002 SDTypeProfile TP = N.TypeProfile; 1003 int ret = TP.NumOperands; 1004} 1005 1006class getDivergentFrag<SDPatternOperator Op> { 1007 assert !or(!isa<SDNode>(Op), !isa<PatFrags>(Op)), "Expected SDNode or PatFrags"; 1008 1009 int NumSrcArgs = !if(!isa<SDNode>(Op), getNumNodeArgs<Op>.ret, 1010 !size(!cast<PatFrags>(Op).Operands)); 1011 PatFrag ret = PatFrag < 1012 !if(!eq(NumSrcArgs, 1), 1013 (ops node:$src0), 1014 !if(!eq(NumSrcArgs, 2), 1015 (ops node:$src0, node:$src1), 1016 (ops node:$src0, node:$src1, node:$src2))), 1017 !if(!eq(NumSrcArgs, 1), 1018 (Op $src0), 1019 !if(!eq(NumSrcArgs, 2), 1020 (Op $src0, $src1), 1021 (Op $src0, $src1, $src2))), 1022 [{ return N->isDivergent(); }] 1023 >; 1024} 1025 1026class VOPPatGen<SDPatternOperator Op, VOPProfile P> { 1027 PatFrag Operator = getDivergentFrag < Op >.ret; 1028 1029 dag Ins = !foreach(tmp, P.Ins32, !subst(ins, Operator, 1030 !subst(P.Src0RC32, P.Src0VT, 1031 !subst(P.Src1RC32, P.Src1VT, tmp)))); 1032 1033 dag Outs = !foreach(tmp, P.Outs32, !subst(outs, set, 1034 !subst(P.DstRC, P.DstVT, tmp))); 1035 1036 list<dag> ret = [!con(Outs, (set Ins))]; 1037} 1038 1039class DivergentUnaryFrag<SDPatternOperator Op> : PatFrag < 1040 (ops node:$src0), 1041 (Op $src0), 1042 [{ return N->isDivergent(); }]> { 1043 // This check is unnecessary as it's captured by the result register 1044 // bank constraint. 1045 // 1046 // FIXME: Should add a way for the emitter to recognize this is a 1047 // trivially true predicate to eliminate the check. 1048 let GISelPredicateCode = [{return true;}]; 1049} 1050 1051class VOPPatOrNull<SDPatternOperator Op, VOPProfile P> { 1052 list<dag> ret = !if(!ne(P.NeedPatGen,PatGenMode.NoPattern), VOPPatGen<Op, P>.ret, []); 1053} 1054 1055class DivergentFragOrOp<SDPatternOperator Op, VOPProfile P> { 1056 SDPatternOperator ret = !if(!eq(P.NeedPatGen,PatGenMode.Pattern), 1057 !if(!isa<SDNode>(Op), getDivergentFrag<Op>.ret, Op), Op); 1058} 1059 1060class getVSrcOp<ValueType vt> { 1061 RegisterOperand ret = !if(!eq(vt.Size, 32), VSrc_b32, VSrc_b16); 1062} 1063 1064// Class for binary integer operations with the clamp bit set for saturation 1065// TODO: Add sub with negated inline constant pattern. 1066class VOPBinOpClampPat<SDPatternOperator node, Instruction inst, ValueType vt> : 1067 GCNPat<(node vt:$src0, vt:$src1), 1068 (inst getVSrcOp<vt>.ret:$src0, getVSrcOp<vt>.ret:$src1, 1069 DSTCLAMP.ENABLE) 1070>; 1071 1072//===----------------------------------------------------------------------===// 1073// VOP3 Classes 1074//===----------------------------------------------------------------------===// 1075 1076class getVOP3ModPat<VOPProfile P, SDPatternOperator node> { 1077 dag src0 = !if(P.HasOMod, 1078 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 1079 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)); 1080 1081 list<dag> ret3 = [(set P.DstVT:$vdst, 1082 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 1083 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), 1084 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))]; 1085 1086 list<dag> ret2 = [(set P.DstVT:$vdst, 1087 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 1088 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))]; 1089 1090 list<dag> ret1 = [(set P.DstVT:$vdst, 1091 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))]; 1092 1093 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1094 !if(!eq(P.NumSrcArgs, 2), ret2, 1095 ret1)); 1096} 1097 1098class getVOP3PModPat<VOPProfile P, SDPatternOperator node, bit HasExplicitClamp, 1099 bit IsDOT = 0, 1100 ComplexPattern SrcPat = !if(IsDOT, VOP3PModsDOT, VOP3PMods)> { 1101 dag src0_dag = (P.Src0VT (SrcPat P.Src0VT:$src0, i32:$src0_modifiers)); 1102 dag src1_dag = (P.Src1VT (SrcPat P.Src1VT:$src1, i32:$src1_modifiers)); 1103 dag src2_dag = (P.Src2VT (SrcPat P.Src2VT:$src2, i32:$src2_modifiers)); 1104 dag clamp_dag = (i1 timm:$clamp); 1105 1106 list<dag> ret3 = [(set P.DstVT:$vdst, 1107 !if(HasExplicitClamp, 1108 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag, clamp_dag), 1109 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag)))]; 1110 1111 list<dag> ret2 = [(set P.DstVT:$vdst, 1112 !if(HasExplicitClamp, 1113 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, clamp_dag), 1114 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag)))]; 1115 1116 list<dag> ret1 = [(set P.DstVT:$vdst, 1117 !if(HasExplicitClamp, 1118 (DivergentFragOrOp<node, P>.ret src0_dag, clamp_dag), 1119 (DivergentFragOrOp<node, P>.ret src0_dag)))]; 1120 1121 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1122 !if(!eq(P.NumSrcArgs, 2), ret2, 1123 ret1)); 1124} 1125 1126class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> { 1127 list<dag> ret3 = [(set P.DstVT:$vdst, 1128 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 1129 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)), 1130 (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))]; 1131 1132 list<dag> ret2 = [(set P.DstVT:$vdst, 1133 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 1134 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))]; 1135 1136 list<dag> ret1 = [(set P.DstVT:$vdst, 1137 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))))]; 1138 1139 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1140 !if(!eq(P.NumSrcArgs, 2), ret2, 1141 ret1)); 1142} 1143 1144class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> { 1145 list<dag> ret3 = [(set P.DstVT:$vdst, 1146 (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers), 1147 (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 1148 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)), 1149 (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))]; 1150 1151 list<dag> ret2 = [(set P.DstVT:$vdst, 1152 (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers)), 1153 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 1154 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))]; 1155 1156 list<dag> ret1 = [(set P.DstVT:$vdst, 1157 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))))]; 1158 1159 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1160 !if(!eq(P.NumSrcArgs, 2), ret2, 1161 ret1)); 1162} 1163 1164class getVOP3FromVOP2Pat<VOPProfile P, SDPatternOperator node> { 1165 list<dag> ret = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]; 1166} 1167// In VOP1, we can have clamp and omod even if !HasModifiers 1168class getVOP3Pat<VOPProfile P, SDPatternOperator node> { 1169 dag src0 = 1170 !if(P.HasOMod, 1171 !if(P.HasClamp, 1172 (VOP3Mods0 P.Src0VT:$src0, i1:$clamp, i32:$omod), 1173 (VOP3Mods0 P.Src0VT:$src0, i32:$omod)), // impossible? 1174 !if(P.HasClamp, 1175 (VOP3Mods0 P.Src0VT:$src0, i1:$clamp), 1176 (VOP3Mods0 P.Src0VT:$src0)) 1177 ); 1178 list<dag> ret3 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), P.Src1VT:$src1, P.Src2VT:$src2))]; 1179 1180 list<dag> ret2 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), P.Src1VT:$src1))]; 1181 1182 list<dag> ret1 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))]; 1183 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1184 !if(!eq(P.NumSrcArgs, 2), ret2, 1185 ret1)); 1186} 1187 1188class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> { 1189 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))]; 1190 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))]; 1191 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))]; 1192 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1193 !if(!eq(P.NumSrcArgs, 2), ret2, 1194 ret1)); 1195} 1196 1197class getVOP3MAIPat<VOPProfile P, SDPatternOperator node> { 1198 list<dag> ret = !if(!eq(P.Src0VT, P.Src1VT), 1199 // mfma 1200 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, 1201 timm:$cbsz, timm:$abid, timm:$blgp))], 1202 // smfmac 1203 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i32:$idx, 1204 timm:$cbsz, timm:$abid))]); 1205} 1206 1207class VOP3Features<bit Clamp, bit OpSel, bit Packed, bit MAI> { 1208 bit HasClamp = Clamp; 1209 bit HasOpSel = OpSel; 1210 bit IsPacked = Packed; 1211 bit IsMAI = MAI; 1212} 1213 1214def VOP3_REGULAR : VOP3Features<0, 0, 0, 0>; 1215def VOP3_CLAMP : VOP3Features<1, 0, 0, 0>; 1216def VOP3_OPSEL : VOP3Features<1, 1, 0, 0>; 1217def VOP3_PACKED : VOP3Features<1, 1, 1, 0>; 1218def VOP3_MAI : VOP3Features<0, 0, 0, 1>; 1219 1220class VOP3_Profile_Base<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProfile<P.ArgVT> { 1221 1222 let HasClamp = !if(Features.HasClamp, 1, P.HasClamp); 1223 let HasOpSel = !if(Features.HasOpSel, 1, P.HasOpSel); 1224 let IsMAI = !if(Features.IsMAI, 1, P.IsMAI); 1225 let IsPacked = !if(Features.IsPacked, 1, P.IsPacked); 1226 1227 let HasModifiers = 1228 !if (Features.IsMAI, 0, 1229 !or(Features.IsPacked, Features.HasOpSel, P.HasModifiers)); 1230} 1231 1232class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOP3_Profile_Base<P, Features> { 1233 let IsSingle = 1; 1234 1235} 1236 1237// consistently gives instructions a _e64 suffix 1238multiclass VOP3Inst_Pseudo_Wrapper<string opName, VOPProfile P, list<dag> pattern = [], bit VOP3Only = 0> { 1239 def _e64 : VOP3_Pseudo<opName, P, pattern, VOP3Only>; 1240} 1241 1242class VOP3InstBase<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit IsVOP2 = 0> : 1243 VOP3_Pseudo<OpName, P, 1244 !if(P.HasOpSel, 1245 !if(P.HasModifiers, 1246 getVOP3OpSelModPat<P, node>.ret, 1247 getVOP3OpSelPat<P, node>.ret), 1248 !if(P.HasModifiers, 1249 getVOP3ModPat<P, node>.ret, 1250 !if(IsVOP2, 1251 getVOP3FromVOP2Pat<P, node>.ret, 1252 !if(P.HasIntClamp, 1253 getVOP3ClampPat<P, node>.ret, 1254 !if (P.IsMAI, 1255 getVOP3MAIPat<P, node>.ret, 1256 getVOP3Pat<P, node>.ret))))), 1257 0, P.HasOpSel> { 1258 1259 let IntClamp = P.HasIntClamp; 1260 let AsmMatchConverter = 1261 !if(P.HasOpSel, 1262 "cvtVOP3OpSel", 1263 !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), 1264 "cvtVOP3", 1265 "")); 1266} 1267 1268multiclass VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> { 1269 def _e64 : VOP3InstBase<OpName, P, node>; 1270 let SubtargetPredicate = isGFX11Plus in { 1271 if P.HasExtVOP3DPP then 1272 def _e64_dpp : VOP3_DPP_Pseudo <OpName, P>; 1273 } // end SubtargetPredicate = isGFX11Plus 1274} 1275 1276//===----------------------------------------------------------------------===// 1277// VOP3 DPP 1278//===----------------------------------------------------------------------===// 1279 1280class Base_VOP3_DPP16<bits<10> op, VOP_DPP_Pseudo ps, string opName = ps.OpName> 1281 : VOP3_DPP<op, opName, ps.Pfl, 1> { 1282 let VOP3_OPSEL = ps.Pfl.HasOpSel; 1283 let IsDOT = ps.IsDOT; 1284 let hasSideEffects = ps.hasSideEffects; 1285 let Defs = ps.Defs; 1286 let SchedRW = ps.SchedRW; 1287 let Uses = ps.Uses; 1288 let AssemblerPredicate = HasDPP16; 1289 let SubtargetPredicate = HasDPP16; 1290 let OtherPredicates = ps.OtherPredicates; 1291} 1292 1293class VOP3_DPP16<bits<10> op, VOP_DPP_Pseudo ps, int subtarget, 1294 string opName = ps.OpName> 1295 : Base_VOP3_DPP16<op, ps, opName>, SIMCInstr<ps.PseudoInstr, subtarget>; 1296 1297class Base_VOP3_DPP8<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1298 : VOP3_DPP8<op, opName, ps.Pfl> { 1299 let VOP3_OPSEL = ps.Pfl.HasOpSel; 1300 let IsDOT = ps.IsDOT; 1301 let hasSideEffects = ps.hasSideEffects; 1302 let Defs = ps.Defs; 1303 let SchedRW = ps.SchedRW; 1304 let Uses = ps.Uses; 1305 1306 let OtherPredicates = ps.OtherPredicates; 1307} 1308 1309class Base_VOP3b_DPP16<bits<10> op, VOP_DPP_Pseudo ps, 1310 string opName = ps.OpName> 1311 : Base_VOP3_DPP16<op, ps, opName> { 1312 bits<7> sdst; 1313 let Inst{14 - 8} = sdst; 1314} 1315 1316class VOP3b_DPP8_Base<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1317 : Base_VOP3_DPP8<op, ps, opName> { 1318 bits<7> sdst; 1319 let Inst{14 - 8} = sdst; 1320} 1321 1322//===----------------------------------------------------------------------===// 1323// VOP3 GFX11 1324//===----------------------------------------------------------------------===// 1325 1326let AssemblerPredicate = isGFX11Only, 1327 DecoderNamespace = "GFX11" in { 1328 multiclass VOP3_Real_Base_gfx11<bits<10> op, string opName = NAME, 1329 bit isSingle = 0> { 1330 defvar ps = !cast<VOP_Pseudo>(opName#"_e64"); 1331 let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in { 1332 if ps.Pfl.HasOpSel then 1333 def _e64_gfx11 : 1334 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1335 VOP3OpSel_gfx11<op, ps.Pfl>; 1336 if !not(ps.Pfl.HasOpSel) then 1337 def _e64_gfx11 : 1338 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1339 VOP3e_gfx11<op, ps.Pfl>; 1340 } 1341 } 1342 multiclass VOP3Dot_Real_Base_gfx11<bits<10> op, string opName = NAME, 1343 bit isSingle = 0> { 1344 defvar ps = !cast<VOP_Pseudo>(opName#"_e64"); 1345 let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in { 1346 def _e64_gfx11 : 1347 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1348 VOP3DotOpSel_gfx11<op, ps.Pfl>; 1349 } 1350 } 1351 multiclass VOP3_Real_with_name_gfx11<bits<10> op, string opName, 1352 string asmName, bit isSingle = 0> { 1353 defvar ps = !cast<VOP_Pseudo>(opName#"_e64"); 1354 let AsmString = asmName # ps.AsmOperands, 1355 IsSingle = !or(isSingle, ps.Pfl.IsSingle) in { 1356 if ps.Pfl.HasOpSel then 1357 def _e64_gfx11 : 1358 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1359 VOP3OpSel_gfx11<op, ps.Pfl>; 1360 if !not(ps.Pfl.HasOpSel) then 1361 def _e64_gfx11 : 1362 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1363 VOP3e_gfx11<op, ps.Pfl>; 1364 } 1365 def _gfx11_VOP3_alias : MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Plus]>, LetDummies; 1366 } 1367 // for READLANE/WRITELANE 1368 multiclass VOP3_Real_No_Suffix_gfx11<bits<10> op, string opName = NAME> { 1369 defvar ps = !cast<VOP_Pseudo>(opName); 1370 def _e64_gfx11 : 1371 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1372 VOP3e_gfx11<op, ps.Pfl>; 1373 } 1374 multiclass VOP3_Real_dpp_Base_gfx11<bits<10> op, string opName = NAME> { 1375 def _e64_dpp_gfx11 : VOP3_DPP16<op, !cast<VOP_DPP_Pseudo>(opName#"_e64"#"_dpp"), SIEncodingFamily.GFX11> { 1376 let DecoderNamespace = "DPPGFX11"; 1377 } 1378 } 1379 1380 multiclass VOP3Dot_Real_dpp_Base_gfx11<bits<10> op, string opName = NAME> { 1381 def _e64_dpp_gfx11 : VOP3_DPP16<op, !cast<VOP_DPP_Pseudo>(opName#"_e64"#"_dpp"), SIEncodingFamily.GFX11> { 1382 let Inst{11} = ?; 1383 let Inst{12} = ?; 1384 let DecoderNamespace = "DPPGFX11"; 1385 } 1386 } 1387 1388 multiclass VOP3_Real_dpp_with_name_gfx11<bits<10> op, string opName, 1389 string asmName> { 1390 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1391 let AsmString = asmName # ps.Pfl.AsmVOP3DPP16, DecoderNamespace = "DPPGFX11" in { 1392 defm NAME : VOP3_Real_dpp_Base_gfx11<op, opName>; 1393 } 1394 } 1395 multiclass VOP3_Real_dpp8_Base_gfx11<bits<10> op, string opName = NAME> { 1396 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1397 def _e64_dpp8_gfx11 : Base_VOP3_DPP8<op, ps> { 1398 let DecoderNamespace = "DPP8GFX11"; 1399 } 1400 } 1401 1402 multiclass VOP3Dot_Real_dpp8_Base_gfx11<bits<10> op, string opName = NAME> { 1403 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1404 def _e64_dpp8_gfx11 : Base_VOP3_DPP8<op, ps> { 1405 let Inst{11} = ?; 1406 let Inst{12} = ?; 1407 let DecoderNamespace = "DPP8GFX11"; 1408 } 1409 } 1410 1411 multiclass VOP3_Real_dpp8_with_name_gfx11<bits<10> op, string opName, 1412 string asmName> { 1413 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1414 let AsmString = asmName # ps.Pfl.AsmVOP3DPP8, DecoderNamespace = "DPP8GFX11" in { 1415 defm NAME : VOP3_Real_dpp8_Base_gfx11<op, opName>; 1416 } 1417 } 1418 multiclass VOP3be_Real_gfx11<bits<10> op, string opName, string asmName, 1419 bit isSingle = 0> { 1420 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1421 let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in 1422 def _e64_gfx11 : 1423 VOP3_Real<ps, SIEncodingFamily.GFX11, asmName>, 1424 VOP3be_gfx11<op, ps.Pfl> ; 1425 } 1426 multiclass VOP3be_Real_dpp_gfx11<bits<10> op, string opName, string asmName> { 1427 defvar ps = !cast<VOP3_Pseudo>(opName #"_e64"); 1428 defvar dpp_ps = !cast<VOP_DPP_Pseudo>(opName #"_e64" #"_dpp"); 1429 def _e64_dpp_gfx11 : Base_VOP3b_DPP16<op, dpp_ps, asmName>, 1430 SIMCInstr<dpp_ps.PseudoInstr, SIEncodingFamily.GFX11> { 1431 let DecoderNamespace = "DPPGFX11"; 1432 } 1433 } 1434 multiclass VOP3be_Real_dpp8_gfx11<bits<10> op, string opName, string asmName> { 1435 defvar ps = !cast<VOP3_Pseudo>(opName #"_e64"); 1436 def _e64_dpp8_gfx11 : VOP3b_DPP8_Base<op, ps, asmName> { 1437 let DecoderNamespace = "DPP8GFX11"; 1438 } 1439 } 1440} // End AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" 1441 1442// VOP1 and VOP2 depend on these triple defs 1443multiclass VOP3_Realtriple_gfx11<bits<10> op, 1444 bit isSingle = 0, string opName = NAME> : 1445 VOP3_Real_Base_gfx11<op, opName, isSingle>, 1446 VOP3_Real_dpp_Base_gfx11<op, opName>, 1447 VOP3_Real_dpp8_Base_gfx11<op, opName>; 1448 1449multiclass VOP3Dot_Realtriple_gfx11<bits<10> op, 1450 bit isSingle = 0, string opName = NAME> : 1451 VOP3Dot_Real_Base_gfx11<op, opName, isSingle>, 1452 VOP3Dot_Real_dpp_Base_gfx11<op, opName>, 1453 VOP3Dot_Real_dpp8_Base_gfx11<op, opName>; 1454 1455multiclass VOP3Only_Realtriple_gfx11<bits<10> op> : 1456 VOP3_Realtriple_gfx11<op, 1>; 1457 1458multiclass VOP3_Realtriple_with_name_gfx11<bits<10> op, string opName, 1459 string asmName, bit isSingle = 0> : 1460 VOP3_Real_with_name_gfx11<op, opName, asmName, isSingle>, 1461 VOP3_Real_dpp_with_name_gfx11<op, opName, asmName>, 1462 VOP3_Real_dpp8_with_name_gfx11<op, opName, asmName>; 1463 1464multiclass VOP3Only_Realtriple_with_name_gfx11<bits<10> op, string opName, 1465 string asmName> : 1466 VOP3_Realtriple_with_name_gfx11<op, opName, asmName, 1>; 1467 1468multiclass VOP3Only_Realtriple_t16_gfx11<bits<10> op, string asmName, 1469 string opName = NAME> 1470 : VOP3Only_Realtriple_with_name_gfx11<op, opName, asmName>; 1471 1472multiclass VOP3be_Realtriple_gfx11< 1473 bits<10> op, bit isSingle = 0, string opName = NAME, 1474 string asmName = !cast<VOP_Pseudo>(opName#"_e64").Mnemonic> : 1475 VOP3be_Real_gfx11<op, opName, asmName, isSingle>, 1476 VOP3be_Real_dpp_gfx11<op, opName, asmName>, 1477 VOP3be_Real_dpp8_gfx11<op, opName, asmName>; 1478 1479multiclass VOP3beOnly_Realtriple_gfx11<bits<10> op> : 1480 VOP3be_Realtriple_gfx11<op, 1>; 1481 1482include "VOPCInstructions.td" 1483include "VOP1Instructions.td" 1484include "VOP2Instructions.td" 1485include "VOP3Instructions.td" 1486include "VOP3PInstructions.td" 1487include "VOPDInstructions.td" 1488 1489class ClassPat<Instruction inst, ValueType vt> : GCNPat < 1490 (is_fpclass (vt (VOP3ModsNonCanonicalizing vt:$src0, i32:$src0_mods)), (i32 timm:$mask)), 1491 (inst i32:$src0_mods, vt:$src0, (V_MOV_B32_e32 timm:$mask)) 1492>; 1493 1494def : ClassPat<V_CMP_CLASS_F16_e64, f16> { 1495 let OtherPredicates = [NotHasTrue16BitInsts, Has16BitInsts]; 1496} 1497 1498def : ClassPat<V_CMP_CLASS_F16_t16_e64, f16> { 1499 let OtherPredicates = [HasTrue16BitInsts]; 1500} 1501 1502def : ClassPat<V_CMP_CLASS_F32_e64, f32>; 1503def : ClassPat<V_CMP_CLASS_F64_e64, f64>; 1504 1505class VOPInfoTable <string Format> : GenericTable { 1506 let FilterClass = Format # "_Real"; 1507 let CppTypeName = "VOPInfo"; 1508 let Fields = ["Opcode", "IsSingle"]; 1509 1510 let PrimaryKey = ["Opcode"]; 1511 let PrimaryKeyName = "get" # Format # "OpcodeHelper"; 1512} 1513 1514def VOP1InfoTable : VOPInfoTable<"VOP1">; 1515def VOP2InfoTable : VOPInfoTable<"VOP2">; 1516def VOP3InfoTable : VOPInfoTable<"VOP3">; 1517 1518class VOPC64Table <string Format> : GenericTable { 1519 let FilterClass = "VOPC64_" # Format # "_Base"; 1520 let CppTypeName = "VOPC64DPPInfo"; 1521 let Fields = ["Opcode"]; 1522 1523 let PrimaryKey = ["Opcode"]; 1524 let PrimaryKeyName = "isVOPC64" # Format # "OpcodeHelper"; 1525} 1526 1527def VOPC64DPPTable : VOPC64Table<"DPP">; 1528def VOPC64DPP8Table : VOPC64Table<"DPP8">; 1529 1530def VOPTrue16Table : GenericTable { 1531 let FilterClass = "VOP_Pseudo"; 1532 let CppTypeName = "VOPTrue16Info"; 1533 let Fields = ["Opcode", "IsTrue16"]; 1534 1535 let PrimaryKey = ["Opcode"]; 1536 let PrimaryKeyName = "getTrue16OpcodeHelper"; 1537} 1538