xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/VOPCInstructions.td (revision 9f44a47fd07924afc035991af15d84e6585dea4f)
1//===-- VOPCInstructions.td - Vector Instruction Definitions --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// Encodings
11//===----------------------------------------------------------------------===//
12
13class VOPCe <bits<8> op> : Enc32 {
14  bits<9> src0;
15  bits<8> src1;
16
17  let Inst{8-0} = src0;
18  let Inst{16-9} = src1;
19  let Inst{24-17} = op;
20  let Inst{31-25} = 0x3e;
21}
22
23class VOPC_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAe <P> {
24  bits<8> src1;
25
26  let Inst{8-0}   = 0xf9; // sdwa
27  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
28  let Inst{24-17} = op;
29  let Inst{31-25} = 0x3e; // encoding
30}
31
32class VOPC_SDWA9e <bits<8> op, VOPProfile P> : VOP_SDWA9Be <P> {
33  bits<9> src1;
34
35  let Inst{8-0}   = 0xf9; // sdwa
36  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
37  let Inst{24-17} = op;
38  let Inst{31-25} = 0x3e; // encoding
39  let Inst{63}    = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
40}
41
42
43//===----------------------------------------------------------------------===//
44// VOPC classes
45//===----------------------------------------------------------------------===//
46
47// VOPC instructions are a special case because for the 32-bit
48// encoding, we want to display the implicit vcc write as if it were
49// an explicit $dst.
50class VOPC_Profile<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> :
51  VOPProfile <[i1, vt0, vt1, untyped]> {
52  // We want to exclude instructions with 64bit operands
53  let HasExtDPP = getHasVOP3DPP<DstVT, Src0VT, Src1VT, Src2VT>.ret;
54  let Asm32 = "$src0, $src1";
55
56  let AsmDPP = !if (HasModifiers,
57                    "$src0_modifiers, $src1_modifiers "
58                    "$dpp_ctrl$row_mask$bank_mask$bound_ctrl",
59                    "$src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl");
60  let AsmDPP8 = "$src0, $src1 $dpp8$fi";
61  let AsmDPP16 = AsmDPP#"$fi";
62  // VOPC DPP Instructions do not need an old operand
63  let TieRegDPP = "";
64  let InsDPP = getInsDPP<VOPDstOperand<Src0DPP>, Src0DPP, Src1DPP, Src2DPP,
65                         NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP,
66                         Src2ModDPP, 0/*HasOld*/>.ret;
67  let InsDPP16 = getInsDPP16<VOPDstOperand<Src0DPP>, Src0DPP, Src1DPP, Src2DPP,
68                             NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP,
69                             Src2ModDPP, 0/*HasOld*/>.ret;
70  let InsDPP8 = getInsDPP8<VOPDstOperand<Src0DPP>, Src0DPP, Src1DPP, Src2DPP,
71                           NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP,
72                           Src2ModDPP, 0/*HasOld*/>.ret;
73
74  // The destination for 32-bit encoding is implicit.
75  let HasDst32 = 0;
76  // VOPC disallows dst_sel and dst_unused as they have no effect on destination
77  let EmitDstSel = 0;
78  let Outs64 = (outs VOPDstS64orS32:$sdst);
79  let OutsVOP3DPP = Outs64;
80  let OutsVOP3DPP8 = Outs64;
81  let InsVOP3DPP = getInsVOP3DPP<InsVOP3Base, Src0VOP3DPP, NumSrcArgs, 0/*HasOld*/>.ret;
82  let InsVOP3DPP16 = getInsVOP3DPP16<InsVOP3Base, Src0VOP3DPP, NumSrcArgs, 0/*HasOld*/>.ret;
83  let InsVOP3DPP8 = getInsVOP3DPP8<InsVOP3Base, Src0VOP3DPP, NumSrcArgs, 0/*HasOld*/>.ret;
84  list<SchedReadWrite> Schedule = sched;
85}
86
87class VOPC_NoSdst_Profile<list<SchedReadWrite> sched, ValueType vt0,
88                          ValueType vt1 = vt0> :
89  VOPC_Profile<sched, vt0, vt1> {
90  let Outs64 = (outs );
91  let OutsVOP3DPP = Outs64;
92  let OutsVOP3DPP8 = Outs64;
93  let OutsSDWA = (outs );
94  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
95                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
96                     src0_sel:$src0_sel, src1_sel:$src1_sel);
97  let Asm64 = !if(isFloatType<Src0VT>.ret, "$src0_modifiers, $src1_modifiers$clamp",
98                                           "$src0, $src1");
99  let AsmVOP3DPPBase = Asm64;
100  let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
101  let EmitDst = 0;
102}
103
104class VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[],
105                   bit DefVcc = 1> :
106  InstSI<(outs), P.Ins32, "", pattern>,
107  VOP <opName>,
108  SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> {
109
110  let isPseudo = 1;
111  let isCodeGenOnly = 1;
112  let UseNamedOperandTable = 1;
113
114  string Mnemonic = opName;
115  string AsmOperands = P.Asm32;
116
117  let Size = 4;
118  let mayLoad = 0;
119  let mayStore = 0;
120  let hasSideEffects = 0;
121
122  let ReadsModeReg = isFloatType<P.Src0VT>.ret;
123
124  let VALU = 1;
125  let VOPC = 1;
126  let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
127  let Defs = !if(DefVcc, [VCC], []);
128
129  VOPProfile Pfl = P;
130}
131
132class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily, string asm_name = ps.PseudoInstr> :
133  InstSI <ps.OutOperandList, ps.InOperandList, asm_name # " " # ps.AsmOperands, []>,
134  SIMCInstr <ps.PseudoInstr, EncodingFamily> {
135
136  let VALU = 1;
137  let VOPC = 1;
138  let isPseudo = 0;
139  let isCodeGenOnly = 0;
140
141  let Constraints     = ps.Constraints;
142  let DisableEncoding = ps.DisableEncoding;
143
144  // copy relevant pseudo op flags
145  let SubtargetPredicate = ps.SubtargetPredicate;
146  let AsmMatchConverter  = ps.AsmMatchConverter;
147  let Constraints        = ps.Constraints;
148  let DisableEncoding    = ps.DisableEncoding;
149  let TSFlags            = ps.TSFlags;
150  let UseNamedOperandTable = ps.UseNamedOperandTable;
151  let Uses                 = ps.Uses;
152  let Defs                 = ps.Defs;
153  let SchedRW              = ps.SchedRW;
154  let mayLoad              = ps.mayLoad;
155  let mayStore             = ps.mayStore;
156}
157
158class VOPC_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
159  VOP_SDWA_Pseudo <OpName, P, pattern> {
160  let AsmMatchConverter = "cvtSdwaVOPC";
161}
162
163// This class is used only with VOPC instructions. Use $sdst for out operand
164class VOPCInstAlias <VOP3_Pseudo ps, Instruction inst,
165                     string Asm32 = ps.Pfl.Asm32, string real_name = ps.OpName,
166                     VOPProfile p = ps.Pfl> :
167  InstAlias <real_name#" "#Asm32, (inst)>, PredicateControl {
168
169  field bit isCompare;
170  field bit isCommutable;
171
172  let ResultInst =
173    !if (p.HasDst32,
174      !if (!eq(p.NumSrcArgs, 0),
175        // 1 dst, 0 src
176        (inst p.DstRC:$sdst),
177      !if (!eq(p.NumSrcArgs, 1),
178        // 1 dst, 1 src
179        (inst p.DstRC:$sdst, p.Src0RC32:$src0),
180      !if (!eq(p.NumSrcArgs, 2),
181        // 1 dst, 2 src
182        (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1),
183      // else - unreachable
184        (inst)))),
185    // else
186      !if (!eq(p.NumSrcArgs, 2),
187        // 0 dst, 2 src
188        (inst p.Src0RC32:$src0, p.Src1RC32:$src1),
189      !if (!eq(p.NumSrcArgs, 1),
190        // 0 dst, 1 src
191        (inst p.Src0RC32:$src1),
192      // else
193        // 0 dst, 0 src
194        (inst))));
195
196  let AsmVariantName = AMDGPUAsmVariants.Default;
197  let SubtargetPredicate = AssemblerPredicate;
198}
199
200multiclass VOPCInstAliases <string old_name, string Arch, string real_name = old_name> {
201  def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"),
202                       !cast<Instruction>(real_name#"_e32_"#Arch),
203                       !cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32,
204                       real_name>;
205  let WaveSizePredicate = isWave32 in {
206    def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"),
207                         !cast<Instruction>(real_name#"_e32_"#Arch),
208                         "vcc_lo, "#!cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32,
209                         real_name>;
210  }
211  let WaveSizePredicate = isWave64 in {
212    def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"),
213                         !cast<Instruction>(real_name#"_e32_"#Arch),
214                         "vcc, "#!cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32,
215                         real_name>;
216  }
217}
218
219multiclass VOPCXInstAliases <string old_name, string Arch, string real_name = old_name> {
220  def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"),
221                       !cast<Instruction>(real_name#"_e32_"#Arch),
222                       !cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32,
223                       real_name>;
224}
225
226class getVOPCPat64 <SDPatternOperator cond, VOPProfile P> : LetDummies {
227  list<dag> ret = !if(P.HasModifiers,
228      [(set i1:$sdst,
229        (setcc (P.Src0VT
230                  !if(P.HasOMod,
231                    (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
232                    (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
233               (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
234               cond))],
235      [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]);
236}
237
238class VCMPXNoSDstTable <bit has_sdst, string Name> {
239  bit HasSDst = has_sdst;
240  string NoSDstOp = Name;
241}
242
243class VCMPVCMPXTable <string Name> {
244  bit IsVCMPX = 0;
245  string VCMPOp = Name;
246}
247
248multiclass VOPC_Pseudos <string opName,
249                         VOPC_Profile P,
250                         SDPatternOperator cond = COND_NULL,
251                         string revOp = opName,
252                         bit DefExec = 0> {
253
254  def _e32 : VOPC_Pseudo <opName, P>,
255             Commutable_REV<revOp#"_e32", !eq(revOp, opName)>,
256             VCMPXNoSDstTable<1, opName#"_e32">,
257             VCMPVCMPXTable<opName#"_e32"> {
258    let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
259    let SchedRW = P.Schedule;
260    let isConvergent = DefExec;
261    let isCompare = 1;
262    let isCommutable = 1;
263  }
264
265  def _e64 : VOP3_Pseudo<opName, P, getVOPCPat64<cond, P>.ret>,
266    Commutable_REV<revOp#"_e64", !eq(revOp, opName)>,
267    VCMPXNoSDstTable<1, opName#"_e64">,
268    VCMPVCMPXTable<opName#"_e64"> {
269    let Defs = !if(DefExec, [EXEC], []);
270    let SchedRW = P.Schedule;
271    let isCompare = 1;
272    let isCommutable = 1;
273  }
274
275  foreach _ = BoolToList<P.HasExtSDWA>.ret in
276  def _sdwa : VOPC_SDWA_Pseudo <opName, P> {
277    let Defs = !if(DefExec, [EXEC], []);
278    let SchedRW = P.Schedule;
279    let isConvergent = DefExec;
280    let isCompare = 1;
281  }
282
283  let SubtargetPredicate = isGFX11Plus in {
284  if P.HasExtDPP then
285      def _e32_dpp : VOP_DPP_Pseudo<opName, P> {
286        let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
287        let SchedRW = P.Schedule;
288        let isConvergent = DefExec;
289        let isCompare = 1;
290        let VOPC = 1;
291        let Constraints = "";
292      }
293  if P.HasExtVOP3DPP then
294      def _e64_dpp : VOP3_DPP_Pseudo<opName, P> {
295        let Defs = !if(DefExec, [EXEC], []);
296        let SchedRW = P.Schedule;
297        let isCompare = 1;
298        let Constraints = "";
299    }
300  } // end SubtargetPredicate = isGFX11Plus
301
302}
303
304let SubtargetPredicate = HasSdstCMPX in {
305multiclass VOPCX_Pseudos <string opName,
306                          VOPC_Profile P, VOPC_Profile P_NoSDst,
307                          SDPatternOperator cond = COND_NULL,
308                          string revOp = opName> :
309           VOPC_Pseudos <opName, P, cond, revOp, 1> {
310
311  def _nosdst_e32 : VOPC_Pseudo <opName#"_nosdst", P_NoSDst, [], 0>,
312             Commutable_REV<revOp#"_nosdst_e32", !eq(revOp, opName)>,
313             VCMPXNoSDstTable<0, opName#"_e32">,
314             VCMPVCMPXTable<!subst("v_cmpx", "v_cmp", opName#"_e32")> {
315    let Defs = [EXEC];
316    let SchedRW = P_NoSDst.Schedule;
317    let isConvergent = 1;
318    let isCompare = 1;
319    let isCommutable = 1;
320    let SubtargetPredicate = HasNoSdstCMPX;
321    let IsVCMPX = 1;
322  }
323
324  def _nosdst_e64 : VOP3_Pseudo<opName#"_nosdst", P_NoSDst>,
325    Commutable_REV<revOp#"_nosdst_e64", !eq(revOp, opName)>,
326    VCMPXNoSDstTable<0, opName#"_e64">,
327    VCMPVCMPXTable<!subst("v_cmpx", "v_cmp", opName#"_e64")> {
328    let Defs = [EXEC];
329    let SchedRW = P_NoSDst.Schedule;
330    let isCompare = 1;
331    let isCommutable = 1;
332    let SubtargetPredicate = HasNoSdstCMPX;
333    let IsVCMPX = 1;
334  }
335
336  foreach _ = BoolToList<P_NoSDst.HasExtSDWA>.ret in
337  def _nosdst_sdwa : VOPC_SDWA_Pseudo <opName#"_nosdst", P_NoSDst> {
338    let Defs = [EXEC];
339    let SchedRW = P_NoSDst.Schedule;
340    let isConvergent = 1;
341    let isCompare = 1;
342    let SubtargetPredicate = HasNoSdstCMPX;
343  }
344
345  let SubtargetPredicate = isGFX11Plus in {
346  if P.HasExtDPP then
347      def _nosdst_e32_dpp : VOP_DPP_Pseudo<opName#"_nosdst", P_NoSDst> {
348        let Defs = [EXEC];
349        let SchedRW = P_NoSDst.Schedule;
350        let isConvergent = 1;
351        let isCompare = 1;
352        let VOPC = 1;
353        let Constraints = "";
354      }
355  if P.HasExtVOP3DPP then
356      def _nosdst_e64_dpp : VOP3_DPP_Pseudo<opName#"_nosdst", P_NoSDst> {
357        let Defs = [EXEC];
358        let SchedRW = P_NoSDst.Schedule;
359        let isCompare = 1;
360        let Constraints = "";
361    }
362  } // end SubtargetPredicate = isGFX11Plus
363}
364} // End SubtargetPredicate = HasSdstCMPX
365
366def VOPC_I1_F16_F16 : VOPC_Profile<[Write32Bit], f16>;
367def VOPC_I1_F32_F32 : VOPC_Profile<[Write32Bit], f32>;
368def VOPC_I1_F64_F64 : VOPC_Profile<[WriteDoubleAdd], f64>;
369def VOPC_I1_I16_I16 : VOPC_Profile<[Write32Bit], i16>;
370def VOPC_I1_I32_I32 : VOPC_Profile<[Write32Bit], i32>;
371def VOPC_I1_I64_I64 : VOPC_Profile<[Write64Bit], i64>;
372
373def VOPC_F16_F16 : VOPC_NoSdst_Profile<[Write32Bit], f16>;
374def VOPC_F32_F32 : VOPC_NoSdst_Profile<[Write32Bit], f32>;
375def VOPC_F64_F64 : VOPC_NoSdst_Profile<[Write64Bit], f64>;
376def VOPC_I16_I16 : VOPC_NoSdst_Profile<[Write32Bit], i16>;
377def VOPC_I32_I32 : VOPC_NoSdst_Profile<[Write32Bit], i32>;
378def VOPC_I64_I64 : VOPC_NoSdst_Profile<[Write64Bit], i64>;
379
380multiclass VOPC_F16 <string opName, SDPatternOperator cond = COND_NULL,
381                     string revOp = opName> :
382  VOPC_Pseudos <opName, VOPC_I1_F16_F16, cond, revOp, 0>;
383
384multiclass VOPC_F32 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> :
385  VOPC_Pseudos <opName, VOPC_I1_F32_F32, cond, revOp, 0>;
386
387multiclass VOPC_F64 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> :
388  VOPC_Pseudos <opName, VOPC_I1_F64_F64, cond, revOp, 0>;
389
390multiclass VOPC_I16 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> :
391  VOPC_Pseudos <opName, VOPC_I1_I16_I16, cond, revOp, 0>;
392
393multiclass VOPC_I32 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> :
394  VOPC_Pseudos <opName, VOPC_I1_I32_I32, cond, revOp, 0>;
395
396multiclass VOPC_I64 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> :
397  VOPC_Pseudos <opName, VOPC_I1_I64_I64, cond, revOp, 0>;
398
399multiclass VOPCX_F16 <string opName, string revOp = opName> :
400  VOPCX_Pseudos <opName, VOPC_I1_F16_F16, VOPC_F16_F16, COND_NULL, revOp>;
401
402multiclass VOPCX_F32 <string opName, string revOp = opName> :
403  VOPCX_Pseudos <opName, VOPC_I1_F32_F32, VOPC_F32_F32, COND_NULL, revOp>;
404
405multiclass VOPCX_F64 <string opName, string revOp = opName> :
406  VOPCX_Pseudos <opName, VOPC_I1_F64_F64, VOPC_F64_F64, COND_NULL, revOp>;
407
408multiclass VOPCX_I16 <string opName, string revOp = opName> :
409  VOPCX_Pseudos <opName, VOPC_I1_I16_I16, VOPC_I16_I16, COND_NULL, revOp>;
410
411multiclass VOPCX_I32 <string opName, string revOp = opName> :
412  VOPCX_Pseudos <opName, VOPC_I1_I32_I32, VOPC_I32_I32, COND_NULL, revOp>;
413
414multiclass VOPCX_I64 <string opName, string revOp = opName> :
415  VOPCX_Pseudos <opName, VOPC_I1_I64_I64, VOPC_I64_I64, COND_NULL, revOp>;
416
417
418//===----------------------------------------------------------------------===//
419// Compare instructions
420//===----------------------------------------------------------------------===//
421
422defm V_CMP_F_F32 : VOPC_F32 <"v_cmp_f_f32">;
423defm V_CMP_LT_F32 : VOPC_F32 <"v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">;
424defm V_CMP_EQ_F32 : VOPC_F32 <"v_cmp_eq_f32", COND_OEQ>;
425defm V_CMP_LE_F32 : VOPC_F32 <"v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">;
426defm V_CMP_GT_F32 : VOPC_F32 <"v_cmp_gt_f32", COND_OGT>;
427defm V_CMP_LG_F32 : VOPC_F32 <"v_cmp_lg_f32", COND_ONE>;
428defm V_CMP_GE_F32 : VOPC_F32 <"v_cmp_ge_f32", COND_OGE>;
429defm V_CMP_O_F32 : VOPC_F32 <"v_cmp_o_f32", COND_O>;
430defm V_CMP_U_F32 : VOPC_F32 <"v_cmp_u_f32", COND_UO>;
431defm V_CMP_NGE_F32 : VOPC_F32 <"v_cmp_nge_f32",  COND_ULT, "v_cmp_nle_f32">;
432defm V_CMP_NLG_F32 : VOPC_F32 <"v_cmp_nlg_f32", COND_UEQ>;
433defm V_CMP_NGT_F32 : VOPC_F32 <"v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">;
434defm V_CMP_NLE_F32 : VOPC_F32 <"v_cmp_nle_f32", COND_UGT>;
435defm V_CMP_NEQ_F32 : VOPC_F32 <"v_cmp_neq_f32", COND_UNE>;
436defm V_CMP_NLT_F32 : VOPC_F32 <"v_cmp_nlt_f32", COND_UGE>;
437defm V_CMP_TRU_F32 : VOPC_F32 <"v_cmp_tru_f32">;
438
439defm V_CMPX_F_F32 : VOPCX_F32 <"v_cmpx_f_f32">;
440defm V_CMPX_LT_F32 : VOPCX_F32 <"v_cmpx_lt_f32", "v_cmpx_gt_f32">;
441defm V_CMPX_EQ_F32 : VOPCX_F32 <"v_cmpx_eq_f32">;
442defm V_CMPX_LE_F32 : VOPCX_F32 <"v_cmpx_le_f32", "v_cmpx_ge_f32">;
443defm V_CMPX_GT_F32 : VOPCX_F32 <"v_cmpx_gt_f32">;
444defm V_CMPX_LG_F32 : VOPCX_F32 <"v_cmpx_lg_f32">;
445defm V_CMPX_GE_F32 : VOPCX_F32 <"v_cmpx_ge_f32">;
446defm V_CMPX_O_F32 : VOPCX_F32 <"v_cmpx_o_f32">;
447defm V_CMPX_U_F32 : VOPCX_F32 <"v_cmpx_u_f32">;
448defm V_CMPX_NGE_F32 : VOPCX_F32 <"v_cmpx_nge_f32", "v_cmpx_nle_f32">;
449defm V_CMPX_NLG_F32 : VOPCX_F32 <"v_cmpx_nlg_f32">;
450defm V_CMPX_NGT_F32 : VOPCX_F32 <"v_cmpx_ngt_f32", "v_cmpx_nlt_f32">;
451defm V_CMPX_NLE_F32 : VOPCX_F32 <"v_cmpx_nle_f32">;
452defm V_CMPX_NEQ_F32 : VOPCX_F32 <"v_cmpx_neq_f32">;
453defm V_CMPX_NLT_F32 : VOPCX_F32 <"v_cmpx_nlt_f32">;
454defm V_CMPX_TRU_F32 : VOPCX_F32 <"v_cmpx_tru_f32">;
455
456defm V_CMP_F_F64 : VOPC_F64 <"v_cmp_f_f64">;
457defm V_CMP_LT_F64 : VOPC_F64 <"v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">;
458defm V_CMP_EQ_F64 : VOPC_F64 <"v_cmp_eq_f64", COND_OEQ>;
459defm V_CMP_LE_F64 : VOPC_F64 <"v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">;
460defm V_CMP_GT_F64 : VOPC_F64 <"v_cmp_gt_f64", COND_OGT>;
461defm V_CMP_LG_F64 : VOPC_F64 <"v_cmp_lg_f64", COND_ONE>;
462defm V_CMP_GE_F64 : VOPC_F64 <"v_cmp_ge_f64", COND_OGE>;
463defm V_CMP_O_F64 : VOPC_F64 <"v_cmp_o_f64", COND_O>;
464defm V_CMP_U_F64 : VOPC_F64 <"v_cmp_u_f64", COND_UO>;
465defm V_CMP_NGE_F64 : VOPC_F64 <"v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">;
466defm V_CMP_NLG_F64 : VOPC_F64 <"v_cmp_nlg_f64", COND_UEQ>;
467defm V_CMP_NGT_F64 : VOPC_F64 <"v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">;
468defm V_CMP_NLE_F64 : VOPC_F64 <"v_cmp_nle_f64", COND_UGT>;
469defm V_CMP_NEQ_F64 : VOPC_F64 <"v_cmp_neq_f64", COND_UNE>;
470defm V_CMP_NLT_F64 : VOPC_F64 <"v_cmp_nlt_f64", COND_UGE>;
471defm V_CMP_TRU_F64 : VOPC_F64 <"v_cmp_tru_f64">;
472
473defm V_CMPX_F_F64 : VOPCX_F64 <"v_cmpx_f_f64">;
474defm V_CMPX_LT_F64 : VOPCX_F64 <"v_cmpx_lt_f64", "v_cmpx_gt_f64">;
475defm V_CMPX_EQ_F64 : VOPCX_F64 <"v_cmpx_eq_f64">;
476defm V_CMPX_LE_F64 : VOPCX_F64 <"v_cmpx_le_f64", "v_cmpx_ge_f64">;
477defm V_CMPX_GT_F64 : VOPCX_F64 <"v_cmpx_gt_f64">;
478defm V_CMPX_LG_F64 : VOPCX_F64 <"v_cmpx_lg_f64">;
479defm V_CMPX_GE_F64 : VOPCX_F64 <"v_cmpx_ge_f64">;
480defm V_CMPX_O_F64 : VOPCX_F64 <"v_cmpx_o_f64">;
481defm V_CMPX_U_F64 : VOPCX_F64 <"v_cmpx_u_f64">;
482defm V_CMPX_NGE_F64 : VOPCX_F64 <"v_cmpx_nge_f64", "v_cmpx_nle_f64">;
483defm V_CMPX_NLG_F64 : VOPCX_F64 <"v_cmpx_nlg_f64">;
484defm V_CMPX_NGT_F64 : VOPCX_F64 <"v_cmpx_ngt_f64", "v_cmpx_nlt_f64">;
485defm V_CMPX_NLE_F64 : VOPCX_F64 <"v_cmpx_nle_f64">;
486defm V_CMPX_NEQ_F64 : VOPCX_F64 <"v_cmpx_neq_f64">;
487defm V_CMPX_NLT_F64 : VOPCX_F64 <"v_cmpx_nlt_f64">;
488defm V_CMPX_TRU_F64 : VOPCX_F64 <"v_cmpx_tru_f64">;
489
490let SubtargetPredicate = isGFX6GFX7 in {
491
492defm V_CMPS_F_F32 : VOPC_F32 <"v_cmps_f_f32">;
493defm V_CMPS_LT_F32 : VOPC_F32 <"v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">;
494defm V_CMPS_EQ_F32 : VOPC_F32 <"v_cmps_eq_f32">;
495defm V_CMPS_LE_F32 : VOPC_F32 <"v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">;
496defm V_CMPS_GT_F32 : VOPC_F32 <"v_cmps_gt_f32">;
497defm V_CMPS_LG_F32 : VOPC_F32 <"v_cmps_lg_f32">;
498defm V_CMPS_GE_F32 : VOPC_F32 <"v_cmps_ge_f32">;
499defm V_CMPS_O_F32 : VOPC_F32 <"v_cmps_o_f32">;
500defm V_CMPS_U_F32 : VOPC_F32 <"v_cmps_u_f32">;
501defm V_CMPS_NGE_F32 : VOPC_F32 <"v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">;
502defm V_CMPS_NLG_F32 : VOPC_F32 <"v_cmps_nlg_f32">;
503defm V_CMPS_NGT_F32 : VOPC_F32 <"v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">;
504defm V_CMPS_NLE_F32 : VOPC_F32 <"v_cmps_nle_f32">;
505defm V_CMPS_NEQ_F32 : VOPC_F32 <"v_cmps_neq_f32">;
506defm V_CMPS_NLT_F32 : VOPC_F32 <"v_cmps_nlt_f32">;
507defm V_CMPS_TRU_F32 : VOPC_F32 <"v_cmps_tru_f32">;
508
509defm V_CMPSX_F_F32 : VOPCX_F32 <"v_cmpsx_f_f32">;
510defm V_CMPSX_LT_F32 : VOPCX_F32 <"v_cmpsx_lt_f32", "v_cmpsx_gt_f32">;
511defm V_CMPSX_EQ_F32 : VOPCX_F32 <"v_cmpsx_eq_f32">;
512defm V_CMPSX_LE_F32 : VOPCX_F32 <"v_cmpsx_le_f32", "v_cmpsx_ge_f32">;
513defm V_CMPSX_GT_F32 : VOPCX_F32 <"v_cmpsx_gt_f32">;
514defm V_CMPSX_LG_F32 : VOPCX_F32 <"v_cmpsx_lg_f32">;
515defm V_CMPSX_GE_F32 : VOPCX_F32 <"v_cmpsx_ge_f32">;
516defm V_CMPSX_O_F32 : VOPCX_F32 <"v_cmpsx_o_f32">;
517defm V_CMPSX_U_F32 : VOPCX_F32 <"v_cmpsx_u_f32">;
518defm V_CMPSX_NGE_F32 : VOPCX_F32 <"v_cmpsx_nge_f32", "v_cmpsx_nle_f32">;
519defm V_CMPSX_NLG_F32 : VOPCX_F32 <"v_cmpsx_nlg_f32">;
520defm V_CMPSX_NGT_F32 : VOPCX_F32 <"v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">;
521defm V_CMPSX_NLE_F32 : VOPCX_F32 <"v_cmpsx_nle_f32">;
522defm V_CMPSX_NEQ_F32 : VOPCX_F32 <"v_cmpsx_neq_f32">;
523defm V_CMPSX_NLT_F32 : VOPCX_F32 <"v_cmpsx_nlt_f32">;
524defm V_CMPSX_TRU_F32 : VOPCX_F32 <"v_cmpsx_tru_f32">;
525
526defm V_CMPS_F_F64 : VOPC_F64 <"v_cmps_f_f64">;
527defm V_CMPS_LT_F64 : VOPC_F64 <"v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">;
528defm V_CMPS_EQ_F64 : VOPC_F64 <"v_cmps_eq_f64">;
529defm V_CMPS_LE_F64 : VOPC_F64 <"v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">;
530defm V_CMPS_GT_F64 : VOPC_F64 <"v_cmps_gt_f64">;
531defm V_CMPS_LG_F64 : VOPC_F64 <"v_cmps_lg_f64">;
532defm V_CMPS_GE_F64 : VOPC_F64 <"v_cmps_ge_f64">;
533defm V_CMPS_O_F64 : VOPC_F64 <"v_cmps_o_f64">;
534defm V_CMPS_U_F64 : VOPC_F64 <"v_cmps_u_f64">;
535defm V_CMPS_NGE_F64 : VOPC_F64 <"v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">;
536defm V_CMPS_NLG_F64 : VOPC_F64 <"v_cmps_nlg_f64">;
537defm V_CMPS_NGT_F64 : VOPC_F64 <"v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">;
538defm V_CMPS_NLE_F64 : VOPC_F64 <"v_cmps_nle_f64">;
539defm V_CMPS_NEQ_F64 : VOPC_F64 <"v_cmps_neq_f64">;
540defm V_CMPS_NLT_F64 : VOPC_F64 <"v_cmps_nlt_f64">;
541defm V_CMPS_TRU_F64 : VOPC_F64 <"v_cmps_tru_f64">;
542
543defm V_CMPSX_F_F64 : VOPCX_F64 <"v_cmpsx_f_f64">;
544defm V_CMPSX_LT_F64 : VOPCX_F64 <"v_cmpsx_lt_f64", "v_cmpsx_gt_f64">;
545defm V_CMPSX_EQ_F64 : VOPCX_F64 <"v_cmpsx_eq_f64">;
546defm V_CMPSX_LE_F64 : VOPCX_F64 <"v_cmpsx_le_f64", "v_cmpsx_ge_f64">;
547defm V_CMPSX_GT_F64 : VOPCX_F64 <"v_cmpsx_gt_f64">;
548defm V_CMPSX_LG_F64 : VOPCX_F64 <"v_cmpsx_lg_f64">;
549defm V_CMPSX_GE_F64 : VOPCX_F64 <"v_cmpsx_ge_f64">;
550defm V_CMPSX_O_F64 : VOPCX_F64 <"v_cmpsx_o_f64">;
551defm V_CMPSX_U_F64 : VOPCX_F64 <"v_cmpsx_u_f64">;
552defm V_CMPSX_NGE_F64 : VOPCX_F64 <"v_cmpsx_nge_f64", "v_cmpsx_nle_f64">;
553defm V_CMPSX_NLG_F64 : VOPCX_F64 <"v_cmpsx_nlg_f64">;
554defm V_CMPSX_NGT_F64 : VOPCX_F64 <"v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">;
555defm V_CMPSX_NLE_F64 : VOPCX_F64 <"v_cmpsx_nle_f64">;
556defm V_CMPSX_NEQ_F64 : VOPCX_F64 <"v_cmpsx_neq_f64">;
557defm V_CMPSX_NLT_F64 : VOPCX_F64 <"v_cmpsx_nlt_f64">;
558defm V_CMPSX_TRU_F64 : VOPCX_F64 <"v_cmpsx_tru_f64">;
559
560} // End SubtargetPredicate = isGFX6GFX7
561
562let SubtargetPredicate = Has16BitInsts in {
563
564defm V_CMP_F_F16    : VOPC_F16 <"v_cmp_f_f16">;
565defm V_CMP_LT_F16   : VOPC_F16 <"v_cmp_lt_f16", COND_OLT, "v_cmp_gt_f16">;
566defm V_CMP_EQ_F16   : VOPC_F16 <"v_cmp_eq_f16", COND_OEQ>;
567defm V_CMP_LE_F16   : VOPC_F16 <"v_cmp_le_f16", COND_OLE, "v_cmp_ge_f16">;
568defm V_CMP_GT_F16   : VOPC_F16 <"v_cmp_gt_f16", COND_OGT>;
569defm V_CMP_LG_F16   : VOPC_F16 <"v_cmp_lg_f16", COND_ONE>;
570defm V_CMP_GE_F16   : VOPC_F16 <"v_cmp_ge_f16", COND_OGE>;
571defm V_CMP_O_F16    : VOPC_F16 <"v_cmp_o_f16", COND_O>;
572defm V_CMP_U_F16    : VOPC_F16 <"v_cmp_u_f16", COND_UO>;
573defm V_CMP_NGE_F16  : VOPC_F16 <"v_cmp_nge_f16", COND_ULT, "v_cmp_nle_f16">;
574defm V_CMP_NLG_F16  : VOPC_F16 <"v_cmp_nlg_f16", COND_UEQ>;
575defm V_CMP_NGT_F16  : VOPC_F16 <"v_cmp_ngt_f16", COND_ULE, "v_cmp_nlt_f16">;
576defm V_CMP_NLE_F16  : VOPC_F16 <"v_cmp_nle_f16", COND_UGT>;
577defm V_CMP_NEQ_F16  : VOPC_F16 <"v_cmp_neq_f16", COND_UNE>;
578defm V_CMP_NLT_F16  : VOPC_F16 <"v_cmp_nlt_f16", COND_UGE>;
579defm V_CMP_TRU_F16  : VOPC_F16 <"v_cmp_tru_f16">;
580
581defm V_CMPX_F_F16   : VOPCX_F16 <"v_cmpx_f_f16">;
582defm V_CMPX_LT_F16  : VOPCX_F16 <"v_cmpx_lt_f16", "v_cmpx_gt_f16">;
583defm V_CMPX_EQ_F16  : VOPCX_F16 <"v_cmpx_eq_f16">;
584defm V_CMPX_LE_F16  : VOPCX_F16 <"v_cmpx_le_f16", "v_cmpx_ge_f16">;
585defm V_CMPX_GT_F16  : VOPCX_F16 <"v_cmpx_gt_f16">;
586defm V_CMPX_LG_F16  : VOPCX_F16 <"v_cmpx_lg_f16">;
587defm V_CMPX_GE_F16  : VOPCX_F16 <"v_cmpx_ge_f16">;
588defm V_CMPX_O_F16   : VOPCX_F16 <"v_cmpx_o_f16">;
589defm V_CMPX_U_F16   : VOPCX_F16 <"v_cmpx_u_f16">;
590defm V_CMPX_NGE_F16 : VOPCX_F16 <"v_cmpx_nge_f16", "v_cmpx_nle_f16">;
591defm V_CMPX_NLG_F16 : VOPCX_F16 <"v_cmpx_nlg_f16">;
592defm V_CMPX_NGT_F16 : VOPCX_F16 <"v_cmpx_ngt_f16", "v_cmpx_nlt_f16">;
593defm V_CMPX_NLE_F16 : VOPCX_F16 <"v_cmpx_nle_f16">;
594defm V_CMPX_NEQ_F16 : VOPCX_F16 <"v_cmpx_neq_f16">;
595defm V_CMPX_NLT_F16 : VOPCX_F16 <"v_cmpx_nlt_f16">;
596defm V_CMPX_TRU_F16 : VOPCX_F16 <"v_cmpx_tru_f16">;
597
598defm V_CMP_F_I16 : VOPC_I16 <"v_cmp_f_i16">;
599defm V_CMP_LT_I16 : VOPC_I16 <"v_cmp_lt_i16", COND_SLT, "v_cmp_gt_i16">;
600defm V_CMP_EQ_I16 : VOPC_I16 <"v_cmp_eq_i16">;
601defm V_CMP_LE_I16 : VOPC_I16 <"v_cmp_le_i16", COND_SLE, "v_cmp_ge_i16">;
602defm V_CMP_GT_I16 : VOPC_I16 <"v_cmp_gt_i16", COND_SGT>;
603defm V_CMP_NE_I16 : VOPC_I16 <"v_cmp_ne_i16">;
604defm V_CMP_GE_I16 : VOPC_I16 <"v_cmp_ge_i16", COND_SGE>;
605defm V_CMP_T_I16 : VOPC_I16 <"v_cmp_t_i16">;
606
607defm V_CMP_F_U16 : VOPC_I16 <"v_cmp_f_u16">;
608defm V_CMP_LT_U16 : VOPC_I16 <"v_cmp_lt_u16", COND_ULT, "v_cmp_gt_u16">;
609defm V_CMP_EQ_U16 : VOPC_I16 <"v_cmp_eq_u16", COND_EQ>;
610defm V_CMP_LE_U16 : VOPC_I16 <"v_cmp_le_u16", COND_ULE, "v_cmp_ge_u16">;
611defm V_CMP_GT_U16 : VOPC_I16 <"v_cmp_gt_u16", COND_UGT>;
612defm V_CMP_NE_U16 : VOPC_I16 <"v_cmp_ne_u16", COND_NE>;
613defm V_CMP_GE_U16 : VOPC_I16 <"v_cmp_ge_u16", COND_UGE>;
614defm V_CMP_T_U16 : VOPC_I16 <"v_cmp_t_u16">;
615
616defm V_CMPX_F_I16 : VOPCX_I16 <"v_cmpx_f_i16">;
617defm V_CMPX_LT_I16 : VOPCX_I16 <"v_cmpx_lt_i16", "v_cmpx_gt_i16">;
618defm V_CMPX_EQ_I16 : VOPCX_I16 <"v_cmpx_eq_i16">;
619defm V_CMPX_LE_I16 : VOPCX_I16 <"v_cmpx_le_i16", "v_cmpx_ge_i16">;
620defm V_CMPX_GT_I16 : VOPCX_I16 <"v_cmpx_gt_i16">;
621defm V_CMPX_NE_I16 : VOPCX_I16 <"v_cmpx_ne_i16">;
622defm V_CMPX_GE_I16 : VOPCX_I16 <"v_cmpx_ge_i16">;
623defm V_CMPX_T_I16 : VOPCX_I16 <"v_cmpx_t_i16">;
624defm V_CMPX_F_U16 : VOPCX_I16 <"v_cmpx_f_u16">;
625
626defm V_CMPX_LT_U16 : VOPCX_I16 <"v_cmpx_lt_u16", "v_cmpx_gt_u16">;
627defm V_CMPX_EQ_U16 : VOPCX_I16 <"v_cmpx_eq_u16">;
628defm V_CMPX_LE_U16 : VOPCX_I16 <"v_cmpx_le_u16", "v_cmpx_ge_u16">;
629defm V_CMPX_GT_U16 : VOPCX_I16 <"v_cmpx_gt_u16">;
630defm V_CMPX_NE_U16 : VOPCX_I16 <"v_cmpx_ne_u16">;
631defm V_CMPX_GE_U16 : VOPCX_I16 <"v_cmpx_ge_u16">;
632defm V_CMPX_T_U16 : VOPCX_I16 <"v_cmpx_t_u16">;
633
634} // End SubtargetPredicate = Has16BitInsts
635
636defm V_CMP_F_I32 : VOPC_I32 <"v_cmp_f_i32">;
637defm V_CMP_LT_I32 : VOPC_I32 <"v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">;
638defm V_CMP_EQ_I32 : VOPC_I32 <"v_cmp_eq_i32">;
639defm V_CMP_LE_I32 : VOPC_I32 <"v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">;
640defm V_CMP_GT_I32 : VOPC_I32 <"v_cmp_gt_i32", COND_SGT>;
641defm V_CMP_NE_I32 : VOPC_I32 <"v_cmp_ne_i32">;
642defm V_CMP_GE_I32 : VOPC_I32 <"v_cmp_ge_i32", COND_SGE>;
643defm V_CMP_T_I32 : VOPC_I32 <"v_cmp_t_i32">;
644
645defm V_CMPX_F_I32 : VOPCX_I32 <"v_cmpx_f_i32">;
646defm V_CMPX_LT_I32 : VOPCX_I32 <"v_cmpx_lt_i32", "v_cmpx_gt_i32">;
647defm V_CMPX_EQ_I32 : VOPCX_I32 <"v_cmpx_eq_i32">;
648defm V_CMPX_LE_I32 : VOPCX_I32 <"v_cmpx_le_i32", "v_cmpx_ge_i32">;
649defm V_CMPX_GT_I32 : VOPCX_I32 <"v_cmpx_gt_i32">;
650defm V_CMPX_NE_I32 : VOPCX_I32 <"v_cmpx_ne_i32">;
651defm V_CMPX_GE_I32 : VOPCX_I32 <"v_cmpx_ge_i32">;
652defm V_CMPX_T_I32 : VOPCX_I32 <"v_cmpx_t_i32">;
653
654defm V_CMP_F_I64 : VOPC_I64 <"v_cmp_f_i64">;
655defm V_CMP_LT_I64 : VOPC_I64 <"v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">;
656defm V_CMP_EQ_I64 : VOPC_I64 <"v_cmp_eq_i64">;
657defm V_CMP_LE_I64 : VOPC_I64 <"v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">;
658defm V_CMP_GT_I64 : VOPC_I64 <"v_cmp_gt_i64", COND_SGT>;
659defm V_CMP_NE_I64 : VOPC_I64 <"v_cmp_ne_i64">;
660defm V_CMP_GE_I64 : VOPC_I64 <"v_cmp_ge_i64", COND_SGE>;
661defm V_CMP_T_I64 : VOPC_I64 <"v_cmp_t_i64">;
662
663defm V_CMPX_F_I64 : VOPCX_I64 <"v_cmpx_f_i64">;
664defm V_CMPX_LT_I64 : VOPCX_I64 <"v_cmpx_lt_i64", "v_cmpx_gt_i64">;
665defm V_CMPX_EQ_I64 : VOPCX_I64 <"v_cmpx_eq_i64">;
666defm V_CMPX_LE_I64 : VOPCX_I64 <"v_cmpx_le_i64", "v_cmpx_ge_i64">;
667defm V_CMPX_GT_I64 : VOPCX_I64 <"v_cmpx_gt_i64">;
668defm V_CMPX_NE_I64 : VOPCX_I64 <"v_cmpx_ne_i64">;
669defm V_CMPX_GE_I64 : VOPCX_I64 <"v_cmpx_ge_i64">;
670defm V_CMPX_T_I64 : VOPCX_I64 <"v_cmpx_t_i64">;
671
672defm V_CMP_F_U32 : VOPC_I32 <"v_cmp_f_u32">;
673defm V_CMP_LT_U32 : VOPC_I32 <"v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">;
674defm V_CMP_EQ_U32 : VOPC_I32 <"v_cmp_eq_u32", COND_EQ>;
675defm V_CMP_LE_U32 : VOPC_I32 <"v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">;
676defm V_CMP_GT_U32 : VOPC_I32 <"v_cmp_gt_u32", COND_UGT>;
677defm V_CMP_NE_U32 : VOPC_I32 <"v_cmp_ne_u32", COND_NE>;
678defm V_CMP_GE_U32 : VOPC_I32 <"v_cmp_ge_u32", COND_UGE>;
679defm V_CMP_T_U32 : VOPC_I32 <"v_cmp_t_u32">;
680
681defm V_CMPX_F_U32 : VOPCX_I32 <"v_cmpx_f_u32">;
682defm V_CMPX_LT_U32 : VOPCX_I32 <"v_cmpx_lt_u32", "v_cmpx_gt_u32">;
683defm V_CMPX_EQ_U32 : VOPCX_I32 <"v_cmpx_eq_u32">;
684defm V_CMPX_LE_U32 : VOPCX_I32 <"v_cmpx_le_u32", "v_cmpx_le_u32">;
685defm V_CMPX_GT_U32 : VOPCX_I32 <"v_cmpx_gt_u32">;
686defm V_CMPX_NE_U32 : VOPCX_I32 <"v_cmpx_ne_u32">;
687defm V_CMPX_GE_U32 : VOPCX_I32 <"v_cmpx_ge_u32">;
688defm V_CMPX_T_U32 : VOPCX_I32 <"v_cmpx_t_u32">;
689
690defm V_CMP_F_U64 : VOPC_I64 <"v_cmp_f_u64">;
691defm V_CMP_LT_U64 : VOPC_I64 <"v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">;
692defm V_CMP_EQ_U64 : VOPC_I64 <"v_cmp_eq_u64", COND_EQ>;
693defm V_CMP_LE_U64 : VOPC_I64 <"v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">;
694defm V_CMP_GT_U64 : VOPC_I64 <"v_cmp_gt_u64", COND_UGT>;
695defm V_CMP_NE_U64 : VOPC_I64 <"v_cmp_ne_u64", COND_NE>;
696defm V_CMP_GE_U64 : VOPC_I64 <"v_cmp_ge_u64", COND_UGE>;
697defm V_CMP_T_U64 : VOPC_I64 <"v_cmp_t_u64">;
698
699defm V_CMPX_F_U64 : VOPCX_I64 <"v_cmpx_f_u64">;
700defm V_CMPX_LT_U64 : VOPCX_I64 <"v_cmpx_lt_u64", "v_cmpx_gt_u64">;
701defm V_CMPX_EQ_U64 : VOPCX_I64 <"v_cmpx_eq_u64">;
702defm V_CMPX_LE_U64 : VOPCX_I64 <"v_cmpx_le_u64", "v_cmpx_ge_u64">;
703defm V_CMPX_GT_U64 : VOPCX_I64 <"v_cmpx_gt_u64">;
704defm V_CMPX_NE_U64 : VOPCX_I64 <"v_cmpx_ne_u64">;
705defm V_CMPX_GE_U64 : VOPCX_I64 <"v_cmpx_ge_u64">;
706defm V_CMPX_T_U64 : VOPCX_I64 <"v_cmpx_t_u64">;
707
708//===----------------------------------------------------------------------===//
709// Class instructions
710//===----------------------------------------------------------------------===//
711
712class VOPC_Class_Profile<list<SchedReadWrite> sched, ValueType vt> :
713  VOPC_Profile<sched, vt, i32> {
714  let AsmDPP = "$src0_modifiers, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
715  let AsmDPP16 = AsmDPP#"$fi";
716  let InsDPP = (ins FPVRegInputMods:$src0_modifiers, VGPR_32:$src0, VGPR_32:$src1, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
717  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
718  // DPP8 forbids modifiers and can inherit from VOPC_Profile
719
720  let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
721  dag InsPartVOP3DPP = (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0, VGPRSrc_32:$src1);
722  let InsVOP3Base = !con(InsPartVOP3DPP, !if(HasOpSel, (ins op_sel0:$op_sel),
723                                                       (ins)));
724  let Asm64 = "$sdst, $src0_modifiers, $src1";
725  let AsmVOP3DPPBase = Asm64;
726
727  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
728                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
729                     clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel);
730
731  let AsmSDWA = " vcc, $src0_modifiers, $src1_modifiers$clamp $src0_sel $src1_sel";
732  let HasSrc1Mods = 0;
733  let HasClamp = 0;
734  let HasOMod = 0;
735}
736
737class VOPC_Class_NoSdst_Profile<list<SchedReadWrite> sched, ValueType vt> :
738  VOPC_Class_Profile<sched, vt> {
739  let Outs64 = (outs );
740  let OutsSDWA = (outs );
741  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
742                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
743                     src0_sel:$src0_sel, src1_sel:$src1_sel);
744  let Asm64 = "$src0_modifiers, $src1";
745  let AsmVOP3DPPBase = Asm64;
746  let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
747  let EmitDst = 0;
748}
749
750class getVOPCClassPat64 <VOPProfile P> {
751  list<dag> ret =
752    [(set i1:$sdst,
753      (AMDGPUfp_class
754        (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers)),
755        P.Src1VT:$src1))];
756}
757
758// Special case for class instructions which only have modifiers on
759// the 1st source operand.
760multiclass VOPC_Class_Pseudos <string opName, VOPC_Profile p, bit DefExec,
761                               bit DefVcc = 1> {
762  def _e32 : VOPC_Pseudo <opName, p>,
763             VCMPXNoSDstTable<1, opName#"_e32"> {
764    let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]),
765                            !if(DefVcc, [VCC], []));
766    let SchedRW = p.Schedule;
767    let isConvergent = DefExec;
768  }
769
770  def _e64 : VOP3_Pseudo<opName, p, getVOPCClassPat64<p>.ret>,
771             VCMPXNoSDstTable<1, opName#"_e64"> {
772    let Defs = !if(DefExec, [EXEC], []);
773    let SchedRW = p.Schedule;
774  }
775
776  foreach _ = BoolToList<p.HasExtSDWA>.ret in
777  def _sdwa : VOPC_SDWA_Pseudo <opName, p> {
778    let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]),
779                            !if(DefVcc, [VCC], []));
780    let SchedRW = p.Schedule;
781    let isConvergent = DefExec;
782  }
783
784  let SubtargetPredicate = isGFX11Plus in {
785  if p.HasExtDPP then
786      def _e32_dpp : VOP_DPP_Pseudo<opName, p> {
787        let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]),
788                                !if(DefVcc, [VCC], []));
789        let SchedRW = p.Schedule;
790        let isConvergent = DefExec;
791        let VOPC = 1;
792        let Constraints = "";
793      }
794  if p.HasExtVOP3DPP then
795      def _e64_dpp : VOP3_DPP_Pseudo<opName, p> {
796        let Defs = !if(DefExec, [EXEC], []);
797        let SchedRW = p.Schedule;
798        let Constraints = "";
799    }
800  } // end SubtargetPredicate = isGFX11Plus
801}
802
803let SubtargetPredicate = HasSdstCMPX in {
804multiclass VOPCX_Class_Pseudos <string opName,
805                                VOPC_Profile P,
806                                VOPC_Profile P_NoSDst> :
807           VOPC_Class_Pseudos <opName, P, 1, 1> {
808
809  def _nosdst_e32 : VOPC_Pseudo <opName#"_nosdst", P_NoSDst, [], 0>,
810                    VCMPXNoSDstTable<0, opName#"_e32"> {
811    let Defs = [EXEC];
812    let SchedRW = P_NoSDst.Schedule;
813    let isConvergent = 1;
814    let SubtargetPredicate = HasNoSdstCMPX;
815  }
816
817  def _nosdst_e64 : VOP3_Pseudo<opName#"_nosdst", P_NoSDst>,
818                    VCMPXNoSDstTable<0, opName#"_e64"> {
819    let Defs = [EXEC];
820    let SchedRW = P_NoSDst.Schedule;
821    let SubtargetPredicate = HasNoSdstCMPX;
822  }
823
824  foreach _ = BoolToList<P_NoSDst.HasExtSDWA>.ret in
825  def _nosdst_sdwa : VOPC_SDWA_Pseudo <opName#"_nosdst", P_NoSDst> {
826    let Defs = [EXEC];
827    let SchedRW = P_NoSDst.Schedule;
828    let isConvergent = 1;
829    let SubtargetPredicate = HasNoSdstCMPX;
830  }
831
832  let SubtargetPredicate = isGFX11Plus in {
833  if P.HasExtDPP then
834      def _nosdst_e32_dpp : VOP_DPP_Pseudo<opName#"_nosdst", P_NoSDst> {
835        let Defs = [EXEC];
836        let SchedRW = P_NoSDst.Schedule;
837        let isConvergent = 1;
838        let VOPC = 1;
839        let Constraints = "";
840      }
841  if P.HasExtVOP3DPP then
842      def _nosdst_e64_dpp : VOP3_DPP_Pseudo<opName#"_nosdst", P_NoSDst> {
843        let Defs = [EXEC];
844        let SchedRW = P_NoSDst.Schedule;
845        let Constraints = "";
846    }
847  } // end SubtargetPredicate = isGFX11Plus
848}
849} // End SubtargetPredicate = HasSdstCMPX
850
851def VOPC_I1_F16_I32 : VOPC_Class_Profile<[Write32Bit], f16>;
852def VOPC_I1_F32_I32 : VOPC_Class_Profile<[Write32Bit], f32>;
853def VOPC_I1_F64_I32 : VOPC_Class_Profile<[WriteDoubleAdd], f64>;
854
855def VOPC_F16_I32 : VOPC_Class_NoSdst_Profile<[Write32Bit], f16>;
856def VOPC_F32_I32 : VOPC_Class_NoSdst_Profile<[Write32Bit], f32>;
857def VOPC_F64_I32 : VOPC_Class_NoSdst_Profile<[Write64Bit], f64>;
858
859multiclass VOPC_CLASS_F16 <string opName> :
860  VOPC_Class_Pseudos <opName, VOPC_I1_F16_I32, 0>;
861
862multiclass VOPCX_CLASS_F16 <string opName> :
863  VOPCX_Class_Pseudos <opName, VOPC_I1_F16_I32, VOPC_F16_I32>;
864
865multiclass VOPC_CLASS_F32 <string opName> :
866  VOPC_Class_Pseudos <opName, VOPC_I1_F32_I32, 0>;
867
868multiclass VOPCX_CLASS_F32 <string opName> :
869  VOPCX_Class_Pseudos <opName, VOPC_I1_F32_I32, VOPC_F32_I32>;
870
871multiclass VOPC_CLASS_F64 <string opName> :
872  VOPC_Class_Pseudos <opName, VOPC_I1_F64_I32, 0>;
873
874multiclass VOPCX_CLASS_F64 <string opName> :
875  VOPCX_Class_Pseudos <opName, VOPC_I1_F64_I32, VOPC_F64_I32>;
876
877// cmp_class ignores the FP mode and faithfully reports the unmodified
878// source value.
879let ReadsModeReg = 0, mayRaiseFPException = 0 in {
880defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <"v_cmp_class_f32">;
881defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <"v_cmpx_class_f32">;
882defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <"v_cmp_class_f64">;
883defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <"v_cmpx_class_f64">;
884
885let SubtargetPredicate = Has16BitInsts in {
886defm V_CMP_CLASS_F16  : VOPC_CLASS_F16 <"v_cmp_class_f16">;
887defm V_CMPX_CLASS_F16 : VOPCX_CLASS_F16 <"v_cmpx_class_f16">;
888}
889} // End ReadsModeReg = 0, mayRaiseFPException = 0
890
891//===----------------------------------------------------------------------===//
892// V_ICMPIntrinsic Pattern.
893//===----------------------------------------------------------------------===//
894
895// We need to use COPY_TO_REGCLASS to w/a the problem when ReplaceAllUsesWith()
896// complaints it cannot replace i1 <-> i64/i32 if node was not morphed in place.
897multiclass ICMP_Pattern <PatFrags cond, Instruction inst, ValueType vt> {
898  let WaveSizePredicate = isWave64 in
899  def : GCNPat <
900    (i64 (AMDGPUsetcc vt:$src0, vt:$src1, cond)),
901    (i64 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_64))
902  >;
903
904  let WaveSizePredicate = isWave32 in
905  def : GCNPat <
906    (i32 (AMDGPUsetcc vt:$src0, vt:$src1, cond)),
907    (i32 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_32))
908  >;
909}
910
911defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U32_e64, i32>;
912defm : ICMP_Pattern <COND_NE, V_CMP_NE_U32_e64, i32>;
913defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U32_e64, i32>;
914defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U32_e64, i32>;
915defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U32_e64, i32>;
916defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U32_e64, i32>;
917defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I32_e64, i32>;
918defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I32_e64, i32>;
919defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I32_e64, i32>;
920defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I32_e64, i32>;
921
922defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U64_e64, i64>;
923defm : ICMP_Pattern <COND_NE, V_CMP_NE_U64_e64, i64>;
924defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U64_e64, i64>;
925defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U64_e64, i64>;
926defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U64_e64, i64>;
927defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U64_e64, i64>;
928defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I64_e64, i64>;
929defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I64_e64, i64>;
930defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I64_e64, i64>;
931defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I64_e64, i64>;
932
933defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U16_e64, i16>;
934defm : ICMP_Pattern <COND_NE, V_CMP_NE_U16_e64, i16>;
935defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U16_e64, i16>;
936defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U16_e64, i16>;
937defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U16_e64, i16>;
938defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U16_e64, i16>;
939defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I16_e64, i16>;
940defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I16_e64, i16>;
941defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I16_e64, i16>;
942defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I16_e64, i16>;
943
944multiclass FCMP_Pattern <PatFrags cond, Instruction inst, ValueType vt> {
945  let WaveSizePredicate = isWave64 in
946  def : GCNPat <
947    (i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
948                 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),
949    (i64 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1,
950                           DSTCLAMP.NONE), SReg_64))
951  >;
952
953  let WaveSizePredicate = isWave32 in
954  def : GCNPat <
955    (i32 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
956                 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),
957    (i32 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1,
958                           DSTCLAMP.NONE), SReg_32))
959  >;
960}
961
962defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>;
963defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F32_e64, f32>;
964defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F32_e64, f32>;
965defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F32_e64, f32>;
966defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F32_e64, f32>;
967defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F32_e64, f32>;
968
969defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F64_e64, f64>;
970defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F64_e64, f64>;
971defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F64_e64, f64>;
972defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F64_e64, f64>;
973defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F64_e64, f64>;
974defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F64_e64, f64>;
975
976defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F16_e64, f16>;
977defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F16_e64, f16>;
978defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F16_e64, f16>;
979defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F16_e64, f16>;
980defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F16_e64, f16>;
981defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F16_e64, f16>;
982
983
984defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F32_e64, f32>;
985defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F32_e64, f32>;
986defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F32_e64, f32>;
987defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F32_e64, f32>;
988defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F32_e64, f32>;
989defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F32_e64, f32>;
990
991defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>;
992defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>;
993defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>;
994defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>;
995defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>;
996defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>;
997
998defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F16_e64, f16>;
999defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F16_e64, f16>;
1000defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F16_e64, f16>;
1001defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F16_e64, f16>;
1002defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F16_e64, f16>;
1003defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F16_e64, f16>;
1004
1005//===----------------------------------------------------------------------===//
1006// DPP Encodings
1007//===----------------------------------------------------------------------===//
1008
1009// VOPC32
1010
1011class VOPC_DPPe_Common<bits<8> op> : Enc64 {
1012  bits<8> src1;
1013  let Inst{16-9} = src1;
1014  let Inst{24-17} = op;
1015  let Inst{31-25} = 0x3e;
1016}
1017
1018class VOPC_DPP_Base<bits<8> op, string OpName, VOPProfile P>
1019    : VOP_DPP_Base<OpName, P, P.InsDPP16, " " #P.AsmDPP16>,
1020      VOPC_DPPe_Common<op> {
1021  bits<2> src0_modifiers;
1022  bits<8> src0;
1023  bits<2> src1_modifiers;
1024  bits<9> dpp_ctrl;
1025  bits<1> bound_ctrl;
1026  bits<4> bank_mask;
1027  bits<4> row_mask;
1028  bit fi;
1029
1030  let Inst{8-0} = 0xfa;
1031
1032  let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, 0);
1033  let Inst{48-40} = dpp_ctrl;
1034  let Inst{50} = fi;
1035  let Inst{51} = bound_ctrl;
1036  let Inst{52} = !if (P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg
1037  let Inst{53} = !if (P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs
1038  let Inst{54} = !if (P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg
1039  let Inst{55} = !if (P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs
1040  let Inst{59-56} = bank_mask;
1041  let Inst{63-60} = row_mask;
1042
1043  let AsmMatchConverter = "cvtDPP";
1044  let VOPC = 1;
1045}
1046
1047class VOPC_DPP8_Base<bits<8> op, string OpName, VOPProfile P>
1048    : VOP_DPP8_Base<OpName, P, P.InsDPP8, " " #P.AsmDPP8>,
1049      VOPC_DPPe_Common<op> {
1050  bits<8> src0;
1051  bits<24> dpp8;
1052  bits<9> fi;
1053
1054  let Inst{8-0} = fi;
1055
1056  let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, 0);
1057  let Inst{63-40} = dpp8{23-0};
1058
1059  let AsmMatchConverter = "cvtDPP8";
1060  let VOPC = 1;
1061}
1062
1063class VOPC_DPP16<bits<8> op, VOP_DPP_Pseudo ps, string opName = ps.OpName>
1064    : VOPC_DPP_Base<op, opName, ps.Pfl> {
1065  let AssemblerPredicate = HasDPP16;
1066  let SubtargetPredicate = HasDPP16;
1067  let hasSideEffects = ps.hasSideEffects;
1068  let Defs = ps.Defs;
1069  let SchedRW = ps.SchedRW;
1070  let Uses = ps.Uses;
1071  let OtherPredicates = ps.OtherPredicates;
1072  let Constraints = ps.Constraints;
1073}
1074
1075class VOPC_DPP16_SIMC<bits<8> op, VOP_DPP_Pseudo ps, int subtarget,
1076                      string opName = ps.OpName>
1077    : VOPC_DPP16<op, ps, opName>, SIMCInstr<ps.PseudoInstr, subtarget>;
1078
1079class VOPC_DPP8<bits<8> op, VOPC_Pseudo ps, string opName = ps.OpName>
1080    : VOPC_DPP8_Base<op, opName, ps.Pfl> {
1081  // Note ps is the non-dpp pseudo
1082  let hasSideEffects = ps.hasSideEffects;
1083  let Defs = ps.Defs;
1084  let SchedRW = ps.SchedRW;
1085  let Uses = ps.Uses;
1086  let OtherPredicates = ps.OtherPredicates;
1087  let Constraints = "";
1088}
1089
1090// VOPC64
1091
1092class VOPC64_DPP_Base<bits<10> op, string OpName, VOPProfile P>
1093    : VOP3_DPP_Base<OpName, P, 1>, VOP3_DPPe_Common<op, P> {
1094  Instruction Opcode = !cast<Instruction>(NAME);
1095
1096  bits<8> src0;
1097  bits<9> dpp_ctrl;
1098  bits<1> bound_ctrl;
1099  bits<4> bank_mask;
1100  bits<4> row_mask;
1101  bit     fi;
1102
1103  let Inst{40-32} = 0xfa;
1104  let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
1105  let Inst{80-72} = dpp_ctrl;
1106  let Inst{82}    = fi;
1107  let Inst{83}    = bound_ctrl;
1108  // Inst{87-84} ignored by hw
1109  let Inst{91-88} = bank_mask;
1110  let Inst{95-92} = row_mask;
1111}
1112
1113class VOPC64_DPP16<bits<10> op, VOP_DPP_Pseudo ps, string opName = ps.OpName>
1114    : VOPC64_DPP_Base<op, opName, ps.Pfl> {
1115  let AssemblerPredicate = HasDPP16;
1116  let SubtargetPredicate = HasDPP16;
1117  let hasSideEffects = ps.hasSideEffects;
1118  let Defs = ps.Defs;
1119  let SchedRW = ps.SchedRW;
1120  let Uses = ps.Uses;
1121  let OtherPredicates = ps.OtherPredicates;
1122  let Constraints = ps.Constraints;
1123}
1124
1125class VOPC64_DPP16_Dst<bits<10> op, VOP_DPP_Pseudo ps,
1126                       string opName = ps.OpName>
1127    : VOPC64_DPP16<op, ps, opName> {
1128  bits<8> sdst;
1129  let Inst{7-0} = sdst;
1130}
1131
1132class VOPC64_DPP16_NoDst<bits<10> op, VOP_DPP_Pseudo ps,
1133                         string opName = ps.OpName>
1134    : VOPC64_DPP16<op, ps, opName> {
1135  let Inst{7-0} = ? ;
1136}
1137
1138class VOPC64_DPP8_Base<bits<10> op, string OpName, VOPProfile P>
1139    : VOP3_DPP8_Base<OpName, P>, VOP3_DPPe_Common<op, P> {
1140  Instruction Opcode = !cast<Instruction>(NAME);
1141
1142  bits<8> src0;
1143  bits<24> dpp8;
1144  bits<9> fi;
1145
1146  let Inst{40-32} = fi;
1147  let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
1148  let Inst{95-72} = dpp8{23-0};
1149}
1150
1151class VOPC64_DPP8<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>
1152    : VOPC64_DPP8_Base<op, opName, ps.Pfl> {
1153  // Note ps is the non-dpp pseudo
1154  let hasSideEffects = ps.hasSideEffects;
1155  let Defs = ps.Defs;
1156  let SchedRW = ps.SchedRW;
1157  let Uses = ps.Uses;
1158  let OtherPredicates = ps.OtherPredicates;
1159}
1160
1161class VOPC64_DPP8_Dst<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>
1162    : VOPC64_DPP8<op, ps, opName> {
1163  bits<8> sdst;
1164  let Inst{7-0} = sdst;
1165  let Constraints = "";
1166}
1167
1168class VOPC64_DPP8_NoDst<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>
1169    : VOPC64_DPP8<op, ps, opName> {
1170  let Inst{7-0} = ? ;
1171  let Constraints = "";
1172}
1173
1174//===----------------------------------------------------------------------===//
1175// Target-specific instruction encodings.
1176//===----------------------------------------------------------------------===//
1177
1178//===----------------------------------------------------------------------===//
1179// GFX11.
1180//===----------------------------------------------------------------------===//
1181
1182let AssemblerPredicate = isGFX11Only in {
1183  multiclass VOPC_Real_gfx11<bits<9> op> {
1184    defvar ps32 = !cast<VOPC_Pseudo>(NAME#"_e32");
1185    defvar ps64 = !cast<VOP3_Pseudo>(NAME#"_e64");
1186    let DecoderNamespace = "GFX11" in {
1187      def _e32_gfx11 : VOPC_Real<ps32, SIEncodingFamily.GFX11>,
1188                       VOPCe<op{7-0}>;
1189      def _e64_gfx11 : VOP3_Real<ps64, SIEncodingFamily.GFX11>,
1190                       VOP3a_gfx11<{0, op}, ps64.Pfl> {
1191        // Encoding used for VOPC instructions encoded as VOP3 differs from
1192        // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
1193        bits<8> sdst;
1194        let Inst{7-0} = sdst;
1195      }
1196    } // End DecoderNamespace = "GFX11"
1197
1198    defm : VOPCInstAliases<NAME, "gfx11">;
1199
1200    foreach _ = BoolToList<ps32.Pfl.HasExtDPP>.ret in {
1201      defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_e32" #"_dpp");
1202      defvar AsmDPP = ps32.Pfl.AsmDPP16;
1203      let DecoderNamespace = "DPPGFX11" in {
1204        def _e32_dpp_gfx11 : VOPC_DPP16_SIMC<op{7-0}, psDPP,
1205                                             SIEncodingFamily.GFX11>;
1206        def _e32_dpp_w32_gfx11 : VOPC_DPP16<op{7-0}, psDPP> {
1207          let AsmString = psDPP.OpName # " vcc_lo, " # AsmDPP;
1208          let isAsmParserOnly = 1;
1209          let WaveSizePredicate = isWave32;
1210        }
1211        def _e32_dpp_w64_gfx11 : VOPC_DPP16<op{7-0}, psDPP> {
1212          let AsmString = psDPP.OpName # " vcc, " # AsmDPP;
1213          let isAsmParserOnly = 1;
1214          let WaveSizePredicate = isWave64;
1215        }
1216      }
1217      defvar AsmDPP8 = ps32.Pfl.AsmDPP8;
1218      let DecoderNamespace = "DPP8GFX11" in {
1219        def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32>;
1220        def _e32_dpp8_w32_gfx11 : VOPC_DPP8<op{7-0}, ps32> {
1221          let AsmString = ps32.OpName # " vcc_lo, " # AsmDPP8;
1222          let isAsmParserOnly = 1;
1223          let WaveSizePredicate = isWave32;
1224        }
1225        def _e32_dpp8_w64_gfx11 : VOPC_DPP8<op{7-0}, ps32> {
1226          let AsmString = ps32.OpName # " vcc, " # AsmDPP8;
1227          let isAsmParserOnly = 1;
1228          let WaveSizePredicate = isWave64;
1229        }
1230      }
1231    }
1232    foreach _ = BoolToList<ps64.Pfl.HasExtVOP3DPP>.ret in {
1233      defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_e64" #"_dpp");
1234      defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16;
1235      let DecoderNamespace = "DPPGFX11" in {
1236        def _e64_dpp_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP>,
1237                             SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11>;
1238        def _e64_dpp_w32_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP> {
1239          let AsmString = psDPP.OpName # " vcc_lo, " # AsmDPP;
1240          let isAsmParserOnly = 1;
1241          let WaveSizePredicate = isWave32;
1242        }
1243        def _e64_dpp_w64_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP> {
1244          let AsmString = psDPP.OpName # " vcc, " # AsmDPP;
1245          let isAsmParserOnly = 1;
1246          let WaveSizePredicate = isWave64;
1247        }
1248      }
1249      defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8;
1250      let DecoderNamespace = "DPP8GFX11" in {
1251        def _e64_dpp8_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64>;
1252        def _e64_dpp8_w32_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64> {
1253          let AsmString = ps32.OpName # " vcc_lo, " # AsmDPP8;
1254          let isAsmParserOnly = 1;
1255          let WaveSizePredicate = isWave32;
1256        }
1257        def _e64_dpp8_w64_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64> {
1258          let AsmString = ps32.OpName # " vcc, " # AsmDPP8;
1259          let isAsmParserOnly = 1;
1260          let WaveSizePredicate = isWave64;
1261        }
1262      }
1263    }
1264
1265  }
1266
1267  multiclass VOPC_Real_with_name_gfx11<bits<9> op, string OpName,
1268        string asm_name> {
1269    defvar ps32 = !cast<VOPC_Pseudo>(OpName#"_e32");
1270    defvar ps64 = !cast<VOP3_Pseudo>(OpName#"_e64");
1271    let DecoderNamespace = "GFX11" in {
1272      def _e32_gfx11 :
1273        // 32 and 64 bit forms of the instruction have _e32 and _e64
1274        // respectively appended to their assembly mnemonic.
1275        // _e64 is printed as part of the VOPDstS64orS32 operand, whereas
1276        // the destination-less 32bit forms add it to the asmString here.
1277        VOPC_Real<ps32, SIEncodingFamily.GFX11, asm_name#"_e32">,
1278        VOPCe<op{7-0}>,
1279        MnemonicAlias<ps32.Mnemonic, asm_name>, Requires<[isGFX11Plus]>;
1280      def _e64_gfx11 :
1281            VOP3_Real<ps64, SIEncodingFamily.GFX11, asm_name>,
1282            VOP3a_gfx11<{0, op}, ps64.Pfl>,
1283            MnemonicAlias<ps64.Mnemonic, asm_name>, Requires<[isGFX11Plus]> {
1284        // Encoding used for VOPC instructions encoded as VOP3 differs from
1285        // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
1286        bits<8> sdst;
1287        let Inst{7-0} = sdst;
1288      }
1289    } // End DecoderNamespace = "GFX11"
1290
1291    defm : VOPCInstAliases<OpName, "gfx11", NAME>;
1292
1293    foreach _ = BoolToList<ps32.Pfl.HasExtDPP>.ret in {
1294      defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName #"_e32" #"_dpp");
1295      defvar AsmDPP = ps32.Pfl.AsmDPP16;
1296      let DecoderNamespace = "DPPGFX11" in {
1297        def _e32_dpp_gfx11 : VOPC_DPP16_SIMC<op{7-0}, psDPP,
1298                                             SIEncodingFamily.GFX11, asm_name>;
1299        def _e32_dpp_w32_gfx11
1300            : VOPC_DPP16<op{7-0}, psDPP, asm_name> {
1301          let AsmString = asm_name # " vcc_lo, " # AsmDPP;
1302          let isAsmParserOnly = 1;
1303          let WaveSizePredicate = isWave32;
1304        }
1305        def _e32_dpp_w64_gfx11
1306            : VOPC_DPP16<op{7-0}, psDPP, asm_name> {
1307          let AsmString = asm_name # " vcc, " # AsmDPP;
1308          let isAsmParserOnly = 1;
1309          let WaveSizePredicate = isWave64;
1310        }
1311      }
1312      defvar AsmDPP8 = ps32.Pfl.AsmDPP8;
1313      let DecoderNamespace = "DPP8GFX11" in {
1314        def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32, asm_name>;
1315        def _e32_dpp8_w32_gfx11
1316            : VOPC_DPP8<op{7-0}, ps32, asm_name> {
1317          let AsmString = asm_name # " vcc_lo, " # AsmDPP8;
1318          let isAsmParserOnly = 1;
1319          let WaveSizePredicate = isWave32;
1320        }
1321        def _e32_dpp8_w64_gfx11
1322            : VOPC_DPP8<op{7-0}, ps32, asm_name> {
1323          let AsmString = asm_name # " vcc, " # AsmDPP8;
1324          let isAsmParserOnly = 1;
1325          let WaveSizePredicate = isWave64;
1326        }
1327      }
1328    }
1329
1330    foreach _ = BoolToList<ps64.Pfl.HasExtVOP3DPP>.ret in {
1331      defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName #"_e64" #"_dpp");
1332      defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16;
1333      let DecoderNamespace = "DPPGFX11" in {
1334        def _e64_dpp_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name>,
1335                             SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11>;
1336        def _e64_dpp_w32_gfx11
1337            : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name> {
1338          let AsmString = asm_name # " vcc_lo, " # AsmDPP;
1339          let isAsmParserOnly = 1;
1340          let WaveSizePredicate = isWave32;
1341        }
1342        def _e64_dpp_w64_gfx11
1343            : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name> {
1344          let AsmString = asm_name # " vcc, " # AsmDPP;
1345          let isAsmParserOnly = 1;
1346          let WaveSizePredicate = isWave64;
1347        }
1348      }
1349      defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8;
1350      let DecoderNamespace = "DPP8GFX11" in {
1351        def _e64_dpp8_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name>;
1352        def _e64_dpp8_w32_gfx11
1353            : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name> {
1354          let AsmString = asm_name # " vcc_lo, " # AsmDPP8;
1355          let isAsmParserOnly = 1;
1356          let WaveSizePredicate = isWave32;
1357        }
1358        def _e64_dpp8_w64_gfx11
1359            : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name> {
1360          let AsmString = asm_name # " vcc, " # AsmDPP8;
1361          let isAsmParserOnly = 1;
1362          let WaveSizePredicate = isWave64;
1363        }
1364      }
1365    }
1366
1367  }
1368
1369  multiclass VOPCX_Real_gfx11<bits<9> op> {
1370    defvar ps32 = !cast<VOPC_Pseudo>(NAME#"_nosdst_e32");
1371    defvar ps64 = !cast<VOP3_Pseudo>(NAME#"_nosdst_e64");
1372    let DecoderNamespace = "GFX11" in {
1373      def _e32_gfx11 :
1374        VOPC_Real<ps32, SIEncodingFamily.GFX11>,
1375        VOPCe<op{7-0}> {
1376          let AsmString = !subst("_nosdst", "", ps32.PseudoInstr)
1377                          # " " # ps32.AsmOperands;
1378        }
1379      def _e64_gfx11 :
1380        VOP3_Real<ps64, SIEncodingFamily.GFX11>,
1381        VOP3a_gfx11<{0, op}, ps64.Pfl> {
1382          let Inst{7-0} = ?; // sdst
1383          let AsmString = !subst("_nosdst", "", ps64.Mnemonic)
1384                          # "{_e64} " # ps64.AsmOperands;
1385        }
1386    } // End DecoderNamespace = "GFX11"
1387
1388    defm : VOPCXInstAliases<NAME, "gfx11">;
1389
1390    foreach _ = BoolToList<ps32.Pfl.HasExtDPP>.ret in {
1391      defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_nosdst_e32" #"_dpp");
1392      defvar AsmDPP = ps32.Pfl.AsmDPP16;
1393      let DecoderNamespace = "DPPGFX11" in {
1394        def _e32_dpp_gfx11
1395            : VOPC_DPP16_SIMC<op{7-0}, psDPP, SIEncodingFamily.GFX11> {
1396          let AsmString = !subst("_nosdst", "", psDPP.OpName) # " " # AsmDPP;
1397        }
1398      }
1399      defvar AsmDPP8 = ps32.Pfl.AsmDPP8;
1400      let DecoderNamespace = "DPP8GFX11" in {
1401        def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32> {
1402          let AsmString = !subst("_nosdst", "", ps32.OpName) # " " # AsmDPP8;
1403        }
1404      }
1405    }
1406
1407    foreach _ = BoolToList<ps64.Pfl.HasExtVOP3DPP>.ret in {
1408      defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_nosdst_e64" #"_dpp");
1409      defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16;
1410      let DecoderNamespace = "DPPGFX11" in {
1411        def _e64_dpp_gfx11
1412            : VOPC64_DPP16_NoDst<{0, op}, psDPP>,
1413              SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11> {
1414          let AsmString = !subst("_nosdst", "", psDPP.OpName)
1415                          # "{_e64_dpp} " # AsmDPP;
1416        }
1417      }
1418      defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8;
1419      let DecoderNamespace = "DPP8GFX11" in {
1420        def _e64_dpp8_gfx11 : VOPC64_DPP8_NoDst<{0, op}, ps64> {
1421          let AsmString = !subst("_nosdst", "", ps64.OpName)
1422                          # "{_e64_dpp} " # AsmDPP8;
1423        }
1424      }
1425    }
1426  }
1427
1428  multiclass VOPCX_Real_with_name_gfx11<bits<9> op, string OpName,
1429        string asm_name> {
1430    defvar ps32 = !cast<VOPC_Pseudo>(OpName#"_nosdst_e32");
1431    defvar ps64 = !cast<VOP3_Pseudo>(OpName#"_nosdst_e64");
1432    let DecoderNamespace = "GFX11" in {
1433      def _e32_gfx11
1434          : VOPC_Real<ps32, SIEncodingFamily.GFX11, asm_name>,
1435            MnemonicAlias<!subst("_nosdst", "", ps32.Mnemonic), asm_name>,
1436            Requires<[isGFX11Plus]>,
1437            VOPCe<op{7-0}> {
1438        let AsmString = asm_name # "{_e32} " # ps32.AsmOperands;
1439      }
1440      def _e64_gfx11
1441          : VOP3_Real<ps64, SIEncodingFamily.GFX11, asm_name>,
1442            MnemonicAlias<!subst("_nosdst", "", ps64.Mnemonic), asm_name>,
1443            Requires<[isGFX11Plus]>,
1444            VOP3a_gfx11<{0, op}, ps64.Pfl> {
1445        let Inst{7-0} = ? ; // sdst
1446        let AsmString = asm_name # "{_e64} " # ps64.AsmOperands;
1447      }
1448    } // End DecoderNamespace = "GFX11"
1449
1450    defm : VOPCXInstAliases<OpName, "gfx11", NAME>;
1451
1452    foreach _ = BoolToList<ps32.Pfl.HasExtDPP>.ret in {
1453      defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName#"_nosdst_e32"#"_dpp");
1454      let DecoderNamespace = "DPPGFX11" in {
1455        def _e32_dpp_gfx11 : VOPC_DPP16_SIMC<op{7-0}, psDPP,
1456                                             SIEncodingFamily.GFX11, asm_name>;
1457      }
1458      let DecoderNamespace = "DPP8GFX11" in {
1459        def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32, asm_name>;
1460      }
1461    }
1462    foreach _ = BoolToList<ps64.Pfl.HasExtVOP3DPP>.ret in {
1463      defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName#"_nosdst_e64"#"_dpp");
1464      defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16;
1465      let DecoderNamespace = "DPPGFX11" in {
1466        def _e64_dpp_gfx11
1467            : VOPC64_DPP16_NoDst<{0, op}, psDPP, asm_name>,
1468              SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11> {
1469          let AsmString = asm_name # "{_e64_dpp} " # AsmDPP;
1470        }
1471      }
1472      defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8;
1473      let DecoderNamespace = "DPP8GFX11" in {
1474        def _e64_dpp8_gfx11 : VOPC64_DPP8_NoDst<{0, op}, ps64, asm_name> {
1475          let AsmString = asm_name # "{_e64_dpp} " # AsmDPP8;
1476        }
1477      }
1478    }
1479
1480  }
1481} // End AssemblerPredicate = isGFX11Only
1482
1483defm V_CMP_F_F16      : VOPC_Real_gfx11<0x000>;
1484defm V_CMP_LT_F16     : VOPC_Real_gfx11<0x001>;
1485defm V_CMP_EQ_F16     : VOPC_Real_gfx11<0x002>;
1486defm V_CMP_LE_F16     : VOPC_Real_gfx11<0x003>;
1487defm V_CMP_GT_F16     : VOPC_Real_gfx11<0x004>;
1488defm V_CMP_LG_F16     : VOPC_Real_gfx11<0x005>;
1489defm V_CMP_GE_F16     : VOPC_Real_gfx11<0x006>;
1490defm V_CMP_O_F16      : VOPC_Real_gfx11<0x007>;
1491defm V_CMP_U_F16      : VOPC_Real_gfx11<0x008>;
1492defm V_CMP_NGE_F16    : VOPC_Real_gfx11<0x009>;
1493defm V_CMP_NLG_F16    : VOPC_Real_gfx11<0x00a>;
1494defm V_CMP_NGT_F16    : VOPC_Real_gfx11<0x00b>;
1495defm V_CMP_NLE_F16    : VOPC_Real_gfx11<0x00c>;
1496defm V_CMP_NEQ_F16    : VOPC_Real_gfx11<0x00d>;
1497defm V_CMP_NLT_F16    : VOPC_Real_gfx11<0x00e>;
1498defm V_CMP_T_F16      : VOPC_Real_with_name_gfx11<0x00f, "V_CMP_TRU_F16", "v_cmp_t_f16">;
1499defm V_CMP_F_F32      : VOPC_Real_gfx11<0x010>;
1500defm V_CMP_LT_F32     : VOPC_Real_gfx11<0x011>;
1501defm V_CMP_EQ_F32     : VOPC_Real_gfx11<0x012>;
1502defm V_CMP_LE_F32     : VOPC_Real_gfx11<0x013>;
1503defm V_CMP_GT_F32     : VOPC_Real_gfx11<0x014>;
1504defm V_CMP_LG_F32     : VOPC_Real_gfx11<0x015>;
1505defm V_CMP_GE_F32     : VOPC_Real_gfx11<0x016>;
1506defm V_CMP_O_F32      : VOPC_Real_gfx11<0x017>;
1507defm V_CMP_U_F32      : VOPC_Real_gfx11<0x018>;
1508defm V_CMP_NGE_F32    : VOPC_Real_gfx11<0x019>;
1509defm V_CMP_NLG_F32    : VOPC_Real_gfx11<0x01a>;
1510defm V_CMP_NGT_F32    : VOPC_Real_gfx11<0x01b>;
1511defm V_CMP_NLE_F32    : VOPC_Real_gfx11<0x01c>;
1512defm V_CMP_NEQ_F32    : VOPC_Real_gfx11<0x01d>;
1513defm V_CMP_NLT_F32    : VOPC_Real_gfx11<0x01e>;
1514defm V_CMP_T_F32      : VOPC_Real_with_name_gfx11<0x01f, "V_CMP_TRU_F32", "v_cmp_t_f32">;
1515defm V_CMP_T_F64      : VOPC_Real_with_name_gfx11<0x02f, "V_CMP_TRU_F64", "v_cmp_t_f64">;
1516defm V_CMP_LT_I16     : VOPC_Real_gfx11<0x031>;
1517defm V_CMP_EQ_I16     : VOPC_Real_gfx11<0x032>;
1518defm V_CMP_LE_I16     : VOPC_Real_gfx11<0x033>;
1519defm V_CMP_GT_I16     : VOPC_Real_gfx11<0x034>;
1520defm V_CMP_NE_I16     : VOPC_Real_gfx11<0x035>;
1521defm V_CMP_GE_I16     : VOPC_Real_gfx11<0x036>;
1522defm V_CMP_LT_U16     : VOPC_Real_gfx11<0x039>;
1523defm V_CMP_EQ_U16     : VOPC_Real_gfx11<0x03a>;
1524defm V_CMP_LE_U16     : VOPC_Real_gfx11<0x03b>;
1525defm V_CMP_GT_U16     : VOPC_Real_gfx11<0x03c>;
1526defm V_CMP_NE_U16     : VOPC_Real_gfx11<0x03d>;
1527defm V_CMP_GE_U16     : VOPC_Real_gfx11<0x03e>;
1528defm V_CMP_F_I32      : VOPC_Real_gfx11<0x040>;
1529defm V_CMP_LT_I32     : VOPC_Real_gfx11<0x041>;
1530defm V_CMP_EQ_I32     : VOPC_Real_gfx11<0x042>;
1531defm V_CMP_LE_I32     : VOPC_Real_gfx11<0x043>;
1532defm V_CMP_GT_I32     : VOPC_Real_gfx11<0x044>;
1533defm V_CMP_NE_I32     : VOPC_Real_gfx11<0x045>;
1534defm V_CMP_GE_I32     : VOPC_Real_gfx11<0x046>;
1535defm V_CMP_T_I32      : VOPC_Real_gfx11<0x047>;
1536defm V_CMP_F_U32      : VOPC_Real_gfx11<0x048>;
1537defm V_CMP_LT_U32     : VOPC_Real_gfx11<0x049>;
1538defm V_CMP_EQ_U32     : VOPC_Real_gfx11<0x04a>;
1539defm V_CMP_LE_U32     : VOPC_Real_gfx11<0x04b>;
1540defm V_CMP_GT_U32     : VOPC_Real_gfx11<0x04c>;
1541defm V_CMP_NE_U32     : VOPC_Real_gfx11<0x04d>;
1542defm V_CMP_GE_U32     : VOPC_Real_gfx11<0x04e>;
1543defm V_CMP_T_U32      : VOPC_Real_gfx11<0x04f>;
1544
1545defm V_CMP_F_I64      : VOPC_Real_gfx11<0x050>;
1546defm V_CMP_LT_I64     : VOPC_Real_gfx11<0x051>;
1547defm V_CMP_EQ_I64     : VOPC_Real_gfx11<0x052>;
1548defm V_CMP_LE_I64     : VOPC_Real_gfx11<0x053>;
1549defm V_CMP_GT_I64     : VOPC_Real_gfx11<0x054>;
1550defm V_CMP_NE_I64     : VOPC_Real_gfx11<0x055>;
1551defm V_CMP_GE_I64     : VOPC_Real_gfx11<0x056>;
1552defm V_CMP_T_I64      : VOPC_Real_gfx11<0x057>;
1553defm V_CMP_F_U64      : VOPC_Real_gfx11<0x058>;
1554defm V_CMP_LT_U64     : VOPC_Real_gfx11<0x059>;
1555defm V_CMP_EQ_U64     : VOPC_Real_gfx11<0x05a>;
1556defm V_CMP_LE_U64     : VOPC_Real_gfx11<0x05b>;
1557defm V_CMP_GT_U64     : VOPC_Real_gfx11<0x05c>;
1558defm V_CMP_NE_U64     : VOPC_Real_gfx11<0x05d>;
1559defm V_CMP_GE_U64     : VOPC_Real_gfx11<0x05e>;
1560defm V_CMP_T_U64      : VOPC_Real_gfx11<0x05f>;
1561
1562defm V_CMP_CLASS_F16  : VOPC_Real_gfx11<0x07d>;
1563defm V_CMP_CLASS_F32  : VOPC_Real_gfx11<0x07e>;
1564defm V_CMP_CLASS_F64  : VOPC_Real_gfx11<0x07f>;
1565
1566defm V_CMPX_F_F16     : VOPCX_Real_gfx11<0x080>;
1567defm V_CMPX_LT_F16    : VOPCX_Real_gfx11<0x081>;
1568defm V_CMPX_EQ_F16    : VOPCX_Real_gfx11<0x082>;
1569defm V_CMPX_LE_F16    : VOPCX_Real_gfx11<0x083>;
1570defm V_CMPX_GT_F16    : VOPCX_Real_gfx11<0x084>;
1571defm V_CMPX_LG_F16    : VOPCX_Real_gfx11<0x085>;
1572defm V_CMPX_GE_F16    : VOPCX_Real_gfx11<0x086>;
1573defm V_CMPX_O_F16     : VOPCX_Real_gfx11<0x087>;
1574defm V_CMPX_U_F16     : VOPCX_Real_gfx11<0x088>;
1575defm V_CMPX_NGE_F16   : VOPCX_Real_gfx11<0x089>;
1576defm V_CMPX_NLG_F16   : VOPCX_Real_gfx11<0x08a>;
1577defm V_CMPX_NGT_F16   : VOPCX_Real_gfx11<0x08b>;
1578defm V_CMPX_NLE_F16   : VOPCX_Real_gfx11<0x08c>;
1579defm V_CMPX_NEQ_F16   : VOPCX_Real_gfx11<0x08d>;
1580defm V_CMPX_NLT_F16   : VOPCX_Real_gfx11<0x08e>;
1581defm V_CMPX_T_F16     : VOPCX_Real_with_name_gfx11<0x08f, "V_CMPX_TRU_F16", "v_cmpx_t_f16">;
1582defm V_CMPX_F_F32     : VOPCX_Real_gfx11<0x090>;
1583defm V_CMPX_LT_F32    : VOPCX_Real_gfx11<0x091>;
1584defm V_CMPX_EQ_F32    : VOPCX_Real_gfx11<0x092>;
1585defm V_CMPX_LE_F32    : VOPCX_Real_gfx11<0x093>;
1586defm V_CMPX_GT_F32    : VOPCX_Real_gfx11<0x094>;
1587defm V_CMPX_LG_F32    : VOPCX_Real_gfx11<0x095>;
1588defm V_CMPX_GE_F32    : VOPCX_Real_gfx11<0x096>;
1589defm V_CMPX_O_F32     : VOPCX_Real_gfx11<0x097>;
1590defm V_CMPX_U_F32     : VOPCX_Real_gfx11<0x098>;
1591defm V_CMPX_NGE_F32   : VOPCX_Real_gfx11<0x099>;
1592defm V_CMPX_NLG_F32   : VOPCX_Real_gfx11<0x09a>;
1593defm V_CMPX_NGT_F32   : VOPCX_Real_gfx11<0x09b>;
1594defm V_CMPX_NLE_F32   : VOPCX_Real_gfx11<0x09c>;
1595defm V_CMPX_NEQ_F32   : VOPCX_Real_gfx11<0x09d>;
1596defm V_CMPX_NLT_F32   : VOPCX_Real_gfx11<0x09e>;
1597defm V_CMPX_T_F32     : VOPCX_Real_with_name_gfx11<0x09f, "V_CMPX_TRU_F32", "v_cmpx_t_f32">;
1598
1599defm V_CMPX_F_F64     : VOPCX_Real_gfx11<0x0a0>;
1600defm V_CMPX_LT_F64    : VOPCX_Real_gfx11<0x0a1>;
1601defm V_CMPX_EQ_F64    : VOPCX_Real_gfx11<0x0a2>;
1602defm V_CMPX_LE_F64    : VOPCX_Real_gfx11<0x0a3>;
1603defm V_CMPX_GT_F64    : VOPCX_Real_gfx11<0x0a4>;
1604defm V_CMPX_LG_F64    : VOPCX_Real_gfx11<0x0a5>;
1605defm V_CMPX_GE_F64    : VOPCX_Real_gfx11<0x0a6>;
1606defm V_CMPX_O_F64     : VOPCX_Real_gfx11<0x0a7>;
1607defm V_CMPX_U_F64     : VOPCX_Real_gfx11<0x0a8>;
1608defm V_CMPX_NGE_F64   : VOPCX_Real_gfx11<0x0a9>;
1609defm V_CMPX_NLG_F64   : VOPCX_Real_gfx11<0x0aa>;
1610defm V_CMPX_NGT_F64   : VOPCX_Real_gfx11<0x0ab>;
1611defm V_CMPX_NLE_F64   : VOPCX_Real_gfx11<0x0ac>;
1612defm V_CMPX_NEQ_F64   : VOPCX_Real_gfx11<0x0ad>;
1613defm V_CMPX_NLT_F64   : VOPCX_Real_gfx11<0x0ae>;
1614defm V_CMPX_T_F64     : VOPCX_Real_with_name_gfx11<0x0af, "V_CMPX_TRU_F64", "v_cmpx_t_f64">;
1615
1616defm V_CMPX_LT_I16    : VOPCX_Real_gfx11<0x0b1>;
1617defm V_CMPX_EQ_I16    : VOPCX_Real_gfx11<0x0b2>;
1618defm V_CMPX_LE_I16    : VOPCX_Real_gfx11<0x0b3>;
1619defm V_CMPX_GT_I16    : VOPCX_Real_gfx11<0x0b4>;
1620defm V_CMPX_NE_I16    : VOPCX_Real_gfx11<0x0b5>;
1621defm V_CMPX_GE_I16    : VOPCX_Real_gfx11<0x0b6>;
1622defm V_CMPX_LT_U16    : VOPCX_Real_gfx11<0x0b9>;
1623defm V_CMPX_EQ_U16    : VOPCX_Real_gfx11<0x0ba>;
1624defm V_CMPX_LE_U16    : VOPCX_Real_gfx11<0x0bb>;
1625defm V_CMPX_GT_U16    : VOPCX_Real_gfx11<0x0bc>;
1626defm V_CMPX_NE_U16    : VOPCX_Real_gfx11<0x0bd>;
1627defm V_CMPX_GE_U16    : VOPCX_Real_gfx11<0x0be>;
1628defm V_CMPX_F_I32     : VOPCX_Real_gfx11<0x0c0>;
1629defm V_CMPX_LT_I32    : VOPCX_Real_gfx11<0x0c1>;
1630defm V_CMPX_EQ_I32    : VOPCX_Real_gfx11<0x0c2>;
1631defm V_CMPX_LE_I32    : VOPCX_Real_gfx11<0x0c3>;
1632defm V_CMPX_GT_I32    : VOPCX_Real_gfx11<0x0c4>;
1633defm V_CMPX_NE_I32    : VOPCX_Real_gfx11<0x0c5>;
1634defm V_CMPX_GE_I32    : VOPCX_Real_gfx11<0x0c6>;
1635defm V_CMPX_T_I32     : VOPCX_Real_gfx11<0x0c7>;
1636defm V_CMPX_F_U32     : VOPCX_Real_gfx11<0x0c8>;
1637defm V_CMPX_LT_U32    : VOPCX_Real_gfx11<0x0c9>;
1638defm V_CMPX_EQ_U32    : VOPCX_Real_gfx11<0x0ca>;
1639defm V_CMPX_LE_U32    : VOPCX_Real_gfx11<0x0cb>;
1640defm V_CMPX_GT_U32    : VOPCX_Real_gfx11<0x0cc>;
1641defm V_CMPX_NE_U32    : VOPCX_Real_gfx11<0x0cd>;
1642defm V_CMPX_GE_U32    : VOPCX_Real_gfx11<0x0ce>;
1643defm V_CMPX_T_U32     : VOPCX_Real_gfx11<0x0cf>;
1644
1645defm V_CMPX_F_I64     : VOPCX_Real_gfx11<0x0d0>;
1646defm V_CMPX_LT_I64    : VOPCX_Real_gfx11<0x0d1>;
1647defm V_CMPX_EQ_I64    : VOPCX_Real_gfx11<0x0d2>;
1648defm V_CMPX_LE_I64    : VOPCX_Real_gfx11<0x0d3>;
1649defm V_CMPX_GT_I64    : VOPCX_Real_gfx11<0x0d4>;
1650defm V_CMPX_NE_I64    : VOPCX_Real_gfx11<0x0d5>;
1651defm V_CMPX_GE_I64    : VOPCX_Real_gfx11<0x0d6>;
1652defm V_CMPX_T_I64     : VOPCX_Real_gfx11<0x0d7>;
1653defm V_CMPX_F_U64     : VOPCX_Real_gfx11<0x0d8>;
1654defm V_CMPX_LT_U64    : VOPCX_Real_gfx11<0x0d9>;
1655defm V_CMPX_EQ_U64    : VOPCX_Real_gfx11<0x0da>;
1656defm V_CMPX_LE_U64    : VOPCX_Real_gfx11<0x0db>;
1657defm V_CMPX_GT_U64    : VOPCX_Real_gfx11<0x0dc>;
1658defm V_CMPX_NE_U64    : VOPCX_Real_gfx11<0x0dd>;
1659defm V_CMPX_GE_U64    : VOPCX_Real_gfx11<0x0de>;
1660defm V_CMPX_T_U64     : VOPCX_Real_gfx11<0x0df>;
1661defm V_CMPX_CLASS_F16 : VOPCX_Real_gfx11<0x0fd>;
1662defm V_CMPX_CLASS_F32 : VOPCX_Real_gfx11<0x0fe>;
1663defm V_CMPX_CLASS_F64 : VOPCX_Real_gfx11<0x0ff>;
1664
1665//===----------------------------------------------------------------------===//
1666// GFX10.
1667//===----------------------------------------------------------------------===//
1668
1669let AssemblerPredicate = isGFX10Only in {
1670  multiclass VOPC_Real_gfx10<bits<9> op> {
1671    let DecoderNamespace = "GFX10" in {
1672      def _e32_gfx10 :
1673        VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
1674        VOPCe<op{7-0}>;
1675      def _e64_gfx10 :
1676        VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1677        VOP3a_gfx10<{0, op}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1678        // Encoding used for VOPC instructions encoded as VOP3 differs from
1679        // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
1680        bits<8> sdst;
1681        let Inst{7-0} = sdst;
1682      }
1683    } // End DecoderNamespace = "GFX10"
1684
1685    foreach _ = BoolToList<!cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
1686    def _sdwa_gfx10 :
1687      VOP_SDWA10_Real<!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>,
1688      VOPC_SDWA9e<op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1689
1690    defm : VOPCInstAliases<NAME, "gfx10">;
1691  }
1692
1693  multiclass VOPCX_Real_gfx10<bits<9> op> {
1694    let DecoderNamespace = "GFX10" in {
1695      def _e32_gfx10 :
1696        VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_nosdst_e32"), SIEncodingFamily.GFX10>,
1697        VOPCe<op{7-0}> {
1698          let AsmString = !subst("_nosdst", "", !cast<VOPC_Pseudo>(NAME#"_nosdst_e32").PseudoInstr)
1699                          # " " # !cast<VOPC_Pseudo>(NAME#"_nosdst_e32").AsmOperands;
1700        }
1701
1702      def _e64_gfx10 :
1703        VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_nosdst_e64"), SIEncodingFamily.GFX10>,
1704        VOP3a_gfx10<{0, op}, !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").Pfl> {
1705          let Inst{7-0} = ?; // sdst
1706          let AsmString = !subst("_nosdst", "", !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").Mnemonic)
1707                          # "{_e64} " # !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").AsmOperands;
1708        }
1709    } // End DecoderNamespace = "GFX10"
1710
1711    foreach _ = BoolToList<!cast<VOPC_Pseudo>(NAME#"_nosdst_e32").Pfl.HasExtSDWA9>.ret in
1712    def _sdwa_gfx10 :
1713      VOP_SDWA10_Real<!cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa")>,
1714      VOPC_SDWA9e<op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").Pfl> {
1715        let AsmString = !subst("_nosdst", "", !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").Mnemonic)
1716                        # "{_sdwa} " # !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").AsmOperands9;
1717      }
1718
1719    defm : VOPCXInstAliases<NAME, "gfx10">;
1720  }
1721} // End AssemblerPredicate = isGFX10Only
1722
1723defm V_CMP_LT_I16     : VOPC_Real_gfx10<0x089>;
1724defm V_CMP_EQ_I16     : VOPC_Real_gfx10<0x08a>;
1725defm V_CMP_LE_I16     : VOPC_Real_gfx10<0x08b>;
1726defm V_CMP_GT_I16     : VOPC_Real_gfx10<0x08c>;
1727defm V_CMP_NE_I16     : VOPC_Real_gfx10<0x08d>;
1728defm V_CMP_GE_I16     : VOPC_Real_gfx10<0x08e>;
1729defm V_CMP_CLASS_F16  : VOPC_Real_gfx10<0x08f>;
1730defm V_CMPX_LT_I16    : VOPCX_Real_gfx10<0x099>;
1731defm V_CMPX_EQ_I16    : VOPCX_Real_gfx10<0x09a>;
1732defm V_CMPX_LE_I16    : VOPCX_Real_gfx10<0x09b>;
1733defm V_CMPX_GT_I16    : VOPCX_Real_gfx10<0x09c>;
1734defm V_CMPX_NE_I16    : VOPCX_Real_gfx10<0x09d>;
1735defm V_CMPX_GE_I16    : VOPCX_Real_gfx10<0x09e>;
1736defm V_CMPX_CLASS_F16 : VOPCX_Real_gfx10<0x09f>;
1737defm V_CMP_LT_U16     : VOPC_Real_gfx10<0x0a9>;
1738defm V_CMP_EQ_U16     : VOPC_Real_gfx10<0x0aa>;
1739defm V_CMP_LE_U16     : VOPC_Real_gfx10<0x0ab>;
1740defm V_CMP_GT_U16     : VOPC_Real_gfx10<0x0ac>;
1741defm V_CMP_NE_U16     : VOPC_Real_gfx10<0x0ad>;
1742defm V_CMP_GE_U16     : VOPC_Real_gfx10<0x0ae>;
1743defm V_CMPX_LT_U16    : VOPCX_Real_gfx10<0x0b9>;
1744defm V_CMPX_EQ_U16    : VOPCX_Real_gfx10<0x0ba>;
1745defm V_CMPX_LE_U16    : VOPCX_Real_gfx10<0x0bb>;
1746defm V_CMPX_GT_U16    : VOPCX_Real_gfx10<0x0bc>;
1747defm V_CMPX_NE_U16    : VOPCX_Real_gfx10<0x0bd>;
1748defm V_CMPX_GE_U16    : VOPCX_Real_gfx10<0x0be>;
1749defm V_CMP_F_F16      : VOPC_Real_gfx10<0x0c8>;
1750defm V_CMP_LT_F16     : VOPC_Real_gfx10<0x0c9>;
1751defm V_CMP_EQ_F16     : VOPC_Real_gfx10<0x0ca>;
1752defm V_CMP_LE_F16     : VOPC_Real_gfx10<0x0cb>;
1753defm V_CMP_GT_F16     : VOPC_Real_gfx10<0x0cc>;
1754defm V_CMP_LG_F16     : VOPC_Real_gfx10<0x0cd>;
1755defm V_CMP_GE_F16     : VOPC_Real_gfx10<0x0ce>;
1756defm V_CMP_O_F16      : VOPC_Real_gfx10<0x0cf>;
1757defm V_CMPX_F_F16     : VOPCX_Real_gfx10<0x0d8>;
1758defm V_CMPX_LT_F16    : VOPCX_Real_gfx10<0x0d9>;
1759defm V_CMPX_EQ_F16    : VOPCX_Real_gfx10<0x0da>;
1760defm V_CMPX_LE_F16    : VOPCX_Real_gfx10<0x0db>;
1761defm V_CMPX_GT_F16    : VOPCX_Real_gfx10<0x0dc>;
1762defm V_CMPX_LG_F16    : VOPCX_Real_gfx10<0x0dd>;
1763defm V_CMPX_GE_F16    : VOPCX_Real_gfx10<0x0de>;
1764defm V_CMPX_O_F16     : VOPCX_Real_gfx10<0x0df>;
1765defm V_CMP_U_F16      : VOPC_Real_gfx10<0x0e8>;
1766defm V_CMP_NGE_F16    : VOPC_Real_gfx10<0x0e9>;
1767defm V_CMP_NLG_F16    : VOPC_Real_gfx10<0x0ea>;
1768defm V_CMP_NGT_F16    : VOPC_Real_gfx10<0x0eb>;
1769defm V_CMP_NLE_F16    : VOPC_Real_gfx10<0x0ec>;
1770defm V_CMP_NEQ_F16    : VOPC_Real_gfx10<0x0ed>;
1771defm V_CMP_NLT_F16    : VOPC_Real_gfx10<0x0ee>;
1772defm V_CMP_TRU_F16    : VOPC_Real_gfx10<0x0ef>;
1773defm V_CMPX_U_F16     : VOPCX_Real_gfx10<0x0f8>;
1774defm V_CMPX_NGE_F16   : VOPCX_Real_gfx10<0x0f9>;
1775defm V_CMPX_NLG_F16   : VOPCX_Real_gfx10<0x0fa>;
1776defm V_CMPX_NGT_F16   : VOPCX_Real_gfx10<0x0fb>;
1777defm V_CMPX_NLE_F16   : VOPCX_Real_gfx10<0x0fc>;
1778defm V_CMPX_NEQ_F16   : VOPCX_Real_gfx10<0x0fd>;
1779defm V_CMPX_NLT_F16   : VOPCX_Real_gfx10<0x0fe>;
1780defm V_CMPX_TRU_F16   : VOPCX_Real_gfx10<0x0ff>;
1781
1782//===----------------------------------------------------------------------===//
1783// GFX6, GFX7, GFX10.
1784//===----------------------------------------------------------------------===//
1785
1786let AssemblerPredicate = isGFX6GFX7 in {
1787  multiclass VOPC_Real_gfx6_gfx7<bits<9> op> {
1788    let DecoderNamespace = "GFX6GFX7" in {
1789      def _e32_gfx6_gfx7 :
1790        VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
1791        VOPCe<op{7-0}>;
1792      def _e64_gfx6_gfx7 :
1793        VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
1794        VOP3a_gfx6_gfx7<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1795        // Encoding used for VOPC instructions encoded as VOP3 differs from
1796        // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
1797        bits<8> sdst;
1798        let Inst{7-0} = sdst;
1799      }
1800    } // End DecoderNamespace = "GFX6GFX7"
1801
1802    defm : VOPCInstAliases<NAME, "gfx6_gfx7">;
1803  }
1804} // End AssemblerPredicate = isGFX6GFX7
1805
1806multiclass VOPC_Real_gfx6_gfx7_gfx10<bits<9> op> :
1807  VOPC_Real_gfx6_gfx7<op>, VOPC_Real_gfx10<op>;
1808
1809multiclass VOPCX_Real_gfx6_gfx7<bits<9> op> :
1810  VOPC_Real_gfx6_gfx7<op>;
1811
1812multiclass VOPCX_Real_gfx6_gfx7_gfx10 <bits<9> op> :
1813  VOPC_Real_gfx6_gfx7<op>, VOPCX_Real_gfx10<op>;
1814
1815multiclass VOPC_Real_gfx6_gfx7_gfx10_gfx11<bits<9> op> :
1816  VOPC_Real_gfx6_gfx7_gfx10<op>, VOPC_Real_gfx11<op>;
1817
1818multiclass VOPCX_Real_gfx6_gfx7_gfx10_gfx11<bits<9> op> :
1819  VOPCX_Real_gfx6_gfx7_gfx10<op>, VOPCX_Real_gfx11<op>;
1820
1821defm V_CMP_F_F32      : VOPC_Real_gfx6_gfx7_gfx10<0x000>;
1822defm V_CMP_LT_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x001>;
1823defm V_CMP_EQ_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x002>;
1824defm V_CMP_LE_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x003>;
1825defm V_CMP_GT_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x004>;
1826defm V_CMP_LG_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x005>;
1827defm V_CMP_GE_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x006>;
1828defm V_CMP_O_F32      : VOPC_Real_gfx6_gfx7_gfx10<0x007>;
1829defm V_CMP_U_F32      : VOPC_Real_gfx6_gfx7_gfx10<0x008>;
1830defm V_CMP_NGE_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x009>;
1831defm V_CMP_NLG_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00a>;
1832defm V_CMP_NGT_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00b>;
1833defm V_CMP_NLE_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00c>;
1834defm V_CMP_NEQ_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00d>;
1835defm V_CMP_NLT_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00e>;
1836defm V_CMP_TRU_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00f>;
1837defm V_CMPX_F_F32     : VOPCX_Real_gfx6_gfx7_gfx10<0x010>;
1838defm V_CMPX_LT_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x011>;
1839defm V_CMPX_EQ_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x012>;
1840defm V_CMPX_LE_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x013>;
1841defm V_CMPX_GT_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x014>;
1842defm V_CMPX_LG_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x015>;
1843defm V_CMPX_GE_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x016>;
1844defm V_CMPX_O_F32     : VOPCX_Real_gfx6_gfx7_gfx10<0x017>;
1845defm V_CMPX_U_F32     : VOPCX_Real_gfx6_gfx7_gfx10<0x018>;
1846defm V_CMPX_NGE_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x019>;
1847defm V_CMPX_NLG_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01a>;
1848defm V_CMPX_NGT_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01b>;
1849defm V_CMPX_NLE_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01c>;
1850defm V_CMPX_NEQ_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01d>;
1851defm V_CMPX_NLT_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01e>;
1852defm V_CMPX_TRU_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01f>;
1853defm V_CMP_F_F64      : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x020>;
1854defm V_CMP_LT_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x021>;
1855defm V_CMP_EQ_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x022>;
1856defm V_CMP_LE_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x023>;
1857defm V_CMP_GT_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x024>;
1858defm V_CMP_LG_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x025>;
1859defm V_CMP_GE_F64     : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x026>;
1860defm V_CMP_O_F64      : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x027>;
1861defm V_CMP_U_F64      : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x028>;
1862defm V_CMP_NGE_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x029>;
1863defm V_CMP_NLG_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02a>;
1864defm V_CMP_NGT_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02b>;
1865defm V_CMP_NLE_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02c>;
1866defm V_CMP_NEQ_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02d>;
1867defm V_CMP_NLT_F64    : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02e>;
1868defm V_CMP_TRU_F64    : VOPC_Real_gfx6_gfx7_gfx10<0x02f>;
1869defm V_CMPX_F_F64     : VOPCX_Real_gfx6_gfx7_gfx10<0x030>;
1870defm V_CMPX_LT_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x031>;
1871defm V_CMPX_EQ_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x032>;
1872defm V_CMPX_LE_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x033>;
1873defm V_CMPX_GT_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x034>;
1874defm V_CMPX_LG_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x035>;
1875defm V_CMPX_GE_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x036>;
1876defm V_CMPX_O_F64     : VOPCX_Real_gfx6_gfx7_gfx10<0x037>;
1877defm V_CMPX_U_F64     : VOPCX_Real_gfx6_gfx7_gfx10<0x038>;
1878defm V_CMPX_NGE_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x039>;
1879defm V_CMPX_NLG_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03a>;
1880defm V_CMPX_NGT_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03b>;
1881defm V_CMPX_NLE_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03c>;
1882defm V_CMPX_NEQ_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03d>;
1883defm V_CMPX_NLT_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03e>;
1884defm V_CMPX_TRU_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03f>;
1885defm V_CMPS_F_F32     : VOPC_Real_gfx6_gfx7<0x040>;
1886defm V_CMPS_LT_F32    : VOPC_Real_gfx6_gfx7<0x041>;
1887defm V_CMPS_EQ_F32    : VOPC_Real_gfx6_gfx7<0x042>;
1888defm V_CMPS_LE_F32    : VOPC_Real_gfx6_gfx7<0x043>;
1889defm V_CMPS_GT_F32    : VOPC_Real_gfx6_gfx7<0x044>;
1890defm V_CMPS_LG_F32    : VOPC_Real_gfx6_gfx7<0x045>;
1891defm V_CMPS_GE_F32    : VOPC_Real_gfx6_gfx7<0x046>;
1892defm V_CMPS_O_F32     : VOPC_Real_gfx6_gfx7<0x047>;
1893defm V_CMPS_U_F32     : VOPC_Real_gfx6_gfx7<0x048>;
1894defm V_CMPS_NGE_F32   : VOPC_Real_gfx6_gfx7<0x049>;
1895defm V_CMPS_NLG_F32   : VOPC_Real_gfx6_gfx7<0x04a>;
1896defm V_CMPS_NGT_F32   : VOPC_Real_gfx6_gfx7<0x04b>;
1897defm V_CMPS_NLE_F32   : VOPC_Real_gfx6_gfx7<0x04c>;
1898defm V_CMPS_NEQ_F32   : VOPC_Real_gfx6_gfx7<0x04d>;
1899defm V_CMPS_NLT_F32   : VOPC_Real_gfx6_gfx7<0x04e>;
1900defm V_CMPS_TRU_F32   : VOPC_Real_gfx6_gfx7<0x04f>;
1901defm V_CMPSX_F_F32    : VOPCX_Real_gfx6_gfx7<0x050>;
1902defm V_CMPSX_LT_F32   : VOPCX_Real_gfx6_gfx7<0x051>;
1903defm V_CMPSX_EQ_F32   : VOPCX_Real_gfx6_gfx7<0x052>;
1904defm V_CMPSX_LE_F32   : VOPCX_Real_gfx6_gfx7<0x053>;
1905defm V_CMPSX_GT_F32   : VOPCX_Real_gfx6_gfx7<0x054>;
1906defm V_CMPSX_LG_F32   : VOPCX_Real_gfx6_gfx7<0x055>;
1907defm V_CMPSX_GE_F32   : VOPCX_Real_gfx6_gfx7<0x056>;
1908defm V_CMPSX_O_F32    : VOPCX_Real_gfx6_gfx7<0x057>;
1909defm V_CMPSX_U_F32    : VOPCX_Real_gfx6_gfx7<0x058>;
1910defm V_CMPSX_NGE_F32  : VOPCX_Real_gfx6_gfx7<0x059>;
1911defm V_CMPSX_NLG_F32  : VOPCX_Real_gfx6_gfx7<0x05a>;
1912defm V_CMPSX_NGT_F32  : VOPCX_Real_gfx6_gfx7<0x05b>;
1913defm V_CMPSX_NLE_F32  : VOPCX_Real_gfx6_gfx7<0x05c>;
1914defm V_CMPSX_NEQ_F32  : VOPCX_Real_gfx6_gfx7<0x05d>;
1915defm V_CMPSX_NLT_F32  : VOPCX_Real_gfx6_gfx7<0x05e>;
1916defm V_CMPSX_TRU_F32  : VOPCX_Real_gfx6_gfx7<0x05f>;
1917defm V_CMPS_F_F64     : VOPC_Real_gfx6_gfx7<0x060>;
1918defm V_CMPS_LT_F64    : VOPC_Real_gfx6_gfx7<0x061>;
1919defm V_CMPS_EQ_F64    : VOPC_Real_gfx6_gfx7<0x062>;
1920defm V_CMPS_LE_F64    : VOPC_Real_gfx6_gfx7<0x063>;
1921defm V_CMPS_GT_F64    : VOPC_Real_gfx6_gfx7<0x064>;
1922defm V_CMPS_LG_F64    : VOPC_Real_gfx6_gfx7<0x065>;
1923defm V_CMPS_GE_F64    : VOPC_Real_gfx6_gfx7<0x066>;
1924defm V_CMPS_O_F64     : VOPC_Real_gfx6_gfx7<0x067>;
1925defm V_CMPS_U_F64     : VOPC_Real_gfx6_gfx7<0x068>;
1926defm V_CMPS_NGE_F64   : VOPC_Real_gfx6_gfx7<0x069>;
1927defm V_CMPS_NLG_F64   : VOPC_Real_gfx6_gfx7<0x06a>;
1928defm V_CMPS_NGT_F64   : VOPC_Real_gfx6_gfx7<0x06b>;
1929defm V_CMPS_NLE_F64   : VOPC_Real_gfx6_gfx7<0x06c>;
1930defm V_CMPS_NEQ_F64   : VOPC_Real_gfx6_gfx7<0x06d>;
1931defm V_CMPS_NLT_F64   : VOPC_Real_gfx6_gfx7<0x06e>;
1932defm V_CMPS_TRU_F64   : VOPC_Real_gfx6_gfx7<0x06f>;
1933defm V_CMPSX_F_F64    : VOPCX_Real_gfx6_gfx7<0x070>;
1934defm V_CMPSX_LT_F64   : VOPCX_Real_gfx6_gfx7<0x071>;
1935defm V_CMPSX_EQ_F64   : VOPCX_Real_gfx6_gfx7<0x072>;
1936defm V_CMPSX_LE_F64   : VOPCX_Real_gfx6_gfx7<0x073>;
1937defm V_CMPSX_GT_F64   : VOPCX_Real_gfx6_gfx7<0x074>;
1938defm V_CMPSX_LG_F64   : VOPCX_Real_gfx6_gfx7<0x075>;
1939defm V_CMPSX_GE_F64   : VOPCX_Real_gfx6_gfx7<0x076>;
1940defm V_CMPSX_O_F64    : VOPCX_Real_gfx6_gfx7<0x077>;
1941defm V_CMPSX_U_F64    : VOPCX_Real_gfx6_gfx7<0x078>;
1942defm V_CMPSX_NGE_F64  : VOPCX_Real_gfx6_gfx7<0x079>;
1943defm V_CMPSX_NLG_F64  : VOPCX_Real_gfx6_gfx7<0x07a>;
1944defm V_CMPSX_NGT_F64  : VOPCX_Real_gfx6_gfx7<0x07b>;
1945defm V_CMPSX_NLE_F64  : VOPCX_Real_gfx6_gfx7<0x07c>;
1946defm V_CMPSX_NEQ_F64  : VOPCX_Real_gfx6_gfx7<0x07d>;
1947defm V_CMPSX_NLT_F64  : VOPCX_Real_gfx6_gfx7<0x07e>;
1948defm V_CMPSX_TRU_F64  : VOPCX_Real_gfx6_gfx7<0x07f>;
1949defm V_CMP_F_I32      : VOPC_Real_gfx6_gfx7_gfx10<0x080>;
1950defm V_CMP_LT_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x081>;
1951defm V_CMP_EQ_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x082>;
1952defm V_CMP_LE_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x083>;
1953defm V_CMP_GT_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x084>;
1954defm V_CMP_NE_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x085>;
1955defm V_CMP_GE_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x086>;
1956defm V_CMP_T_I32      : VOPC_Real_gfx6_gfx7_gfx10<0x087>;
1957defm V_CMP_CLASS_F32  : VOPC_Real_gfx6_gfx7_gfx10<0x088>;
1958defm V_CMPX_F_I32     : VOPCX_Real_gfx6_gfx7_gfx10<0x090>;
1959defm V_CMPX_LT_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x091>;
1960defm V_CMPX_EQ_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x092>;
1961defm V_CMPX_LE_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x093>;
1962defm V_CMPX_GT_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x094>;
1963defm V_CMPX_NE_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x095>;
1964defm V_CMPX_GE_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x096>;
1965defm V_CMPX_T_I32     : VOPCX_Real_gfx6_gfx7_gfx10<0x097>;
1966defm V_CMPX_CLASS_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x098>;
1967defm V_CMP_F_I64      : VOPC_Real_gfx6_gfx7_gfx10<0x0a0>;
1968defm V_CMP_LT_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a1>;
1969defm V_CMP_EQ_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a2>;
1970defm V_CMP_LE_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a3>;
1971defm V_CMP_GT_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a4>;
1972defm V_CMP_NE_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a5>;
1973defm V_CMP_GE_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a6>;
1974defm V_CMP_T_I64      : VOPC_Real_gfx6_gfx7_gfx10<0x0a7>;
1975defm V_CMP_CLASS_F64  : VOPC_Real_gfx6_gfx7_gfx10<0x0a8>;
1976defm V_CMPX_F_I64     : VOPCX_Real_gfx6_gfx7_gfx10<0x0b0>;
1977defm V_CMPX_LT_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b1>;
1978defm V_CMPX_EQ_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b2>;
1979defm V_CMPX_LE_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b3>;
1980defm V_CMPX_GT_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b4>;
1981defm V_CMPX_NE_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b5>;
1982defm V_CMPX_GE_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b6>;
1983defm V_CMPX_T_I64     : VOPCX_Real_gfx6_gfx7_gfx10<0x0b7>;
1984defm V_CMPX_CLASS_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b8>;
1985defm V_CMP_F_U32      : VOPC_Real_gfx6_gfx7_gfx10<0x0c0>;
1986defm V_CMP_LT_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c1>;
1987defm V_CMP_EQ_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c2>;
1988defm V_CMP_LE_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c3>;
1989defm V_CMP_GT_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c4>;
1990defm V_CMP_NE_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c5>;
1991defm V_CMP_GE_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c6>;
1992defm V_CMP_T_U32      : VOPC_Real_gfx6_gfx7_gfx10<0x0c7>;
1993defm V_CMPX_F_U32     : VOPCX_Real_gfx6_gfx7_gfx10<0x0d0>;
1994defm V_CMPX_LT_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d1>;
1995defm V_CMPX_EQ_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d2>;
1996defm V_CMPX_LE_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d3>;
1997defm V_CMPX_GT_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d4>;
1998defm V_CMPX_NE_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d5>;
1999defm V_CMPX_GE_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d6>;
2000defm V_CMPX_T_U32     : VOPCX_Real_gfx6_gfx7_gfx10<0x0d7>;
2001defm V_CMP_F_U64      : VOPC_Real_gfx6_gfx7_gfx10<0x0e0>;
2002defm V_CMP_LT_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e1>;
2003defm V_CMP_EQ_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e2>;
2004defm V_CMP_LE_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e3>;
2005defm V_CMP_GT_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e4>;
2006defm V_CMP_NE_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e5>;
2007defm V_CMP_GE_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e6>;
2008defm V_CMP_T_U64      : VOPC_Real_gfx6_gfx7_gfx10<0x0e7>;
2009defm V_CMPX_F_U64     : VOPCX_Real_gfx6_gfx7_gfx10<0x0f0>;
2010defm V_CMPX_LT_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f1>;
2011defm V_CMPX_EQ_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f2>;
2012defm V_CMPX_LE_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f3>;
2013defm V_CMPX_GT_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f4>;
2014defm V_CMPX_NE_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f5>;
2015defm V_CMPX_GE_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f6>;
2016defm V_CMPX_T_U64     : VOPCX_Real_gfx6_gfx7_gfx10<0x0f7>;
2017
2018//===----------------------------------------------------------------------===//
2019// GFX8, GFX9 (VI).
2020//===----------------------------------------------------------------------===//
2021
2022multiclass VOPC_Real_vi <bits<10> op> {
2023  let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
2024    def _e32_vi :
2025      VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
2026      VOPCe<op{7-0}>;
2027
2028    def _e64_vi :
2029      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
2030      VOP3a_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
2031      // Encoding used for VOPC instructions encoded as VOP3
2032      // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
2033      bits<8> sdst;
2034      let Inst{7-0} = sdst;
2035    }
2036  }
2037
2038  foreach _ = BoolToList<!cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA>.ret in
2039  def _sdwa_vi :
2040    VOP_SDWA_Real <!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>,
2041    VOPC_SDWAe <op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
2042
2043  foreach _ = BoolToList<!cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
2044  def _sdwa_gfx9 :
2045    VOP_SDWA9_Real <!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>,
2046    VOPC_SDWA9e <op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
2047
2048  let AssemblerPredicate = isGFX8GFX9 in {
2049    defm : VOPCInstAliases<NAME, "vi">;
2050  }
2051}
2052
2053defm V_CMP_CLASS_F32  : VOPC_Real_vi <0x10>;
2054defm V_CMPX_CLASS_F32 : VOPC_Real_vi <0x11>;
2055defm V_CMP_CLASS_F64  : VOPC_Real_vi <0x12>;
2056defm V_CMPX_CLASS_F64 : VOPC_Real_vi <0x13>;
2057defm V_CMP_CLASS_F16  : VOPC_Real_vi <0x14>;
2058defm V_CMPX_CLASS_F16 : VOPC_Real_vi <0x15>;
2059
2060defm V_CMP_F_F16      : VOPC_Real_vi <0x20>;
2061defm V_CMP_LT_F16     : VOPC_Real_vi <0x21>;
2062defm V_CMP_EQ_F16     : VOPC_Real_vi <0x22>;
2063defm V_CMP_LE_F16     : VOPC_Real_vi <0x23>;
2064defm V_CMP_GT_F16     : VOPC_Real_vi <0x24>;
2065defm V_CMP_LG_F16     : VOPC_Real_vi <0x25>;
2066defm V_CMP_GE_F16     : VOPC_Real_vi <0x26>;
2067defm V_CMP_O_F16      : VOPC_Real_vi <0x27>;
2068defm V_CMP_U_F16      : VOPC_Real_vi <0x28>;
2069defm V_CMP_NGE_F16    : VOPC_Real_vi <0x29>;
2070defm V_CMP_NLG_F16    : VOPC_Real_vi <0x2a>;
2071defm V_CMP_NGT_F16    : VOPC_Real_vi <0x2b>;
2072defm V_CMP_NLE_F16    : VOPC_Real_vi <0x2c>;
2073defm V_CMP_NEQ_F16    : VOPC_Real_vi <0x2d>;
2074defm V_CMP_NLT_F16    : VOPC_Real_vi <0x2e>;
2075defm V_CMP_TRU_F16    : VOPC_Real_vi <0x2f>;
2076
2077defm V_CMPX_F_F16     : VOPC_Real_vi <0x30>;
2078defm V_CMPX_LT_F16    : VOPC_Real_vi <0x31>;
2079defm V_CMPX_EQ_F16    : VOPC_Real_vi <0x32>;
2080defm V_CMPX_LE_F16    : VOPC_Real_vi <0x33>;
2081defm V_CMPX_GT_F16    : VOPC_Real_vi <0x34>;
2082defm V_CMPX_LG_F16    : VOPC_Real_vi <0x35>;
2083defm V_CMPX_GE_F16    : VOPC_Real_vi <0x36>;
2084defm V_CMPX_O_F16     : VOPC_Real_vi <0x37>;
2085defm V_CMPX_U_F16     : VOPC_Real_vi <0x38>;
2086defm V_CMPX_NGE_F16   : VOPC_Real_vi <0x39>;
2087defm V_CMPX_NLG_F16   : VOPC_Real_vi <0x3a>;
2088defm V_CMPX_NGT_F16   : VOPC_Real_vi <0x3b>;
2089defm V_CMPX_NLE_F16   : VOPC_Real_vi <0x3c>;
2090defm V_CMPX_NEQ_F16   : VOPC_Real_vi <0x3d>;
2091defm V_CMPX_NLT_F16   : VOPC_Real_vi <0x3e>;
2092defm V_CMPX_TRU_F16   : VOPC_Real_vi <0x3f>;
2093
2094defm V_CMP_F_F32      : VOPC_Real_vi <0x40>;
2095defm V_CMP_LT_F32     : VOPC_Real_vi <0x41>;
2096defm V_CMP_EQ_F32     : VOPC_Real_vi <0x42>;
2097defm V_CMP_LE_F32     : VOPC_Real_vi <0x43>;
2098defm V_CMP_GT_F32     : VOPC_Real_vi <0x44>;
2099defm V_CMP_LG_F32     : VOPC_Real_vi <0x45>;
2100defm V_CMP_GE_F32     : VOPC_Real_vi <0x46>;
2101defm V_CMP_O_F32      : VOPC_Real_vi <0x47>;
2102defm V_CMP_U_F32      : VOPC_Real_vi <0x48>;
2103defm V_CMP_NGE_F32    : VOPC_Real_vi <0x49>;
2104defm V_CMP_NLG_F32    : VOPC_Real_vi <0x4a>;
2105defm V_CMP_NGT_F32    : VOPC_Real_vi <0x4b>;
2106defm V_CMP_NLE_F32    : VOPC_Real_vi <0x4c>;
2107defm V_CMP_NEQ_F32    : VOPC_Real_vi <0x4d>;
2108defm V_CMP_NLT_F32    : VOPC_Real_vi <0x4e>;
2109defm V_CMP_TRU_F32    : VOPC_Real_vi <0x4f>;
2110
2111defm V_CMPX_F_F32     : VOPC_Real_vi <0x50>;
2112defm V_CMPX_LT_F32    : VOPC_Real_vi <0x51>;
2113defm V_CMPX_EQ_F32    : VOPC_Real_vi <0x52>;
2114defm V_CMPX_LE_F32    : VOPC_Real_vi <0x53>;
2115defm V_CMPX_GT_F32    : VOPC_Real_vi <0x54>;
2116defm V_CMPX_LG_F32    : VOPC_Real_vi <0x55>;
2117defm V_CMPX_GE_F32    : VOPC_Real_vi <0x56>;
2118defm V_CMPX_O_F32     : VOPC_Real_vi <0x57>;
2119defm V_CMPX_U_F32     : VOPC_Real_vi <0x58>;
2120defm V_CMPX_NGE_F32   : VOPC_Real_vi <0x59>;
2121defm V_CMPX_NLG_F32   : VOPC_Real_vi <0x5a>;
2122defm V_CMPX_NGT_F32   : VOPC_Real_vi <0x5b>;
2123defm V_CMPX_NLE_F32   : VOPC_Real_vi <0x5c>;
2124defm V_CMPX_NEQ_F32   : VOPC_Real_vi <0x5d>;
2125defm V_CMPX_NLT_F32   : VOPC_Real_vi <0x5e>;
2126defm V_CMPX_TRU_F32   : VOPC_Real_vi <0x5f>;
2127
2128defm V_CMP_F_F64      : VOPC_Real_vi <0x60>;
2129defm V_CMP_LT_F64     : VOPC_Real_vi <0x61>;
2130defm V_CMP_EQ_F64     : VOPC_Real_vi <0x62>;
2131defm V_CMP_LE_F64     : VOPC_Real_vi <0x63>;
2132defm V_CMP_GT_F64     : VOPC_Real_vi <0x64>;
2133defm V_CMP_LG_F64     : VOPC_Real_vi <0x65>;
2134defm V_CMP_GE_F64     : VOPC_Real_vi <0x66>;
2135defm V_CMP_O_F64      : VOPC_Real_vi <0x67>;
2136defm V_CMP_U_F64      : VOPC_Real_vi <0x68>;
2137defm V_CMP_NGE_F64    : VOPC_Real_vi <0x69>;
2138defm V_CMP_NLG_F64    : VOPC_Real_vi <0x6a>;
2139defm V_CMP_NGT_F64    : VOPC_Real_vi <0x6b>;
2140defm V_CMP_NLE_F64    : VOPC_Real_vi <0x6c>;
2141defm V_CMP_NEQ_F64    : VOPC_Real_vi <0x6d>;
2142defm V_CMP_NLT_F64    : VOPC_Real_vi <0x6e>;
2143defm V_CMP_TRU_F64    : VOPC_Real_vi <0x6f>;
2144
2145defm V_CMPX_F_F64     : VOPC_Real_vi <0x70>;
2146defm V_CMPX_LT_F64    : VOPC_Real_vi <0x71>;
2147defm V_CMPX_EQ_F64    : VOPC_Real_vi <0x72>;
2148defm V_CMPX_LE_F64    : VOPC_Real_vi <0x73>;
2149defm V_CMPX_GT_F64    : VOPC_Real_vi <0x74>;
2150defm V_CMPX_LG_F64    : VOPC_Real_vi <0x75>;
2151defm V_CMPX_GE_F64    : VOPC_Real_vi <0x76>;
2152defm V_CMPX_O_F64     : VOPC_Real_vi <0x77>;
2153defm V_CMPX_U_F64     : VOPC_Real_vi <0x78>;
2154defm V_CMPX_NGE_F64   : VOPC_Real_vi <0x79>;
2155defm V_CMPX_NLG_F64   : VOPC_Real_vi <0x7a>;
2156defm V_CMPX_NGT_F64   : VOPC_Real_vi <0x7b>;
2157defm V_CMPX_NLE_F64   : VOPC_Real_vi <0x7c>;
2158defm V_CMPX_NEQ_F64   : VOPC_Real_vi <0x7d>;
2159defm V_CMPX_NLT_F64   : VOPC_Real_vi <0x7e>;
2160defm V_CMPX_TRU_F64   : VOPC_Real_vi <0x7f>;
2161
2162defm V_CMP_F_I16      : VOPC_Real_vi <0xa0>;
2163defm V_CMP_LT_I16     : VOPC_Real_vi <0xa1>;
2164defm V_CMP_EQ_I16     : VOPC_Real_vi <0xa2>;
2165defm V_CMP_LE_I16     : VOPC_Real_vi <0xa3>;
2166defm V_CMP_GT_I16     : VOPC_Real_vi <0xa4>;
2167defm V_CMP_NE_I16     : VOPC_Real_vi <0xa5>;
2168defm V_CMP_GE_I16     : VOPC_Real_vi <0xa6>;
2169defm V_CMP_T_I16      : VOPC_Real_vi <0xa7>;
2170
2171defm V_CMP_F_U16      : VOPC_Real_vi <0xa8>;
2172defm V_CMP_LT_U16     : VOPC_Real_vi <0xa9>;
2173defm V_CMP_EQ_U16     : VOPC_Real_vi <0xaa>;
2174defm V_CMP_LE_U16     : VOPC_Real_vi <0xab>;
2175defm V_CMP_GT_U16     : VOPC_Real_vi <0xac>;
2176defm V_CMP_NE_U16     : VOPC_Real_vi <0xad>;
2177defm V_CMP_GE_U16     : VOPC_Real_vi <0xae>;
2178defm V_CMP_T_U16      : VOPC_Real_vi <0xaf>;
2179
2180defm V_CMPX_F_I16 : VOPC_Real_vi <0xb0>;
2181defm V_CMPX_LT_I16 : VOPC_Real_vi <0xb1>;
2182defm V_CMPX_EQ_I16 : VOPC_Real_vi <0xb2>;
2183defm V_CMPX_LE_I16 : VOPC_Real_vi <0xb3>;
2184defm V_CMPX_GT_I16 : VOPC_Real_vi <0xb4>;
2185defm V_CMPX_NE_I16 : VOPC_Real_vi <0xb5>;
2186defm V_CMPX_GE_I16 : VOPC_Real_vi <0xb6>;
2187defm V_CMPX_T_I16 : VOPC_Real_vi <0xb7>;
2188
2189defm V_CMPX_F_U16 : VOPC_Real_vi <0xb8>;
2190defm V_CMPX_LT_U16 : VOPC_Real_vi <0xb9>;
2191defm V_CMPX_EQ_U16 : VOPC_Real_vi <0xba>;
2192defm V_CMPX_LE_U16 : VOPC_Real_vi <0xbb>;
2193defm V_CMPX_GT_U16 : VOPC_Real_vi <0xbc>;
2194defm V_CMPX_NE_U16 : VOPC_Real_vi <0xbd>;
2195defm V_CMPX_GE_U16 : VOPC_Real_vi <0xbe>;
2196defm V_CMPX_T_U16 : VOPC_Real_vi <0xbf>;
2197
2198defm V_CMP_F_I32      : VOPC_Real_vi <0xc0>;
2199defm V_CMP_LT_I32     : VOPC_Real_vi <0xc1>;
2200defm V_CMP_EQ_I32     : VOPC_Real_vi <0xc2>;
2201defm V_CMP_LE_I32     : VOPC_Real_vi <0xc3>;
2202defm V_CMP_GT_I32     : VOPC_Real_vi <0xc4>;
2203defm V_CMP_NE_I32     : VOPC_Real_vi <0xc5>;
2204defm V_CMP_GE_I32     : VOPC_Real_vi <0xc6>;
2205defm V_CMP_T_I32      : VOPC_Real_vi <0xc7>;
2206
2207defm V_CMPX_F_I32     : VOPC_Real_vi <0xd0>;
2208defm V_CMPX_LT_I32    : VOPC_Real_vi <0xd1>;
2209defm V_CMPX_EQ_I32    : VOPC_Real_vi <0xd2>;
2210defm V_CMPX_LE_I32    : VOPC_Real_vi <0xd3>;
2211defm V_CMPX_GT_I32    : VOPC_Real_vi <0xd4>;
2212defm V_CMPX_NE_I32    : VOPC_Real_vi <0xd5>;
2213defm V_CMPX_GE_I32    : VOPC_Real_vi <0xd6>;
2214defm V_CMPX_T_I32     : VOPC_Real_vi <0xd7>;
2215
2216defm V_CMP_F_I64      : VOPC_Real_vi <0xe0>;
2217defm V_CMP_LT_I64     : VOPC_Real_vi <0xe1>;
2218defm V_CMP_EQ_I64     : VOPC_Real_vi <0xe2>;
2219defm V_CMP_LE_I64     : VOPC_Real_vi <0xe3>;
2220defm V_CMP_GT_I64     : VOPC_Real_vi <0xe4>;
2221defm V_CMP_NE_I64     : VOPC_Real_vi <0xe5>;
2222defm V_CMP_GE_I64     : VOPC_Real_vi <0xe6>;
2223defm V_CMP_T_I64      : VOPC_Real_vi <0xe7>;
2224
2225defm V_CMPX_F_I64     : VOPC_Real_vi <0xf0>;
2226defm V_CMPX_LT_I64    : VOPC_Real_vi <0xf1>;
2227defm V_CMPX_EQ_I64    : VOPC_Real_vi <0xf2>;
2228defm V_CMPX_LE_I64    : VOPC_Real_vi <0xf3>;
2229defm V_CMPX_GT_I64    : VOPC_Real_vi <0xf4>;
2230defm V_CMPX_NE_I64    : VOPC_Real_vi <0xf5>;
2231defm V_CMPX_GE_I64    : VOPC_Real_vi <0xf6>;
2232defm V_CMPX_T_I64     : VOPC_Real_vi <0xf7>;
2233
2234defm V_CMP_F_U32      : VOPC_Real_vi <0xc8>;
2235defm V_CMP_LT_U32     : VOPC_Real_vi <0xc9>;
2236defm V_CMP_EQ_U32     : VOPC_Real_vi <0xca>;
2237defm V_CMP_LE_U32     : VOPC_Real_vi <0xcb>;
2238defm V_CMP_GT_U32     : VOPC_Real_vi <0xcc>;
2239defm V_CMP_NE_U32     : VOPC_Real_vi <0xcd>;
2240defm V_CMP_GE_U32     : VOPC_Real_vi <0xce>;
2241defm V_CMP_T_U32      : VOPC_Real_vi <0xcf>;
2242
2243defm V_CMPX_F_U32     : VOPC_Real_vi <0xd8>;
2244defm V_CMPX_LT_U32    : VOPC_Real_vi <0xd9>;
2245defm V_CMPX_EQ_U32    : VOPC_Real_vi <0xda>;
2246defm V_CMPX_LE_U32    : VOPC_Real_vi <0xdb>;
2247defm V_CMPX_GT_U32    : VOPC_Real_vi <0xdc>;
2248defm V_CMPX_NE_U32    : VOPC_Real_vi <0xdd>;
2249defm V_CMPX_GE_U32    : VOPC_Real_vi <0xde>;
2250defm V_CMPX_T_U32     : VOPC_Real_vi <0xdf>;
2251
2252defm V_CMP_F_U64      : VOPC_Real_vi <0xe8>;
2253defm V_CMP_LT_U64     : VOPC_Real_vi <0xe9>;
2254defm V_CMP_EQ_U64     : VOPC_Real_vi <0xea>;
2255defm V_CMP_LE_U64     : VOPC_Real_vi <0xeb>;
2256defm V_CMP_GT_U64     : VOPC_Real_vi <0xec>;
2257defm V_CMP_NE_U64     : VOPC_Real_vi <0xed>;
2258defm V_CMP_GE_U64     : VOPC_Real_vi <0xee>;
2259defm V_CMP_T_U64      : VOPC_Real_vi <0xef>;
2260
2261defm V_CMPX_F_U64     : VOPC_Real_vi <0xf8>;
2262defm V_CMPX_LT_U64    : VOPC_Real_vi <0xf9>;
2263defm V_CMPX_EQ_U64    : VOPC_Real_vi <0xfa>;
2264defm V_CMPX_LE_U64    : VOPC_Real_vi <0xfb>;
2265defm V_CMPX_GT_U64    : VOPC_Real_vi <0xfc>;
2266defm V_CMPX_NE_U64    : VOPC_Real_vi <0xfd>;
2267defm V_CMPX_GE_U64    : VOPC_Real_vi <0xfe>;
2268defm V_CMPX_T_U64     : VOPC_Real_vi <0xff>;
2269