1//===-- VOPCInstructions.td - Vector Instruction Definitions --------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Encodings 11//===----------------------------------------------------------------------===// 12 13class VOPCe <bits<8> op> : Enc32 { 14 bits<9> src0; 15 bits<8> src1; 16 17 let Inst{8-0} = src0; 18 let Inst{16-9} = src1; 19 let Inst{24-17} = op; 20 let Inst{31-25} = 0x3e; 21} 22 23class VOPC_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAe <P> { 24 bits<8> src1; 25 26 let Inst{8-0} = 0xf9; // sdwa 27 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 28 let Inst{24-17} = op; 29 let Inst{31-25} = 0x3e; // encoding 30} 31 32class VOPC_SDWA9e <bits<8> op, VOPProfile P> : VOP_SDWA9Be <P> { 33 bits<9> src1; 34 35 let Inst{8-0} = 0xf9; // sdwa 36 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 37 let Inst{24-17} = op; 38 let Inst{31-25} = 0x3e; // encoding 39 let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr 40} 41 42 43//===----------------------------------------------------------------------===// 44// VOPC classes 45//===----------------------------------------------------------------------===// 46 47// VOPC instructions are a special case because for the 32-bit 48// encoding, we want to display the implicit vcc write as if it were 49// an explicit $dst. 50class VOPC_Profile<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> : 51 VOPProfile <[i1, vt0, vt1, untyped]> { 52 // We want to exclude instructions with 64bit operands 53 let HasExtDPP = getHasVOP3DPP<DstVT, Src0VT, Src1VT, Src2VT>.ret; 54 let Asm32 = "$src0, $src1"; 55 56 let AsmDPP = !if (HasModifiers, 57 "$src0_modifiers, $src1_modifiers " 58 "$dpp_ctrl$row_mask$bank_mask$bound_ctrl", 59 "$src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl"); 60 let AsmDPP8 = "$src0, $src1 $dpp8$fi"; 61 let AsmDPP16 = AsmDPP#"$fi"; 62 // VOPC DPP Instructions do not need an old operand 63 let TieRegDPP = ""; 64 let InsDPP = getInsDPP<VOPDstOperand<Src0DPP>, Src0DPP, Src1DPP, Src2DPP, 65 NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP, 66 Src2ModDPP, 0/*HasOld*/>.ret; 67 let InsDPP16 = getInsDPP16<VOPDstOperand<Src0DPP>, Src0DPP, Src1DPP, Src2DPP, 68 NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP, 69 Src2ModDPP, 0/*HasOld*/>.ret; 70 let InsDPP8 = getInsDPP8<VOPDstOperand<Src0DPP>, Src0DPP, Src1DPP, Src2DPP, 71 NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP, 72 Src2ModDPP, 0/*HasOld*/>.ret; 73 74 // The destination for 32-bit encoding is implicit. 75 let HasDst32 = 0; 76 // VOPC disallows dst_sel and dst_unused as they have no effect on destination 77 let EmitDstSel = 0; 78 let Outs64 = (outs VOPDstS64orS32:$sdst); 79 let OutsVOP3DPP = Outs64; 80 let OutsVOP3DPP8 = Outs64; 81 let InsVOP3DPP = getInsVOP3DPP<InsVOP3Base, Src0VOP3DPP, NumSrcArgs, 0/*HasOld*/>.ret; 82 let InsVOP3DPP16 = getInsVOP3DPP16<InsVOP3Base, Src0VOP3DPP, NumSrcArgs, 0/*HasOld*/>.ret; 83 let InsVOP3DPP8 = getInsVOP3DPP8<InsVOP3Base, Src0VOP3DPP, NumSrcArgs, 0/*HasOld*/>.ret; 84 list<SchedReadWrite> Schedule = sched; 85} 86 87multiclass VOPC_Profile_t16<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> { 88 def NAME : VOPC_Profile<sched, vt0, vt1>; 89 def _t16 : VOPC_Profile<sched, vt0, vt1> { 90 let IsTrue16 = 1; 91 let Src1RC32 = RegisterOperand<getVregSrcForVT_t16<Src1VT>.ret>; 92 let Src0DPP = getVregSrcForVT_t16<Src0VT>.ret; 93 let Src1DPP = getVregSrcForVT_t16<Src1VT>.ret; 94 let Src2DPP = getVregSrcForVT_t16<Src2VT>.ret; 95 let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret; 96 let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret; 97 let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret; 98 } 99} 100 101class VOPC_NoSdst_Profile<list<SchedReadWrite> sched, ValueType vt0, 102 ValueType vt1 = vt0> : 103 VOPC_Profile<sched, vt0, vt1> { 104 let Outs64 = (outs ); 105 let OutsVOP3DPP = Outs64; 106 let OutsVOP3DPP8 = Outs64; 107 let OutsSDWA = (outs ); 108 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 109 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 110 src0_sel:$src0_sel, src1_sel:$src1_sel); 111 let AsmVOP3Base = !if(isFloatType<Src0VT>.ret, "$src0_modifiers, $src1_modifiers$clamp", 112 "$src0, $src1"); 113 let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel"; 114 let EmitDst = 0; 115} 116 117multiclass VOPC_NoSdst_Profile_t16<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> { 118 def NAME : VOPC_NoSdst_Profile<sched, vt0, vt1>; 119 def _t16 : VOPC_NoSdst_Profile<sched, vt0, vt1> { 120 let IsTrue16 = 1; 121 let Src1RC32 = RegisterOperand<getVregSrcForVT_t16<Src1VT>.ret>; 122 let Src0DPP = getVregSrcForVT_t16<Src0VT>.ret; 123 let Src1DPP = getVregSrcForVT_t16<Src1VT>.ret; 124 let Src2DPP = getVregSrcForVT_t16<Src2VT>.ret; 125 let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret; 126 let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret; 127 let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret; 128 } 129} 130 131class VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[], 132 bit DefVcc = 1> : 133 InstSI<(outs), P.Ins32, "", pattern>, 134 VOP <opName>, 135 SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> { 136 137 let isPseudo = 1; 138 let isCodeGenOnly = 1; 139 let UseNamedOperandTable = 1; 140 141 string Mnemonic = opName; 142 string AsmOperands = P.Asm32; 143 144 let Size = 4; 145 let mayLoad = 0; 146 let mayStore = 0; 147 let hasSideEffects = 0; 148 149 let ReadsModeReg = isFloatType<P.Src0VT>.ret; 150 151 let VALU = 1; 152 let VOPC = 1; 153 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 154 let Defs = !if(DefVcc, [VCC], []); 155 156 VOPProfile Pfl = P; 157} 158 159class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily, string asm_name = ps.PseudoInstr> : 160 InstSI <ps.OutOperandList, ps.InOperandList, asm_name # " " # ps.AsmOperands, []>, 161 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 162 163 let VALU = 1; 164 let VOPC = 1; 165 let isPseudo = 0; 166 let isCodeGenOnly = 0; 167 168 let Constraints = ps.Constraints; 169 let DisableEncoding = ps.DisableEncoding; 170 171 // copy relevant pseudo op flags 172 let SubtargetPredicate = ps.SubtargetPredicate; 173 let AsmMatchConverter = ps.AsmMatchConverter; 174 let Constraints = ps.Constraints; 175 let DisableEncoding = ps.DisableEncoding; 176 let TSFlags = ps.TSFlags; 177 let UseNamedOperandTable = ps.UseNamedOperandTable; 178 let Uses = ps.Uses; 179 let Defs = ps.Defs; 180 let SchedRW = ps.SchedRW; 181 let mayLoad = ps.mayLoad; 182 let mayStore = ps.mayStore; 183} 184 185class VOPC_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 186 VOP_SDWA_Pseudo <OpName, P, pattern> { 187 let AsmMatchConverter = "cvtSdwaVOPC"; 188} 189 190// This class is used only with VOPC instructions. Use $sdst for out operand 191class VOPCInstAlias <VOP3_Pseudo ps, Instruction inst, 192 string Asm32 = ps.Pfl.Asm32, string real_name = ps.OpName, 193 VOPProfile p = ps.Pfl> : 194 InstAlias <real_name#" "#Asm32, (inst)>, PredicateControl { 195 196 field bit isCompare; 197 field bit isCommutable; 198 199 let ResultInst = 200 !if (p.HasDst32, 201 !if (!eq(p.NumSrcArgs, 0), 202 // 1 dst, 0 src 203 (inst p.DstRC:$sdst), 204 !if (!eq(p.NumSrcArgs, 1), 205 // 1 dst, 1 src 206 (inst p.DstRC:$sdst, p.Src0RC32:$src0), 207 !if (!eq(p.NumSrcArgs, 2), 208 // 1 dst, 2 src 209 (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1), 210 // else - unreachable 211 (inst)))), 212 // else 213 !if (!eq(p.NumSrcArgs, 2), 214 // 0 dst, 2 src 215 (inst p.Src0RC32:$src0, p.Src1RC32:$src1), 216 !if (!eq(p.NumSrcArgs, 1), 217 // 0 dst, 1 src 218 (inst p.Src0RC32:$src1), 219 // else 220 // 0 dst, 0 src 221 (inst)))); 222 223 let AsmVariantName = AMDGPUAsmVariants.Default; 224 let SubtargetPredicate = AssemblerPredicate; 225} 226 227multiclass VOPCInstAliases <string old_name, string Arch, string real_name = old_name, string mnemonic_from = real_name> { 228 def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"), 229 !cast<Instruction>(real_name#"_e32_"#Arch), 230 !cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32, 231 mnemonic_from>; 232 let WaveSizePredicate = isWave32 in { 233 def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"), 234 !cast<Instruction>(real_name#"_e32_"#Arch), 235 "vcc_lo, "#!cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32, 236 mnemonic_from>; 237 } 238 let WaveSizePredicate = isWave64 in { 239 def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"), 240 !cast<Instruction>(real_name#"_e32_"#Arch), 241 "vcc, "#!cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32, 242 mnemonic_from>; 243 } 244} 245 246multiclass VOPCXInstAliases <string old_name, string Arch, string real_name = old_name, string mnemonic_from = real_name> { 247 def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"), 248 !cast<Instruction>(real_name#"_e32_"#Arch), 249 !cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32, 250 mnemonic_from>; 251} 252 253class getVOPCPat64 <SDPatternOperator cond, VOPProfile P> : LetDummies { 254 list<dag> ret = !if(P.HasModifiers, 255 [(set i1:$sdst, 256 (setcc (P.Src0VT 257 !if(P.HasOMod, 258 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 259 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))), 260 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), 261 cond))], 262 [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]); 263} 264 265class VCMPXNoSDstTable <bit has_sdst, string Name> { 266 bit HasSDst = has_sdst; 267 string NoSDstOp = Name; 268} 269 270class VCMPVCMPXTable <string Name> { 271 bit IsVCMPX = 0; 272 string VCMPOp = Name; 273} 274 275multiclass VOPC_Pseudos <string opName, 276 VOPC_Profile P, 277 SDPatternOperator cond = COND_NULL, 278 string revOp = opName, 279 bit DefExec = 0> { 280 281 def _e32 : VOPC_Pseudo <opName, P>, 282 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>, 283 VCMPXNoSDstTable<1, opName#"_e32">, 284 VCMPVCMPXTable<opName#"_e32"> { 285 let Defs = !if(DefExec, [VCC, EXEC], [VCC]); 286 let SchedRW = P.Schedule; 287 let isConvergent = DefExec; 288 let isCompare = 1; 289 let isCommutable = 1; 290 } 291 292 def _e64 : VOP3_Pseudo<opName, P, getVOPCPat64<cond, P>.ret>, 293 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>, 294 VCMPXNoSDstTable<1, opName#"_e64">, 295 VCMPVCMPXTable<opName#"_e64"> { 296 let Defs = !if(DefExec, [EXEC], []); 297 let SchedRW = P.Schedule; 298 let isCompare = 1; 299 let isCommutable = 1; 300 } 301 302 if P.HasExtSDWA then 303 def _sdwa : VOPC_SDWA_Pseudo <opName, P> { 304 let Defs = !if(DefExec, [EXEC], []); 305 let SchedRW = P.Schedule; 306 let isConvergent = DefExec; 307 let isCompare = 1; 308 } 309 310 let SubtargetPredicate = isGFX11Plus in { 311 if P.HasExtDPP then 312 def _e32_dpp : VOP_DPP_Pseudo<opName, P> { 313 let Defs = !if(DefExec, [VCC, EXEC], [VCC]); 314 let SchedRW = P.Schedule; 315 let isConvergent = DefExec; 316 let isCompare = 1; 317 let VOPC = 1; 318 let Constraints = ""; 319 } 320 if P.HasExtVOP3DPP then 321 def _e64_dpp : VOP3_DPP_Pseudo<opName, P> { 322 let Defs = !if(DefExec, [EXEC], []); 323 let SchedRW = P.Schedule; 324 let isCompare = 1; 325 let Constraints = ""; 326 } 327 } // end SubtargetPredicate = isGFX11Plus 328 329} 330 331let SubtargetPredicate = HasSdstCMPX in { 332multiclass VOPCX_Pseudos <string opName, 333 VOPC_Profile P, VOPC_Profile P_NoSDst, 334 SDPatternOperator cond = COND_NULL, 335 string revOp = opName> : 336 VOPC_Pseudos <opName, P, cond, revOp, 1> { 337 338 def _nosdst_e32 : VOPC_Pseudo <opName#"_nosdst", P_NoSDst, [], 0>, 339 Commutable_REV<revOp#"_nosdst_e32", !eq(revOp, opName)>, 340 VCMPXNoSDstTable<0, opName#"_e32">, 341 VCMPVCMPXTable<!subst("v_cmpx", "v_cmp", opName#"_e32")> { 342 let Defs = [EXEC]; 343 let SchedRW = P_NoSDst.Schedule; 344 let isConvergent = 1; 345 let isCompare = 1; 346 let isCommutable = 1; 347 let SubtargetPredicate = HasNoSdstCMPX; 348 let IsVCMPX = 1; 349 } 350 351 def _nosdst_e64 : VOP3_Pseudo<opName#"_nosdst", P_NoSDst>, 352 Commutable_REV<revOp#"_nosdst_e64", !eq(revOp, opName)>, 353 VCMPXNoSDstTable<0, opName#"_e64">, 354 VCMPVCMPXTable<!subst("v_cmpx", "v_cmp", opName#"_e64")> { 355 let Defs = [EXEC]; 356 let SchedRW = P_NoSDst.Schedule; 357 let isCompare = 1; 358 let isCommutable = 1; 359 let SubtargetPredicate = HasNoSdstCMPX; 360 let IsVCMPX = 1; 361 } 362 363 if P_NoSDst.HasExtSDWA then 364 def _nosdst_sdwa : VOPC_SDWA_Pseudo <opName#"_nosdst", P_NoSDst> { 365 let Defs = [EXEC]; 366 let SchedRW = P_NoSDst.Schedule; 367 let isConvergent = 1; 368 let isCompare = 1; 369 let SubtargetPredicate = HasNoSdstCMPX; 370 } 371 372 let SubtargetPredicate = isGFX11Plus in { 373 if P.HasExtDPP then 374 def _nosdst_e32_dpp : VOP_DPP_Pseudo<opName#"_nosdst", P_NoSDst> { 375 let Defs = [EXEC]; 376 let SchedRW = P_NoSDst.Schedule; 377 let isConvergent = 1; 378 let isCompare = 1; 379 let VOPC = 1; 380 let Constraints = ""; 381 } 382 if P.HasExtVOP3DPP then 383 def _nosdst_e64_dpp : VOP3_DPP_Pseudo<opName#"_nosdst", P_NoSDst> { 384 let Defs = [EXEC]; 385 let SchedRW = P_NoSDst.Schedule; 386 let isCompare = 1; 387 let Constraints = ""; 388 } 389 } // end SubtargetPredicate = isGFX11Plus 390} 391} // End SubtargetPredicate = HasSdstCMPX 392 393defm VOPC_I1_F16_F16 : VOPC_Profile_t16<[Write32Bit], f16>; 394def VOPC_I1_F32_F32 : VOPC_Profile<[Write32Bit], f32>; 395def VOPC_I1_F64_F64 : VOPC_Profile<[WriteDoubleAdd], f64>; 396defm VOPC_I1_I16_I16 : VOPC_Profile_t16<[Write32Bit], i16>; 397def VOPC_I1_I32_I32 : VOPC_Profile<[Write32Bit], i32>; 398def VOPC_I1_I64_I64 : VOPC_Profile<[Write64Bit], i64>; 399 400defm VOPC_F16_F16 : VOPC_NoSdst_Profile_t16<[Write32Bit], f16>; 401def VOPC_F32_F32 : VOPC_NoSdst_Profile<[Write32Bit], f32>; 402def VOPC_F64_F64 : VOPC_NoSdst_Profile<[Write64Bit], f64>; 403defm VOPC_I16_I16 : VOPC_NoSdst_Profile_t16<[Write32Bit], i16>; 404def VOPC_I32_I32 : VOPC_NoSdst_Profile<[Write32Bit], i32>; 405def VOPC_I64_I64 : VOPC_NoSdst_Profile<[Write64Bit], i64>; 406 407multiclass VOPC_F16 <string opName, SDPatternOperator cond = COND_NULL, 408 string revOp = opName> { 409 let OtherPredicates = [NotHasTrue16BitInsts, Has16BitInsts] in { 410 defm NAME : VOPC_Pseudos <opName, VOPC_I1_F16_F16, cond, revOp, 0>; 411 } 412 let OtherPredicates = [HasTrue16BitInsts] in { 413 defm _t16 : VOPC_Pseudos <opName#"_t16", VOPC_I1_F16_F16_t16, cond, revOp#"_t16", 0>; 414 } 415} 416 417multiclass VOPC_F32 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> : 418 VOPC_Pseudos <opName, VOPC_I1_F32_F32, cond, revOp, 0>; 419 420multiclass VOPC_F64 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> : 421 VOPC_Pseudos <opName, VOPC_I1_F64_F64, cond, revOp, 0>; 422 423multiclass VOPC_I16 <string opName, SDPatternOperator cond = COND_NULL, 424 string revOp = opName> { 425 let OtherPredicates = [NotHasTrue16BitInsts, Has16BitInsts] in { 426 defm NAME : VOPC_Pseudos <opName, VOPC_I1_I16_I16, cond, revOp, 0>; 427 } 428 let OtherPredicates = [HasTrue16BitInsts] in { 429 defm _t16 : VOPC_Pseudos <opName#"_t16", VOPC_I1_I16_I16_t16, cond, revOp#"_t16", 0>; 430 } 431} 432 433multiclass VOPC_I32 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> : 434 VOPC_Pseudos <opName, VOPC_I1_I32_I32, cond, revOp, 0>; 435 436multiclass VOPC_I64 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> : 437 VOPC_Pseudos <opName, VOPC_I1_I64_I64, cond, revOp, 0>; 438 439multiclass VOPCX_F16<string opName, string revOp = opName> { 440 let OtherPredicates = [NotHasTrue16BitInsts, Has16BitInsts] in { 441 defm NAME : VOPCX_Pseudos <opName, VOPC_I1_F16_F16, VOPC_F16_F16, COND_NULL, revOp>; 442 } 443 let OtherPredicates = [HasTrue16BitInsts] in { 444 defm _t16 : VOPCX_Pseudos <opName#"_t16", VOPC_I1_F16_F16_t16, VOPC_F16_F16_t16, COND_NULL, revOp#"_t16">; 445 } 446} 447 448multiclass VOPCX_F32 <string opName, string revOp = opName> : 449 VOPCX_Pseudos <opName, VOPC_I1_F32_F32, VOPC_F32_F32, COND_NULL, revOp>; 450 451multiclass VOPCX_F64 <string opName, string revOp = opName> : 452 VOPCX_Pseudos <opName, VOPC_I1_F64_F64, VOPC_F64_F64, COND_NULL, revOp>; 453 454multiclass VOPCX_I16<string opName, string revOp = opName> { 455 let OtherPredicates = [NotHasTrue16BitInsts, Has16BitInsts] in { 456 defm NAME : VOPCX_Pseudos <opName, VOPC_I1_I16_I16, VOPC_I16_I16, COND_NULL, revOp>; 457 } 458 let OtherPredicates = [HasTrue16BitInsts] in { 459 defm _t16 : VOPCX_Pseudos <opName#"_t16", VOPC_I1_I16_I16_t16, VOPC_I16_I16_t16, COND_NULL, revOp#"_t16">; 460 } 461} 462 463multiclass VOPCX_I32 <string opName, string revOp = opName> : 464 VOPCX_Pseudos <opName, VOPC_I1_I32_I32, VOPC_I32_I32, COND_NULL, revOp>; 465 466multiclass VOPCX_I64 <string opName, string revOp = opName> : 467 VOPCX_Pseudos <opName, VOPC_I1_I64_I64, VOPC_I64_I64, COND_NULL, revOp>; 468 469 470//===----------------------------------------------------------------------===// 471// Compare instructions 472//===----------------------------------------------------------------------===// 473 474defm V_CMP_F_F32 : VOPC_F32 <"v_cmp_f_f32">; 475defm V_CMP_LT_F32 : VOPC_F32 <"v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">; 476defm V_CMP_EQ_F32 : VOPC_F32 <"v_cmp_eq_f32", COND_OEQ>; 477defm V_CMP_LE_F32 : VOPC_F32 <"v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">; 478defm V_CMP_GT_F32 : VOPC_F32 <"v_cmp_gt_f32", COND_OGT>; 479defm V_CMP_LG_F32 : VOPC_F32 <"v_cmp_lg_f32", COND_ONE>; 480defm V_CMP_GE_F32 : VOPC_F32 <"v_cmp_ge_f32", COND_OGE>; 481defm V_CMP_O_F32 : VOPC_F32 <"v_cmp_o_f32", COND_O>; 482defm V_CMP_U_F32 : VOPC_F32 <"v_cmp_u_f32", COND_UO>; 483defm V_CMP_NGE_F32 : VOPC_F32 <"v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">; 484defm V_CMP_NLG_F32 : VOPC_F32 <"v_cmp_nlg_f32", COND_UEQ>; 485defm V_CMP_NGT_F32 : VOPC_F32 <"v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">; 486defm V_CMP_NLE_F32 : VOPC_F32 <"v_cmp_nle_f32", COND_UGT>; 487defm V_CMP_NEQ_F32 : VOPC_F32 <"v_cmp_neq_f32", COND_UNE>; 488defm V_CMP_NLT_F32 : VOPC_F32 <"v_cmp_nlt_f32", COND_UGE>; 489defm V_CMP_TRU_F32 : VOPC_F32 <"v_cmp_tru_f32">; 490 491defm V_CMPX_F_F32 : VOPCX_F32 <"v_cmpx_f_f32">; 492defm V_CMPX_LT_F32 : VOPCX_F32 <"v_cmpx_lt_f32", "v_cmpx_gt_f32">; 493defm V_CMPX_EQ_F32 : VOPCX_F32 <"v_cmpx_eq_f32">; 494defm V_CMPX_LE_F32 : VOPCX_F32 <"v_cmpx_le_f32", "v_cmpx_ge_f32">; 495defm V_CMPX_GT_F32 : VOPCX_F32 <"v_cmpx_gt_f32">; 496defm V_CMPX_LG_F32 : VOPCX_F32 <"v_cmpx_lg_f32">; 497defm V_CMPX_GE_F32 : VOPCX_F32 <"v_cmpx_ge_f32">; 498defm V_CMPX_O_F32 : VOPCX_F32 <"v_cmpx_o_f32">; 499defm V_CMPX_U_F32 : VOPCX_F32 <"v_cmpx_u_f32">; 500defm V_CMPX_NGE_F32 : VOPCX_F32 <"v_cmpx_nge_f32", "v_cmpx_nle_f32">; 501defm V_CMPX_NLG_F32 : VOPCX_F32 <"v_cmpx_nlg_f32">; 502defm V_CMPX_NGT_F32 : VOPCX_F32 <"v_cmpx_ngt_f32", "v_cmpx_nlt_f32">; 503defm V_CMPX_NLE_F32 : VOPCX_F32 <"v_cmpx_nle_f32">; 504defm V_CMPX_NEQ_F32 : VOPCX_F32 <"v_cmpx_neq_f32">; 505defm V_CMPX_NLT_F32 : VOPCX_F32 <"v_cmpx_nlt_f32">; 506defm V_CMPX_TRU_F32 : VOPCX_F32 <"v_cmpx_tru_f32">; 507 508defm V_CMP_F_F64 : VOPC_F64 <"v_cmp_f_f64">; 509defm V_CMP_LT_F64 : VOPC_F64 <"v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">; 510defm V_CMP_EQ_F64 : VOPC_F64 <"v_cmp_eq_f64", COND_OEQ>; 511defm V_CMP_LE_F64 : VOPC_F64 <"v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">; 512defm V_CMP_GT_F64 : VOPC_F64 <"v_cmp_gt_f64", COND_OGT>; 513defm V_CMP_LG_F64 : VOPC_F64 <"v_cmp_lg_f64", COND_ONE>; 514defm V_CMP_GE_F64 : VOPC_F64 <"v_cmp_ge_f64", COND_OGE>; 515defm V_CMP_O_F64 : VOPC_F64 <"v_cmp_o_f64", COND_O>; 516defm V_CMP_U_F64 : VOPC_F64 <"v_cmp_u_f64", COND_UO>; 517defm V_CMP_NGE_F64 : VOPC_F64 <"v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">; 518defm V_CMP_NLG_F64 : VOPC_F64 <"v_cmp_nlg_f64", COND_UEQ>; 519defm V_CMP_NGT_F64 : VOPC_F64 <"v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">; 520defm V_CMP_NLE_F64 : VOPC_F64 <"v_cmp_nle_f64", COND_UGT>; 521defm V_CMP_NEQ_F64 : VOPC_F64 <"v_cmp_neq_f64", COND_UNE>; 522defm V_CMP_NLT_F64 : VOPC_F64 <"v_cmp_nlt_f64", COND_UGE>; 523defm V_CMP_TRU_F64 : VOPC_F64 <"v_cmp_tru_f64">; 524 525defm V_CMPX_F_F64 : VOPCX_F64 <"v_cmpx_f_f64">; 526defm V_CMPX_LT_F64 : VOPCX_F64 <"v_cmpx_lt_f64", "v_cmpx_gt_f64">; 527defm V_CMPX_EQ_F64 : VOPCX_F64 <"v_cmpx_eq_f64">; 528defm V_CMPX_LE_F64 : VOPCX_F64 <"v_cmpx_le_f64", "v_cmpx_ge_f64">; 529defm V_CMPX_GT_F64 : VOPCX_F64 <"v_cmpx_gt_f64">; 530defm V_CMPX_LG_F64 : VOPCX_F64 <"v_cmpx_lg_f64">; 531defm V_CMPX_GE_F64 : VOPCX_F64 <"v_cmpx_ge_f64">; 532defm V_CMPX_O_F64 : VOPCX_F64 <"v_cmpx_o_f64">; 533defm V_CMPX_U_F64 : VOPCX_F64 <"v_cmpx_u_f64">; 534defm V_CMPX_NGE_F64 : VOPCX_F64 <"v_cmpx_nge_f64", "v_cmpx_nle_f64">; 535defm V_CMPX_NLG_F64 : VOPCX_F64 <"v_cmpx_nlg_f64">; 536defm V_CMPX_NGT_F64 : VOPCX_F64 <"v_cmpx_ngt_f64", "v_cmpx_nlt_f64">; 537defm V_CMPX_NLE_F64 : VOPCX_F64 <"v_cmpx_nle_f64">; 538defm V_CMPX_NEQ_F64 : VOPCX_F64 <"v_cmpx_neq_f64">; 539defm V_CMPX_NLT_F64 : VOPCX_F64 <"v_cmpx_nlt_f64">; 540defm V_CMPX_TRU_F64 : VOPCX_F64 <"v_cmpx_tru_f64">; 541 542let SubtargetPredicate = isGFX6GFX7 in { 543 544defm V_CMPS_F_F32 : VOPC_F32 <"v_cmps_f_f32">; 545defm V_CMPS_LT_F32 : VOPC_F32 <"v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">; 546defm V_CMPS_EQ_F32 : VOPC_F32 <"v_cmps_eq_f32">; 547defm V_CMPS_LE_F32 : VOPC_F32 <"v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">; 548defm V_CMPS_GT_F32 : VOPC_F32 <"v_cmps_gt_f32">; 549defm V_CMPS_LG_F32 : VOPC_F32 <"v_cmps_lg_f32">; 550defm V_CMPS_GE_F32 : VOPC_F32 <"v_cmps_ge_f32">; 551defm V_CMPS_O_F32 : VOPC_F32 <"v_cmps_o_f32">; 552defm V_CMPS_U_F32 : VOPC_F32 <"v_cmps_u_f32">; 553defm V_CMPS_NGE_F32 : VOPC_F32 <"v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">; 554defm V_CMPS_NLG_F32 : VOPC_F32 <"v_cmps_nlg_f32">; 555defm V_CMPS_NGT_F32 : VOPC_F32 <"v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">; 556defm V_CMPS_NLE_F32 : VOPC_F32 <"v_cmps_nle_f32">; 557defm V_CMPS_NEQ_F32 : VOPC_F32 <"v_cmps_neq_f32">; 558defm V_CMPS_NLT_F32 : VOPC_F32 <"v_cmps_nlt_f32">; 559defm V_CMPS_TRU_F32 : VOPC_F32 <"v_cmps_tru_f32">; 560 561defm V_CMPSX_F_F32 : VOPCX_F32 <"v_cmpsx_f_f32">; 562defm V_CMPSX_LT_F32 : VOPCX_F32 <"v_cmpsx_lt_f32", "v_cmpsx_gt_f32">; 563defm V_CMPSX_EQ_F32 : VOPCX_F32 <"v_cmpsx_eq_f32">; 564defm V_CMPSX_LE_F32 : VOPCX_F32 <"v_cmpsx_le_f32", "v_cmpsx_ge_f32">; 565defm V_CMPSX_GT_F32 : VOPCX_F32 <"v_cmpsx_gt_f32">; 566defm V_CMPSX_LG_F32 : VOPCX_F32 <"v_cmpsx_lg_f32">; 567defm V_CMPSX_GE_F32 : VOPCX_F32 <"v_cmpsx_ge_f32">; 568defm V_CMPSX_O_F32 : VOPCX_F32 <"v_cmpsx_o_f32">; 569defm V_CMPSX_U_F32 : VOPCX_F32 <"v_cmpsx_u_f32">; 570defm V_CMPSX_NGE_F32 : VOPCX_F32 <"v_cmpsx_nge_f32", "v_cmpsx_nle_f32">; 571defm V_CMPSX_NLG_F32 : VOPCX_F32 <"v_cmpsx_nlg_f32">; 572defm V_CMPSX_NGT_F32 : VOPCX_F32 <"v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">; 573defm V_CMPSX_NLE_F32 : VOPCX_F32 <"v_cmpsx_nle_f32">; 574defm V_CMPSX_NEQ_F32 : VOPCX_F32 <"v_cmpsx_neq_f32">; 575defm V_CMPSX_NLT_F32 : VOPCX_F32 <"v_cmpsx_nlt_f32">; 576defm V_CMPSX_TRU_F32 : VOPCX_F32 <"v_cmpsx_tru_f32">; 577 578defm V_CMPS_F_F64 : VOPC_F64 <"v_cmps_f_f64">; 579defm V_CMPS_LT_F64 : VOPC_F64 <"v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">; 580defm V_CMPS_EQ_F64 : VOPC_F64 <"v_cmps_eq_f64">; 581defm V_CMPS_LE_F64 : VOPC_F64 <"v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">; 582defm V_CMPS_GT_F64 : VOPC_F64 <"v_cmps_gt_f64">; 583defm V_CMPS_LG_F64 : VOPC_F64 <"v_cmps_lg_f64">; 584defm V_CMPS_GE_F64 : VOPC_F64 <"v_cmps_ge_f64">; 585defm V_CMPS_O_F64 : VOPC_F64 <"v_cmps_o_f64">; 586defm V_CMPS_U_F64 : VOPC_F64 <"v_cmps_u_f64">; 587defm V_CMPS_NGE_F64 : VOPC_F64 <"v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">; 588defm V_CMPS_NLG_F64 : VOPC_F64 <"v_cmps_nlg_f64">; 589defm V_CMPS_NGT_F64 : VOPC_F64 <"v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">; 590defm V_CMPS_NLE_F64 : VOPC_F64 <"v_cmps_nle_f64">; 591defm V_CMPS_NEQ_F64 : VOPC_F64 <"v_cmps_neq_f64">; 592defm V_CMPS_NLT_F64 : VOPC_F64 <"v_cmps_nlt_f64">; 593defm V_CMPS_TRU_F64 : VOPC_F64 <"v_cmps_tru_f64">; 594 595defm V_CMPSX_F_F64 : VOPCX_F64 <"v_cmpsx_f_f64">; 596defm V_CMPSX_LT_F64 : VOPCX_F64 <"v_cmpsx_lt_f64", "v_cmpsx_gt_f64">; 597defm V_CMPSX_EQ_F64 : VOPCX_F64 <"v_cmpsx_eq_f64">; 598defm V_CMPSX_LE_F64 : VOPCX_F64 <"v_cmpsx_le_f64", "v_cmpsx_ge_f64">; 599defm V_CMPSX_GT_F64 : VOPCX_F64 <"v_cmpsx_gt_f64">; 600defm V_CMPSX_LG_F64 : VOPCX_F64 <"v_cmpsx_lg_f64">; 601defm V_CMPSX_GE_F64 : VOPCX_F64 <"v_cmpsx_ge_f64">; 602defm V_CMPSX_O_F64 : VOPCX_F64 <"v_cmpsx_o_f64">; 603defm V_CMPSX_U_F64 : VOPCX_F64 <"v_cmpsx_u_f64">; 604defm V_CMPSX_NGE_F64 : VOPCX_F64 <"v_cmpsx_nge_f64", "v_cmpsx_nle_f64">; 605defm V_CMPSX_NLG_F64 : VOPCX_F64 <"v_cmpsx_nlg_f64">; 606defm V_CMPSX_NGT_F64 : VOPCX_F64 <"v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">; 607defm V_CMPSX_NLE_F64 : VOPCX_F64 <"v_cmpsx_nle_f64">; 608defm V_CMPSX_NEQ_F64 : VOPCX_F64 <"v_cmpsx_neq_f64">; 609defm V_CMPSX_NLT_F64 : VOPCX_F64 <"v_cmpsx_nlt_f64">; 610defm V_CMPSX_TRU_F64 : VOPCX_F64 <"v_cmpsx_tru_f64">; 611 612} // End SubtargetPredicate = isGFX6GFX7 613 614let SubtargetPredicate = Has16BitInsts in { 615 616defm V_CMP_F_F16 : VOPC_F16 <"v_cmp_f_f16">; 617defm V_CMP_LT_F16 : VOPC_F16 <"v_cmp_lt_f16", COND_OLT, "v_cmp_gt_f16">; 618defm V_CMP_EQ_F16 : VOPC_F16 <"v_cmp_eq_f16", COND_OEQ>; 619defm V_CMP_LE_F16 : VOPC_F16 <"v_cmp_le_f16", COND_OLE, "v_cmp_ge_f16">; 620defm V_CMP_GT_F16 : VOPC_F16 <"v_cmp_gt_f16", COND_OGT>; 621defm V_CMP_LG_F16 : VOPC_F16 <"v_cmp_lg_f16", COND_ONE>; 622defm V_CMP_GE_F16 : VOPC_F16 <"v_cmp_ge_f16", COND_OGE>; 623defm V_CMP_O_F16 : VOPC_F16 <"v_cmp_o_f16", COND_O>; 624defm V_CMP_U_F16 : VOPC_F16 <"v_cmp_u_f16", COND_UO>; 625defm V_CMP_NGE_F16 : VOPC_F16 <"v_cmp_nge_f16", COND_ULT, "v_cmp_nle_f16">; 626defm V_CMP_NLG_F16 : VOPC_F16 <"v_cmp_nlg_f16", COND_UEQ>; 627defm V_CMP_NGT_F16 : VOPC_F16 <"v_cmp_ngt_f16", COND_ULE, "v_cmp_nlt_f16">; 628defm V_CMP_NLE_F16 : VOPC_F16 <"v_cmp_nle_f16", COND_UGT>; 629defm V_CMP_NEQ_F16 : VOPC_F16 <"v_cmp_neq_f16", COND_UNE>; 630defm V_CMP_NLT_F16 : VOPC_F16 <"v_cmp_nlt_f16", COND_UGE>; 631defm V_CMP_TRU_F16 : VOPC_F16 <"v_cmp_tru_f16">; 632 633defm V_CMPX_F_F16 : VOPCX_F16 <"v_cmpx_f_f16">; 634defm V_CMPX_LT_F16 : VOPCX_F16 <"v_cmpx_lt_f16", "v_cmpx_gt_f16">; 635defm V_CMPX_EQ_F16 : VOPCX_F16 <"v_cmpx_eq_f16">; 636defm V_CMPX_LE_F16 : VOPCX_F16 <"v_cmpx_le_f16", "v_cmpx_ge_f16">; 637defm V_CMPX_GT_F16 : VOPCX_F16 <"v_cmpx_gt_f16">; 638defm V_CMPX_LG_F16 : VOPCX_F16 <"v_cmpx_lg_f16">; 639defm V_CMPX_GE_F16 : VOPCX_F16 <"v_cmpx_ge_f16">; 640defm V_CMPX_O_F16 : VOPCX_F16 <"v_cmpx_o_f16">; 641defm V_CMPX_U_F16 : VOPCX_F16 <"v_cmpx_u_f16">; 642defm V_CMPX_NGE_F16 : VOPCX_F16 <"v_cmpx_nge_f16", "v_cmpx_nle_f16">; 643defm V_CMPX_NLG_F16 : VOPCX_F16 <"v_cmpx_nlg_f16">; 644defm V_CMPX_NGT_F16 : VOPCX_F16 <"v_cmpx_ngt_f16", "v_cmpx_nlt_f16">; 645defm V_CMPX_NLE_F16 : VOPCX_F16 <"v_cmpx_nle_f16">; 646defm V_CMPX_NEQ_F16 : VOPCX_F16 <"v_cmpx_neq_f16">; 647defm V_CMPX_NLT_F16 : VOPCX_F16 <"v_cmpx_nlt_f16">; 648defm V_CMPX_TRU_F16 : VOPCX_F16 <"v_cmpx_tru_f16">; 649 650defm V_CMP_F_I16 : VOPC_I16 <"v_cmp_f_i16">; 651defm V_CMP_LT_I16 : VOPC_I16 <"v_cmp_lt_i16", COND_SLT, "v_cmp_gt_i16">; 652defm V_CMP_EQ_I16 : VOPC_I16 <"v_cmp_eq_i16">; 653defm V_CMP_LE_I16 : VOPC_I16 <"v_cmp_le_i16", COND_SLE, "v_cmp_ge_i16">; 654defm V_CMP_GT_I16 : VOPC_I16 <"v_cmp_gt_i16", COND_SGT>; 655defm V_CMP_NE_I16 : VOPC_I16 <"v_cmp_ne_i16">; 656defm V_CMP_GE_I16 : VOPC_I16 <"v_cmp_ge_i16", COND_SGE>; 657defm V_CMP_T_I16 : VOPC_I16 <"v_cmp_t_i16">; 658 659defm V_CMP_F_U16 : VOPC_I16 <"v_cmp_f_u16">; 660defm V_CMP_LT_U16 : VOPC_I16 <"v_cmp_lt_u16", COND_ULT, "v_cmp_gt_u16">; 661defm V_CMP_EQ_U16 : VOPC_I16 <"v_cmp_eq_u16", COND_EQ>; 662defm V_CMP_LE_U16 : VOPC_I16 <"v_cmp_le_u16", COND_ULE, "v_cmp_ge_u16">; 663defm V_CMP_GT_U16 : VOPC_I16 <"v_cmp_gt_u16", COND_UGT>; 664defm V_CMP_NE_U16 : VOPC_I16 <"v_cmp_ne_u16", COND_NE>; 665defm V_CMP_GE_U16 : VOPC_I16 <"v_cmp_ge_u16", COND_UGE>; 666defm V_CMP_T_U16 : VOPC_I16 <"v_cmp_t_u16">; 667 668defm V_CMPX_F_I16 : VOPCX_I16 <"v_cmpx_f_i16">; 669defm V_CMPX_LT_I16 : VOPCX_I16 <"v_cmpx_lt_i16", "v_cmpx_gt_i16">; 670defm V_CMPX_EQ_I16 : VOPCX_I16 <"v_cmpx_eq_i16">; 671defm V_CMPX_LE_I16 : VOPCX_I16 <"v_cmpx_le_i16", "v_cmpx_ge_i16">; 672defm V_CMPX_GT_I16 : VOPCX_I16 <"v_cmpx_gt_i16">; 673defm V_CMPX_NE_I16 : VOPCX_I16 <"v_cmpx_ne_i16">; 674defm V_CMPX_GE_I16 : VOPCX_I16 <"v_cmpx_ge_i16">; 675defm V_CMPX_T_I16 : VOPCX_I16 <"v_cmpx_t_i16">; 676 677defm V_CMPX_F_U16 : VOPCX_I16 <"v_cmpx_f_u16">; 678defm V_CMPX_LT_U16 : VOPCX_I16 <"v_cmpx_lt_u16", "v_cmpx_gt_u16">; 679defm V_CMPX_EQ_U16 : VOPCX_I16 <"v_cmpx_eq_u16">; 680defm V_CMPX_LE_U16 : VOPCX_I16 <"v_cmpx_le_u16", "v_cmpx_ge_u16">; 681defm V_CMPX_GT_U16 : VOPCX_I16 <"v_cmpx_gt_u16">; 682defm V_CMPX_NE_U16 : VOPCX_I16 <"v_cmpx_ne_u16">; 683defm V_CMPX_GE_U16 : VOPCX_I16 <"v_cmpx_ge_u16">; 684defm V_CMPX_T_U16 : VOPCX_I16 <"v_cmpx_t_u16">; 685 686} // End SubtargetPredicate = Has16BitInsts 687 688defm V_CMP_F_I32 : VOPC_I32 <"v_cmp_f_i32">; 689defm V_CMP_LT_I32 : VOPC_I32 <"v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">; 690defm V_CMP_EQ_I32 : VOPC_I32 <"v_cmp_eq_i32">; 691defm V_CMP_LE_I32 : VOPC_I32 <"v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">; 692defm V_CMP_GT_I32 : VOPC_I32 <"v_cmp_gt_i32", COND_SGT>; 693defm V_CMP_NE_I32 : VOPC_I32 <"v_cmp_ne_i32">; 694defm V_CMP_GE_I32 : VOPC_I32 <"v_cmp_ge_i32", COND_SGE>; 695defm V_CMP_T_I32 : VOPC_I32 <"v_cmp_t_i32">; 696 697defm V_CMPX_F_I32 : VOPCX_I32 <"v_cmpx_f_i32">; 698defm V_CMPX_LT_I32 : VOPCX_I32 <"v_cmpx_lt_i32", "v_cmpx_gt_i32">; 699defm V_CMPX_EQ_I32 : VOPCX_I32 <"v_cmpx_eq_i32">; 700defm V_CMPX_LE_I32 : VOPCX_I32 <"v_cmpx_le_i32", "v_cmpx_ge_i32">; 701defm V_CMPX_GT_I32 : VOPCX_I32 <"v_cmpx_gt_i32">; 702defm V_CMPX_NE_I32 : VOPCX_I32 <"v_cmpx_ne_i32">; 703defm V_CMPX_GE_I32 : VOPCX_I32 <"v_cmpx_ge_i32">; 704defm V_CMPX_T_I32 : VOPCX_I32 <"v_cmpx_t_i32">; 705 706defm V_CMP_F_I64 : VOPC_I64 <"v_cmp_f_i64">; 707defm V_CMP_LT_I64 : VOPC_I64 <"v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">; 708defm V_CMP_EQ_I64 : VOPC_I64 <"v_cmp_eq_i64">; 709defm V_CMP_LE_I64 : VOPC_I64 <"v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">; 710defm V_CMP_GT_I64 : VOPC_I64 <"v_cmp_gt_i64", COND_SGT>; 711defm V_CMP_NE_I64 : VOPC_I64 <"v_cmp_ne_i64">; 712defm V_CMP_GE_I64 : VOPC_I64 <"v_cmp_ge_i64", COND_SGE>; 713defm V_CMP_T_I64 : VOPC_I64 <"v_cmp_t_i64">; 714 715defm V_CMPX_F_I64 : VOPCX_I64 <"v_cmpx_f_i64">; 716defm V_CMPX_LT_I64 : VOPCX_I64 <"v_cmpx_lt_i64", "v_cmpx_gt_i64">; 717defm V_CMPX_EQ_I64 : VOPCX_I64 <"v_cmpx_eq_i64">; 718defm V_CMPX_LE_I64 : VOPCX_I64 <"v_cmpx_le_i64", "v_cmpx_ge_i64">; 719defm V_CMPX_GT_I64 : VOPCX_I64 <"v_cmpx_gt_i64">; 720defm V_CMPX_NE_I64 : VOPCX_I64 <"v_cmpx_ne_i64">; 721defm V_CMPX_GE_I64 : VOPCX_I64 <"v_cmpx_ge_i64">; 722defm V_CMPX_T_I64 : VOPCX_I64 <"v_cmpx_t_i64">; 723 724defm V_CMP_F_U32 : VOPC_I32 <"v_cmp_f_u32">; 725defm V_CMP_LT_U32 : VOPC_I32 <"v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">; 726defm V_CMP_EQ_U32 : VOPC_I32 <"v_cmp_eq_u32", COND_EQ>; 727defm V_CMP_LE_U32 : VOPC_I32 <"v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">; 728defm V_CMP_GT_U32 : VOPC_I32 <"v_cmp_gt_u32", COND_UGT>; 729defm V_CMP_NE_U32 : VOPC_I32 <"v_cmp_ne_u32", COND_NE>; 730defm V_CMP_GE_U32 : VOPC_I32 <"v_cmp_ge_u32", COND_UGE>; 731defm V_CMP_T_U32 : VOPC_I32 <"v_cmp_t_u32">; 732 733defm V_CMPX_F_U32 : VOPCX_I32 <"v_cmpx_f_u32">; 734defm V_CMPX_LT_U32 : VOPCX_I32 <"v_cmpx_lt_u32", "v_cmpx_gt_u32">; 735defm V_CMPX_EQ_U32 : VOPCX_I32 <"v_cmpx_eq_u32">; 736defm V_CMPX_LE_U32 : VOPCX_I32 <"v_cmpx_le_u32", "v_cmpx_le_u32">; 737defm V_CMPX_GT_U32 : VOPCX_I32 <"v_cmpx_gt_u32">; 738defm V_CMPX_NE_U32 : VOPCX_I32 <"v_cmpx_ne_u32">; 739defm V_CMPX_GE_U32 : VOPCX_I32 <"v_cmpx_ge_u32">; 740defm V_CMPX_T_U32 : VOPCX_I32 <"v_cmpx_t_u32">; 741 742defm V_CMP_F_U64 : VOPC_I64 <"v_cmp_f_u64">; 743defm V_CMP_LT_U64 : VOPC_I64 <"v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">; 744defm V_CMP_EQ_U64 : VOPC_I64 <"v_cmp_eq_u64", COND_EQ>; 745defm V_CMP_LE_U64 : VOPC_I64 <"v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">; 746defm V_CMP_GT_U64 : VOPC_I64 <"v_cmp_gt_u64", COND_UGT>; 747defm V_CMP_NE_U64 : VOPC_I64 <"v_cmp_ne_u64", COND_NE>; 748defm V_CMP_GE_U64 : VOPC_I64 <"v_cmp_ge_u64", COND_UGE>; 749defm V_CMP_T_U64 : VOPC_I64 <"v_cmp_t_u64">; 750 751defm V_CMPX_F_U64 : VOPCX_I64 <"v_cmpx_f_u64">; 752defm V_CMPX_LT_U64 : VOPCX_I64 <"v_cmpx_lt_u64", "v_cmpx_gt_u64">; 753defm V_CMPX_EQ_U64 : VOPCX_I64 <"v_cmpx_eq_u64">; 754defm V_CMPX_LE_U64 : VOPCX_I64 <"v_cmpx_le_u64", "v_cmpx_ge_u64">; 755defm V_CMPX_GT_U64 : VOPCX_I64 <"v_cmpx_gt_u64">; 756defm V_CMPX_NE_U64 : VOPCX_I64 <"v_cmpx_ne_u64">; 757defm V_CMPX_GE_U64 : VOPCX_I64 <"v_cmpx_ge_u64">; 758defm V_CMPX_T_U64 : VOPCX_I64 <"v_cmpx_t_u64">; 759 760//===----------------------------------------------------------------------===// 761// Class instructions 762//===----------------------------------------------------------------------===// 763 764class VOPC_Class_Profile<list<SchedReadWrite> sched, ValueType src0VT, ValueType src1VT = i32> : 765 VOPC_Profile<sched, src0VT, src1VT> { 766 let AsmDPP = "$src0_modifiers, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 767 let AsmDPP16 = AsmDPP#"$fi"; 768 let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, Src1DPP:$src1, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); 769 let InsDPP16 = !con(InsDPP, (ins FI:$fi)); 770 // DPP8 forbids modifiers and can inherit from VOPC_Profile 771 772 let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1); 773 dag InsPartVOP3DPP = (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0, VRegSrc_32:$src1); 774 let InsVOP3Base = !con(InsPartVOP3DPP, !if(HasOpSel, (ins op_sel0:$op_sel), 775 (ins))); 776 let AsmVOP3Base = "$sdst, $src0_modifiers, $src1"; 777 778 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 779 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 780 clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel); 781 782 let AsmSDWA = " vcc, $src0_modifiers, $src1_modifiers$clamp $src0_sel $src1_sel"; 783 let HasSrc1Mods = 0; 784 let HasClamp = 0; 785 let HasOMod = 0; 786} 787 788multiclass VOPC_Class_Profile_t16<list<SchedReadWrite> sched> { 789 def NAME : VOPC_Class_Profile<sched, f16>; 790 def _t16 : VOPC_Class_Profile<sched, f16, i16> { 791 let IsTrue16 = 1; 792 let Src1RC32 = RegisterOperand<getVregSrcForVT_t16<Src1VT>.ret>; 793 let Src1RC64 = VSrc_b32; 794 let Src0DPP = getVregSrcForVT_t16<Src0VT>.ret; 795 let Src1DPP = getVregSrcForVT_t16<Src1VT>.ret; 796 let Src2DPP = getVregSrcForVT_t16<Src2VT>.ret; 797 let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret; 798 let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret; 799 let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret; 800 } 801} 802 803class VOPC_Class_NoSdst_Profile<list<SchedReadWrite> sched, ValueType src0VT, ValueType src1VT = i32> : 804 VOPC_Class_Profile<sched, src0VT, src1VT> { 805 let Outs64 = (outs ); 806 let OutsSDWA = (outs ); 807 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 808 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 809 src0_sel:$src0_sel, src1_sel:$src1_sel); 810 let AsmVOP3Base = "$src0_modifiers, $src1"; 811 let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel"; 812 let EmitDst = 0; 813} 814 815multiclass VOPC_Class_NoSdst_Profile_t16<list<SchedReadWrite> sched> { 816 def NAME : VOPC_Class_NoSdst_Profile<sched, f16>; 817 def _t16 : VOPC_Class_NoSdst_Profile<sched, f16, i16> { 818 let IsTrue16 = 1; 819 let Src1RC32 = RegisterOperand<getVregSrcForVT_t16<Src1VT>.ret>; 820 let Src1RC64 = VSrc_b32; 821 let Src0DPP = getVregSrcForVT_t16<Src0VT>.ret; 822 let Src1DPP = getVregSrcForVT_t16<Src1VT>.ret; 823 let Src2DPP = getVregSrcForVT_t16<Src2VT>.ret; 824 let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret; 825 let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret; 826 let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret; 827 } 828} 829 830class getVOPCClassPat64 <VOPProfile P> { 831 list<dag> ret = 832 [(set i1:$sdst, 833 (AMDGPUfp_class 834 (P.Src0VT (VOP3ModsNonCanonicalizing P.Src0VT:$src0, i32:$src0_modifiers)), 835 i32:$src1))]; 836} 837 838 839// Special case for class instructions which only have modifiers on 840// the 1st source operand. 841multiclass VOPC_Class_Pseudos <string opName, VOPC_Profile p, bit DefExec, 842 bit DefVcc = 1> { 843 def _e32 : VOPC_Pseudo <opName, p>, 844 VCMPXNoSDstTable<1, opName#"_e32"> { 845 let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]), 846 !if(DefVcc, [VCC], [])); 847 let SchedRW = p.Schedule; 848 let isConvergent = DefExec; 849 } 850 851 def _e64 : VOP3_Pseudo<opName, p, getVOPCClassPat64<p>.ret>, 852 VCMPXNoSDstTable<1, opName#"_e64"> { 853 let Defs = !if(DefExec, [EXEC], []); 854 let SchedRW = p.Schedule; 855 } 856 857 if p.HasExtSDWA then 858 def _sdwa : VOPC_SDWA_Pseudo <opName, p> { 859 let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]), 860 !if(DefVcc, [VCC], [])); 861 let SchedRW = p.Schedule; 862 let isConvergent = DefExec; 863 } 864 865 let SubtargetPredicate = isGFX11Plus in { 866 if p.HasExtDPP then 867 def _e32_dpp : VOP_DPP_Pseudo<opName, p> { 868 let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]), 869 !if(DefVcc, [VCC], [])); 870 let SchedRW = p.Schedule; 871 let isConvergent = DefExec; 872 let VOPC = 1; 873 let Constraints = ""; 874 } 875 if p.HasExtVOP3DPP then 876 def _e64_dpp : VOP3_DPP_Pseudo<opName, p> { 877 let Defs = !if(DefExec, [EXEC], []); 878 let SchedRW = p.Schedule; 879 let Constraints = ""; 880 } 881 } // end SubtargetPredicate = isGFX11Plus 882} 883 884let SubtargetPredicate = HasSdstCMPX in { 885multiclass VOPCX_Class_Pseudos <string opName, 886 VOPC_Profile P, 887 VOPC_Profile P_NoSDst> : 888 VOPC_Class_Pseudos <opName, P, 1, 1> { 889 890 def _nosdst_e32 : VOPC_Pseudo <opName#"_nosdst", P_NoSDst, [], 0>, 891 VCMPXNoSDstTable<0, opName#"_e32"> { 892 let Defs = [EXEC]; 893 let SchedRW = P_NoSDst.Schedule; 894 let isConvergent = 1; 895 let SubtargetPredicate = HasNoSdstCMPX; 896 } 897 898 def _nosdst_e64 : VOP3_Pseudo<opName#"_nosdst", P_NoSDst>, 899 VCMPXNoSDstTable<0, opName#"_e64"> { 900 let Defs = [EXEC]; 901 let SchedRW = P_NoSDst.Schedule; 902 let SubtargetPredicate = HasNoSdstCMPX; 903 } 904 905 if P_NoSDst.HasExtSDWA then 906 def _nosdst_sdwa : VOPC_SDWA_Pseudo <opName#"_nosdst", P_NoSDst> { 907 let Defs = [EXEC]; 908 let SchedRW = P_NoSDst.Schedule; 909 let isConvergent = 1; 910 let SubtargetPredicate = HasNoSdstCMPX; 911 } 912 913 let SubtargetPredicate = isGFX11Plus in { 914 if P.HasExtDPP then 915 def _nosdst_e32_dpp : VOP_DPP_Pseudo<opName#"_nosdst", P_NoSDst> { 916 let Defs = [EXEC]; 917 let SchedRW = P_NoSDst.Schedule; 918 let isConvergent = 1; 919 let VOPC = 1; 920 let Constraints = ""; 921 } 922 if P.HasExtVOP3DPP then 923 def _nosdst_e64_dpp : VOP3_DPP_Pseudo<opName#"_nosdst", P_NoSDst> { 924 let Defs = [EXEC]; 925 let SchedRW = P_NoSDst.Schedule; 926 let Constraints = ""; 927 } 928 } // end SubtargetPredicate = isGFX11Plus 929} 930} // End SubtargetPredicate = HasSdstCMPX 931 932defm VOPC_I1_F16_I16 : VOPC_Class_Profile_t16<[Write32Bit]>; 933def VOPC_I1_F32_I32 : VOPC_Class_Profile<[Write32Bit], f32>; 934def VOPC_I1_F64_I32 : VOPC_Class_Profile<[WriteDoubleAdd], f64>; 935 936defm VOPC_F16_I16 : VOPC_Class_NoSdst_Profile_t16<[Write32Bit]>; 937def VOPC_F32_I32 : VOPC_Class_NoSdst_Profile<[Write32Bit], f32>; 938def VOPC_F64_I32 : VOPC_Class_NoSdst_Profile<[Write64Bit], f64>; 939 940multiclass VOPC_CLASS_F16 <string opName> { 941 let OtherPredicates = [NotHasTrue16BitInsts, Has16BitInsts] in { 942 defm NAME : VOPC_Class_Pseudos <opName, VOPC_I1_F16_I16, 0>; 943 } 944 let OtherPredicates = [HasTrue16BitInsts] in { 945 defm _t16 : VOPC_Class_Pseudos <opName#"_t16", VOPC_I1_F16_I16_t16, 0>; 946 } 947} 948 949multiclass VOPCX_CLASS_F16 <string opName> { 950 let OtherPredicates = [NotHasTrue16BitInsts, Has16BitInsts] in { 951 defm NAME : VOPCX_Class_Pseudos <opName, VOPC_I1_F16_I16, VOPC_F16_I16>; 952 } 953 let OtherPredicates = [HasTrue16BitInsts] in { 954 defm _t16 : VOPCX_Class_Pseudos <opName#"_t16", VOPC_I1_F16_I16_t16, VOPC_F16_I16_t16>; 955 } 956} 957 958multiclass VOPC_CLASS_F32 <string opName> : 959 VOPC_Class_Pseudos <opName, VOPC_I1_F32_I32, 0>; 960 961multiclass VOPCX_CLASS_F32 <string opName> : 962 VOPCX_Class_Pseudos <opName, VOPC_I1_F32_I32, VOPC_F32_I32>; 963 964multiclass VOPC_CLASS_F64 <string opName> : 965 VOPC_Class_Pseudos <opName, VOPC_I1_F64_I32, 0>; 966 967multiclass VOPCX_CLASS_F64 <string opName> : 968 VOPCX_Class_Pseudos <opName, VOPC_I1_F64_I32, VOPC_F64_I32>; 969 970// cmp_class ignores the FP mode and faithfully reports the unmodified 971// source value. 972let ReadsModeReg = 0, mayRaiseFPException = 0 in { 973defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <"v_cmp_class_f32">; 974defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <"v_cmpx_class_f32">; 975defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <"v_cmp_class_f64">; 976defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <"v_cmpx_class_f64">; 977 978defm V_CMP_CLASS_F16 : VOPC_CLASS_F16 <"v_cmp_class_f16">; 979defm V_CMPX_CLASS_F16 : VOPCX_CLASS_F16 <"v_cmpx_class_f16">; 980} // End ReadsModeReg = 0, mayRaiseFPException = 0 981 982//===----------------------------------------------------------------------===// 983// V_ICMPIntrinsic Pattern. 984//===----------------------------------------------------------------------===// 985 986// We need to use COPY_TO_REGCLASS to w/a the problem when ReplaceAllUsesWith() 987// complaints it cannot replace i1 <-> i64/i32 if node was not morphed in place. 988multiclass ICMP_Pattern <PatFrags cond, Instruction inst, ValueType vt> { 989 let WaveSizePredicate = isWave64 in 990 def : GCNPat < 991 (i64 (AMDGPUsetcc vt:$src0, vt:$src1, cond)), 992 (i64 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_64)) 993 >; 994 995 let WaveSizePredicate = isWave32 in { 996 def : GCNPat < 997 (i32 (AMDGPUsetcc vt:$src0, vt:$src1, cond)), 998 (i32 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_32)) 999 >; 1000 1001 // Support codegen of i64 setcc in wave32 mode. 1002 def : GCNPat < 1003 (i64 (AMDGPUsetcc vt:$src0, vt:$src1, cond)), 1004 (i64 (REG_SEQUENCE SReg_64, (inst $src0, $src1), sub0, (S_MOV_B32 (i32 0)), sub1)) 1005 >; 1006 } 1007} 1008 1009defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U32_e64, i32>; 1010defm : ICMP_Pattern <COND_NE, V_CMP_NE_U32_e64, i32>; 1011defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U32_e64, i32>; 1012defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U32_e64, i32>; 1013defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U32_e64, i32>; 1014defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U32_e64, i32>; 1015defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I32_e64, i32>; 1016defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I32_e64, i32>; 1017defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I32_e64, i32>; 1018defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I32_e64, i32>; 1019 1020defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U64_e64, i64>; 1021defm : ICMP_Pattern <COND_NE, V_CMP_NE_U64_e64, i64>; 1022defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U64_e64, i64>; 1023defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U64_e64, i64>; 1024defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U64_e64, i64>; 1025defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U64_e64, i64>; 1026defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I64_e64, i64>; 1027defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I64_e64, i64>; 1028defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I64_e64, i64>; 1029defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I64_e64, i64>; 1030 1031let OtherPredicates = [HasTrue16BitInsts] in { 1032defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U16_t16_e64, i16>; 1033defm : ICMP_Pattern <COND_NE, V_CMP_NE_U16_t16_e64, i16>; 1034defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U16_t16_e64, i16>; 1035defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U16_t16_e64, i16>; 1036defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U16_t16_e64, i16>; 1037defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U16_t16_e64, i16>; 1038defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I16_t16_e64, i16>; 1039defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I16_t16_e64, i16>; 1040defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I16_t16_e64, i16>; 1041defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I16_t16_e64, i16>; 1042} // End OtherPredicates = [HasTrue16BitInsts] 1043 1044let OtherPredicates = [NotHasTrue16BitInsts] in { 1045defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U16_e64, i16>; 1046defm : ICMP_Pattern <COND_NE, V_CMP_NE_U16_e64, i16>; 1047defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U16_e64, i16>; 1048defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U16_e64, i16>; 1049defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U16_e64, i16>; 1050defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U16_e64, i16>; 1051defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I16_e64, i16>; 1052defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I16_e64, i16>; 1053defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I16_e64, i16>; 1054defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I16_e64, i16>; 1055} // End OtherPredicates = [NotHasTrue16BitInsts] 1056 1057multiclass FCMP_Pattern <PatFrags cond, Instruction inst, ValueType vt> { 1058 let WaveSizePredicate = isWave64 in 1059 def : GCNPat < 1060 (i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), 1061 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)), 1062 (i64 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1, 1063 DSTCLAMP.NONE), SReg_64)) 1064 >; 1065 1066 let WaveSizePredicate = isWave32 in { 1067 def : GCNPat < 1068 (i32 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), 1069 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)), 1070 (i32 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1, 1071 DSTCLAMP.NONE), SReg_32)) 1072 >; 1073 1074 def : GCNPat < 1075 (i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), 1076 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)), 1077 (i64 (REG_SEQUENCE SReg_64, (inst $src0_modifiers, $src0, $src1_modifiers, $src1, 1078 DSTCLAMP.NONE), sub0, 1079 (S_MOV_B32 (i32 0)), sub1)) 1080 >; 1081 } 1082} 1083 1084defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>; 1085defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F32_e64, f32>; 1086defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F32_e64, f32>; 1087defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F32_e64, f32>; 1088defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F32_e64, f32>; 1089defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F32_e64, f32>; 1090 1091defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F64_e64, f64>; 1092defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F64_e64, f64>; 1093defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F64_e64, f64>; 1094defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F64_e64, f64>; 1095defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F64_e64, f64>; 1096defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F64_e64, f64>; 1097 1098defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F32_e64, f32>; 1099defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F32_e64, f32>; 1100defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F32_e64, f32>; 1101defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F32_e64, f32>; 1102defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F32_e64, f32>; 1103defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F32_e64, f32>; 1104 1105defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>; 1106defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>; 1107defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>; 1108defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>; 1109defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>; 1110defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>; 1111 1112let OtherPredicates = [HasTrue16BitInsts] in { 1113defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F16_t16_e64, f16>; 1114defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F16_t16_e64, f16>; 1115defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F16_t16_e64, f16>; 1116defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F16_t16_e64, f16>; 1117defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F16_t16_e64, f16>; 1118defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F16_t16_e64, f16>; 1119 1120defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F16_t16_e64, f16>; 1121defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F16_t16_e64, f16>; 1122defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F16_t16_e64, f16>; 1123defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F16_t16_e64, f16>; 1124defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F16_t16_e64, f16>; 1125defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F16_t16_e64, f16>; 1126} // End OtherPredicates = [HasTrue16BitInsts] 1127 1128let OtherPredicates = [NotHasTrue16BitInsts] in { 1129defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F16_e64, f16>; 1130defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F16_e64, f16>; 1131defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F16_e64, f16>; 1132defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F16_e64, f16>; 1133defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F16_e64, f16>; 1134defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F16_e64, f16>; 1135 1136defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F16_e64, f16>; 1137defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F16_e64, f16>; 1138defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F16_e64, f16>; 1139defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F16_e64, f16>; 1140defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F16_e64, f16>; 1141defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F16_e64, f16>; 1142} // End OtherPredicates = [NotHasTrue16BitInsts] 1143 1144//===----------------------------------------------------------------------===// 1145// DPP Encodings 1146//===----------------------------------------------------------------------===// 1147 1148// VOPC32 1149 1150class VOPC_DPPe_Common<bits<8> op> : Enc64 { 1151 bits<8> src1; 1152 let Inst{16-9} = src1; 1153 let Inst{24-17} = op; 1154 let Inst{31-25} = 0x3e; 1155} 1156 1157class VOPC_DPP_Base<bits<8> op, string OpName, VOPProfile P> 1158 : VOP_DPP_Base<OpName, P, P.InsDPP16, " " #P.AsmDPP16>, 1159 VOPC_DPPe_Common<op> { 1160 bits<2> src0_modifiers; 1161 bits<8> src0; 1162 bits<2> src1_modifiers; 1163 bits<9> dpp_ctrl; 1164 bits<1> bound_ctrl; 1165 bits<4> bank_mask; 1166 bits<4> row_mask; 1167 bit fi; 1168 1169 let Inst{8-0} = 0xfa; 1170 1171 let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, 0); 1172 let Inst{48-40} = dpp_ctrl; 1173 let Inst{50} = fi; 1174 let Inst{51} = bound_ctrl; 1175 let Inst{52} = !if (P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg 1176 let Inst{53} = !if (P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs 1177 let Inst{54} = !if (P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg 1178 let Inst{55} = !if (P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs 1179 let Inst{59-56} = bank_mask; 1180 let Inst{63-60} = row_mask; 1181 1182 let AsmMatchConverter = "cvtDPP"; 1183 let VOPC = 1; 1184} 1185 1186class VOPC_DPP8_Base<bits<8> op, string OpName, VOPProfile P> 1187 : VOP_DPP8_Base<OpName, P, P.InsDPP8, " " #P.AsmDPP8>, 1188 VOPC_DPPe_Common<op> { 1189 bits<8> src0; 1190 bits<24> dpp8; 1191 bits<9> fi; 1192 1193 let Inst{8-0} = fi; 1194 1195 let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, 0); 1196 let Inst{63-40} = dpp8{23-0}; 1197 1198 let AsmMatchConverter = "cvtDPP8"; 1199 let VOPC = 1; 1200} 1201 1202class VOPC_DPP16<bits<8> op, VOP_DPP_Pseudo ps, string opName = ps.OpName> 1203 : VOPC_DPP_Base<op, opName, ps.Pfl> { 1204 let AssemblerPredicate = HasDPP16; 1205 let SubtargetPredicate = HasDPP16; 1206 let hasSideEffects = ps.hasSideEffects; 1207 let Defs = ps.Defs; 1208 let SchedRW = ps.SchedRW; 1209 let Uses = ps.Uses; 1210 let OtherPredicates = ps.OtherPredicates; 1211 let Constraints = ps.Constraints; 1212} 1213 1214class VOPC_DPP16_SIMC<bits<8> op, VOP_DPP_Pseudo ps, int subtarget, 1215 string opName = ps.OpName> 1216 : VOPC_DPP16<op, ps, opName>, SIMCInstr<ps.PseudoInstr, subtarget>; 1217 1218class VOPC_DPP8<bits<8> op, VOPC_Pseudo ps, string opName = ps.OpName> 1219 : VOPC_DPP8_Base<op, opName, ps.Pfl> { 1220 // Note ps is the non-dpp pseudo 1221 let hasSideEffects = ps.hasSideEffects; 1222 let Defs = ps.Defs; 1223 let SchedRW = ps.SchedRW; 1224 let Uses = ps.Uses; 1225 let OtherPredicates = ps.OtherPredicates; 1226 let Constraints = ""; 1227} 1228 1229// VOPC64 1230 1231class VOPC64_DPP_Base<bits<10> op, string OpName, VOPProfile P> 1232 : VOP3_DPP_Base<OpName, P, 1>, VOP3_DPPe_Common<op, P> { 1233 Instruction Opcode = !cast<Instruction>(NAME); 1234 1235 bits<8> src0; 1236 bits<9> dpp_ctrl; 1237 bits<1> bound_ctrl; 1238 bits<4> bank_mask; 1239 bits<4> row_mask; 1240 bit fi; 1241 1242 let Inst{40-32} = 0xfa; 1243 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 1244 let Inst{80-72} = dpp_ctrl; 1245 let Inst{82} = fi; 1246 let Inst{83} = bound_ctrl; 1247 // Inst{87-84} ignored by hw 1248 let Inst{91-88} = bank_mask; 1249 let Inst{95-92} = row_mask; 1250} 1251 1252class VOPC64_DPP16<bits<10> op, VOP_DPP_Pseudo ps, string opName = ps.OpName> 1253 : VOPC64_DPP_Base<op, opName, ps.Pfl> { 1254 let AssemblerPredicate = HasDPP16; 1255 let SubtargetPredicate = HasDPP16; 1256 let hasSideEffects = ps.hasSideEffects; 1257 let Defs = ps.Defs; 1258 let SchedRW = ps.SchedRW; 1259 let Uses = ps.Uses; 1260 let OtherPredicates = ps.OtherPredicates; 1261 let Constraints = ps.Constraints; 1262} 1263 1264class VOPC64_DPP16_Dst<bits<10> op, VOP_DPP_Pseudo ps, 1265 string opName = ps.OpName> 1266 : VOPC64_DPP16<op, ps, opName> { 1267 bits<8> sdst; 1268 let Inst{7-0} = sdst; 1269} 1270 1271class VOPC64_DPP16_NoDst<bits<10> op, VOP_DPP_Pseudo ps, 1272 string opName = ps.OpName> 1273 : VOPC64_DPP16<op, ps, opName> { 1274 let Inst{7-0} = ? ; 1275} 1276 1277class VOPC64_DPP8_Base<bits<10> op, string OpName, VOPProfile P> 1278 : VOP3_DPP8_Base<OpName, P>, VOP3_DPPe_Common<op, P> { 1279 Instruction Opcode = !cast<Instruction>(NAME); 1280 1281 bits<8> src0; 1282 bits<24> dpp8; 1283 bits<9> fi; 1284 1285 let Inst{40-32} = fi; 1286 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 1287 let Inst{95-72} = dpp8{23-0}; 1288} 1289 1290class VOPC64_DPP8<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1291 : VOPC64_DPP8_Base<op, opName, ps.Pfl> { 1292 // Note ps is the non-dpp pseudo 1293 let hasSideEffects = ps.hasSideEffects; 1294 let Defs = ps.Defs; 1295 let SchedRW = ps.SchedRW; 1296 let Uses = ps.Uses; 1297 let OtherPredicates = ps.OtherPredicates; 1298} 1299 1300class VOPC64_DPP8_Dst<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1301 : VOPC64_DPP8<op, ps, opName> { 1302 bits<8> sdst; 1303 let Inst{7-0} = sdst; 1304 let Constraints = ""; 1305} 1306 1307class VOPC64_DPP8_NoDst<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1308 : VOPC64_DPP8<op, ps, opName> { 1309 let Inst{7-0} = ? ; 1310 let Constraints = ""; 1311} 1312 1313//===----------------------------------------------------------------------===// 1314// Target-specific instruction encodings. 1315//===----------------------------------------------------------------------===// 1316 1317//===----------------------------------------------------------------------===// 1318// GFX11. 1319//===----------------------------------------------------------------------===// 1320 1321let AssemblerPredicate = isGFX11Only in { 1322 multiclass VOPC_Real_gfx11<bits<9> op> { 1323 defvar ps32 = !cast<VOPC_Pseudo>(NAME#"_e32"); 1324 defvar ps64 = !cast<VOP3_Pseudo>(NAME#"_e64"); 1325 let DecoderNamespace = "GFX11" in { 1326 def _e32_gfx11 : VOPC_Real<ps32, SIEncodingFamily.GFX11>, 1327 VOPCe<op{7-0}>; 1328 def _e64_gfx11 : VOP3_Real<ps64, SIEncodingFamily.GFX11>, 1329 VOP3a_gfx11<{0, op}, ps64.Pfl> { 1330 // Encoding used for VOPC instructions encoded as VOP3 differs from 1331 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. 1332 bits<8> sdst; 1333 let Inst{7-0} = sdst; 1334 } 1335 } // End DecoderNamespace = "GFX11" 1336 1337 defm : VOPCInstAliases<NAME, "gfx11">; 1338 1339 if ps32.Pfl.HasExtDPP then { 1340 defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_e32" #"_dpp"); 1341 defvar AsmDPP = ps32.Pfl.AsmDPP16; 1342 let DecoderNamespace = "DPPGFX11" in { 1343 def _e32_dpp_gfx11 : VOPC_DPP16_SIMC<op{7-0}, psDPP, 1344 SIEncodingFamily.GFX11>; 1345 def _e32_dpp_w32_gfx11 : VOPC_DPP16<op{7-0}, psDPP> { 1346 let AsmString = psDPP.OpName # " vcc_lo, " # AsmDPP; 1347 let isAsmParserOnly = 1; 1348 let WaveSizePredicate = isWave32; 1349 } 1350 def _e32_dpp_w64_gfx11 : VOPC_DPP16<op{7-0}, psDPP> { 1351 let AsmString = psDPP.OpName # " vcc, " # AsmDPP; 1352 let isAsmParserOnly = 1; 1353 let WaveSizePredicate = isWave64; 1354 } 1355 } 1356 defvar AsmDPP8 = ps32.Pfl.AsmDPP8; 1357 let DecoderNamespace = "DPP8GFX11" in { 1358 def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32>; 1359 def _e32_dpp8_w32_gfx11 : VOPC_DPP8<op{7-0}, ps32> { 1360 let AsmString = ps32.OpName # " vcc_lo, " # AsmDPP8; 1361 let isAsmParserOnly = 1; 1362 let WaveSizePredicate = isWave32; 1363 } 1364 def _e32_dpp8_w64_gfx11 : VOPC_DPP8<op{7-0}, ps32> { 1365 let AsmString = ps32.OpName # " vcc, " # AsmDPP8; 1366 let isAsmParserOnly = 1; 1367 let WaveSizePredicate = isWave64; 1368 } 1369 } 1370 } 1371 if ps64.Pfl.HasExtVOP3DPP then { 1372 defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_e64" #"_dpp"); 1373 defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16; 1374 let DecoderNamespace = "DPPGFX11" in { 1375 def _e64_dpp_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP>, 1376 SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11>; 1377 def _e64_dpp_w32_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP> { 1378 let AsmString = psDPP.OpName # " vcc_lo, " # AsmDPP; 1379 let isAsmParserOnly = 1; 1380 let WaveSizePredicate = isWave32; 1381 } 1382 def _e64_dpp_w64_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP> { 1383 let AsmString = psDPP.OpName # " vcc, " # AsmDPP; 1384 let isAsmParserOnly = 1; 1385 let WaveSizePredicate = isWave64; 1386 } 1387 } 1388 defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8; 1389 let DecoderNamespace = "DPP8GFX11" in { 1390 def _e64_dpp8_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64>; 1391 def _e64_dpp8_w32_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64> { 1392 let AsmString = ps32.OpName # " vcc_lo, " # AsmDPP8; 1393 let isAsmParserOnly = 1; 1394 let WaveSizePredicate = isWave32; 1395 } 1396 def _e64_dpp8_w64_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64> { 1397 let AsmString = ps32.OpName # " vcc, " # AsmDPP8; 1398 let isAsmParserOnly = 1; 1399 let WaveSizePredicate = isWave64; 1400 } 1401 } 1402 } 1403 1404 } 1405 1406 multiclass VOPC_Real_with_name_gfx11<bits<9> op, string OpName, 1407 string asm_name, string pseudo_mnemonic = ""> { 1408 defvar ps32 = !cast<VOPC_Pseudo>(OpName#"_e32"); 1409 defvar ps64 = !cast<VOP3_Pseudo>(OpName#"_e64"); 1410 let DecoderNamespace = "GFX11" in { 1411 def _e32_gfx11 : 1412 // 32 and 64 bit forms of the instruction have _e32 and _e64 1413 // respectively appended to their assembly mnemonic. 1414 // _e64 is printed as part of the VOPDstS64orS32 operand, whereas 1415 // the destination-less 32bit forms add it to the asmString here. 1416 VOPC_Real<ps32, SIEncodingFamily.GFX11, asm_name#"_e32">, 1417 VOPCe<op{7-0}>, 1418 MnemonicAlias<!if(!empty(pseudo_mnemonic), ps32.Mnemonic, 1419 pseudo_mnemonic), 1420 asm_name, ps32.AsmVariantName>, 1421 Requires<[isGFX11Plus]>; 1422 def _e64_gfx11 : 1423 VOP3_Real<ps64, SIEncodingFamily.GFX11, asm_name>, 1424 VOP3a_gfx11<{0, op}, ps64.Pfl>, 1425 MnemonicAlias<!if(!empty(pseudo_mnemonic), ps64.Mnemonic, 1426 pseudo_mnemonic), 1427 asm_name, ps64.AsmVariantName>, 1428 Requires<[isGFX11Plus]> { 1429 // Encoding used for VOPC instructions encoded as VOP3 differs from 1430 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. 1431 bits<8> sdst; 1432 let Inst{7-0} = sdst; 1433 } 1434 } // End DecoderNamespace = "GFX11" 1435 1436 defm : VOPCInstAliases<OpName, "gfx11", NAME, asm_name>; 1437 1438 if ps32.Pfl.HasExtDPP then { 1439 defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName #"_e32" #"_dpp"); 1440 defvar AsmDPP = ps32.Pfl.AsmDPP16; 1441 let DecoderNamespace = "DPPGFX11" in { 1442 def _e32_dpp_gfx11 : VOPC_DPP16_SIMC<op{7-0}, psDPP, 1443 SIEncodingFamily.GFX11, asm_name>; 1444 def _e32_dpp_w32_gfx11 1445 : VOPC_DPP16<op{7-0}, psDPP, asm_name> { 1446 let AsmString = asm_name # " vcc_lo, " # AsmDPP; 1447 let isAsmParserOnly = 1; 1448 let WaveSizePredicate = isWave32; 1449 } 1450 def _e32_dpp_w64_gfx11 1451 : VOPC_DPP16<op{7-0}, psDPP, asm_name> { 1452 let AsmString = asm_name # " vcc, " # AsmDPP; 1453 let isAsmParserOnly = 1; 1454 let WaveSizePredicate = isWave64; 1455 } 1456 } 1457 defvar AsmDPP8 = ps32.Pfl.AsmDPP8; 1458 let DecoderNamespace = "DPP8GFX11" in { 1459 def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32, asm_name>; 1460 def _e32_dpp8_w32_gfx11 1461 : VOPC_DPP8<op{7-0}, ps32, asm_name> { 1462 let AsmString = asm_name # " vcc_lo, " # AsmDPP8; 1463 let isAsmParserOnly = 1; 1464 let WaveSizePredicate = isWave32; 1465 } 1466 def _e32_dpp8_w64_gfx11 1467 : VOPC_DPP8<op{7-0}, ps32, asm_name> { 1468 let AsmString = asm_name # " vcc, " # AsmDPP8; 1469 let isAsmParserOnly = 1; 1470 let WaveSizePredicate = isWave64; 1471 } 1472 } 1473 } 1474 1475 if ps64.Pfl.HasExtVOP3DPP then { 1476 defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName #"_e64" #"_dpp"); 1477 defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16; 1478 let DecoderNamespace = "DPPGFX11" in { 1479 def _e64_dpp_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name>, 1480 SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11>; 1481 def _e64_dpp_w32_gfx11 1482 : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name> { 1483 let AsmString = asm_name # " vcc_lo, " # AsmDPP; 1484 let isAsmParserOnly = 1; 1485 let WaveSizePredicate = isWave32; 1486 } 1487 def _e64_dpp_w64_gfx11 1488 : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name> { 1489 let AsmString = asm_name # " vcc, " # AsmDPP; 1490 let isAsmParserOnly = 1; 1491 let WaveSizePredicate = isWave64; 1492 } 1493 } 1494 defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8; 1495 let DecoderNamespace = "DPP8GFX11" in { 1496 def _e64_dpp8_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name>; 1497 def _e64_dpp8_w32_gfx11 1498 : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name> { 1499 let AsmString = asm_name # " vcc_lo, " # AsmDPP8; 1500 let isAsmParserOnly = 1; 1501 let WaveSizePredicate = isWave32; 1502 } 1503 def _e64_dpp8_w64_gfx11 1504 : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name> { 1505 let AsmString = asm_name # " vcc, " # AsmDPP8; 1506 let isAsmParserOnly = 1; 1507 let WaveSizePredicate = isWave64; 1508 } 1509 } 1510 } 1511 } 1512 1513 multiclass VOPC_Real_t16_gfx11<bits<9> op, string asm_name, 1514 string OpName = NAME> : VOPC_Real_with_name_gfx11<op, OpName, asm_name>; 1515 1516 multiclass VOPCX_Real_gfx11<bits<9> op> { 1517 defvar ps32 = !cast<VOPC_Pseudo>(NAME#"_nosdst_e32"); 1518 defvar ps64 = !cast<VOP3_Pseudo>(NAME#"_nosdst_e64"); 1519 let DecoderNamespace = "GFX11" in { 1520 def _e32_gfx11 : 1521 VOPC_Real<ps32, SIEncodingFamily.GFX11>, 1522 VOPCe<op{7-0}> { 1523 let AsmString = !subst("_nosdst", "", ps32.PseudoInstr) 1524 # " " # ps32.AsmOperands; 1525 } 1526 def _e64_gfx11 : 1527 VOP3_Real<ps64, SIEncodingFamily.GFX11>, 1528 VOP3a_gfx11<{0, op}, ps64.Pfl> { 1529 let Inst{7-0} = ?; // sdst 1530 let AsmString = !subst("_nosdst", "", ps64.Mnemonic) 1531 # "{_e64} " # ps64.AsmOperands; 1532 } 1533 } // End DecoderNamespace = "GFX11" 1534 1535 defm : VOPCXInstAliases<NAME, "gfx11">; 1536 1537 if ps32.Pfl.HasExtDPP then { 1538 defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_nosdst_e32" #"_dpp"); 1539 defvar AsmDPP = ps32.Pfl.AsmDPP16; 1540 let DecoderNamespace = "DPPGFX11" in { 1541 def _e32_dpp_gfx11 1542 : VOPC_DPP16_SIMC<op{7-0}, psDPP, SIEncodingFamily.GFX11> { 1543 let AsmString = !subst("_nosdst", "", psDPP.OpName) # " " # AsmDPP; 1544 } 1545 } 1546 defvar AsmDPP8 = ps32.Pfl.AsmDPP8; 1547 let DecoderNamespace = "DPP8GFX11" in { 1548 def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32> { 1549 let AsmString = !subst("_nosdst", "", ps32.OpName) # " " # AsmDPP8; 1550 } 1551 } 1552 } 1553 1554 if ps64.Pfl.HasExtVOP3DPP then { 1555 defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_nosdst_e64" #"_dpp"); 1556 defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16; 1557 let DecoderNamespace = "DPPGFX11" in { 1558 def _e64_dpp_gfx11 1559 : VOPC64_DPP16_NoDst<{0, op}, psDPP>, 1560 SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11> { 1561 let AsmString = !subst("_nosdst", "", psDPP.OpName) 1562 # "{_e64_dpp} " # AsmDPP; 1563 } 1564 } 1565 defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8; 1566 let DecoderNamespace = "DPP8GFX11" in { 1567 def _e64_dpp8_gfx11 : VOPC64_DPP8_NoDst<{0, op}, ps64> { 1568 let AsmString = !subst("_nosdst", "", ps64.OpName) 1569 # "{_e64_dpp} " # AsmDPP8; 1570 } 1571 } 1572 } 1573 } 1574 1575 multiclass VOPCX_Real_with_name_gfx11<bits<9> op, string OpName, 1576 string asm_name, string pseudo_mnemonic = ""> { 1577 defvar ps32 = !cast<VOPC_Pseudo>(OpName#"_nosdst_e32"); 1578 defvar ps64 = !cast<VOP3_Pseudo>(OpName#"_nosdst_e64"); 1579 let DecoderNamespace = "GFX11" in { 1580 def _e32_gfx11 1581 : VOPC_Real<ps32, SIEncodingFamily.GFX11, asm_name>, 1582 MnemonicAlias<!if(!empty(pseudo_mnemonic), !subst("_nosdst", "", ps32.Mnemonic), 1583 pseudo_mnemonic), 1584 asm_name, ps32.AsmVariantName>, 1585 Requires<[isGFX11Plus]>, 1586 VOPCe<op{7-0}> { 1587 let AsmString = asm_name # "{_e32} " # ps32.AsmOperands; 1588 } 1589 def _e64_gfx11 1590 : VOP3_Real<ps64, SIEncodingFamily.GFX11, asm_name>, 1591 MnemonicAlias<!if(!empty(pseudo_mnemonic), !subst("_nosdst", "", ps64.Mnemonic), 1592 pseudo_mnemonic), 1593 asm_name, ps64.AsmVariantName>, 1594 Requires<[isGFX11Plus]>, 1595 VOP3a_gfx11<{0, op}, ps64.Pfl> { 1596 let Inst{7-0} = ? ; // sdst 1597 let AsmString = asm_name # "{_e64} " # ps64.AsmOperands; 1598 } 1599 } // End DecoderNamespace = "GFX11" 1600 1601 defm : VOPCXInstAliases<OpName, "gfx11", NAME, asm_name>; 1602 1603 if ps32.Pfl.HasExtDPP then { 1604 defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName#"_nosdst_e32"#"_dpp"); 1605 let DecoderNamespace = "DPPGFX11" in { 1606 def _e32_dpp_gfx11 : VOPC_DPP16_SIMC<op{7-0}, psDPP, 1607 SIEncodingFamily.GFX11, asm_name>; 1608 } 1609 let DecoderNamespace = "DPP8GFX11" in { 1610 def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32, asm_name>; 1611 } 1612 } 1613 if ps64.Pfl.HasExtVOP3DPP then { 1614 defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName#"_nosdst_e64"#"_dpp"); 1615 defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16; 1616 let DecoderNamespace = "DPPGFX11" in { 1617 def _e64_dpp_gfx11 1618 : VOPC64_DPP16_NoDst<{0, op}, psDPP, asm_name>, 1619 SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11> { 1620 let AsmString = asm_name # "{_e64_dpp} " # AsmDPP; 1621 } 1622 } 1623 defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8; 1624 let DecoderNamespace = "DPP8GFX11" in { 1625 def _e64_dpp8_gfx11 : VOPC64_DPP8_NoDst<{0, op}, ps64, asm_name> { 1626 let AsmString = asm_name # "{_e64_dpp} " # AsmDPP8; 1627 } 1628 } 1629 } 1630 } 1631 1632 multiclass VOPCX_Real_t16_gfx11<bits<9> op, string asm_name, 1633 string OpName = NAME> : VOPCX_Real_with_name_gfx11<op, OpName, asm_name>; 1634 1635 1636} // End AssemblerPredicate = isGFX11Only 1637 1638defm V_CMP_F_F16_t16 : VOPC_Real_t16_gfx11<0x000, "v_cmp_f_f16">; 1639defm V_CMP_LT_F16_t16 : VOPC_Real_t16_gfx11<0x001, "v_cmp_lt_f16">; 1640defm V_CMP_EQ_F16_t16 : VOPC_Real_t16_gfx11<0x002, "v_cmp_eq_f16">; 1641defm V_CMP_LE_F16_t16 : VOPC_Real_t16_gfx11<0x003, "v_cmp_le_f16">; 1642defm V_CMP_GT_F16_t16 : VOPC_Real_t16_gfx11<0x004, "v_cmp_gt_f16">; 1643defm V_CMP_LG_F16_t16 : VOPC_Real_t16_gfx11<0x005, "v_cmp_lg_f16">; 1644defm V_CMP_GE_F16_t16 : VOPC_Real_t16_gfx11<0x006, "v_cmp_ge_f16">; 1645defm V_CMP_O_F16_t16 : VOPC_Real_t16_gfx11<0x007, "v_cmp_o_f16">; 1646defm V_CMP_U_F16_t16 : VOPC_Real_t16_gfx11<0x008, "v_cmp_u_f16">; 1647defm V_CMP_NGE_F16_t16 : VOPC_Real_t16_gfx11<0x009, "v_cmp_nge_f16">; 1648defm V_CMP_NLG_F16_t16 : VOPC_Real_t16_gfx11<0x00a, "v_cmp_nlg_f16">; 1649defm V_CMP_NGT_F16_t16 : VOPC_Real_t16_gfx11<0x00b, "v_cmp_ngt_f16">; 1650defm V_CMP_NLE_F16_t16 : VOPC_Real_t16_gfx11<0x00c, "v_cmp_nle_f16">; 1651defm V_CMP_NEQ_F16_t16 : VOPC_Real_t16_gfx11<0x00d, "v_cmp_neq_f16">; 1652defm V_CMP_NLT_F16_t16 : VOPC_Real_t16_gfx11<0x00e, "v_cmp_nlt_f16">; 1653defm V_CMP_T_F16_t16 : VOPC_Real_with_name_gfx11<0x00f, "V_CMP_TRU_F16_t16", "v_cmp_t_f16", "v_cmp_tru_f16">; 1654defm V_CMP_F_F32 : VOPC_Real_gfx11<0x010>; 1655defm V_CMP_LT_F32 : VOPC_Real_gfx11<0x011>; 1656defm V_CMP_EQ_F32 : VOPC_Real_gfx11<0x012>; 1657defm V_CMP_LE_F32 : VOPC_Real_gfx11<0x013>; 1658defm V_CMP_GT_F32 : VOPC_Real_gfx11<0x014>; 1659defm V_CMP_LG_F32 : VOPC_Real_gfx11<0x015>; 1660defm V_CMP_GE_F32 : VOPC_Real_gfx11<0x016>; 1661defm V_CMP_O_F32 : VOPC_Real_gfx11<0x017>; 1662defm V_CMP_U_F32 : VOPC_Real_gfx11<0x018>; 1663defm V_CMP_NGE_F32 : VOPC_Real_gfx11<0x019>; 1664defm V_CMP_NLG_F32 : VOPC_Real_gfx11<0x01a>; 1665defm V_CMP_NGT_F32 : VOPC_Real_gfx11<0x01b>; 1666defm V_CMP_NLE_F32 : VOPC_Real_gfx11<0x01c>; 1667defm V_CMP_NEQ_F32 : VOPC_Real_gfx11<0x01d>; 1668defm V_CMP_NLT_F32 : VOPC_Real_gfx11<0x01e>; 1669defm V_CMP_T_F32 : VOPC_Real_with_name_gfx11<0x01f, "V_CMP_TRU_F32", "v_cmp_t_f32">; 1670defm V_CMP_T_F64 : VOPC_Real_with_name_gfx11<0x02f, "V_CMP_TRU_F64", "v_cmp_t_f64">; 1671defm V_CMP_LT_I16_t16 : VOPC_Real_t16_gfx11<0x031, "v_cmp_lt_i16">; 1672defm V_CMP_EQ_I16_t16 : VOPC_Real_t16_gfx11<0x032, "v_cmp_eq_i16">; 1673defm V_CMP_LE_I16_t16 : VOPC_Real_t16_gfx11<0x033, "v_cmp_le_i16">; 1674defm V_CMP_GT_I16_t16 : VOPC_Real_t16_gfx11<0x034, "v_cmp_gt_i16">; 1675defm V_CMP_NE_I16_t16 : VOPC_Real_t16_gfx11<0x035, "v_cmp_ne_i16">; 1676defm V_CMP_GE_I16_t16 : VOPC_Real_t16_gfx11<0x036, "v_cmp_ge_i16">; 1677defm V_CMP_LT_U16_t16 : VOPC_Real_t16_gfx11<0x039, "v_cmp_lt_u16">; 1678defm V_CMP_EQ_U16_t16 : VOPC_Real_t16_gfx11<0x03a, "v_cmp_eq_u16">; 1679defm V_CMP_LE_U16_t16 : VOPC_Real_t16_gfx11<0x03b, "v_cmp_le_u16">; 1680defm V_CMP_GT_U16_t16 : VOPC_Real_t16_gfx11<0x03c, "v_cmp_gt_u16">; 1681defm V_CMP_NE_U16_t16 : VOPC_Real_t16_gfx11<0x03d, "v_cmp_ne_u16">; 1682defm V_CMP_GE_U16_t16 : VOPC_Real_t16_gfx11<0x03e, "v_cmp_ge_u16">; 1683defm V_CMP_F_I32 : VOPC_Real_gfx11<0x040>; 1684defm V_CMP_LT_I32 : VOPC_Real_gfx11<0x041>; 1685defm V_CMP_EQ_I32 : VOPC_Real_gfx11<0x042>; 1686defm V_CMP_LE_I32 : VOPC_Real_gfx11<0x043>; 1687defm V_CMP_GT_I32 : VOPC_Real_gfx11<0x044>; 1688defm V_CMP_NE_I32 : VOPC_Real_gfx11<0x045>; 1689defm V_CMP_GE_I32 : VOPC_Real_gfx11<0x046>; 1690defm V_CMP_T_I32 : VOPC_Real_gfx11<0x047>; 1691defm V_CMP_F_U32 : VOPC_Real_gfx11<0x048>; 1692defm V_CMP_LT_U32 : VOPC_Real_gfx11<0x049>; 1693defm V_CMP_EQ_U32 : VOPC_Real_gfx11<0x04a>; 1694defm V_CMP_LE_U32 : VOPC_Real_gfx11<0x04b>; 1695defm V_CMP_GT_U32 : VOPC_Real_gfx11<0x04c>; 1696defm V_CMP_NE_U32 : VOPC_Real_gfx11<0x04d>; 1697defm V_CMP_GE_U32 : VOPC_Real_gfx11<0x04e>; 1698defm V_CMP_T_U32 : VOPC_Real_gfx11<0x04f>; 1699 1700defm V_CMP_F_I64 : VOPC_Real_gfx11<0x050>; 1701defm V_CMP_LT_I64 : VOPC_Real_gfx11<0x051>; 1702defm V_CMP_EQ_I64 : VOPC_Real_gfx11<0x052>; 1703defm V_CMP_LE_I64 : VOPC_Real_gfx11<0x053>; 1704defm V_CMP_GT_I64 : VOPC_Real_gfx11<0x054>; 1705defm V_CMP_NE_I64 : VOPC_Real_gfx11<0x055>; 1706defm V_CMP_GE_I64 : VOPC_Real_gfx11<0x056>; 1707defm V_CMP_T_I64 : VOPC_Real_gfx11<0x057>; 1708defm V_CMP_F_U64 : VOPC_Real_gfx11<0x058>; 1709defm V_CMP_LT_U64 : VOPC_Real_gfx11<0x059>; 1710defm V_CMP_EQ_U64 : VOPC_Real_gfx11<0x05a>; 1711defm V_CMP_LE_U64 : VOPC_Real_gfx11<0x05b>; 1712defm V_CMP_GT_U64 : VOPC_Real_gfx11<0x05c>; 1713defm V_CMP_NE_U64 : VOPC_Real_gfx11<0x05d>; 1714defm V_CMP_GE_U64 : VOPC_Real_gfx11<0x05e>; 1715defm V_CMP_T_U64 : VOPC_Real_gfx11<0x05f>; 1716 1717defm V_CMP_CLASS_F16_t16 : VOPC_Real_t16_gfx11<0x07d, "v_cmp_class_f16">; 1718defm V_CMP_CLASS_F32 : VOPC_Real_gfx11<0x07e>; 1719defm V_CMP_CLASS_F64 : VOPC_Real_gfx11<0x07f>; 1720 1721defm V_CMPX_F_F16_t16 : VOPCX_Real_t16_gfx11<0x080, "v_cmpx_f_f16">; 1722defm V_CMPX_LT_F16_t16 : VOPCX_Real_t16_gfx11<0x081, "v_cmpx_lt_f16">; 1723defm V_CMPX_EQ_F16_t16 : VOPCX_Real_t16_gfx11<0x082, "v_cmpx_eq_f16">; 1724defm V_CMPX_LE_F16_t16 : VOPCX_Real_t16_gfx11<0x083, "v_cmpx_le_f16">; 1725defm V_CMPX_GT_F16_t16 : VOPCX_Real_t16_gfx11<0x084, "v_cmpx_gt_f16">; 1726defm V_CMPX_LG_F16_t16 : VOPCX_Real_t16_gfx11<0x085, "v_cmpx_lg_f16">; 1727defm V_CMPX_GE_F16_t16 : VOPCX_Real_t16_gfx11<0x086, "v_cmpx_ge_f16">; 1728defm V_CMPX_O_F16_t16 : VOPCX_Real_t16_gfx11<0x087, "v_cmpx_o_f16">; 1729defm V_CMPX_U_F16_t16 : VOPCX_Real_t16_gfx11<0x088, "v_cmpx_u_f16">; 1730defm V_CMPX_NGE_F16_t16 : VOPCX_Real_t16_gfx11<0x089, "v_cmpx_nge_f16">; 1731defm V_CMPX_NLG_F16_t16 : VOPCX_Real_t16_gfx11<0x08a, "v_cmpx_nlg_f16">; 1732defm V_CMPX_NGT_F16_t16 : VOPCX_Real_t16_gfx11<0x08b, "v_cmpx_ngt_f16">; 1733defm V_CMPX_NLE_F16_t16 : VOPCX_Real_t16_gfx11<0x08c, "v_cmpx_nle_f16">; 1734defm V_CMPX_NEQ_F16_t16 : VOPCX_Real_t16_gfx11<0x08d, "v_cmpx_neq_f16">; 1735defm V_CMPX_NLT_F16_t16 : VOPCX_Real_t16_gfx11<0x08e, "v_cmpx_nlt_f16">; 1736defm V_CMPX_T_F16_t16 : VOPCX_Real_with_name_gfx11<0x08f, "V_CMPX_TRU_F16_t16", "v_cmpx_t_f16", "v_cmpx_tru_f16">; 1737defm V_CMPX_F_F32 : VOPCX_Real_gfx11<0x090>; 1738defm V_CMPX_LT_F32 : VOPCX_Real_gfx11<0x091>; 1739defm V_CMPX_EQ_F32 : VOPCX_Real_gfx11<0x092>; 1740defm V_CMPX_LE_F32 : VOPCX_Real_gfx11<0x093>; 1741defm V_CMPX_GT_F32 : VOPCX_Real_gfx11<0x094>; 1742defm V_CMPX_LG_F32 : VOPCX_Real_gfx11<0x095>; 1743defm V_CMPX_GE_F32 : VOPCX_Real_gfx11<0x096>; 1744defm V_CMPX_O_F32 : VOPCX_Real_gfx11<0x097>; 1745defm V_CMPX_U_F32 : VOPCX_Real_gfx11<0x098>; 1746defm V_CMPX_NGE_F32 : VOPCX_Real_gfx11<0x099>; 1747defm V_CMPX_NLG_F32 : VOPCX_Real_gfx11<0x09a>; 1748defm V_CMPX_NGT_F32 : VOPCX_Real_gfx11<0x09b>; 1749defm V_CMPX_NLE_F32 : VOPCX_Real_gfx11<0x09c>; 1750defm V_CMPX_NEQ_F32 : VOPCX_Real_gfx11<0x09d>; 1751defm V_CMPX_NLT_F32 : VOPCX_Real_gfx11<0x09e>; 1752defm V_CMPX_T_F32 : VOPCX_Real_with_name_gfx11<0x09f, "V_CMPX_TRU_F32", "v_cmpx_t_f32">; 1753 1754defm V_CMPX_F_F64 : VOPCX_Real_gfx11<0x0a0>; 1755defm V_CMPX_LT_F64 : VOPCX_Real_gfx11<0x0a1>; 1756defm V_CMPX_EQ_F64 : VOPCX_Real_gfx11<0x0a2>; 1757defm V_CMPX_LE_F64 : VOPCX_Real_gfx11<0x0a3>; 1758defm V_CMPX_GT_F64 : VOPCX_Real_gfx11<0x0a4>; 1759defm V_CMPX_LG_F64 : VOPCX_Real_gfx11<0x0a5>; 1760defm V_CMPX_GE_F64 : VOPCX_Real_gfx11<0x0a6>; 1761defm V_CMPX_O_F64 : VOPCX_Real_gfx11<0x0a7>; 1762defm V_CMPX_U_F64 : VOPCX_Real_gfx11<0x0a8>; 1763defm V_CMPX_NGE_F64 : VOPCX_Real_gfx11<0x0a9>; 1764defm V_CMPX_NLG_F64 : VOPCX_Real_gfx11<0x0aa>; 1765defm V_CMPX_NGT_F64 : VOPCX_Real_gfx11<0x0ab>; 1766defm V_CMPX_NLE_F64 : VOPCX_Real_gfx11<0x0ac>; 1767defm V_CMPX_NEQ_F64 : VOPCX_Real_gfx11<0x0ad>; 1768defm V_CMPX_NLT_F64 : VOPCX_Real_gfx11<0x0ae>; 1769defm V_CMPX_T_F64 : VOPCX_Real_with_name_gfx11<0x0af, "V_CMPX_TRU_F64", "v_cmpx_t_f64">; 1770 1771defm V_CMPX_LT_I16_t16 : VOPCX_Real_t16_gfx11<0x0b1, "v_cmpx_lt_i16">; 1772defm V_CMPX_EQ_I16_t16 : VOPCX_Real_t16_gfx11<0x0b2, "v_cmpx_eq_i16">; 1773defm V_CMPX_LE_I16_t16 : VOPCX_Real_t16_gfx11<0x0b3, "v_cmpx_le_i16">; 1774defm V_CMPX_GT_I16_t16 : VOPCX_Real_t16_gfx11<0x0b4, "v_cmpx_gt_i16">; 1775defm V_CMPX_NE_I16_t16 : VOPCX_Real_t16_gfx11<0x0b5, "v_cmpx_ne_i16">; 1776defm V_CMPX_GE_I16_t16 : VOPCX_Real_t16_gfx11<0x0b6, "v_cmpx_ge_i16">; 1777defm V_CMPX_LT_U16_t16 : VOPCX_Real_t16_gfx11<0x0b9, "v_cmpx_lt_u16">; 1778defm V_CMPX_EQ_U16_t16 : VOPCX_Real_t16_gfx11<0x0ba, "v_cmpx_eq_u16">; 1779defm V_CMPX_LE_U16_t16 : VOPCX_Real_t16_gfx11<0x0bb, "v_cmpx_le_u16">; 1780defm V_CMPX_GT_U16_t16 : VOPCX_Real_t16_gfx11<0x0bc, "v_cmpx_gt_u16">; 1781defm V_CMPX_NE_U16_t16 : VOPCX_Real_t16_gfx11<0x0bd, "v_cmpx_ne_u16">; 1782defm V_CMPX_GE_U16_t16 : VOPCX_Real_t16_gfx11<0x0be, "v_cmpx_ge_u16">; 1783defm V_CMPX_F_I32 : VOPCX_Real_gfx11<0x0c0>; 1784defm V_CMPX_LT_I32 : VOPCX_Real_gfx11<0x0c1>; 1785defm V_CMPX_EQ_I32 : VOPCX_Real_gfx11<0x0c2>; 1786defm V_CMPX_LE_I32 : VOPCX_Real_gfx11<0x0c3>; 1787defm V_CMPX_GT_I32 : VOPCX_Real_gfx11<0x0c4>; 1788defm V_CMPX_NE_I32 : VOPCX_Real_gfx11<0x0c5>; 1789defm V_CMPX_GE_I32 : VOPCX_Real_gfx11<0x0c6>; 1790defm V_CMPX_T_I32 : VOPCX_Real_gfx11<0x0c7>; 1791defm V_CMPX_F_U32 : VOPCX_Real_gfx11<0x0c8>; 1792defm V_CMPX_LT_U32 : VOPCX_Real_gfx11<0x0c9>; 1793defm V_CMPX_EQ_U32 : VOPCX_Real_gfx11<0x0ca>; 1794defm V_CMPX_LE_U32 : VOPCX_Real_gfx11<0x0cb>; 1795defm V_CMPX_GT_U32 : VOPCX_Real_gfx11<0x0cc>; 1796defm V_CMPX_NE_U32 : VOPCX_Real_gfx11<0x0cd>; 1797defm V_CMPX_GE_U32 : VOPCX_Real_gfx11<0x0ce>; 1798defm V_CMPX_T_U32 : VOPCX_Real_gfx11<0x0cf>; 1799 1800defm V_CMPX_F_I64 : VOPCX_Real_gfx11<0x0d0>; 1801defm V_CMPX_LT_I64 : VOPCX_Real_gfx11<0x0d1>; 1802defm V_CMPX_EQ_I64 : VOPCX_Real_gfx11<0x0d2>; 1803defm V_CMPX_LE_I64 : VOPCX_Real_gfx11<0x0d3>; 1804defm V_CMPX_GT_I64 : VOPCX_Real_gfx11<0x0d4>; 1805defm V_CMPX_NE_I64 : VOPCX_Real_gfx11<0x0d5>; 1806defm V_CMPX_GE_I64 : VOPCX_Real_gfx11<0x0d6>; 1807defm V_CMPX_T_I64 : VOPCX_Real_gfx11<0x0d7>; 1808defm V_CMPX_F_U64 : VOPCX_Real_gfx11<0x0d8>; 1809defm V_CMPX_LT_U64 : VOPCX_Real_gfx11<0x0d9>; 1810defm V_CMPX_EQ_U64 : VOPCX_Real_gfx11<0x0da>; 1811defm V_CMPX_LE_U64 : VOPCX_Real_gfx11<0x0db>; 1812defm V_CMPX_GT_U64 : VOPCX_Real_gfx11<0x0dc>; 1813defm V_CMPX_NE_U64 : VOPCX_Real_gfx11<0x0dd>; 1814defm V_CMPX_GE_U64 : VOPCX_Real_gfx11<0x0de>; 1815defm V_CMPX_T_U64 : VOPCX_Real_gfx11<0x0df>; 1816defm V_CMPX_CLASS_F16_t16 : VOPCX_Real_t16_gfx11<0x0fd, "v_cmpx_class_f16">; 1817defm V_CMPX_CLASS_F32 : VOPCX_Real_gfx11<0x0fe>; 1818defm V_CMPX_CLASS_F64 : VOPCX_Real_gfx11<0x0ff>; 1819 1820//===----------------------------------------------------------------------===// 1821// GFX10. 1822//===----------------------------------------------------------------------===// 1823 1824let AssemblerPredicate = isGFX10Only in { 1825 multiclass VOPC_Real_gfx10<bits<9> op> { 1826 let DecoderNamespace = "GFX10" in { 1827 def _e32_gfx10 : 1828 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>, 1829 VOPCe<op{7-0}>; 1830 def _e64_gfx10 : 1831 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 1832 VOP3a_gfx10<{0, op}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1833 // Encoding used for VOPC instructions encoded as VOP3 differs from 1834 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. 1835 bits<8> sdst; 1836 let Inst{7-0} = sdst; 1837 } 1838 } // End DecoderNamespace = "GFX10" 1839 1840 if !cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then 1841 def _sdwa_gfx10 : 1842 VOP_SDWA10_Real<!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>, 1843 VOPC_SDWA9e<op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 1844 1845 defm : VOPCInstAliases<NAME, "gfx10">; 1846 } 1847 1848 multiclass VOPCX_Real_gfx10<bits<9> op> { 1849 let DecoderNamespace = "GFX10" in { 1850 def _e32_gfx10 : 1851 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_nosdst_e32"), SIEncodingFamily.GFX10>, 1852 VOPCe<op{7-0}> { 1853 let AsmString = !subst("_nosdst", "", !cast<VOPC_Pseudo>(NAME#"_nosdst_e32").PseudoInstr) 1854 # " " # !cast<VOPC_Pseudo>(NAME#"_nosdst_e32").AsmOperands; 1855 } 1856 1857 def _e64_gfx10 : 1858 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_nosdst_e64"), SIEncodingFamily.GFX10>, 1859 VOP3a_gfx10<{0, op}, !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").Pfl> { 1860 let Inst{7-0} = ?; // sdst 1861 let AsmString = !subst("_nosdst", "", !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").Mnemonic) 1862 # "{_e64} " # !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").AsmOperands; 1863 } 1864 } // End DecoderNamespace = "GFX10" 1865 1866 if !cast<VOPC_Pseudo>(NAME#"_nosdst_e32").Pfl.HasExtSDWA9 then 1867 def _sdwa_gfx10 : 1868 VOP_SDWA10_Real<!cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa")>, 1869 VOPC_SDWA9e<op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").Pfl> { 1870 let AsmString = !subst("_nosdst", "", !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").Mnemonic) 1871 # "{_sdwa} " # !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").AsmOperands9; 1872 } 1873 1874 defm : VOPCXInstAliases<NAME, "gfx10">; 1875 } 1876} // End AssemblerPredicate = isGFX10Only 1877 1878defm V_CMP_LT_I16 : VOPC_Real_gfx10<0x089>; 1879defm V_CMP_EQ_I16 : VOPC_Real_gfx10<0x08a>; 1880defm V_CMP_LE_I16 : VOPC_Real_gfx10<0x08b>; 1881defm V_CMP_GT_I16 : VOPC_Real_gfx10<0x08c>; 1882defm V_CMP_NE_I16 : VOPC_Real_gfx10<0x08d>; 1883defm V_CMP_GE_I16 : VOPC_Real_gfx10<0x08e>; 1884defm V_CMP_CLASS_F16 : VOPC_Real_gfx10<0x08f>; 1885defm V_CMPX_LT_I16 : VOPCX_Real_gfx10<0x099>; 1886defm V_CMPX_EQ_I16 : VOPCX_Real_gfx10<0x09a>; 1887defm V_CMPX_LE_I16 : VOPCX_Real_gfx10<0x09b>; 1888defm V_CMPX_GT_I16 : VOPCX_Real_gfx10<0x09c>; 1889defm V_CMPX_NE_I16 : VOPCX_Real_gfx10<0x09d>; 1890defm V_CMPX_GE_I16 : VOPCX_Real_gfx10<0x09e>; 1891defm V_CMPX_CLASS_F16 : VOPCX_Real_gfx10<0x09f>; 1892defm V_CMP_LT_U16 : VOPC_Real_gfx10<0x0a9>; 1893defm V_CMP_EQ_U16 : VOPC_Real_gfx10<0x0aa>; 1894defm V_CMP_LE_U16 : VOPC_Real_gfx10<0x0ab>; 1895defm V_CMP_GT_U16 : VOPC_Real_gfx10<0x0ac>; 1896defm V_CMP_NE_U16 : VOPC_Real_gfx10<0x0ad>; 1897defm V_CMP_GE_U16 : VOPC_Real_gfx10<0x0ae>; 1898defm V_CMPX_LT_U16 : VOPCX_Real_gfx10<0x0b9>; 1899defm V_CMPX_EQ_U16 : VOPCX_Real_gfx10<0x0ba>; 1900defm V_CMPX_LE_U16 : VOPCX_Real_gfx10<0x0bb>; 1901defm V_CMPX_GT_U16 : VOPCX_Real_gfx10<0x0bc>; 1902defm V_CMPX_NE_U16 : VOPCX_Real_gfx10<0x0bd>; 1903defm V_CMPX_GE_U16 : VOPCX_Real_gfx10<0x0be>; 1904defm V_CMP_F_F16 : VOPC_Real_gfx10<0x0c8>; 1905defm V_CMP_LT_F16 : VOPC_Real_gfx10<0x0c9>; 1906defm V_CMP_EQ_F16 : VOPC_Real_gfx10<0x0ca>; 1907defm V_CMP_LE_F16 : VOPC_Real_gfx10<0x0cb>; 1908defm V_CMP_GT_F16 : VOPC_Real_gfx10<0x0cc>; 1909defm V_CMP_LG_F16 : VOPC_Real_gfx10<0x0cd>; 1910defm V_CMP_GE_F16 : VOPC_Real_gfx10<0x0ce>; 1911defm V_CMP_O_F16 : VOPC_Real_gfx10<0x0cf>; 1912defm V_CMPX_F_F16 : VOPCX_Real_gfx10<0x0d8>; 1913defm V_CMPX_LT_F16 : VOPCX_Real_gfx10<0x0d9>; 1914defm V_CMPX_EQ_F16 : VOPCX_Real_gfx10<0x0da>; 1915defm V_CMPX_LE_F16 : VOPCX_Real_gfx10<0x0db>; 1916defm V_CMPX_GT_F16 : VOPCX_Real_gfx10<0x0dc>; 1917defm V_CMPX_LG_F16 : VOPCX_Real_gfx10<0x0dd>; 1918defm V_CMPX_GE_F16 : VOPCX_Real_gfx10<0x0de>; 1919defm V_CMPX_O_F16 : VOPCX_Real_gfx10<0x0df>; 1920defm V_CMP_U_F16 : VOPC_Real_gfx10<0x0e8>; 1921defm V_CMP_NGE_F16 : VOPC_Real_gfx10<0x0e9>; 1922defm V_CMP_NLG_F16 : VOPC_Real_gfx10<0x0ea>; 1923defm V_CMP_NGT_F16 : VOPC_Real_gfx10<0x0eb>; 1924defm V_CMP_NLE_F16 : VOPC_Real_gfx10<0x0ec>; 1925defm V_CMP_NEQ_F16 : VOPC_Real_gfx10<0x0ed>; 1926defm V_CMP_NLT_F16 : VOPC_Real_gfx10<0x0ee>; 1927defm V_CMP_TRU_F16 : VOPC_Real_gfx10<0x0ef>; 1928defm V_CMPX_U_F16 : VOPCX_Real_gfx10<0x0f8>; 1929defm V_CMPX_NGE_F16 : VOPCX_Real_gfx10<0x0f9>; 1930defm V_CMPX_NLG_F16 : VOPCX_Real_gfx10<0x0fa>; 1931defm V_CMPX_NGT_F16 : VOPCX_Real_gfx10<0x0fb>; 1932defm V_CMPX_NLE_F16 : VOPCX_Real_gfx10<0x0fc>; 1933defm V_CMPX_NEQ_F16 : VOPCX_Real_gfx10<0x0fd>; 1934defm V_CMPX_NLT_F16 : VOPCX_Real_gfx10<0x0fe>; 1935defm V_CMPX_TRU_F16 : VOPCX_Real_gfx10<0x0ff>; 1936 1937//===----------------------------------------------------------------------===// 1938// GFX6, GFX7, GFX10. 1939//===----------------------------------------------------------------------===// 1940 1941let AssemblerPredicate = isGFX6GFX7 in { 1942 multiclass VOPC_Real_gfx6_gfx7<bits<9> op> { 1943 let DecoderNamespace = "GFX6GFX7" in { 1944 def _e32_gfx6_gfx7 : 1945 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>, 1946 VOPCe<op{7-0}>; 1947 def _e64_gfx6_gfx7 : 1948 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 1949 VOP3a_gfx6_gfx7<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1950 // Encoding used for VOPC instructions encoded as VOP3 differs from 1951 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. 1952 bits<8> sdst; 1953 let Inst{7-0} = sdst; 1954 } 1955 } // End DecoderNamespace = "GFX6GFX7" 1956 1957 defm : VOPCInstAliases<NAME, "gfx6_gfx7">; 1958 } 1959} // End AssemblerPredicate = isGFX6GFX7 1960 1961multiclass VOPC_Real_gfx6_gfx7_gfx10<bits<9> op> : 1962 VOPC_Real_gfx6_gfx7<op>, VOPC_Real_gfx10<op>; 1963 1964multiclass VOPCX_Real_gfx6_gfx7<bits<9> op> : 1965 VOPC_Real_gfx6_gfx7<op>; 1966 1967multiclass VOPCX_Real_gfx6_gfx7_gfx10 <bits<9> op> : 1968 VOPC_Real_gfx6_gfx7<op>, VOPCX_Real_gfx10<op>; 1969 1970multiclass VOPC_Real_gfx6_gfx7_gfx10_gfx11<bits<9> op> : 1971 VOPC_Real_gfx6_gfx7_gfx10<op>, VOPC_Real_gfx11<op>; 1972 1973multiclass VOPCX_Real_gfx6_gfx7_gfx10_gfx11<bits<9> op> : 1974 VOPCX_Real_gfx6_gfx7_gfx10<op>, VOPCX_Real_gfx11<op>; 1975 1976defm V_CMP_F_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x000>; 1977defm V_CMP_LT_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x001>; 1978defm V_CMP_EQ_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x002>; 1979defm V_CMP_LE_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x003>; 1980defm V_CMP_GT_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x004>; 1981defm V_CMP_LG_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x005>; 1982defm V_CMP_GE_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x006>; 1983defm V_CMP_O_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x007>; 1984defm V_CMP_U_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x008>; 1985defm V_CMP_NGE_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x009>; 1986defm V_CMP_NLG_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00a>; 1987defm V_CMP_NGT_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00b>; 1988defm V_CMP_NLE_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00c>; 1989defm V_CMP_NEQ_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00d>; 1990defm V_CMP_NLT_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00e>; 1991defm V_CMP_TRU_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00f>; 1992defm V_CMPX_F_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x010>; 1993defm V_CMPX_LT_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x011>; 1994defm V_CMPX_EQ_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x012>; 1995defm V_CMPX_LE_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x013>; 1996defm V_CMPX_GT_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x014>; 1997defm V_CMPX_LG_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x015>; 1998defm V_CMPX_GE_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x016>; 1999defm V_CMPX_O_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x017>; 2000defm V_CMPX_U_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x018>; 2001defm V_CMPX_NGE_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x019>; 2002defm V_CMPX_NLG_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01a>; 2003defm V_CMPX_NGT_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01b>; 2004defm V_CMPX_NLE_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01c>; 2005defm V_CMPX_NEQ_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01d>; 2006defm V_CMPX_NLT_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01e>; 2007defm V_CMPX_TRU_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01f>; 2008defm V_CMP_F_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x020>; 2009defm V_CMP_LT_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x021>; 2010defm V_CMP_EQ_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x022>; 2011defm V_CMP_LE_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x023>; 2012defm V_CMP_GT_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x024>; 2013defm V_CMP_LG_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x025>; 2014defm V_CMP_GE_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x026>; 2015defm V_CMP_O_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x027>; 2016defm V_CMP_U_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x028>; 2017defm V_CMP_NGE_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x029>; 2018defm V_CMP_NLG_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02a>; 2019defm V_CMP_NGT_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02b>; 2020defm V_CMP_NLE_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02c>; 2021defm V_CMP_NEQ_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02d>; 2022defm V_CMP_NLT_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02e>; 2023defm V_CMP_TRU_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x02f>; 2024defm V_CMPX_F_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x030>; 2025defm V_CMPX_LT_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x031>; 2026defm V_CMPX_EQ_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x032>; 2027defm V_CMPX_LE_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x033>; 2028defm V_CMPX_GT_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x034>; 2029defm V_CMPX_LG_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x035>; 2030defm V_CMPX_GE_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x036>; 2031defm V_CMPX_O_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x037>; 2032defm V_CMPX_U_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x038>; 2033defm V_CMPX_NGE_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x039>; 2034defm V_CMPX_NLG_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03a>; 2035defm V_CMPX_NGT_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03b>; 2036defm V_CMPX_NLE_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03c>; 2037defm V_CMPX_NEQ_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03d>; 2038defm V_CMPX_NLT_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03e>; 2039defm V_CMPX_TRU_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03f>; 2040defm V_CMPS_F_F32 : VOPC_Real_gfx6_gfx7<0x040>; 2041defm V_CMPS_LT_F32 : VOPC_Real_gfx6_gfx7<0x041>; 2042defm V_CMPS_EQ_F32 : VOPC_Real_gfx6_gfx7<0x042>; 2043defm V_CMPS_LE_F32 : VOPC_Real_gfx6_gfx7<0x043>; 2044defm V_CMPS_GT_F32 : VOPC_Real_gfx6_gfx7<0x044>; 2045defm V_CMPS_LG_F32 : VOPC_Real_gfx6_gfx7<0x045>; 2046defm V_CMPS_GE_F32 : VOPC_Real_gfx6_gfx7<0x046>; 2047defm V_CMPS_O_F32 : VOPC_Real_gfx6_gfx7<0x047>; 2048defm V_CMPS_U_F32 : VOPC_Real_gfx6_gfx7<0x048>; 2049defm V_CMPS_NGE_F32 : VOPC_Real_gfx6_gfx7<0x049>; 2050defm V_CMPS_NLG_F32 : VOPC_Real_gfx6_gfx7<0x04a>; 2051defm V_CMPS_NGT_F32 : VOPC_Real_gfx6_gfx7<0x04b>; 2052defm V_CMPS_NLE_F32 : VOPC_Real_gfx6_gfx7<0x04c>; 2053defm V_CMPS_NEQ_F32 : VOPC_Real_gfx6_gfx7<0x04d>; 2054defm V_CMPS_NLT_F32 : VOPC_Real_gfx6_gfx7<0x04e>; 2055defm V_CMPS_TRU_F32 : VOPC_Real_gfx6_gfx7<0x04f>; 2056defm V_CMPSX_F_F32 : VOPCX_Real_gfx6_gfx7<0x050>; 2057defm V_CMPSX_LT_F32 : VOPCX_Real_gfx6_gfx7<0x051>; 2058defm V_CMPSX_EQ_F32 : VOPCX_Real_gfx6_gfx7<0x052>; 2059defm V_CMPSX_LE_F32 : VOPCX_Real_gfx6_gfx7<0x053>; 2060defm V_CMPSX_GT_F32 : VOPCX_Real_gfx6_gfx7<0x054>; 2061defm V_CMPSX_LG_F32 : VOPCX_Real_gfx6_gfx7<0x055>; 2062defm V_CMPSX_GE_F32 : VOPCX_Real_gfx6_gfx7<0x056>; 2063defm V_CMPSX_O_F32 : VOPCX_Real_gfx6_gfx7<0x057>; 2064defm V_CMPSX_U_F32 : VOPCX_Real_gfx6_gfx7<0x058>; 2065defm V_CMPSX_NGE_F32 : VOPCX_Real_gfx6_gfx7<0x059>; 2066defm V_CMPSX_NLG_F32 : VOPCX_Real_gfx6_gfx7<0x05a>; 2067defm V_CMPSX_NGT_F32 : VOPCX_Real_gfx6_gfx7<0x05b>; 2068defm V_CMPSX_NLE_F32 : VOPCX_Real_gfx6_gfx7<0x05c>; 2069defm V_CMPSX_NEQ_F32 : VOPCX_Real_gfx6_gfx7<0x05d>; 2070defm V_CMPSX_NLT_F32 : VOPCX_Real_gfx6_gfx7<0x05e>; 2071defm V_CMPSX_TRU_F32 : VOPCX_Real_gfx6_gfx7<0x05f>; 2072defm V_CMPS_F_F64 : VOPC_Real_gfx6_gfx7<0x060>; 2073defm V_CMPS_LT_F64 : VOPC_Real_gfx6_gfx7<0x061>; 2074defm V_CMPS_EQ_F64 : VOPC_Real_gfx6_gfx7<0x062>; 2075defm V_CMPS_LE_F64 : VOPC_Real_gfx6_gfx7<0x063>; 2076defm V_CMPS_GT_F64 : VOPC_Real_gfx6_gfx7<0x064>; 2077defm V_CMPS_LG_F64 : VOPC_Real_gfx6_gfx7<0x065>; 2078defm V_CMPS_GE_F64 : VOPC_Real_gfx6_gfx7<0x066>; 2079defm V_CMPS_O_F64 : VOPC_Real_gfx6_gfx7<0x067>; 2080defm V_CMPS_U_F64 : VOPC_Real_gfx6_gfx7<0x068>; 2081defm V_CMPS_NGE_F64 : VOPC_Real_gfx6_gfx7<0x069>; 2082defm V_CMPS_NLG_F64 : VOPC_Real_gfx6_gfx7<0x06a>; 2083defm V_CMPS_NGT_F64 : VOPC_Real_gfx6_gfx7<0x06b>; 2084defm V_CMPS_NLE_F64 : VOPC_Real_gfx6_gfx7<0x06c>; 2085defm V_CMPS_NEQ_F64 : VOPC_Real_gfx6_gfx7<0x06d>; 2086defm V_CMPS_NLT_F64 : VOPC_Real_gfx6_gfx7<0x06e>; 2087defm V_CMPS_TRU_F64 : VOPC_Real_gfx6_gfx7<0x06f>; 2088defm V_CMPSX_F_F64 : VOPCX_Real_gfx6_gfx7<0x070>; 2089defm V_CMPSX_LT_F64 : VOPCX_Real_gfx6_gfx7<0x071>; 2090defm V_CMPSX_EQ_F64 : VOPCX_Real_gfx6_gfx7<0x072>; 2091defm V_CMPSX_LE_F64 : VOPCX_Real_gfx6_gfx7<0x073>; 2092defm V_CMPSX_GT_F64 : VOPCX_Real_gfx6_gfx7<0x074>; 2093defm V_CMPSX_LG_F64 : VOPCX_Real_gfx6_gfx7<0x075>; 2094defm V_CMPSX_GE_F64 : VOPCX_Real_gfx6_gfx7<0x076>; 2095defm V_CMPSX_O_F64 : VOPCX_Real_gfx6_gfx7<0x077>; 2096defm V_CMPSX_U_F64 : VOPCX_Real_gfx6_gfx7<0x078>; 2097defm V_CMPSX_NGE_F64 : VOPCX_Real_gfx6_gfx7<0x079>; 2098defm V_CMPSX_NLG_F64 : VOPCX_Real_gfx6_gfx7<0x07a>; 2099defm V_CMPSX_NGT_F64 : VOPCX_Real_gfx6_gfx7<0x07b>; 2100defm V_CMPSX_NLE_F64 : VOPCX_Real_gfx6_gfx7<0x07c>; 2101defm V_CMPSX_NEQ_F64 : VOPCX_Real_gfx6_gfx7<0x07d>; 2102defm V_CMPSX_NLT_F64 : VOPCX_Real_gfx6_gfx7<0x07e>; 2103defm V_CMPSX_TRU_F64 : VOPCX_Real_gfx6_gfx7<0x07f>; 2104defm V_CMP_F_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x080>; 2105defm V_CMP_LT_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x081>; 2106defm V_CMP_EQ_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x082>; 2107defm V_CMP_LE_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x083>; 2108defm V_CMP_GT_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x084>; 2109defm V_CMP_NE_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x085>; 2110defm V_CMP_GE_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x086>; 2111defm V_CMP_T_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x087>; 2112defm V_CMP_CLASS_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x088>; 2113defm V_CMPX_F_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x090>; 2114defm V_CMPX_LT_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x091>; 2115defm V_CMPX_EQ_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x092>; 2116defm V_CMPX_LE_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x093>; 2117defm V_CMPX_GT_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x094>; 2118defm V_CMPX_NE_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x095>; 2119defm V_CMPX_GE_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x096>; 2120defm V_CMPX_T_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x097>; 2121defm V_CMPX_CLASS_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x098>; 2122defm V_CMP_F_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a0>; 2123defm V_CMP_LT_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a1>; 2124defm V_CMP_EQ_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a2>; 2125defm V_CMP_LE_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a3>; 2126defm V_CMP_GT_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a4>; 2127defm V_CMP_NE_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a5>; 2128defm V_CMP_GE_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a6>; 2129defm V_CMP_T_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a7>; 2130defm V_CMP_CLASS_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a8>; 2131defm V_CMPX_F_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b0>; 2132defm V_CMPX_LT_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b1>; 2133defm V_CMPX_EQ_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b2>; 2134defm V_CMPX_LE_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b3>; 2135defm V_CMPX_GT_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b4>; 2136defm V_CMPX_NE_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b5>; 2137defm V_CMPX_GE_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b6>; 2138defm V_CMPX_T_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b7>; 2139defm V_CMPX_CLASS_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b8>; 2140defm V_CMP_F_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c0>; 2141defm V_CMP_LT_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c1>; 2142defm V_CMP_EQ_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c2>; 2143defm V_CMP_LE_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c3>; 2144defm V_CMP_GT_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c4>; 2145defm V_CMP_NE_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c5>; 2146defm V_CMP_GE_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c6>; 2147defm V_CMP_T_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c7>; 2148defm V_CMPX_F_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d0>; 2149defm V_CMPX_LT_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d1>; 2150defm V_CMPX_EQ_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d2>; 2151defm V_CMPX_LE_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d3>; 2152defm V_CMPX_GT_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d4>; 2153defm V_CMPX_NE_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d5>; 2154defm V_CMPX_GE_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d6>; 2155defm V_CMPX_T_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d7>; 2156defm V_CMP_F_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e0>; 2157defm V_CMP_LT_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e1>; 2158defm V_CMP_EQ_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e2>; 2159defm V_CMP_LE_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e3>; 2160defm V_CMP_GT_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e4>; 2161defm V_CMP_NE_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e5>; 2162defm V_CMP_GE_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e6>; 2163defm V_CMP_T_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e7>; 2164defm V_CMPX_F_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f0>; 2165defm V_CMPX_LT_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f1>; 2166defm V_CMPX_EQ_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f2>; 2167defm V_CMPX_LE_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f3>; 2168defm V_CMPX_GT_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f4>; 2169defm V_CMPX_NE_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f5>; 2170defm V_CMPX_GE_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f6>; 2171defm V_CMPX_T_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f7>; 2172 2173//===----------------------------------------------------------------------===// 2174// GFX8, GFX9 (VI). 2175//===----------------------------------------------------------------------===// 2176 2177multiclass VOPC_Real_vi <bits<10> op> { 2178 let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { 2179 def _e32_vi : 2180 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>, 2181 VOPCe<op{7-0}>; 2182 2183 def _e64_vi : 2184 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 2185 VOP3a_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 2186 // Encoding used for VOPC instructions encoded as VOP3 2187 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst 2188 bits<8> sdst; 2189 let Inst{7-0} = sdst; 2190 } 2191 } 2192 2193 if !cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA then 2194 def _sdwa_vi : 2195 VOP_SDWA_Real <!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>, 2196 VOPC_SDWAe <op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 2197 2198 if !cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then 2199 def _sdwa_gfx9 : 2200 VOP_SDWA9_Real <!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>, 2201 VOPC_SDWA9e <op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 2202 2203 let AssemblerPredicate = isGFX8GFX9 in { 2204 defm : VOPCInstAliases<NAME, "vi">; 2205 } 2206} 2207 2208defm V_CMP_CLASS_F32 : VOPC_Real_vi <0x10>; 2209defm V_CMPX_CLASS_F32 : VOPC_Real_vi <0x11>; 2210defm V_CMP_CLASS_F64 : VOPC_Real_vi <0x12>; 2211defm V_CMPX_CLASS_F64 : VOPC_Real_vi <0x13>; 2212defm V_CMP_CLASS_F16 : VOPC_Real_vi <0x14>; 2213defm V_CMPX_CLASS_F16 : VOPC_Real_vi <0x15>; 2214 2215defm V_CMP_F_F16 : VOPC_Real_vi <0x20>; 2216defm V_CMP_LT_F16 : VOPC_Real_vi <0x21>; 2217defm V_CMP_EQ_F16 : VOPC_Real_vi <0x22>; 2218defm V_CMP_LE_F16 : VOPC_Real_vi <0x23>; 2219defm V_CMP_GT_F16 : VOPC_Real_vi <0x24>; 2220defm V_CMP_LG_F16 : VOPC_Real_vi <0x25>; 2221defm V_CMP_GE_F16 : VOPC_Real_vi <0x26>; 2222defm V_CMP_O_F16 : VOPC_Real_vi <0x27>; 2223defm V_CMP_U_F16 : VOPC_Real_vi <0x28>; 2224defm V_CMP_NGE_F16 : VOPC_Real_vi <0x29>; 2225defm V_CMP_NLG_F16 : VOPC_Real_vi <0x2a>; 2226defm V_CMP_NGT_F16 : VOPC_Real_vi <0x2b>; 2227defm V_CMP_NLE_F16 : VOPC_Real_vi <0x2c>; 2228defm V_CMP_NEQ_F16 : VOPC_Real_vi <0x2d>; 2229defm V_CMP_NLT_F16 : VOPC_Real_vi <0x2e>; 2230defm V_CMP_TRU_F16 : VOPC_Real_vi <0x2f>; 2231 2232defm V_CMPX_F_F16 : VOPC_Real_vi <0x30>; 2233defm V_CMPX_LT_F16 : VOPC_Real_vi <0x31>; 2234defm V_CMPX_EQ_F16 : VOPC_Real_vi <0x32>; 2235defm V_CMPX_LE_F16 : VOPC_Real_vi <0x33>; 2236defm V_CMPX_GT_F16 : VOPC_Real_vi <0x34>; 2237defm V_CMPX_LG_F16 : VOPC_Real_vi <0x35>; 2238defm V_CMPX_GE_F16 : VOPC_Real_vi <0x36>; 2239defm V_CMPX_O_F16 : VOPC_Real_vi <0x37>; 2240defm V_CMPX_U_F16 : VOPC_Real_vi <0x38>; 2241defm V_CMPX_NGE_F16 : VOPC_Real_vi <0x39>; 2242defm V_CMPX_NLG_F16 : VOPC_Real_vi <0x3a>; 2243defm V_CMPX_NGT_F16 : VOPC_Real_vi <0x3b>; 2244defm V_CMPX_NLE_F16 : VOPC_Real_vi <0x3c>; 2245defm V_CMPX_NEQ_F16 : VOPC_Real_vi <0x3d>; 2246defm V_CMPX_NLT_F16 : VOPC_Real_vi <0x3e>; 2247defm V_CMPX_TRU_F16 : VOPC_Real_vi <0x3f>; 2248 2249defm V_CMP_F_F32 : VOPC_Real_vi <0x40>; 2250defm V_CMP_LT_F32 : VOPC_Real_vi <0x41>; 2251defm V_CMP_EQ_F32 : VOPC_Real_vi <0x42>; 2252defm V_CMP_LE_F32 : VOPC_Real_vi <0x43>; 2253defm V_CMP_GT_F32 : VOPC_Real_vi <0x44>; 2254defm V_CMP_LG_F32 : VOPC_Real_vi <0x45>; 2255defm V_CMP_GE_F32 : VOPC_Real_vi <0x46>; 2256defm V_CMP_O_F32 : VOPC_Real_vi <0x47>; 2257defm V_CMP_U_F32 : VOPC_Real_vi <0x48>; 2258defm V_CMP_NGE_F32 : VOPC_Real_vi <0x49>; 2259defm V_CMP_NLG_F32 : VOPC_Real_vi <0x4a>; 2260defm V_CMP_NGT_F32 : VOPC_Real_vi <0x4b>; 2261defm V_CMP_NLE_F32 : VOPC_Real_vi <0x4c>; 2262defm V_CMP_NEQ_F32 : VOPC_Real_vi <0x4d>; 2263defm V_CMP_NLT_F32 : VOPC_Real_vi <0x4e>; 2264defm V_CMP_TRU_F32 : VOPC_Real_vi <0x4f>; 2265 2266defm V_CMPX_F_F32 : VOPC_Real_vi <0x50>; 2267defm V_CMPX_LT_F32 : VOPC_Real_vi <0x51>; 2268defm V_CMPX_EQ_F32 : VOPC_Real_vi <0x52>; 2269defm V_CMPX_LE_F32 : VOPC_Real_vi <0x53>; 2270defm V_CMPX_GT_F32 : VOPC_Real_vi <0x54>; 2271defm V_CMPX_LG_F32 : VOPC_Real_vi <0x55>; 2272defm V_CMPX_GE_F32 : VOPC_Real_vi <0x56>; 2273defm V_CMPX_O_F32 : VOPC_Real_vi <0x57>; 2274defm V_CMPX_U_F32 : VOPC_Real_vi <0x58>; 2275defm V_CMPX_NGE_F32 : VOPC_Real_vi <0x59>; 2276defm V_CMPX_NLG_F32 : VOPC_Real_vi <0x5a>; 2277defm V_CMPX_NGT_F32 : VOPC_Real_vi <0x5b>; 2278defm V_CMPX_NLE_F32 : VOPC_Real_vi <0x5c>; 2279defm V_CMPX_NEQ_F32 : VOPC_Real_vi <0x5d>; 2280defm V_CMPX_NLT_F32 : VOPC_Real_vi <0x5e>; 2281defm V_CMPX_TRU_F32 : VOPC_Real_vi <0x5f>; 2282 2283defm V_CMP_F_F64 : VOPC_Real_vi <0x60>; 2284defm V_CMP_LT_F64 : VOPC_Real_vi <0x61>; 2285defm V_CMP_EQ_F64 : VOPC_Real_vi <0x62>; 2286defm V_CMP_LE_F64 : VOPC_Real_vi <0x63>; 2287defm V_CMP_GT_F64 : VOPC_Real_vi <0x64>; 2288defm V_CMP_LG_F64 : VOPC_Real_vi <0x65>; 2289defm V_CMP_GE_F64 : VOPC_Real_vi <0x66>; 2290defm V_CMP_O_F64 : VOPC_Real_vi <0x67>; 2291defm V_CMP_U_F64 : VOPC_Real_vi <0x68>; 2292defm V_CMP_NGE_F64 : VOPC_Real_vi <0x69>; 2293defm V_CMP_NLG_F64 : VOPC_Real_vi <0x6a>; 2294defm V_CMP_NGT_F64 : VOPC_Real_vi <0x6b>; 2295defm V_CMP_NLE_F64 : VOPC_Real_vi <0x6c>; 2296defm V_CMP_NEQ_F64 : VOPC_Real_vi <0x6d>; 2297defm V_CMP_NLT_F64 : VOPC_Real_vi <0x6e>; 2298defm V_CMP_TRU_F64 : VOPC_Real_vi <0x6f>; 2299 2300defm V_CMPX_F_F64 : VOPC_Real_vi <0x70>; 2301defm V_CMPX_LT_F64 : VOPC_Real_vi <0x71>; 2302defm V_CMPX_EQ_F64 : VOPC_Real_vi <0x72>; 2303defm V_CMPX_LE_F64 : VOPC_Real_vi <0x73>; 2304defm V_CMPX_GT_F64 : VOPC_Real_vi <0x74>; 2305defm V_CMPX_LG_F64 : VOPC_Real_vi <0x75>; 2306defm V_CMPX_GE_F64 : VOPC_Real_vi <0x76>; 2307defm V_CMPX_O_F64 : VOPC_Real_vi <0x77>; 2308defm V_CMPX_U_F64 : VOPC_Real_vi <0x78>; 2309defm V_CMPX_NGE_F64 : VOPC_Real_vi <0x79>; 2310defm V_CMPX_NLG_F64 : VOPC_Real_vi <0x7a>; 2311defm V_CMPX_NGT_F64 : VOPC_Real_vi <0x7b>; 2312defm V_CMPX_NLE_F64 : VOPC_Real_vi <0x7c>; 2313defm V_CMPX_NEQ_F64 : VOPC_Real_vi <0x7d>; 2314defm V_CMPX_NLT_F64 : VOPC_Real_vi <0x7e>; 2315defm V_CMPX_TRU_F64 : VOPC_Real_vi <0x7f>; 2316 2317defm V_CMP_F_I16 : VOPC_Real_vi <0xa0>; 2318defm V_CMP_LT_I16 : VOPC_Real_vi <0xa1>; 2319defm V_CMP_EQ_I16 : VOPC_Real_vi <0xa2>; 2320defm V_CMP_LE_I16 : VOPC_Real_vi <0xa3>; 2321defm V_CMP_GT_I16 : VOPC_Real_vi <0xa4>; 2322defm V_CMP_NE_I16 : VOPC_Real_vi <0xa5>; 2323defm V_CMP_GE_I16 : VOPC_Real_vi <0xa6>; 2324defm V_CMP_T_I16 : VOPC_Real_vi <0xa7>; 2325 2326defm V_CMP_F_U16 : VOPC_Real_vi <0xa8>; 2327defm V_CMP_LT_U16 : VOPC_Real_vi <0xa9>; 2328defm V_CMP_EQ_U16 : VOPC_Real_vi <0xaa>; 2329defm V_CMP_LE_U16 : VOPC_Real_vi <0xab>; 2330defm V_CMP_GT_U16 : VOPC_Real_vi <0xac>; 2331defm V_CMP_NE_U16 : VOPC_Real_vi <0xad>; 2332defm V_CMP_GE_U16 : VOPC_Real_vi <0xae>; 2333defm V_CMP_T_U16 : VOPC_Real_vi <0xaf>; 2334 2335defm V_CMPX_F_I16 : VOPC_Real_vi <0xb0>; 2336defm V_CMPX_LT_I16 : VOPC_Real_vi <0xb1>; 2337defm V_CMPX_EQ_I16 : VOPC_Real_vi <0xb2>; 2338defm V_CMPX_LE_I16 : VOPC_Real_vi <0xb3>; 2339defm V_CMPX_GT_I16 : VOPC_Real_vi <0xb4>; 2340defm V_CMPX_NE_I16 : VOPC_Real_vi <0xb5>; 2341defm V_CMPX_GE_I16 : VOPC_Real_vi <0xb6>; 2342defm V_CMPX_T_I16 : VOPC_Real_vi <0xb7>; 2343 2344defm V_CMPX_F_U16 : VOPC_Real_vi <0xb8>; 2345defm V_CMPX_LT_U16 : VOPC_Real_vi <0xb9>; 2346defm V_CMPX_EQ_U16 : VOPC_Real_vi <0xba>; 2347defm V_CMPX_LE_U16 : VOPC_Real_vi <0xbb>; 2348defm V_CMPX_GT_U16 : VOPC_Real_vi <0xbc>; 2349defm V_CMPX_NE_U16 : VOPC_Real_vi <0xbd>; 2350defm V_CMPX_GE_U16 : VOPC_Real_vi <0xbe>; 2351defm V_CMPX_T_U16 : VOPC_Real_vi <0xbf>; 2352 2353defm V_CMP_F_I32 : VOPC_Real_vi <0xc0>; 2354defm V_CMP_LT_I32 : VOPC_Real_vi <0xc1>; 2355defm V_CMP_EQ_I32 : VOPC_Real_vi <0xc2>; 2356defm V_CMP_LE_I32 : VOPC_Real_vi <0xc3>; 2357defm V_CMP_GT_I32 : VOPC_Real_vi <0xc4>; 2358defm V_CMP_NE_I32 : VOPC_Real_vi <0xc5>; 2359defm V_CMP_GE_I32 : VOPC_Real_vi <0xc6>; 2360defm V_CMP_T_I32 : VOPC_Real_vi <0xc7>; 2361 2362defm V_CMPX_F_I32 : VOPC_Real_vi <0xd0>; 2363defm V_CMPX_LT_I32 : VOPC_Real_vi <0xd1>; 2364defm V_CMPX_EQ_I32 : VOPC_Real_vi <0xd2>; 2365defm V_CMPX_LE_I32 : VOPC_Real_vi <0xd3>; 2366defm V_CMPX_GT_I32 : VOPC_Real_vi <0xd4>; 2367defm V_CMPX_NE_I32 : VOPC_Real_vi <0xd5>; 2368defm V_CMPX_GE_I32 : VOPC_Real_vi <0xd6>; 2369defm V_CMPX_T_I32 : VOPC_Real_vi <0xd7>; 2370 2371defm V_CMP_F_I64 : VOPC_Real_vi <0xe0>; 2372defm V_CMP_LT_I64 : VOPC_Real_vi <0xe1>; 2373defm V_CMP_EQ_I64 : VOPC_Real_vi <0xe2>; 2374defm V_CMP_LE_I64 : VOPC_Real_vi <0xe3>; 2375defm V_CMP_GT_I64 : VOPC_Real_vi <0xe4>; 2376defm V_CMP_NE_I64 : VOPC_Real_vi <0xe5>; 2377defm V_CMP_GE_I64 : VOPC_Real_vi <0xe6>; 2378defm V_CMP_T_I64 : VOPC_Real_vi <0xe7>; 2379 2380defm V_CMPX_F_I64 : VOPC_Real_vi <0xf0>; 2381defm V_CMPX_LT_I64 : VOPC_Real_vi <0xf1>; 2382defm V_CMPX_EQ_I64 : VOPC_Real_vi <0xf2>; 2383defm V_CMPX_LE_I64 : VOPC_Real_vi <0xf3>; 2384defm V_CMPX_GT_I64 : VOPC_Real_vi <0xf4>; 2385defm V_CMPX_NE_I64 : VOPC_Real_vi <0xf5>; 2386defm V_CMPX_GE_I64 : VOPC_Real_vi <0xf6>; 2387defm V_CMPX_T_I64 : VOPC_Real_vi <0xf7>; 2388 2389defm V_CMP_F_U32 : VOPC_Real_vi <0xc8>; 2390defm V_CMP_LT_U32 : VOPC_Real_vi <0xc9>; 2391defm V_CMP_EQ_U32 : VOPC_Real_vi <0xca>; 2392defm V_CMP_LE_U32 : VOPC_Real_vi <0xcb>; 2393defm V_CMP_GT_U32 : VOPC_Real_vi <0xcc>; 2394defm V_CMP_NE_U32 : VOPC_Real_vi <0xcd>; 2395defm V_CMP_GE_U32 : VOPC_Real_vi <0xce>; 2396defm V_CMP_T_U32 : VOPC_Real_vi <0xcf>; 2397 2398defm V_CMPX_F_U32 : VOPC_Real_vi <0xd8>; 2399defm V_CMPX_LT_U32 : VOPC_Real_vi <0xd9>; 2400defm V_CMPX_EQ_U32 : VOPC_Real_vi <0xda>; 2401defm V_CMPX_LE_U32 : VOPC_Real_vi <0xdb>; 2402defm V_CMPX_GT_U32 : VOPC_Real_vi <0xdc>; 2403defm V_CMPX_NE_U32 : VOPC_Real_vi <0xdd>; 2404defm V_CMPX_GE_U32 : VOPC_Real_vi <0xde>; 2405defm V_CMPX_T_U32 : VOPC_Real_vi <0xdf>; 2406 2407defm V_CMP_F_U64 : VOPC_Real_vi <0xe8>; 2408defm V_CMP_LT_U64 : VOPC_Real_vi <0xe9>; 2409defm V_CMP_EQ_U64 : VOPC_Real_vi <0xea>; 2410defm V_CMP_LE_U64 : VOPC_Real_vi <0xeb>; 2411defm V_CMP_GT_U64 : VOPC_Real_vi <0xec>; 2412defm V_CMP_NE_U64 : VOPC_Real_vi <0xed>; 2413defm V_CMP_GE_U64 : VOPC_Real_vi <0xee>; 2414defm V_CMP_T_U64 : VOPC_Real_vi <0xef>; 2415 2416defm V_CMPX_F_U64 : VOPC_Real_vi <0xf8>; 2417defm V_CMPX_LT_U64 : VOPC_Real_vi <0xf9>; 2418defm V_CMPX_EQ_U64 : VOPC_Real_vi <0xfa>; 2419defm V_CMPX_LE_U64 : VOPC_Real_vi <0xfb>; 2420defm V_CMPX_GT_U64 : VOPC_Real_vi <0xfc>; 2421defm V_CMPX_NE_U64 : VOPC_Real_vi <0xfd>; 2422defm V_CMPX_GE_U64 : VOPC_Real_vi <0xfe>; 2423defm V_CMPX_T_U64 : VOPC_Real_vi <0xff>; 2424