1//===-- VOPCInstructions.td - Vector Instruction Definitions --------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Encodings 11//===----------------------------------------------------------------------===// 12 13class VOPCe <bits<8> op> : Enc32 { 14 bits<9> src0; 15 bits<8> src1; 16 17 let Inst{8-0} = src0; 18 let Inst{16-9} = src1; 19 let Inst{24-17} = op; 20 let Inst{31-25} = 0x3e; 21} 22 23class VOPC_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAe <P> { 24 bits<8> src1; 25 26 let Inst{8-0} = 0xf9; // sdwa 27 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 28 let Inst{24-17} = op; 29 let Inst{31-25} = 0x3e; // encoding 30} 31 32class VOPC_SDWA9e <bits<8> op, VOPProfile P> : VOP_SDWA9Be <P> { 33 bits<9> src1; 34 35 let Inst{8-0} = 0xf9; // sdwa 36 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); 37 let Inst{24-17} = op; 38 let Inst{31-25} = 0x3e; // encoding 39 let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr 40} 41 42 43//===----------------------------------------------------------------------===// 44// VOPC classes 45//===----------------------------------------------------------------------===// 46 47// VOPC instructions are a special case because for the 32-bit 48// encoding, we want to display the implicit vcc write as if it were 49// an explicit $dst. 50class VOPC_Profile<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> : 51 VOPProfile <[i1, vt0, vt1, untyped]> { 52 // We want to exclude instructions with 64bit operands 53 let HasExtDPP = getHasVOP3DPP<DstVT, Src0VT, Src1VT, Src2VT>.ret; 54 let Asm32 = "$src0, $src1"; 55 56 let AsmDPP = !if (HasModifiers, 57 "$src0_modifiers, $src1_modifiers " 58 "$dpp_ctrl$row_mask$bank_mask$bound_ctrl", 59 "$src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl"); 60 let AsmDPP8 = "$src0, $src1 $dpp8$fi"; 61 let AsmDPP16 = AsmDPP#"$fi"; 62 // VOPC DPP Instructions do not need an old operand 63 let TieRegDPP = ""; 64 let InsDPP = getInsDPP<VOPDstOperand<Src0DPP.RegClass>, Src0DPP, Src1DPP, Src2DPP, 65 NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP, 66 Src2ModDPP, 0/*HasOld*/>.ret; 67 let InsDPP16 = getInsDPP16<VOPDstOperand<Src0DPP.RegClass>, Src0DPP, Src1DPP, Src2DPP, 68 NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP, 69 Src2ModDPP, 0/*HasOld*/>.ret; 70 let InsDPP8 = getInsDPP8<VOPDstOperand<Src0DPP.RegClass>, Src0DPP, Src1DPP, Src2DPP, 71 NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP, 72 Src2ModDPP, 0/*HasOld*/>.ret; 73 74 // The destination for 32-bit encoding is implicit. 75 let HasDst32 = 0; 76 // VOPC disallows dst_sel and dst_unused as they have no effect on destination 77 let EmitDstSel = 0; 78 let Outs64 = (outs VOPDstS64orS32:$sdst); 79 let OutsVOP3DPP = Outs64; 80 let OutsVOP3DPP8 = Outs64; 81 let InsVOP3DPP = getInsVOP3DPP<InsVOP3Base, Src0VOP3DPP, NumSrcArgs, 0/*HasOld*/>.ret; 82 let InsVOP3DPP16 = getInsVOP3DPP16<InsVOP3Base, Src0VOP3DPP, NumSrcArgs, 0/*HasOld*/>.ret; 83 let InsVOP3DPP8 = getInsVOP3DPP8<InsVOP3Base, Src0VOP3DPP, NumSrcArgs, 0/*HasOld*/>.ret; 84 list<SchedReadWrite> Schedule = sched; 85} 86 87multiclass VOPC_Profile_t16<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> { 88 def NAME : VOPC_Profile<sched, vt0, vt1>; 89 def _t16 : VOPC_Profile<sched, vt0, vt1> { 90 let IsTrue16 = 1; 91 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 92 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 93 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 94 let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 95 let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret; 96 let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret; 97 let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret; 98 } 99} 100 101class VOPC_NoSdst_Profile<list<SchedReadWrite> sched, ValueType vt0, 102 ValueType vt1 = vt0> : 103 VOPC_Profile<sched, vt0, vt1> { 104 let Outs64 = (outs ); 105 let OutsVOP3DPP = Outs64; 106 let OutsVOP3DPP8 = Outs64; 107 let OutsSDWA = (outs ); 108 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 109 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 110 src0_sel:$src0_sel, src1_sel:$src1_sel); 111 let AsmVOP3Base = !if(Src0VT.isFP, "$src0_modifiers, $src1_modifiers$clamp", 112 "$src0, $src1"); 113 let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel"; 114 let EmitDst = 0; 115} 116 117multiclass VOPC_NoSdst_Profile_t16<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> { 118 def NAME : VOPC_NoSdst_Profile<sched, vt0, vt1>; 119 def _t16 : VOPC_NoSdst_Profile<sched, vt0, vt1> { 120 let IsTrue16 = 1; 121 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 122 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 123 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 124 let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 125 let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret; 126 let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret; 127 let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret; 128 } 129} 130 131class VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[], 132 bit DefVcc = 1> : 133 InstSI<(outs), P.Ins32, "", pattern>, 134 VOP <opName>, 135 SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> { 136 137 let isPseudo = 1; 138 let isCodeGenOnly = 1; 139 let UseNamedOperandTable = 1; 140 141 string Mnemonic = opName; 142 string AsmOperands = P.Asm32; 143 144 let Size = 4; 145 let mayLoad = 0; 146 let mayStore = 0; 147 let hasSideEffects = 0; 148 149 let ReadsModeReg = P.Src0VT.isFP; 150 151 let VALU = 1; 152 let VOPC = 1; 153 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 154 let Defs = !if(DefVcc, [VCC], []); 155 156 VOPProfile Pfl = P; 157} 158 159class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily, string asm_name = ps.PseudoInstr> : 160 InstSI <ps.OutOperandList, ps.InOperandList, asm_name # " " # ps.AsmOperands, []>, 161 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 162 163 let VALU = 1; 164 let VOPC = 1; 165 let isPseudo = 0; 166 let isCodeGenOnly = 0; 167 168 let Constraints = ps.Constraints; 169 let DisableEncoding = ps.DisableEncoding; 170 171 // copy relevant pseudo op flags 172 let SubtargetPredicate = ps.SubtargetPredicate; 173 let AsmMatchConverter = ps.AsmMatchConverter; 174 let Constraints = ps.Constraints; 175 let DisableEncoding = ps.DisableEncoding; 176 let TSFlags = ps.TSFlags; 177 let UseNamedOperandTable = ps.UseNamedOperandTable; 178 let Uses = ps.Uses; 179 let Defs = ps.Defs; 180 let SchedRW = ps.SchedRW; 181 let mayLoad = ps.mayLoad; 182 let mayStore = ps.mayStore; 183} 184 185class VOPC_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> : 186 VOP_SDWA_Pseudo <OpName, P, pattern> { 187 let AsmMatchConverter = "cvtSdwaVOPC"; 188} 189 190// This class is used only with VOPC instructions. Use $sdst for out operand 191class VOPCInstAlias <VOP3_Pseudo ps, Instruction inst, 192 string Asm32 = ps.Pfl.Asm32, string real_name = ps.OpName, 193 VOPProfile p = ps.Pfl> : 194 InstAlias <real_name#" "#Asm32, (inst)>, PredicateControl { 195 196 field bit isCompare; 197 field bit isCommutable; 198 199 let ResultInst = 200 !if (p.HasDst32, 201 !if (!eq(p.NumSrcArgs, 0), 202 // 1 dst, 0 src 203 (inst p.DstRC:$sdst), 204 !if (!eq(p.NumSrcArgs, 1), 205 // 1 dst, 1 src 206 (inst p.DstRC:$sdst, p.Src0RC32:$src0), 207 !if (!eq(p.NumSrcArgs, 2), 208 // 1 dst, 2 src 209 (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1), 210 // else - unreachable 211 (inst)))), 212 // else 213 !if (!eq(p.NumSrcArgs, 2), 214 // 0 dst, 2 src 215 (inst p.Src0RC32:$src0, p.Src1RC32:$src1), 216 !if (!eq(p.NumSrcArgs, 1), 217 // 0 dst, 1 src 218 (inst p.Src0RC32:$src1), 219 // else 220 // 0 dst, 0 src 221 (inst)))); 222 223 let AsmVariantName = AMDGPUAsmVariants.Default; 224 let SubtargetPredicate = AssemblerPredicate; 225 226 string DecoderNamespace; // dummy 227} 228 229multiclass VOPCInstAliases <string old_name, string Arch, string real_name = old_name, string mnemonic_from = real_name> { 230 def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"), 231 !cast<Instruction>(real_name#"_e32_"#Arch), 232 !cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32, 233 mnemonic_from>; 234 let WaveSizePredicate = isWave32 in { 235 def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"), 236 !cast<Instruction>(real_name#"_e32_"#Arch), 237 "vcc_lo, "#!cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32, 238 mnemonic_from>; 239 } 240 let WaveSizePredicate = isWave64 in { 241 def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"), 242 !cast<Instruction>(real_name#"_e32_"#Arch), 243 "vcc, "#!cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32, 244 mnemonic_from>; 245 } 246} 247 248multiclass VOPCXInstAliases <string old_name, string Arch, string real_name = old_name, string mnemonic_from = real_name> { 249 def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"), 250 !cast<Instruction>(real_name#"_e32_"#Arch), 251 !cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32, 252 mnemonic_from>; 253} 254 255class getVOPCPat64 <SDPatternOperator cond, VOPProfile P> : LetDummies { 256 list<dag> ret = !if(P.HasModifiers, 257 [(set i1:$sdst, 258 (setcc (P.Src0VT 259 !if(P.HasOMod, 260 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 261 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))), 262 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), 263 cond))], 264 [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]); 265} 266 267class VCMPXNoSDstTable <bit has_sdst, string Name> { 268 bit HasSDst = has_sdst; 269 string NoSDstOp = Name; 270} 271 272class VCMPVCMPXTable <string Name> { 273 bit IsVCMPX = 0; 274 string VCMPOp = Name; 275} 276 277multiclass VOPC_Pseudos <string opName, 278 VOPC_Profile P, 279 SDPatternOperator cond = COND_NULL, 280 string revOp = opName, 281 bit DefExec = 0> { 282 283 def _e32 : VOPC_Pseudo <opName, P>, 284 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>, 285 VCMPXNoSDstTable<1, opName#"_e32">, 286 VCMPVCMPXTable<opName#"_e32"> { 287 let Defs = !if(DefExec, [VCC, EXEC], [VCC]); 288 let SchedRW = P.Schedule; 289 let isConvergent = DefExec; 290 let isCompare = 1; 291 let isCommutable = 1; 292 } 293 294 def _e64 : VOP3_Pseudo<opName, P, getVOPCPat64<cond, P>.ret>, 295 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>, 296 VCMPXNoSDstTable<1, opName#"_e64">, 297 VCMPVCMPXTable<opName#"_e64"> { 298 let Defs = !if(DefExec, [EXEC], []); 299 let SchedRW = P.Schedule; 300 let isCompare = 1; 301 let isCommutable = 1; 302 } 303 304 if P.HasExtSDWA then 305 def _sdwa : VOPC_SDWA_Pseudo <opName, P> { 306 let Defs = !if(DefExec, [EXEC], []); 307 let SchedRW = P.Schedule; 308 let isConvergent = DefExec; 309 let isCompare = 1; 310 } 311 312 let SubtargetPredicate = isGFX11Plus in { 313 if P.HasExtDPP then 314 def _e32_dpp : VOP_DPP_Pseudo<opName, P> { 315 let Defs = !if(DefExec, [VCC, EXEC], [VCC]); 316 let SchedRW = P.Schedule; 317 let isConvergent = DefExec; 318 let isCompare = 1; 319 let VOPC = 1; 320 let Constraints = ""; 321 } 322 if P.HasExtVOP3DPP then 323 def _e64_dpp : VOP3_DPP_Pseudo<opName, P> { 324 let Defs = !if(DefExec, [EXEC], []); 325 let SchedRW = P.Schedule; 326 let isCompare = 1; 327 let Constraints = ""; 328 } 329 } // end SubtargetPredicate = isGFX11Plus 330 331} 332 333let SubtargetPredicate = HasSdstCMPX in { 334multiclass VOPCX_Pseudos <string opName, 335 VOPC_Profile P, VOPC_Profile P_NoSDst, 336 SDPatternOperator cond = COND_NULL, 337 string revOp = opName> : 338 VOPC_Pseudos <opName, P, cond, revOp, 1> { 339 340 def _nosdst_e32 : VOPC_Pseudo <opName#"_nosdst", P_NoSDst, [], 0>, 341 Commutable_REV<revOp#"_nosdst_e32", !eq(revOp, opName)>, 342 VCMPXNoSDstTable<0, opName#"_e32">, 343 VCMPVCMPXTable<!subst("v_cmpx", "v_cmp", opName#"_e32")> { 344 let Defs = [EXEC]; 345 let SchedRW = P_NoSDst.Schedule; 346 let isConvergent = 1; 347 let isCompare = 1; 348 let isCommutable = 1; 349 let SubtargetPredicate = HasNoSdstCMPX; 350 let IsVCMPX = 1; 351 } 352 353 def _nosdst_e64 : VOP3_Pseudo<opName#"_nosdst", P_NoSDst>, 354 Commutable_REV<revOp#"_nosdst_e64", !eq(revOp, opName)>, 355 VCMPXNoSDstTable<0, opName#"_e64">, 356 VCMPVCMPXTable<!subst("v_cmpx", "v_cmp", opName#"_e64")> { 357 let Defs = [EXEC]; 358 let SchedRW = P_NoSDst.Schedule; 359 let isCompare = 1; 360 let isCommutable = 1; 361 let SubtargetPredicate = HasNoSdstCMPX; 362 let IsVCMPX = 1; 363 } 364 365 if P_NoSDst.HasExtSDWA then 366 def _nosdst_sdwa : VOPC_SDWA_Pseudo <opName#"_nosdst", P_NoSDst> { 367 let Defs = [EXEC]; 368 let SchedRW = P_NoSDst.Schedule; 369 let isConvergent = 1; 370 let isCompare = 1; 371 let SubtargetPredicate = HasNoSdstCMPX; 372 } 373 374 let SubtargetPredicate = isGFX11Plus in { 375 if P.HasExtDPP then 376 def _nosdst_e32_dpp : VOP_DPP_Pseudo<opName#"_nosdst", P_NoSDst> { 377 let Defs = [EXEC]; 378 let SchedRW = P_NoSDst.Schedule; 379 let isConvergent = 1; 380 let isCompare = 1; 381 let VOPC = 1; 382 let Constraints = ""; 383 } 384 if P.HasExtVOP3DPP then 385 def _nosdst_e64_dpp : VOP3_DPP_Pseudo<opName#"_nosdst", P_NoSDst> { 386 let Defs = [EXEC]; 387 let SchedRW = P_NoSDst.Schedule; 388 let isCompare = 1; 389 let Constraints = ""; 390 } 391 } // end SubtargetPredicate = isGFX11Plus 392} 393} // End SubtargetPredicate = HasSdstCMPX 394 395defm VOPC_I1_F16_F16 : VOPC_Profile_t16<[Write32Bit], f16>; 396def VOPC_I1_F32_F32 : VOPC_Profile<[Write32Bit], f32>; 397def VOPC_I1_F64_F64 : VOPC_Profile<[WriteDoubleAdd], f64>; 398defm VOPC_I1_I16_I16 : VOPC_Profile_t16<[Write32Bit], i16>; 399def VOPC_I1_I32_I32 : VOPC_Profile<[Write32Bit], i32>; 400def VOPC_I1_I64_I64 : VOPC_Profile<[Write64Bit], i64>; 401 402defm VOPC_F16_F16 : VOPC_NoSdst_Profile_t16<[Write32Bit], f16>; 403def VOPC_F32_F32 : VOPC_NoSdst_Profile<[Write32Bit], f32>; 404def VOPC_F64_F64 : VOPC_NoSdst_Profile<[Write64Bit], f64>; 405defm VOPC_I16_I16 : VOPC_NoSdst_Profile_t16<[Write32Bit], i16>; 406def VOPC_I32_I32 : VOPC_NoSdst_Profile<[Write32Bit], i32>; 407def VOPC_I64_I64 : VOPC_NoSdst_Profile<[Write64Bit], i64>; 408 409multiclass VOPC_F16 <string opName, SDPatternOperator cond = COND_NULL, 410 string revOp = opName> { 411 let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in { 412 defm NAME : VOPC_Pseudos <opName, VOPC_I1_F16_F16, cond, revOp, 0>; 413 } 414 let OtherPredicates = [HasTrue16BitInsts] in { 415 defm _t16 : VOPC_Pseudos <opName#"_t16", VOPC_I1_F16_F16_t16, cond, revOp#"_t16", 0>; 416 } 417} 418 419multiclass VOPC_F32 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> : 420 VOPC_Pseudos <opName, VOPC_I1_F32_F32, cond, revOp, 0>; 421 422multiclass VOPC_F64 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> : 423 VOPC_Pseudos <opName, VOPC_I1_F64_F64, cond, revOp, 0>; 424 425multiclass VOPC_I16 <string opName, SDPatternOperator cond = COND_NULL, 426 string revOp = opName> { 427 let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in { 428 defm NAME : VOPC_Pseudos <opName, VOPC_I1_I16_I16, cond, revOp, 0>; 429 } 430 let OtherPredicates = [HasTrue16BitInsts] in { 431 defm _t16 : VOPC_Pseudos <opName#"_t16", VOPC_I1_I16_I16_t16, cond, revOp#"_t16", 0>; 432 } 433} 434 435multiclass VOPC_I32 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> : 436 VOPC_Pseudos <opName, VOPC_I1_I32_I32, cond, revOp, 0>; 437 438let IsInvalidSingleUseConsumer = 1 in { 439 multiclass VOPC_I64 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> : 440 VOPC_Pseudos <opName, VOPC_I1_I64_I64, cond, revOp, 0>; 441} 442 443multiclass VOPCX_F16<string opName, string revOp = opName> { 444 let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in { 445 defm NAME : VOPCX_Pseudos <opName, VOPC_I1_F16_F16, VOPC_F16_F16, COND_NULL, revOp>; 446 } 447 let OtherPredicates = [HasTrue16BitInsts] in { 448 defm _t16 : VOPCX_Pseudos <opName#"_t16", VOPC_I1_F16_F16_t16, VOPC_F16_F16_t16, COND_NULL, revOp#"_t16">; 449 } 450} 451 452multiclass VOPCX_F32 <string opName, string revOp = opName> : 453 VOPCX_Pseudos <opName, VOPC_I1_F32_F32, VOPC_F32_F32, COND_NULL, revOp>; 454 455multiclass VOPCX_F64 <string opName, string revOp = opName> : 456 VOPCX_Pseudos <opName, VOPC_I1_F64_F64, VOPC_F64_F64, COND_NULL, revOp>; 457 458multiclass VOPCX_I16<string opName, string revOp = opName> { 459 let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in { 460 defm NAME : VOPCX_Pseudos <opName, VOPC_I1_I16_I16, VOPC_I16_I16, COND_NULL, revOp>; 461 } 462 let OtherPredicates = [HasTrue16BitInsts] in { 463 defm _t16 : VOPCX_Pseudos <opName#"_t16", VOPC_I1_I16_I16_t16, VOPC_I16_I16_t16, COND_NULL, revOp#"_t16">; 464 } 465} 466 467multiclass VOPCX_I32 <string opName, string revOp = opName> : 468 VOPCX_Pseudos <opName, VOPC_I1_I32_I32, VOPC_I32_I32, COND_NULL, revOp>; 469 470let IsInvalidSingleUseConsumer = 1 in { 471 multiclass VOPCX_I64 <string opName, string revOp = opName> : 472 VOPCX_Pseudos <opName, VOPC_I1_I64_I64, VOPC_I64_I64, COND_NULL, revOp>; 473} 474 475 476//===----------------------------------------------------------------------===// 477// Compare instructions 478//===----------------------------------------------------------------------===// 479 480defm V_CMP_F_F32 : VOPC_F32 <"v_cmp_f_f32">; 481defm V_CMP_LT_F32 : VOPC_F32 <"v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">; 482defm V_CMP_EQ_F32 : VOPC_F32 <"v_cmp_eq_f32", COND_OEQ>; 483defm V_CMP_LE_F32 : VOPC_F32 <"v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">; 484defm V_CMP_GT_F32 : VOPC_F32 <"v_cmp_gt_f32", COND_OGT>; 485defm V_CMP_LG_F32 : VOPC_F32 <"v_cmp_lg_f32", COND_ONE>; 486defm V_CMP_GE_F32 : VOPC_F32 <"v_cmp_ge_f32", COND_OGE>; 487defm V_CMP_O_F32 : VOPC_F32 <"v_cmp_o_f32", COND_O>; 488defm V_CMP_U_F32 : VOPC_F32 <"v_cmp_u_f32", COND_UO>; 489defm V_CMP_NGE_F32 : VOPC_F32 <"v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">; 490defm V_CMP_NLG_F32 : VOPC_F32 <"v_cmp_nlg_f32", COND_UEQ>; 491defm V_CMP_NGT_F32 : VOPC_F32 <"v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">; 492defm V_CMP_NLE_F32 : VOPC_F32 <"v_cmp_nle_f32", COND_UGT>; 493defm V_CMP_NEQ_F32 : VOPC_F32 <"v_cmp_neq_f32", COND_UNE>; 494defm V_CMP_NLT_F32 : VOPC_F32 <"v_cmp_nlt_f32", COND_UGE>; 495defm V_CMP_TRU_F32 : VOPC_F32 <"v_cmp_tru_f32">; 496 497defm V_CMPX_F_F32 : VOPCX_F32 <"v_cmpx_f_f32">; 498defm V_CMPX_LT_F32 : VOPCX_F32 <"v_cmpx_lt_f32", "v_cmpx_gt_f32">; 499defm V_CMPX_EQ_F32 : VOPCX_F32 <"v_cmpx_eq_f32">; 500defm V_CMPX_LE_F32 : VOPCX_F32 <"v_cmpx_le_f32", "v_cmpx_ge_f32">; 501defm V_CMPX_GT_F32 : VOPCX_F32 <"v_cmpx_gt_f32">; 502defm V_CMPX_LG_F32 : VOPCX_F32 <"v_cmpx_lg_f32">; 503defm V_CMPX_GE_F32 : VOPCX_F32 <"v_cmpx_ge_f32">; 504defm V_CMPX_O_F32 : VOPCX_F32 <"v_cmpx_o_f32">; 505defm V_CMPX_U_F32 : VOPCX_F32 <"v_cmpx_u_f32">; 506defm V_CMPX_NGE_F32 : VOPCX_F32 <"v_cmpx_nge_f32", "v_cmpx_nle_f32">; 507defm V_CMPX_NLG_F32 : VOPCX_F32 <"v_cmpx_nlg_f32">; 508defm V_CMPX_NGT_F32 : VOPCX_F32 <"v_cmpx_ngt_f32", "v_cmpx_nlt_f32">; 509defm V_CMPX_NLE_F32 : VOPCX_F32 <"v_cmpx_nle_f32">; 510defm V_CMPX_NEQ_F32 : VOPCX_F32 <"v_cmpx_neq_f32">; 511defm V_CMPX_NLT_F32 : VOPCX_F32 <"v_cmpx_nlt_f32">; 512defm V_CMPX_TRU_F32 : VOPCX_F32 <"v_cmpx_tru_f32">; 513 514defm V_CMP_F_F64 : VOPC_F64 <"v_cmp_f_f64">; 515defm V_CMP_LT_F64 : VOPC_F64 <"v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">; 516defm V_CMP_EQ_F64 : VOPC_F64 <"v_cmp_eq_f64", COND_OEQ>; 517defm V_CMP_LE_F64 : VOPC_F64 <"v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">; 518defm V_CMP_GT_F64 : VOPC_F64 <"v_cmp_gt_f64", COND_OGT>; 519defm V_CMP_LG_F64 : VOPC_F64 <"v_cmp_lg_f64", COND_ONE>; 520defm V_CMP_GE_F64 : VOPC_F64 <"v_cmp_ge_f64", COND_OGE>; 521defm V_CMP_O_F64 : VOPC_F64 <"v_cmp_o_f64", COND_O>; 522defm V_CMP_U_F64 : VOPC_F64 <"v_cmp_u_f64", COND_UO>; 523defm V_CMP_NGE_F64 : VOPC_F64 <"v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">; 524defm V_CMP_NLG_F64 : VOPC_F64 <"v_cmp_nlg_f64", COND_UEQ>; 525defm V_CMP_NGT_F64 : VOPC_F64 <"v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">; 526defm V_CMP_NLE_F64 : VOPC_F64 <"v_cmp_nle_f64", COND_UGT>; 527defm V_CMP_NEQ_F64 : VOPC_F64 <"v_cmp_neq_f64", COND_UNE>; 528defm V_CMP_NLT_F64 : VOPC_F64 <"v_cmp_nlt_f64", COND_UGE>; 529defm V_CMP_TRU_F64 : VOPC_F64 <"v_cmp_tru_f64">; 530 531defm V_CMPX_F_F64 : VOPCX_F64 <"v_cmpx_f_f64">; 532defm V_CMPX_LT_F64 : VOPCX_F64 <"v_cmpx_lt_f64", "v_cmpx_gt_f64">; 533defm V_CMPX_EQ_F64 : VOPCX_F64 <"v_cmpx_eq_f64">; 534defm V_CMPX_LE_F64 : VOPCX_F64 <"v_cmpx_le_f64", "v_cmpx_ge_f64">; 535defm V_CMPX_GT_F64 : VOPCX_F64 <"v_cmpx_gt_f64">; 536defm V_CMPX_LG_F64 : VOPCX_F64 <"v_cmpx_lg_f64">; 537defm V_CMPX_GE_F64 : VOPCX_F64 <"v_cmpx_ge_f64">; 538defm V_CMPX_O_F64 : VOPCX_F64 <"v_cmpx_o_f64">; 539defm V_CMPX_U_F64 : VOPCX_F64 <"v_cmpx_u_f64">; 540defm V_CMPX_NGE_F64 : VOPCX_F64 <"v_cmpx_nge_f64", "v_cmpx_nle_f64">; 541defm V_CMPX_NLG_F64 : VOPCX_F64 <"v_cmpx_nlg_f64">; 542defm V_CMPX_NGT_F64 : VOPCX_F64 <"v_cmpx_ngt_f64", "v_cmpx_nlt_f64">; 543defm V_CMPX_NLE_F64 : VOPCX_F64 <"v_cmpx_nle_f64">; 544defm V_CMPX_NEQ_F64 : VOPCX_F64 <"v_cmpx_neq_f64">; 545defm V_CMPX_NLT_F64 : VOPCX_F64 <"v_cmpx_nlt_f64">; 546defm V_CMPX_TRU_F64 : VOPCX_F64 <"v_cmpx_tru_f64">; 547 548let SubtargetPredicate = isGFX6GFX7 in { 549 550defm V_CMPS_F_F32 : VOPC_F32 <"v_cmps_f_f32">; 551defm V_CMPS_LT_F32 : VOPC_F32 <"v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">; 552defm V_CMPS_EQ_F32 : VOPC_F32 <"v_cmps_eq_f32">; 553defm V_CMPS_LE_F32 : VOPC_F32 <"v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">; 554defm V_CMPS_GT_F32 : VOPC_F32 <"v_cmps_gt_f32">; 555defm V_CMPS_LG_F32 : VOPC_F32 <"v_cmps_lg_f32">; 556defm V_CMPS_GE_F32 : VOPC_F32 <"v_cmps_ge_f32">; 557defm V_CMPS_O_F32 : VOPC_F32 <"v_cmps_o_f32">; 558defm V_CMPS_U_F32 : VOPC_F32 <"v_cmps_u_f32">; 559defm V_CMPS_NGE_F32 : VOPC_F32 <"v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">; 560defm V_CMPS_NLG_F32 : VOPC_F32 <"v_cmps_nlg_f32">; 561defm V_CMPS_NGT_F32 : VOPC_F32 <"v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">; 562defm V_CMPS_NLE_F32 : VOPC_F32 <"v_cmps_nle_f32">; 563defm V_CMPS_NEQ_F32 : VOPC_F32 <"v_cmps_neq_f32">; 564defm V_CMPS_NLT_F32 : VOPC_F32 <"v_cmps_nlt_f32">; 565defm V_CMPS_TRU_F32 : VOPC_F32 <"v_cmps_tru_f32">; 566 567defm V_CMPSX_F_F32 : VOPCX_F32 <"v_cmpsx_f_f32">; 568defm V_CMPSX_LT_F32 : VOPCX_F32 <"v_cmpsx_lt_f32", "v_cmpsx_gt_f32">; 569defm V_CMPSX_EQ_F32 : VOPCX_F32 <"v_cmpsx_eq_f32">; 570defm V_CMPSX_LE_F32 : VOPCX_F32 <"v_cmpsx_le_f32", "v_cmpsx_ge_f32">; 571defm V_CMPSX_GT_F32 : VOPCX_F32 <"v_cmpsx_gt_f32">; 572defm V_CMPSX_LG_F32 : VOPCX_F32 <"v_cmpsx_lg_f32">; 573defm V_CMPSX_GE_F32 : VOPCX_F32 <"v_cmpsx_ge_f32">; 574defm V_CMPSX_O_F32 : VOPCX_F32 <"v_cmpsx_o_f32">; 575defm V_CMPSX_U_F32 : VOPCX_F32 <"v_cmpsx_u_f32">; 576defm V_CMPSX_NGE_F32 : VOPCX_F32 <"v_cmpsx_nge_f32", "v_cmpsx_nle_f32">; 577defm V_CMPSX_NLG_F32 : VOPCX_F32 <"v_cmpsx_nlg_f32">; 578defm V_CMPSX_NGT_F32 : VOPCX_F32 <"v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">; 579defm V_CMPSX_NLE_F32 : VOPCX_F32 <"v_cmpsx_nle_f32">; 580defm V_CMPSX_NEQ_F32 : VOPCX_F32 <"v_cmpsx_neq_f32">; 581defm V_CMPSX_NLT_F32 : VOPCX_F32 <"v_cmpsx_nlt_f32">; 582defm V_CMPSX_TRU_F32 : VOPCX_F32 <"v_cmpsx_tru_f32">; 583 584defm V_CMPS_F_F64 : VOPC_F64 <"v_cmps_f_f64">; 585defm V_CMPS_LT_F64 : VOPC_F64 <"v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">; 586defm V_CMPS_EQ_F64 : VOPC_F64 <"v_cmps_eq_f64">; 587defm V_CMPS_LE_F64 : VOPC_F64 <"v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">; 588defm V_CMPS_GT_F64 : VOPC_F64 <"v_cmps_gt_f64">; 589defm V_CMPS_LG_F64 : VOPC_F64 <"v_cmps_lg_f64">; 590defm V_CMPS_GE_F64 : VOPC_F64 <"v_cmps_ge_f64">; 591defm V_CMPS_O_F64 : VOPC_F64 <"v_cmps_o_f64">; 592defm V_CMPS_U_F64 : VOPC_F64 <"v_cmps_u_f64">; 593defm V_CMPS_NGE_F64 : VOPC_F64 <"v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">; 594defm V_CMPS_NLG_F64 : VOPC_F64 <"v_cmps_nlg_f64">; 595defm V_CMPS_NGT_F64 : VOPC_F64 <"v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">; 596defm V_CMPS_NLE_F64 : VOPC_F64 <"v_cmps_nle_f64">; 597defm V_CMPS_NEQ_F64 : VOPC_F64 <"v_cmps_neq_f64">; 598defm V_CMPS_NLT_F64 : VOPC_F64 <"v_cmps_nlt_f64">; 599defm V_CMPS_TRU_F64 : VOPC_F64 <"v_cmps_tru_f64">; 600 601defm V_CMPSX_F_F64 : VOPCX_F64 <"v_cmpsx_f_f64">; 602defm V_CMPSX_LT_F64 : VOPCX_F64 <"v_cmpsx_lt_f64", "v_cmpsx_gt_f64">; 603defm V_CMPSX_EQ_F64 : VOPCX_F64 <"v_cmpsx_eq_f64">; 604defm V_CMPSX_LE_F64 : VOPCX_F64 <"v_cmpsx_le_f64", "v_cmpsx_ge_f64">; 605defm V_CMPSX_GT_F64 : VOPCX_F64 <"v_cmpsx_gt_f64">; 606defm V_CMPSX_LG_F64 : VOPCX_F64 <"v_cmpsx_lg_f64">; 607defm V_CMPSX_GE_F64 : VOPCX_F64 <"v_cmpsx_ge_f64">; 608defm V_CMPSX_O_F64 : VOPCX_F64 <"v_cmpsx_o_f64">; 609defm V_CMPSX_U_F64 : VOPCX_F64 <"v_cmpsx_u_f64">; 610defm V_CMPSX_NGE_F64 : VOPCX_F64 <"v_cmpsx_nge_f64", "v_cmpsx_nle_f64">; 611defm V_CMPSX_NLG_F64 : VOPCX_F64 <"v_cmpsx_nlg_f64">; 612defm V_CMPSX_NGT_F64 : VOPCX_F64 <"v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">; 613defm V_CMPSX_NLE_F64 : VOPCX_F64 <"v_cmpsx_nle_f64">; 614defm V_CMPSX_NEQ_F64 : VOPCX_F64 <"v_cmpsx_neq_f64">; 615defm V_CMPSX_NLT_F64 : VOPCX_F64 <"v_cmpsx_nlt_f64">; 616defm V_CMPSX_TRU_F64 : VOPCX_F64 <"v_cmpsx_tru_f64">; 617 618} // End SubtargetPredicate = isGFX6GFX7 619 620let SubtargetPredicate = Has16BitInsts in { 621 622defm V_CMP_F_F16 : VOPC_F16 <"v_cmp_f_f16">; 623defm V_CMP_LT_F16 : VOPC_F16 <"v_cmp_lt_f16", COND_OLT, "v_cmp_gt_f16">; 624defm V_CMP_EQ_F16 : VOPC_F16 <"v_cmp_eq_f16", COND_OEQ>; 625defm V_CMP_LE_F16 : VOPC_F16 <"v_cmp_le_f16", COND_OLE, "v_cmp_ge_f16">; 626defm V_CMP_GT_F16 : VOPC_F16 <"v_cmp_gt_f16", COND_OGT>; 627defm V_CMP_LG_F16 : VOPC_F16 <"v_cmp_lg_f16", COND_ONE>; 628defm V_CMP_GE_F16 : VOPC_F16 <"v_cmp_ge_f16", COND_OGE>; 629defm V_CMP_O_F16 : VOPC_F16 <"v_cmp_o_f16", COND_O>; 630defm V_CMP_U_F16 : VOPC_F16 <"v_cmp_u_f16", COND_UO>; 631defm V_CMP_NGE_F16 : VOPC_F16 <"v_cmp_nge_f16", COND_ULT, "v_cmp_nle_f16">; 632defm V_CMP_NLG_F16 : VOPC_F16 <"v_cmp_nlg_f16", COND_UEQ>; 633defm V_CMP_NGT_F16 : VOPC_F16 <"v_cmp_ngt_f16", COND_ULE, "v_cmp_nlt_f16">; 634defm V_CMP_NLE_F16 : VOPC_F16 <"v_cmp_nle_f16", COND_UGT>; 635defm V_CMP_NEQ_F16 : VOPC_F16 <"v_cmp_neq_f16", COND_UNE>; 636defm V_CMP_NLT_F16 : VOPC_F16 <"v_cmp_nlt_f16", COND_UGE>; 637defm V_CMP_TRU_F16 : VOPC_F16 <"v_cmp_tru_f16">; 638 639defm V_CMPX_F_F16 : VOPCX_F16 <"v_cmpx_f_f16">; 640defm V_CMPX_LT_F16 : VOPCX_F16 <"v_cmpx_lt_f16", "v_cmpx_gt_f16">; 641defm V_CMPX_EQ_F16 : VOPCX_F16 <"v_cmpx_eq_f16">; 642defm V_CMPX_LE_F16 : VOPCX_F16 <"v_cmpx_le_f16", "v_cmpx_ge_f16">; 643defm V_CMPX_GT_F16 : VOPCX_F16 <"v_cmpx_gt_f16">; 644defm V_CMPX_LG_F16 : VOPCX_F16 <"v_cmpx_lg_f16">; 645defm V_CMPX_GE_F16 : VOPCX_F16 <"v_cmpx_ge_f16">; 646defm V_CMPX_O_F16 : VOPCX_F16 <"v_cmpx_o_f16">; 647defm V_CMPX_U_F16 : VOPCX_F16 <"v_cmpx_u_f16">; 648defm V_CMPX_NGE_F16 : VOPCX_F16 <"v_cmpx_nge_f16", "v_cmpx_nle_f16">; 649defm V_CMPX_NLG_F16 : VOPCX_F16 <"v_cmpx_nlg_f16">; 650defm V_CMPX_NGT_F16 : VOPCX_F16 <"v_cmpx_ngt_f16", "v_cmpx_nlt_f16">; 651defm V_CMPX_NLE_F16 : VOPCX_F16 <"v_cmpx_nle_f16">; 652defm V_CMPX_NEQ_F16 : VOPCX_F16 <"v_cmpx_neq_f16">; 653defm V_CMPX_NLT_F16 : VOPCX_F16 <"v_cmpx_nlt_f16">; 654defm V_CMPX_TRU_F16 : VOPCX_F16 <"v_cmpx_tru_f16">; 655 656defm V_CMP_F_I16 : VOPC_I16 <"v_cmp_f_i16">; 657defm V_CMP_LT_I16 : VOPC_I16 <"v_cmp_lt_i16", COND_SLT, "v_cmp_gt_i16">; 658defm V_CMP_EQ_I16 : VOPC_I16 <"v_cmp_eq_i16">; 659defm V_CMP_LE_I16 : VOPC_I16 <"v_cmp_le_i16", COND_SLE, "v_cmp_ge_i16">; 660defm V_CMP_GT_I16 : VOPC_I16 <"v_cmp_gt_i16", COND_SGT>; 661defm V_CMP_NE_I16 : VOPC_I16 <"v_cmp_ne_i16">; 662defm V_CMP_GE_I16 : VOPC_I16 <"v_cmp_ge_i16", COND_SGE>; 663defm V_CMP_T_I16 : VOPC_I16 <"v_cmp_t_i16">; 664 665defm V_CMP_F_U16 : VOPC_I16 <"v_cmp_f_u16">; 666defm V_CMP_LT_U16 : VOPC_I16 <"v_cmp_lt_u16", COND_ULT, "v_cmp_gt_u16">; 667defm V_CMP_EQ_U16 : VOPC_I16 <"v_cmp_eq_u16", COND_EQ>; 668defm V_CMP_LE_U16 : VOPC_I16 <"v_cmp_le_u16", COND_ULE, "v_cmp_ge_u16">; 669defm V_CMP_GT_U16 : VOPC_I16 <"v_cmp_gt_u16", COND_UGT>; 670defm V_CMP_NE_U16 : VOPC_I16 <"v_cmp_ne_u16", COND_NE>; 671defm V_CMP_GE_U16 : VOPC_I16 <"v_cmp_ge_u16", COND_UGE>; 672defm V_CMP_T_U16 : VOPC_I16 <"v_cmp_t_u16">; 673 674defm V_CMPX_F_I16 : VOPCX_I16 <"v_cmpx_f_i16">; 675defm V_CMPX_LT_I16 : VOPCX_I16 <"v_cmpx_lt_i16", "v_cmpx_gt_i16">; 676defm V_CMPX_EQ_I16 : VOPCX_I16 <"v_cmpx_eq_i16">; 677defm V_CMPX_LE_I16 : VOPCX_I16 <"v_cmpx_le_i16", "v_cmpx_ge_i16">; 678defm V_CMPX_GT_I16 : VOPCX_I16 <"v_cmpx_gt_i16">; 679defm V_CMPX_NE_I16 : VOPCX_I16 <"v_cmpx_ne_i16">; 680defm V_CMPX_GE_I16 : VOPCX_I16 <"v_cmpx_ge_i16">; 681defm V_CMPX_T_I16 : VOPCX_I16 <"v_cmpx_t_i16">; 682 683defm V_CMPX_F_U16 : VOPCX_I16 <"v_cmpx_f_u16">; 684defm V_CMPX_LT_U16 : VOPCX_I16 <"v_cmpx_lt_u16", "v_cmpx_gt_u16">; 685defm V_CMPX_EQ_U16 : VOPCX_I16 <"v_cmpx_eq_u16">; 686defm V_CMPX_LE_U16 : VOPCX_I16 <"v_cmpx_le_u16", "v_cmpx_ge_u16">; 687defm V_CMPX_GT_U16 : VOPCX_I16 <"v_cmpx_gt_u16">; 688defm V_CMPX_NE_U16 : VOPCX_I16 <"v_cmpx_ne_u16">; 689defm V_CMPX_GE_U16 : VOPCX_I16 <"v_cmpx_ge_u16">; 690defm V_CMPX_T_U16 : VOPCX_I16 <"v_cmpx_t_u16">; 691 692} // End SubtargetPredicate = Has16BitInsts 693 694defm V_CMP_F_I32 : VOPC_I32 <"v_cmp_f_i32">; 695defm V_CMP_LT_I32 : VOPC_I32 <"v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">; 696defm V_CMP_EQ_I32 : VOPC_I32 <"v_cmp_eq_i32">; 697defm V_CMP_LE_I32 : VOPC_I32 <"v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">; 698defm V_CMP_GT_I32 : VOPC_I32 <"v_cmp_gt_i32", COND_SGT>; 699defm V_CMP_NE_I32 : VOPC_I32 <"v_cmp_ne_i32">; 700defm V_CMP_GE_I32 : VOPC_I32 <"v_cmp_ge_i32", COND_SGE>; 701defm V_CMP_T_I32 : VOPC_I32 <"v_cmp_t_i32">; 702 703defm V_CMPX_F_I32 : VOPCX_I32 <"v_cmpx_f_i32">; 704defm V_CMPX_LT_I32 : VOPCX_I32 <"v_cmpx_lt_i32", "v_cmpx_gt_i32">; 705defm V_CMPX_EQ_I32 : VOPCX_I32 <"v_cmpx_eq_i32">; 706defm V_CMPX_LE_I32 : VOPCX_I32 <"v_cmpx_le_i32", "v_cmpx_ge_i32">; 707defm V_CMPX_GT_I32 : VOPCX_I32 <"v_cmpx_gt_i32">; 708defm V_CMPX_NE_I32 : VOPCX_I32 <"v_cmpx_ne_i32">; 709defm V_CMPX_GE_I32 : VOPCX_I32 <"v_cmpx_ge_i32">; 710defm V_CMPX_T_I32 : VOPCX_I32 <"v_cmpx_t_i32">; 711 712defm V_CMP_F_I64 : VOPC_I64 <"v_cmp_f_i64">; 713defm V_CMP_LT_I64 : VOPC_I64 <"v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">; 714defm V_CMP_EQ_I64 : VOPC_I64 <"v_cmp_eq_i64">; 715defm V_CMP_LE_I64 : VOPC_I64 <"v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">; 716defm V_CMP_GT_I64 : VOPC_I64 <"v_cmp_gt_i64", COND_SGT>; 717defm V_CMP_NE_I64 : VOPC_I64 <"v_cmp_ne_i64">; 718defm V_CMP_GE_I64 : VOPC_I64 <"v_cmp_ge_i64", COND_SGE>; 719defm V_CMP_T_I64 : VOPC_I64 <"v_cmp_t_i64">; 720 721defm V_CMPX_F_I64 : VOPCX_I64 <"v_cmpx_f_i64">; 722defm V_CMPX_LT_I64 : VOPCX_I64 <"v_cmpx_lt_i64", "v_cmpx_gt_i64">; 723defm V_CMPX_EQ_I64 : VOPCX_I64 <"v_cmpx_eq_i64">; 724defm V_CMPX_LE_I64 : VOPCX_I64 <"v_cmpx_le_i64", "v_cmpx_ge_i64">; 725defm V_CMPX_GT_I64 : VOPCX_I64 <"v_cmpx_gt_i64">; 726defm V_CMPX_NE_I64 : VOPCX_I64 <"v_cmpx_ne_i64">; 727defm V_CMPX_GE_I64 : VOPCX_I64 <"v_cmpx_ge_i64">; 728defm V_CMPX_T_I64 : VOPCX_I64 <"v_cmpx_t_i64">; 729 730defm V_CMP_F_U32 : VOPC_I32 <"v_cmp_f_u32">; 731defm V_CMP_LT_U32 : VOPC_I32 <"v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">; 732defm V_CMP_EQ_U32 : VOPC_I32 <"v_cmp_eq_u32", COND_EQ>; 733defm V_CMP_LE_U32 : VOPC_I32 <"v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">; 734defm V_CMP_GT_U32 : VOPC_I32 <"v_cmp_gt_u32", COND_UGT>; 735defm V_CMP_NE_U32 : VOPC_I32 <"v_cmp_ne_u32", COND_NE>; 736defm V_CMP_GE_U32 : VOPC_I32 <"v_cmp_ge_u32", COND_UGE>; 737defm V_CMP_T_U32 : VOPC_I32 <"v_cmp_t_u32">; 738 739defm V_CMPX_F_U32 : VOPCX_I32 <"v_cmpx_f_u32">; 740defm V_CMPX_LT_U32 : VOPCX_I32 <"v_cmpx_lt_u32", "v_cmpx_gt_u32">; 741defm V_CMPX_EQ_U32 : VOPCX_I32 <"v_cmpx_eq_u32">; 742defm V_CMPX_LE_U32 : VOPCX_I32 <"v_cmpx_le_u32", "v_cmpx_le_u32">; 743defm V_CMPX_GT_U32 : VOPCX_I32 <"v_cmpx_gt_u32">; 744defm V_CMPX_NE_U32 : VOPCX_I32 <"v_cmpx_ne_u32">; 745defm V_CMPX_GE_U32 : VOPCX_I32 <"v_cmpx_ge_u32">; 746defm V_CMPX_T_U32 : VOPCX_I32 <"v_cmpx_t_u32">; 747 748defm V_CMP_F_U64 : VOPC_I64 <"v_cmp_f_u64">; 749defm V_CMP_LT_U64 : VOPC_I64 <"v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">; 750defm V_CMP_EQ_U64 : VOPC_I64 <"v_cmp_eq_u64", COND_EQ>; 751defm V_CMP_LE_U64 : VOPC_I64 <"v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">; 752defm V_CMP_GT_U64 : VOPC_I64 <"v_cmp_gt_u64", COND_UGT>; 753defm V_CMP_NE_U64 : VOPC_I64 <"v_cmp_ne_u64", COND_NE>; 754defm V_CMP_GE_U64 : VOPC_I64 <"v_cmp_ge_u64", COND_UGE>; 755defm V_CMP_T_U64 : VOPC_I64 <"v_cmp_t_u64">; 756 757defm V_CMPX_F_U64 : VOPCX_I64 <"v_cmpx_f_u64">; 758defm V_CMPX_LT_U64 : VOPCX_I64 <"v_cmpx_lt_u64", "v_cmpx_gt_u64">; 759defm V_CMPX_EQ_U64 : VOPCX_I64 <"v_cmpx_eq_u64">; 760defm V_CMPX_LE_U64 : VOPCX_I64 <"v_cmpx_le_u64", "v_cmpx_ge_u64">; 761defm V_CMPX_GT_U64 : VOPCX_I64 <"v_cmpx_gt_u64">; 762defm V_CMPX_NE_U64 : VOPCX_I64 <"v_cmpx_ne_u64">; 763defm V_CMPX_GE_U64 : VOPCX_I64 <"v_cmpx_ge_u64">; 764defm V_CMPX_T_U64 : VOPCX_I64 <"v_cmpx_t_u64">; 765 766//===----------------------------------------------------------------------===// 767// Class instructions 768//===----------------------------------------------------------------------===// 769 770class VOPC_Class_Profile<list<SchedReadWrite> sched, ValueType src0VT, ValueType src1VT = i32> : 771 VOPC_Profile<sched, src0VT, src1VT> { 772 let AsmDPP = "$src0_modifiers, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; 773 let AsmDPP16 = AsmDPP#"$fi"; 774 let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0, Src1DPP:$src1, dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask, DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl); 775 let InsDPP16 = !con(InsDPP, (ins Dpp16FI:$fi)); 776 // DPP8 forbids modifiers and can inherit from VOPC_Profile 777 778 let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1); 779 dag InsPartVOP3DPP = (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0, VCSrc_b32:$src1); 780 let InsVOP3Base = !con(InsPartVOP3DPP, !if(HasOpSel, (ins op_sel0:$op_sel), 781 (ins))); 782 let AsmVOP3Base = "$sdst, $src0_modifiers, $src1"; 783 784 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 785 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 786 Clamp:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel); 787 788 let AsmSDWA = " vcc, $src0_modifiers, $src1_modifiers$clamp $src0_sel $src1_sel"; 789 let HasSrc1Mods = 0; 790 let HasClamp = 0; 791 let HasOMod = 0; 792} 793 794multiclass VOPC_Class_Profile_t16<list<SchedReadWrite> sched> { 795 def NAME : VOPC_Class_Profile<sched, f16>; 796 def _t16 : VOPC_Class_Profile<sched, f16, i16> { 797 let IsTrue16 = 1; 798 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 799 let Src1RC64 = VSrc_b32; 800 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 801 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 802 let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 803 let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret; 804 let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret; 805 let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret; 806 } 807} 808 809class VOPC_Class_NoSdst_Profile<list<SchedReadWrite> sched, ValueType src0VT, ValueType src1VT = i32> : 810 VOPC_Class_Profile<sched, src0VT, src1VT> { 811 let Outs64 = (outs ); 812 let OutsSDWA = (outs ); 813 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0, 814 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1, 815 src0_sel:$src0_sel, src1_sel:$src1_sel); 816 let AsmVOP3Base = "$src0_modifiers, $src1"; 817 let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel"; 818 let EmitDst = 0; 819} 820 821multiclass VOPC_Class_NoSdst_Profile_t16<list<SchedReadWrite> sched> { 822 def NAME : VOPC_Class_NoSdst_Profile<sched, f16>; 823 def _t16 : VOPC_Class_NoSdst_Profile<sched, f16, i16> { 824 let IsTrue16 = 1; 825 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 826 let Src1RC64 = VSrc_b32; 827 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 828 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 829 let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 1/*IsFake16*/>.ret; 830 let Src0ModDPP = getSrcModDPP_t16<Src0VT>.ret; 831 let Src1ModDPP = getSrcModDPP_t16<Src1VT>.ret; 832 let Src2ModDPP = getSrcModDPP_t16<Src2VT>.ret; 833 } 834} 835 836class getVOPCClassPat64 <VOPProfile P> { 837 list<dag> ret = 838 [(set i1:$sdst, 839 (AMDGPUfp_class 840 (P.Src0VT (VOP3ModsNonCanonicalizing P.Src0VT:$src0, i32:$src0_modifiers)), 841 i32:$src1))]; 842} 843 844 845// Special case for class instructions which only have modifiers on 846// the 1st source operand. 847multiclass VOPC_Class_Pseudos <string opName, VOPC_Profile p, bit DefExec, 848 bit DefVcc = 1> { 849 def _e32 : VOPC_Pseudo <opName, p>, 850 VCMPXNoSDstTable<1, opName#"_e32"> { 851 let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]), 852 !if(DefVcc, [VCC], [])); 853 let SchedRW = p.Schedule; 854 let isConvergent = DefExec; 855 } 856 857 def _e64 : VOP3_Pseudo<opName, p, getVOPCClassPat64<p>.ret>, 858 VCMPXNoSDstTable<1, opName#"_e64"> { 859 let Defs = !if(DefExec, [EXEC], []); 860 let SchedRW = p.Schedule; 861 } 862 863 if p.HasExtSDWA then 864 def _sdwa : VOPC_SDWA_Pseudo <opName, p> { 865 let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]), 866 !if(DefVcc, [VCC], [])); 867 let SchedRW = p.Schedule; 868 let isConvergent = DefExec; 869 } 870 871 let SubtargetPredicate = isGFX11Plus in { 872 if p.HasExtDPP then 873 def _e32_dpp : VOP_DPP_Pseudo<opName, p> { 874 let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]), 875 !if(DefVcc, [VCC], [])); 876 let SchedRW = p.Schedule; 877 let isConvergent = DefExec; 878 let VOPC = 1; 879 let Constraints = ""; 880 } 881 if p.HasExtVOP3DPP then 882 def _e64_dpp : VOP3_DPP_Pseudo<opName, p> { 883 let Defs = !if(DefExec, [EXEC], []); 884 let SchedRW = p.Schedule; 885 let Constraints = ""; 886 } 887 } // end SubtargetPredicate = isGFX11Plus 888} 889 890let SubtargetPredicate = HasSdstCMPX in { 891multiclass VOPCX_Class_Pseudos <string opName, 892 VOPC_Profile P, 893 VOPC_Profile P_NoSDst> : 894 VOPC_Class_Pseudos <opName, P, 1, 1> { 895 896 def _nosdst_e32 : VOPC_Pseudo <opName#"_nosdst", P_NoSDst, [], 0>, 897 VCMPXNoSDstTable<0, opName#"_e32"> { 898 let Defs = [EXEC]; 899 let SchedRW = P_NoSDst.Schedule; 900 let isConvergent = 1; 901 let SubtargetPredicate = HasNoSdstCMPX; 902 } 903 904 def _nosdst_e64 : VOP3_Pseudo<opName#"_nosdst", P_NoSDst>, 905 VCMPXNoSDstTable<0, opName#"_e64"> { 906 let Defs = [EXEC]; 907 let SchedRW = P_NoSDst.Schedule; 908 let SubtargetPredicate = HasNoSdstCMPX; 909 } 910 911 if P_NoSDst.HasExtSDWA then 912 def _nosdst_sdwa : VOPC_SDWA_Pseudo <opName#"_nosdst", P_NoSDst> { 913 let Defs = [EXEC]; 914 let SchedRW = P_NoSDst.Schedule; 915 let isConvergent = 1; 916 let SubtargetPredicate = HasNoSdstCMPX; 917 } 918 919 let SubtargetPredicate = isGFX11Plus in { 920 if P.HasExtDPP then 921 def _nosdst_e32_dpp : VOP_DPP_Pseudo<opName#"_nosdst", P_NoSDst> { 922 let Defs = [EXEC]; 923 let SchedRW = P_NoSDst.Schedule; 924 let isConvergent = 1; 925 let VOPC = 1; 926 let Constraints = ""; 927 } 928 if P.HasExtVOP3DPP then 929 def _nosdst_e64_dpp : VOP3_DPP_Pseudo<opName#"_nosdst", P_NoSDst> { 930 let Defs = [EXEC]; 931 let SchedRW = P_NoSDst.Schedule; 932 let Constraints = ""; 933 } 934 } // end SubtargetPredicate = isGFX11Plus 935} 936} // End SubtargetPredicate = HasSdstCMPX 937 938defm VOPC_I1_F16_I16 : VOPC_Class_Profile_t16<[Write32Bit]>; 939def VOPC_I1_F32_I32 : VOPC_Class_Profile<[Write32Bit], f32>; 940def VOPC_I1_F64_I32 : VOPC_Class_Profile<[WriteDoubleAdd], f64>; 941 942defm VOPC_F16_I16 : VOPC_Class_NoSdst_Profile_t16<[Write32Bit]>; 943def VOPC_F32_I32 : VOPC_Class_NoSdst_Profile<[Write32Bit], f32>; 944def VOPC_F64_I32 : VOPC_Class_NoSdst_Profile<[Write64Bit], f64>; 945 946multiclass VOPC_CLASS_F16 <string opName> { 947 let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in { 948 defm NAME : VOPC_Class_Pseudos <opName, VOPC_I1_F16_I16, 0>; 949 } 950 let OtherPredicates = [HasTrue16BitInsts] in { 951 defm _t16 : VOPC_Class_Pseudos <opName#"_t16", VOPC_I1_F16_I16_t16, 0>; 952 } 953} 954 955multiclass VOPCX_CLASS_F16 <string opName> { 956 let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in { 957 defm NAME : VOPCX_Class_Pseudos <opName, VOPC_I1_F16_I16, VOPC_F16_I16>; 958 } 959 let OtherPredicates = [HasTrue16BitInsts] in { 960 defm _t16 : VOPCX_Class_Pseudos <opName#"_t16", VOPC_I1_F16_I16_t16, VOPC_F16_I16_t16>; 961 } 962} 963 964multiclass VOPC_CLASS_F32 <string opName> : 965 VOPC_Class_Pseudos <opName, VOPC_I1_F32_I32, 0>; 966 967multiclass VOPCX_CLASS_F32 <string opName> : 968 VOPCX_Class_Pseudos <opName, VOPC_I1_F32_I32, VOPC_F32_I32>; 969 970multiclass VOPC_CLASS_F64 <string opName> : 971 VOPC_Class_Pseudos <opName, VOPC_I1_F64_I32, 0>; 972 973multiclass VOPCX_CLASS_F64 <string opName> : 974 VOPCX_Class_Pseudos <opName, VOPC_I1_F64_I32, VOPC_F64_I32>; 975 976// cmp_class ignores the FP mode and faithfully reports the unmodified 977// source value. 978let ReadsModeReg = 0, mayRaiseFPException = 0 in { 979defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <"v_cmp_class_f32">; 980defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <"v_cmpx_class_f32">; 981defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <"v_cmp_class_f64">; 982defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <"v_cmpx_class_f64">; 983 984defm V_CMP_CLASS_F16 : VOPC_CLASS_F16 <"v_cmp_class_f16">; 985defm V_CMPX_CLASS_F16 : VOPCX_CLASS_F16 <"v_cmpx_class_f16">; 986} // End ReadsModeReg = 0, mayRaiseFPException = 0 987 988//===----------------------------------------------------------------------===// 989// V_ICMPIntrinsic Pattern. 990//===----------------------------------------------------------------------===// 991 992// We need to use COPY_TO_REGCLASS to w/a the problem when ReplaceAllUsesWith() 993// complaints it cannot replace i1 <-> i64/i32 if node was not morphed in place. 994multiclass ICMP_Pattern <PatFrags cond, Instruction inst, ValueType vt> { 995 let WaveSizePredicate = isWave64 in 996 def : GCNPat < 997 (i64 (AMDGPUsetcc vt:$src0, vt:$src1, cond)), 998 (i64 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_64)) 999 >; 1000 1001 let WaveSizePredicate = isWave32 in { 1002 def : GCNPat < 1003 (i32 (AMDGPUsetcc vt:$src0, vt:$src1, cond)), 1004 (i32 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_32)) 1005 >; 1006 1007 // Support codegen of i64 setcc in wave32 mode. 1008 def : GCNPat < 1009 (i64 (AMDGPUsetcc vt:$src0, vt:$src1, cond)), 1010 (i64 (REG_SEQUENCE SReg_64, (inst $src0, $src1), sub0, (S_MOV_B32 (i32 0)), sub1)) 1011 >; 1012 } 1013} 1014 1015defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U32_e64, i32>; 1016defm : ICMP_Pattern <COND_NE, V_CMP_NE_U32_e64, i32>; 1017defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U32_e64, i32>; 1018defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U32_e64, i32>; 1019defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U32_e64, i32>; 1020defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U32_e64, i32>; 1021defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I32_e64, i32>; 1022defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I32_e64, i32>; 1023defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I32_e64, i32>; 1024defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I32_e64, i32>; 1025 1026defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U64_e64, i64>; 1027defm : ICMP_Pattern <COND_NE, V_CMP_NE_U64_e64, i64>; 1028defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U64_e64, i64>; 1029defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U64_e64, i64>; 1030defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U64_e64, i64>; 1031defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U64_e64, i64>; 1032defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I64_e64, i64>; 1033defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I64_e64, i64>; 1034defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I64_e64, i64>; 1035defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I64_e64, i64>; 1036 1037let OtherPredicates = [HasTrue16BitInsts] in { 1038defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U16_t16_e64, i16>; 1039defm : ICMP_Pattern <COND_NE, V_CMP_NE_U16_t16_e64, i16>; 1040defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U16_t16_e64, i16>; 1041defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U16_t16_e64, i16>; 1042defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U16_t16_e64, i16>; 1043defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U16_t16_e64, i16>; 1044defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I16_t16_e64, i16>; 1045defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I16_t16_e64, i16>; 1046defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I16_t16_e64, i16>; 1047defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I16_t16_e64, i16>; 1048} // End OtherPredicates = [HasTrue16BitInsts] 1049 1050let OtherPredicates = [NotHasTrue16BitInsts] in { 1051defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U16_e64, i16>; 1052defm : ICMP_Pattern <COND_NE, V_CMP_NE_U16_e64, i16>; 1053defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U16_e64, i16>; 1054defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U16_e64, i16>; 1055defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U16_e64, i16>; 1056defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U16_e64, i16>; 1057defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I16_e64, i16>; 1058defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I16_e64, i16>; 1059defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I16_e64, i16>; 1060defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I16_e64, i16>; 1061} // End OtherPredicates = [NotHasTrue16BitInsts] 1062 1063multiclass FCMP_Pattern <PatFrags cond, Instruction inst, ValueType vt> { 1064 let WaveSizePredicate = isWave64 in 1065 def : GCNPat < 1066 (i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), 1067 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)), 1068 (i64 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1, 1069 DSTCLAMP.NONE), SReg_64)) 1070 >; 1071 1072 let WaveSizePredicate = isWave32 in { 1073 def : GCNPat < 1074 (i32 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), 1075 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)), 1076 (i32 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1, 1077 DSTCLAMP.NONE), SReg_32)) 1078 >; 1079 1080 def : GCNPat < 1081 (i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), 1082 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)), 1083 (i64 (REG_SEQUENCE SReg_64, (inst $src0_modifiers, $src0, $src1_modifiers, $src1, 1084 DSTCLAMP.NONE), sub0, 1085 (S_MOV_B32 (i32 0)), sub1)) 1086 >; 1087 } 1088} 1089 1090defm : FCMP_Pattern <COND_O, V_CMP_O_F32_e64, f32>; 1091defm : FCMP_Pattern <COND_UO, V_CMP_U_F32_e64, f32>; 1092defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>; 1093defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F32_e64, f32>; 1094defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F32_e64, f32>; 1095defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F32_e64, f32>; 1096defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F32_e64, f32>; 1097defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F32_e64, f32>; 1098 1099defm : FCMP_Pattern <COND_O, V_CMP_O_F64_e64, f64>; 1100defm : FCMP_Pattern <COND_UO, V_CMP_U_F64_e64, f64>; 1101defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F64_e64, f64>; 1102defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F64_e64, f64>; 1103defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F64_e64, f64>; 1104defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F64_e64, f64>; 1105defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F64_e64, f64>; 1106defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F64_e64, f64>; 1107 1108defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F32_e64, f32>; 1109defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F32_e64, f32>; 1110defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F32_e64, f32>; 1111defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F32_e64, f32>; 1112defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F32_e64, f32>; 1113defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F32_e64, f32>; 1114 1115defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>; 1116defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>; 1117defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>; 1118defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>; 1119defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>; 1120defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>; 1121 1122let OtherPredicates = [HasTrue16BitInsts] in { 1123defm : FCMP_Pattern <COND_O, V_CMP_O_F16_t16_e64, f16>; 1124defm : FCMP_Pattern <COND_UO, V_CMP_U_F16_t16_e64, f16>; 1125defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F16_t16_e64, f16>; 1126defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F16_t16_e64, f16>; 1127defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F16_t16_e64, f16>; 1128defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F16_t16_e64, f16>; 1129defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F16_t16_e64, f16>; 1130defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F16_t16_e64, f16>; 1131 1132defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F16_t16_e64, f16>; 1133defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F16_t16_e64, f16>; 1134defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F16_t16_e64, f16>; 1135defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F16_t16_e64, f16>; 1136defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F16_t16_e64, f16>; 1137defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F16_t16_e64, f16>; 1138} // End OtherPredicates = [HasTrue16BitInsts] 1139 1140let OtherPredicates = [NotHasTrue16BitInsts] in { 1141defm : FCMP_Pattern <COND_O, V_CMP_O_F16_e64, f16>; 1142defm : FCMP_Pattern <COND_UO, V_CMP_U_F16_e64, f16>; 1143defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F16_e64, f16>; 1144defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F16_e64, f16>; 1145defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F16_e64, f16>; 1146defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F16_e64, f16>; 1147defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F16_e64, f16>; 1148defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F16_e64, f16>; 1149 1150defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F16_e64, f16>; 1151defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F16_e64, f16>; 1152defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F16_e64, f16>; 1153defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F16_e64, f16>; 1154defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F16_e64, f16>; 1155defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F16_e64, f16>; 1156} // End OtherPredicates = [NotHasTrue16BitInsts] 1157 1158//===----------------------------------------------------------------------===// 1159// DPP Encodings 1160//===----------------------------------------------------------------------===// 1161 1162// VOPC32 1163 1164class VOPC_DPPe_Common<bits<8> op> : Enc64 { 1165 bits<8> src1; 1166 let Inst{16-9} = src1; 1167 let Inst{24-17} = op; 1168 let Inst{31-25} = 0x3e; 1169} 1170 1171class VOPC_DPP_Base<bits<8> op, string OpName, VOPProfile P> 1172 : VOP_DPP_Base<OpName, P, P.InsDPP16, " " #P.AsmDPP16>, 1173 VOPC_DPPe_Common<op> { 1174 Instruction Opcode = !cast<Instruction>(NAME); 1175 1176 bits<2> src0_modifiers; 1177 bits<8> src0; 1178 bits<2> src1_modifiers; 1179 bits<9> dpp_ctrl; 1180 bits<1> bound_ctrl; 1181 bits<4> bank_mask; 1182 bits<4> row_mask; 1183 bit fi; 1184 1185 let Inst{8-0} = 0xfa; 1186 1187 let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, 0); 1188 let Inst{48-40} = dpp_ctrl; 1189 let Inst{50} = fi; 1190 let Inst{51} = bound_ctrl; 1191 let Inst{52} = !if (P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg 1192 let Inst{53} = !if (P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs 1193 let Inst{54} = !if (P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg 1194 let Inst{55} = !if (P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs 1195 let Inst{59-56} = bank_mask; 1196 let Inst{63-60} = row_mask; 1197 1198 let AsmMatchConverter = "cvtDPP"; 1199 let VOPC = 1; 1200} 1201 1202class VOPC_DPP8_Base<bits<8> op, string OpName, VOPProfile P> 1203 : VOP_DPP8_Base<OpName, P, P.InsDPP8, " " #P.AsmDPP8>, 1204 VOPC_DPPe_Common<op> { 1205 Instruction Opcode = !cast<Instruction>(NAME); 1206 1207 bits<8> src0; 1208 bits<24> dpp8; 1209 bits<9> fi; 1210 1211 let Inst{8-0} = fi; 1212 1213 let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, 0); 1214 let Inst{63-40} = dpp8{23-0}; 1215 1216 let AsmMatchConverter = "cvtDPP8"; 1217 let VOPC = 1; 1218} 1219 1220class VOPC_DPP16<bits<8> op, VOP_DPP_Pseudo ps, string opName = ps.OpName> 1221 : VOPC_DPP_Base<op, opName, ps.Pfl> { 1222 let AssemblerPredicate = HasDPP16; 1223 let SubtargetPredicate = HasDPP16; 1224 let hasSideEffects = ps.hasSideEffects; 1225 let Defs = ps.Defs; 1226 let SchedRW = ps.SchedRW; 1227 let Uses = ps.Uses; 1228 let OtherPredicates = ps.OtherPredicates; 1229 let Constraints = ps.Constraints; 1230} 1231 1232class VOPC_DPP16_SIMC<bits<8> op, VOP_DPP_Pseudo ps, int subtarget, 1233 string opName = ps.OpName> 1234 : VOPC_DPP16<op, ps, opName>, SIMCInstr<ps.PseudoInstr, subtarget>; 1235 1236class VOPC_DPP8<bits<8> op, VOPC_Pseudo ps, string opName = ps.OpName> 1237 : VOPC_DPP8_Base<op, opName, ps.Pfl> { 1238 // Note ps is the non-dpp pseudo 1239 let hasSideEffects = ps.hasSideEffects; 1240 let Defs = ps.Defs; 1241 let SchedRW = ps.SchedRW; 1242 let Uses = ps.Uses; 1243 let OtherPredicates = ps.OtherPredicates; 1244 let Constraints = ""; 1245} 1246 1247// VOPC64 1248 1249class VOPC64_DPP_Base<bits<10> op, string OpName, VOPProfile P> 1250 : VOP3_DPP_Base<OpName, P, 1>, VOP3_DPPe_Common<op, P> { 1251 Instruction Opcode = !cast<Instruction>(NAME); 1252 1253 bits<8> src0; 1254 bits<9> dpp_ctrl; 1255 bits<1> bound_ctrl; 1256 bits<4> bank_mask; 1257 bits<4> row_mask; 1258 bit fi; 1259 1260 let Inst{40-32} = 0xfa; 1261 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 1262 let Inst{80-72} = dpp_ctrl; 1263 let Inst{82} = fi; 1264 let Inst{83} = bound_ctrl; 1265 // Inst{87-84} ignored by hw 1266 let Inst{91-88} = bank_mask; 1267 let Inst{95-92} = row_mask; 1268} 1269 1270class VOPC64_DPP16<bits<10> op, VOP_DPP_Pseudo ps, string opName = ps.OpName> 1271 : VOPC64_DPP_Base<op, opName, ps.Pfl> { 1272 let AssemblerPredicate = HasDPP16; 1273 let SubtargetPredicate = HasDPP16; 1274 let hasSideEffects = ps.hasSideEffects; 1275 let Defs = ps.Defs; 1276 let SchedRW = ps.SchedRW; 1277 let Uses = ps.Uses; 1278 let OtherPredicates = ps.OtherPredicates; 1279 let Constraints = ps.Constraints; 1280} 1281 1282class VOPC64_DPP16_Dst<bits<10> op, VOP_DPP_Pseudo ps, 1283 string opName = ps.OpName> 1284 : VOPC64_DPP16<op, ps, opName> { 1285 bits<8> sdst; 1286 let Inst{7-0} = sdst; 1287} 1288 1289class VOPC64_DPP16_NoDst<bits<10> op, VOP_DPP_Pseudo ps, 1290 string opName = ps.OpName> 1291 : VOPC64_DPP16<op, ps, opName> { 1292 let Inst{7-0} = ? ; 1293} 1294 1295class VOPC64_DPP8_Base<bits<10> op, string OpName, VOPProfile P> 1296 : VOP3_DPP8_Base<OpName, P>, VOP3_DPPe_Common<op, P> { 1297 Instruction Opcode = !cast<Instruction>(NAME); 1298 1299 bits<8> src0; 1300 bits<24> dpp8; 1301 bits<9> fi; 1302 1303 let Inst{40-32} = fi; 1304 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 1305 let Inst{95-72} = dpp8{23-0}; 1306} 1307 1308class VOPC64_DPP8<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1309 : VOPC64_DPP8_Base<op, opName, ps.Pfl> { 1310 // Note ps is the non-dpp pseudo 1311 let hasSideEffects = ps.hasSideEffects; 1312 let Defs = ps.Defs; 1313 let SchedRW = ps.SchedRW; 1314 let Uses = ps.Uses; 1315 let OtherPredicates = ps.OtherPredicates; 1316} 1317 1318class VOPC64_DPP8_Dst<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1319 : VOPC64_DPP8<op, ps, opName> { 1320 bits<8> sdst; 1321 let Inst{7-0} = sdst; 1322 let Constraints = ""; 1323} 1324 1325class VOPC64_DPP8_NoDst<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1326 : VOPC64_DPP8<op, ps, opName> { 1327 let Inst{7-0} = ? ; 1328 let Constraints = ""; 1329} 1330 1331//===----------------------------------------------------------------------===// 1332// Target-specific instruction encodings. 1333//===----------------------------------------------------------------------===// 1334 1335//===----------------------------------------------------------------------===// 1336// GFX11, GFX12 1337//===----------------------------------------------------------------------===// 1338 1339multiclass VOPC_Real_Base<GFXGen Gen, bits<9> op> { 1340 let AssemblerPredicate = Gen.AssemblerPredicate, DecoderNamespace = Gen.DecoderNamespace in { 1341 defvar ps32 = !cast<VOPC_Pseudo>(NAME#"_e32"); 1342 defvar ps64 = !cast<VOP3_Pseudo>(NAME#"_e64"); 1343 def _e32#Gen.Suffix : VOPC_Real<ps32, Gen.Subtarget>, 1344 VOPCe<op{7-0}>; 1345 def _e64#Gen.Suffix : VOP3_Real<ps64, Gen.Subtarget>, 1346 VOP3a_gfx11_gfx12<{0, op}, ps64.Pfl> { 1347 // Encoding used for VOPC instructions encoded as VOP3 differs from 1348 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. 1349 bits<8> sdst; 1350 let Inst{7-0} = sdst; 1351 } 1352 1353 defm : VOPCInstAliases<NAME, !substr(Gen.Suffix,1)>; 1354 1355 if ps32.Pfl.HasExtDPP then { 1356 defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_e32" #"_dpp"); 1357 defvar AsmDPP = ps32.Pfl.AsmDPP16; 1358 def _e32_dpp#Gen.Suffix : VOPC_DPP16_SIMC<op{7-0}, psDPP, Gen.Subtarget>; 1359 def _e32_dpp_w32#Gen.Suffix : VOPC_DPP16<op{7-0}, psDPP> { 1360 let AsmString = psDPP.OpName # " vcc_lo, " # AsmDPP; 1361 let isAsmParserOnly = 1; 1362 let WaveSizePredicate = isWave32; 1363 } 1364 def _e32_dpp_w64#Gen.Suffix : VOPC_DPP16<op{7-0}, psDPP> { 1365 let AsmString = psDPP.OpName # " vcc, " # AsmDPP; 1366 let isAsmParserOnly = 1; 1367 let WaveSizePredicate = isWave64; 1368 } 1369 defvar AsmDPP8 = ps32.Pfl.AsmDPP8; 1370 def _e32_dpp8#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32>; 1371 def _e32_dpp8_w32#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32> { 1372 let AsmString = ps32.OpName # " vcc_lo, " # AsmDPP8; 1373 let isAsmParserOnly = 1; 1374 let WaveSizePredicate = isWave32; 1375 } 1376 def _e32_dpp8_w64#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32> { 1377 let AsmString = ps32.OpName # " vcc, " # AsmDPP8; 1378 let isAsmParserOnly = 1; 1379 let WaveSizePredicate = isWave64; 1380 } 1381 } 1382 if ps64.Pfl.HasExtVOP3DPP then { 1383 defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_e64" #"_dpp"); 1384 def _e64_dpp#Gen.Suffix : VOPC64_DPP16_Dst<{0, op}, psDPP>, 1385 SIMCInstr<psDPP.PseudoInstr, Gen.Subtarget>; 1386 def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_Dst<{0, op}, ps64>; 1387 } 1388 } // AssemblerPredicate = Gen.AssemblerPredicate, DecoderNamespace = Gen.DecoderNamespace 1389} 1390 1391multiclass VOPC_Real_with_name<GFXGen Gen, bits<9> op, string OpName, 1392 string asm_name, string pseudo_mnemonic = ""> { 1393 defvar ps32 = !cast<VOPC_Pseudo>(OpName#"_e32"); 1394 defvar ps64 = !cast<VOP3_Pseudo>(OpName#"_e64"); 1395 let AssemblerPredicate = Gen.AssemblerPredicate in { 1396 def : AMDGPUMnemonicAlias<!if(!empty(pseudo_mnemonic), ps32.Mnemonic, 1397 pseudo_mnemonic), 1398 asm_name, ps32.AsmVariantName>; 1399 def : AMDGPUMnemonicAlias<!if(!empty(pseudo_mnemonic), ps64.Mnemonic, 1400 pseudo_mnemonic), 1401 asm_name, ps64.AsmVariantName>; 1402 1403 let DecoderNamespace = Gen.DecoderNamespace in { 1404 def _e32#Gen.Suffix : 1405 // 32 and 64 bit forms of the instruction have _e32 and _e64 1406 // respectively appended to their assembly mnemonic. 1407 // _e64 is printed as part of the VOPDstS64orS32 operand, whereas 1408 // the destination-less 32bit forms add it to the asmString here. 1409 VOPC_Real<ps32, Gen.Subtarget, asm_name#"_e32">, 1410 VOPCe<op{7-0}>; 1411 def _e64#Gen.Suffix : 1412 VOP3_Real_Gen<ps64, Gen, asm_name>, 1413 VOP3a_gfx11_gfx12<{0, op}, ps64.Pfl> { 1414 // Encoding used for VOPC instructions encoded as VOP3 differs from 1415 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. 1416 bits<8> sdst; 1417 let Inst{7-0} = sdst; 1418 } 1419 1420 defm : VOPCInstAliases<OpName, !substr(Gen.Suffix, 1), NAME, asm_name>; 1421 1422 if ps32.Pfl.HasExtDPP then { 1423 defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName #"_e32" #"_dpp"); 1424 defvar AsmDPP = ps32.Pfl.AsmDPP16; 1425 def _e32_dpp#Gen.Suffix : VOPC_DPP16_SIMC<op{7-0}, psDPP, 1426 Gen.Subtarget, asm_name>; 1427 def _e32_dpp_w32#Gen.Suffix 1428 : VOPC_DPP16<op{7-0}, psDPP, asm_name> { 1429 let AsmString = asm_name # " vcc_lo, " # AsmDPP; 1430 let isAsmParserOnly = 1; 1431 let WaveSizePredicate = isWave32; 1432 } 1433 def _e32_dpp_w64#Gen.Suffix 1434 : VOPC_DPP16<op{7-0}, psDPP, asm_name> { 1435 let AsmString = asm_name # " vcc, " # AsmDPP; 1436 let isAsmParserOnly = 1; 1437 let WaveSizePredicate = isWave64; 1438 } 1439 defvar AsmDPP8 = ps32.Pfl.AsmDPP8; 1440 def _e32_dpp8#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32, asm_name>; 1441 def _e32_dpp8_w32#Gen.Suffix 1442 : VOPC_DPP8<op{7-0}, ps32, asm_name> { 1443 let AsmString = asm_name # " vcc_lo, " # AsmDPP8; 1444 let isAsmParserOnly = 1; 1445 let WaveSizePredicate = isWave32; 1446 } 1447 def _e32_dpp8_w64#Gen.Suffix 1448 : VOPC_DPP8<op{7-0}, ps32, asm_name> { 1449 let AsmString = asm_name # " vcc, " # AsmDPP8; 1450 let isAsmParserOnly = 1; 1451 let WaveSizePredicate = isWave64; 1452 } 1453 } 1454 1455 if ps64.Pfl.HasExtVOP3DPP then { 1456 defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName #"_e64" #"_dpp"); 1457 def _e64_dpp#Gen.Suffix : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name>, 1458 SIMCInstr<psDPP.PseudoInstr, Gen.Subtarget>; 1459 def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name>; 1460 } // end if ps64.Pfl.HasExtVOP3DPP 1461 } // End DecoderNamespace 1462 } // End AssemblerPredicate 1463} 1464 1465multiclass VOPC_Real_t16<GFXGen Gen, bits<9> op, string asm_name, 1466 string OpName = NAME, string pseudo_mnemonic = ""> : 1467 VOPC_Real_with_name<Gen, op, OpName, asm_name, pseudo_mnemonic>; 1468 1469multiclass VOPCX_Real<GFXGen Gen, bits<9> op> { 1470 let AssemblerPredicate = Gen.AssemblerPredicate, DecoderNamespace = Gen.DecoderNamespace in { 1471 defvar ps32 = !cast<VOPC_Pseudo>(NAME#"_nosdst_e32"); 1472 defvar ps64 = !cast<VOP3_Pseudo>(NAME#"_nosdst_e64"); 1473 def _e32#Gen.Suffix : 1474 VOPC_Real<ps32, Gen.Subtarget>, 1475 VOPCe<op{7-0}> { 1476 let AsmString = !subst("_nosdst", "", ps32.PseudoInstr) 1477 # " " # ps32.AsmOperands; 1478 } 1479 def _e64#Gen.Suffix : 1480 VOP3_Real<ps64, Gen.Subtarget>, 1481 VOP3a_gfx11_gfx12<{0, op}, ps64.Pfl> { 1482 let Inst{7-0} = ?; // sdst 1483 let AsmString = !subst("_nosdst", "", ps64.Mnemonic) 1484 # "{_e64} " # ps64.AsmOperands; 1485 } 1486 1487 defm : VOPCXInstAliases<NAME, !substr(Gen.Suffix, 1)>; 1488 1489 if ps32.Pfl.HasExtDPP then { 1490 defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_nosdst_e32" #"_dpp"); 1491 defvar AsmDPP = ps32.Pfl.AsmDPP16; 1492 def _e32_dpp#Gen.Suffix 1493 : VOPC_DPP16_SIMC<op{7-0}, psDPP, Gen.Subtarget> { 1494 let AsmString = !subst("_nosdst", "", psDPP.OpName) # " " # AsmDPP; 1495 } 1496 defvar AsmDPP8 = ps32.Pfl.AsmDPP8; 1497 def _e32_dpp8#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32> { 1498 let AsmString = !subst("_nosdst", "", ps32.OpName) # " " # AsmDPP8; 1499 } 1500 } 1501 1502 if ps64.Pfl.HasExtVOP3DPP then { 1503 defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_nosdst_e64" #"_dpp"); 1504 defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16; 1505 def _e64_dpp#Gen.Suffix 1506 : VOPC64_DPP16_NoDst<{0, op}, psDPP>, 1507 SIMCInstr<psDPP.PseudoInstr, Gen.Subtarget> { 1508 let AsmString = !subst("_nosdst", "", psDPP.OpName) 1509 # "{_e64_dpp} " # AsmDPP; 1510 } 1511 defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8; 1512 def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_NoDst<{0, op}, ps64> { 1513 let AsmString = !subst("_nosdst", "", ps64.OpName) 1514 # "{_e64_dpp} " # AsmDPP8; 1515 } 1516 } 1517 } // End AssemblerPredicate = Gen.AssemblerPredicate, DecoderNamespace = Gen.DecoderNamespace 1518} 1519 1520multiclass VOPCX_Real_with_name<GFXGen Gen, bits<9> op, string OpName, 1521 string asm_name, string pseudo_mnemonic = ""> { 1522 defvar ps32 = !cast<VOPC_Pseudo>(OpName#"_nosdst_e32"); 1523 defvar ps64 = !cast<VOP3_Pseudo>(OpName#"_nosdst_e64"); 1524 let AssemblerPredicate = Gen.AssemblerPredicate in { 1525 def : AMDGPUMnemonicAlias<!if(!empty(pseudo_mnemonic), !subst("_nosdst", "", ps32.Mnemonic), 1526 pseudo_mnemonic), 1527 asm_name, ps32.AsmVariantName>; 1528 def : AMDGPUMnemonicAlias<!if(!empty(pseudo_mnemonic), !subst("_nosdst", "", ps64.Mnemonic), 1529 pseudo_mnemonic), 1530 asm_name, ps64.AsmVariantName>; 1531 1532 let DecoderNamespace = Gen.DecoderNamespace in { 1533 def _e32#Gen.Suffix 1534 : VOPC_Real<ps32, Gen.Subtarget, asm_name>, 1535 VOPCe<op{7-0}> { 1536 let AsmString = asm_name # "{_e32} " # ps32.AsmOperands; 1537 } 1538 def _e64#Gen.Suffix 1539 : VOP3_Real_Gen<ps64, Gen, asm_name>, 1540 VOP3a_gfx11_gfx12<{0, op}, ps64.Pfl> { 1541 let Inst{7-0} = ? ; // sdst 1542 let AsmString = asm_name # "{_e64} " # ps64.AsmOperands; 1543 } 1544 1545 defm : VOPCXInstAliases<OpName, !substr(Gen.Suffix, 1), NAME, asm_name>; 1546 1547 if ps32.Pfl.HasExtDPP then { 1548 defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName#"_nosdst_e32"#"_dpp"); 1549 def _e32_dpp#Gen.Suffix : VOPC_DPP16_SIMC<op{7-0}, psDPP, 1550 Gen.Subtarget, asm_name>; 1551 def _e32_dpp8#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32, asm_name>; 1552 } 1553 if ps64.Pfl.HasExtVOP3DPP then { 1554 defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName#"_nosdst_e64"#"_dpp"); 1555 defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16; 1556 def _e64_dpp#Gen.Suffix 1557 : VOPC64_DPP16_NoDst<{0, op}, psDPP, asm_name>, 1558 SIMCInstr<psDPP.PseudoInstr, Gen.Subtarget> { 1559 let AsmString = asm_name # "{_e64_dpp} " # AsmDPP; 1560 } 1561 defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8; 1562 def _e64_dpp8#Gen.Suffix : VOPC64_DPP8_NoDst<{0, op}, ps64, asm_name> { 1563 let AsmString = asm_name # "{_e64_dpp} " # AsmDPP8; 1564 } 1565 } // End if ps64.Pfl.HasExtVOP3DPP 1566 } // End DecoderNamespace 1567 } // End AssemblerPredicate 1568} 1569 1570multiclass VOPCX_Real_t16<GFXGen Gen, bits<9> op, string asm_name, 1571 string OpName = NAME, string pseudo_mnemonic = ""> : 1572 VOPCX_Real_with_name<Gen, op, OpName, asm_name, pseudo_mnemonic>; 1573 1574multiclass VOPC_Real_gfx11<bits<9> op> : VOPC_Real_Base<GFX11Gen, op>; 1575 1576multiclass VOPC_Real_with_name_gfx11<bits<9> op, string OpName, string asm_name, 1577 string pseudo_mnemonic = ""> 1578 : VOPC_Real_with_name<GFX11Gen, op, OpName, asm_name, pseudo_mnemonic>; 1579 1580multiclass VOPCX_Real_gfx11<bits<9> op> : VOPCX_Real<GFX11Gen, op>; 1581 1582multiclass VOPCX_Real_with_name_gfx11<bits<9> op, string OpName, 1583 string asm_name, string pseudo_mnemonic = ""> : 1584 VOPCX_Real_with_name<GFX11Gen, op, OpName, asm_name, pseudo_mnemonic>; 1585 1586multiclass VOPC_Real_gfx11_gfx12<bits<9> op> : 1587 VOPC_Real_Base<GFX11Gen, op>, VOPC_Real_Base<GFX12Gen, op>; 1588 1589multiclass VOPCX_Real_gfx11_gfx12<bits<9> op> : 1590 VOPCX_Real<GFX11Gen, op>, VOPCX_Real<GFX12Gen, op>; 1591 1592multiclass VOPC_Real_t16_gfx11<bits <9> op, string asm_name, 1593 string OpName = NAME, string pseudo_mnemonic = ""> : 1594 VOPC_Real_t16<GFX11Gen, op, asm_name, OpName, pseudo_mnemonic>; 1595 1596multiclass VOPC_Real_t16_gfx11_gfx12<bits <9> op, string asm_name, 1597 string OpName = NAME, string pseudo_mnemonic = ""> : 1598 VOPC_Real_t16<GFX11Gen, op, asm_name, OpName, pseudo_mnemonic>, 1599 VOPC_Real_t16<GFX12Gen, op, asm_name, OpName, pseudo_mnemonic>; 1600 1601multiclass VOPCX_Real_t16_gfx11<bits<9> op, string asm_name, 1602 string OpName = NAME, string pseudo_mnemonic = ""> : 1603 VOPCX_Real_t16<GFX11Gen, op, asm_name, OpName, pseudo_mnemonic>; 1604 1605multiclass VOPCX_Real_t16_gfx11_gfx12<bits<9> op, string asm_name, 1606 string OpName = NAME, string pseudo_mnemonic = ""> : 1607 VOPCX_Real_t16<GFX11Gen, op, asm_name, OpName, pseudo_mnemonic>, 1608 VOPCX_Real_t16<GFX12Gen, op, asm_name, OpName, pseudo_mnemonic>; 1609 1610defm V_CMP_F_F16_t16 : VOPC_Real_t16_gfx11<0x000, "v_cmp_f_f16">; 1611defm V_CMP_LT_F16_t16 : VOPC_Real_t16_gfx11_gfx12<0x001, "v_cmp_lt_f16">; 1612defm V_CMP_EQ_F16_t16 : VOPC_Real_t16_gfx11_gfx12<0x002, "v_cmp_eq_f16">; 1613defm V_CMP_LE_F16_t16 : VOPC_Real_t16_gfx11_gfx12<0x003, "v_cmp_le_f16">; 1614defm V_CMP_GT_F16_t16 : VOPC_Real_t16_gfx11_gfx12<0x004, "v_cmp_gt_f16">; 1615defm V_CMP_LG_F16_t16 : VOPC_Real_t16_gfx11_gfx12<0x005, "v_cmp_lg_f16">; 1616defm V_CMP_GE_F16_t16 : VOPC_Real_t16_gfx11_gfx12<0x006, "v_cmp_ge_f16">; 1617defm V_CMP_O_F16_t16 : VOPC_Real_t16_gfx11_gfx12<0x007, "v_cmp_o_f16">; 1618defm V_CMP_U_F16_t16 : VOPC_Real_t16_gfx11_gfx12<0x008, "v_cmp_u_f16">; 1619defm V_CMP_NGE_F16_t16 : VOPC_Real_t16_gfx11_gfx12<0x009, "v_cmp_nge_f16">; 1620defm V_CMP_NLG_F16_t16 : VOPC_Real_t16_gfx11_gfx12<0x00a, "v_cmp_nlg_f16">; 1621defm V_CMP_NGT_F16_t16 : VOPC_Real_t16_gfx11_gfx12<0x00b, "v_cmp_ngt_f16">; 1622defm V_CMP_NLE_F16_t16 : VOPC_Real_t16_gfx11_gfx12<0x00c, "v_cmp_nle_f16">; 1623defm V_CMP_NEQ_F16_t16 : VOPC_Real_t16_gfx11_gfx12<0x00d, "v_cmp_neq_f16">; 1624defm V_CMP_NLT_F16_t16 : VOPC_Real_t16_gfx11_gfx12<0x00e, "v_cmp_nlt_f16">; 1625defm V_CMP_T_F16_t16 : VOPC_Real_with_name_gfx11<0x00f, "V_CMP_TRU_F16_t16", "v_cmp_t_f16", "v_cmp_tru_f16">; 1626defm V_CMP_F_F32 : VOPC_Real_gfx11<0x010>; 1627defm V_CMP_LT_F32 : VOPC_Real_gfx11_gfx12<0x011>; 1628defm V_CMP_EQ_F32 : VOPC_Real_gfx11_gfx12<0x012>; 1629defm V_CMP_LE_F32 : VOPC_Real_gfx11_gfx12<0x013>; 1630defm V_CMP_GT_F32 : VOPC_Real_gfx11_gfx12<0x014>; 1631defm V_CMP_LG_F32 : VOPC_Real_gfx11_gfx12<0x015>; 1632defm V_CMP_GE_F32 : VOPC_Real_gfx11_gfx12<0x016>; 1633defm V_CMP_O_F32 : VOPC_Real_gfx11_gfx12<0x017>; 1634defm V_CMP_U_F32 : VOPC_Real_gfx11_gfx12<0x018>; 1635defm V_CMP_NGE_F32 : VOPC_Real_gfx11_gfx12<0x019>; 1636defm V_CMP_NLG_F32 : VOPC_Real_gfx11_gfx12<0x01a>; 1637defm V_CMP_NGT_F32 : VOPC_Real_gfx11_gfx12<0x01b>; 1638defm V_CMP_NLE_F32 : VOPC_Real_gfx11_gfx12<0x01c>; 1639defm V_CMP_NEQ_F32 : VOPC_Real_gfx11_gfx12<0x01d>; 1640defm V_CMP_NLT_F32 : VOPC_Real_gfx11_gfx12<0x01e>; 1641defm V_CMP_T_F32 : VOPC_Real_with_name_gfx11<0x01f, "V_CMP_TRU_F32", "v_cmp_t_f32">; 1642defm V_CMP_T_F64 : VOPC_Real_with_name_gfx11<0x02f, "V_CMP_TRU_F64", "v_cmp_t_f64">; 1643defm V_CMP_LT_I16_t16 : VOPC_Real_t16_gfx11_gfx12<0x031, "v_cmp_lt_i16">; 1644defm V_CMP_EQ_I16_t16 : VOPC_Real_t16_gfx11_gfx12<0x032, "v_cmp_eq_i16">; 1645defm V_CMP_LE_I16_t16 : VOPC_Real_t16_gfx11_gfx12<0x033, "v_cmp_le_i16">; 1646defm V_CMP_GT_I16_t16 : VOPC_Real_t16_gfx11_gfx12<0x034, "v_cmp_gt_i16">; 1647defm V_CMP_NE_I16_t16 : VOPC_Real_t16_gfx11_gfx12<0x035, "v_cmp_ne_i16">; 1648defm V_CMP_GE_I16_t16 : VOPC_Real_t16_gfx11_gfx12<0x036, "v_cmp_ge_i16">; 1649defm V_CMP_LT_U16_t16 : VOPC_Real_t16_gfx11_gfx12<0x039, "v_cmp_lt_u16">; 1650defm V_CMP_EQ_U16_t16 : VOPC_Real_t16_gfx11_gfx12<0x03a, "v_cmp_eq_u16">; 1651defm V_CMP_LE_U16_t16 : VOPC_Real_t16_gfx11_gfx12<0x03b, "v_cmp_le_u16">; 1652defm V_CMP_GT_U16_t16 : VOPC_Real_t16_gfx11_gfx12<0x03c, "v_cmp_gt_u16">; 1653defm V_CMP_NE_U16_t16 : VOPC_Real_t16_gfx11_gfx12<0x03d, "v_cmp_ne_u16">; 1654defm V_CMP_GE_U16_t16 : VOPC_Real_t16_gfx11_gfx12<0x03e, "v_cmp_ge_u16">; 1655defm V_CMP_F_I32 : VOPC_Real_gfx11<0x040>; 1656defm V_CMP_LT_I32 : VOPC_Real_gfx11_gfx12<0x041>; 1657defm V_CMP_EQ_I32 : VOPC_Real_gfx11_gfx12<0x042>; 1658defm V_CMP_LE_I32 : VOPC_Real_gfx11_gfx12<0x043>; 1659defm V_CMP_GT_I32 : VOPC_Real_gfx11_gfx12<0x044>; 1660defm V_CMP_NE_I32 : VOPC_Real_gfx11_gfx12<0x045>; 1661defm V_CMP_GE_I32 : VOPC_Real_gfx11_gfx12<0x046>; 1662defm V_CMP_T_I32 : VOPC_Real_gfx11<0x047>; 1663defm V_CMP_F_U32 : VOPC_Real_gfx11<0x048>; 1664defm V_CMP_LT_U32 : VOPC_Real_gfx11_gfx12<0x049>; 1665defm V_CMP_EQ_U32 : VOPC_Real_gfx11_gfx12<0x04a>; 1666defm V_CMP_LE_U32 : VOPC_Real_gfx11_gfx12<0x04b>; 1667defm V_CMP_GT_U32 : VOPC_Real_gfx11_gfx12<0x04c>; 1668defm V_CMP_NE_U32 : VOPC_Real_gfx11_gfx12<0x04d>; 1669defm V_CMP_GE_U32 : VOPC_Real_gfx11_gfx12<0x04e>; 1670defm V_CMP_T_U32 : VOPC_Real_gfx11<0x04f>; 1671 1672defm V_CMP_F_I64 : VOPC_Real_gfx11<0x050>; 1673defm V_CMP_LT_I64 : VOPC_Real_gfx11_gfx12<0x051>; 1674defm V_CMP_EQ_I64 : VOPC_Real_gfx11_gfx12<0x052>; 1675defm V_CMP_LE_I64 : VOPC_Real_gfx11_gfx12<0x053>; 1676defm V_CMP_GT_I64 : VOPC_Real_gfx11_gfx12<0x054>; 1677defm V_CMP_NE_I64 : VOPC_Real_gfx11_gfx12<0x055>; 1678defm V_CMP_GE_I64 : VOPC_Real_gfx11_gfx12<0x056>; 1679defm V_CMP_T_I64 : VOPC_Real_gfx11<0x057>; 1680defm V_CMP_F_U64 : VOPC_Real_gfx11<0x058>; 1681defm V_CMP_LT_U64 : VOPC_Real_gfx11_gfx12<0x059>; 1682defm V_CMP_EQ_U64 : VOPC_Real_gfx11_gfx12<0x05a>; 1683defm V_CMP_LE_U64 : VOPC_Real_gfx11_gfx12<0x05b>; 1684defm V_CMP_GT_U64 : VOPC_Real_gfx11_gfx12<0x05c>; 1685defm V_CMP_NE_U64 : VOPC_Real_gfx11_gfx12<0x05d>; 1686defm V_CMP_GE_U64 : VOPC_Real_gfx11_gfx12<0x05e>; 1687defm V_CMP_T_U64 : VOPC_Real_gfx11<0x05f>; 1688 1689defm V_CMP_CLASS_F16_t16 : VOPC_Real_t16_gfx11_gfx12<0x07d, "v_cmp_class_f16">; 1690defm V_CMP_CLASS_F32 : VOPC_Real_gfx11_gfx12<0x07e>; 1691defm V_CMP_CLASS_F64 : VOPC_Real_gfx11_gfx12<0x07f>; 1692 1693defm V_CMPX_F_F16_t16 : VOPCX_Real_t16_gfx11<0x080, "v_cmpx_f_f16">; 1694defm V_CMPX_LT_F16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x081, "v_cmpx_lt_f16">; 1695defm V_CMPX_EQ_F16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x082, "v_cmpx_eq_f16">; 1696defm V_CMPX_LE_F16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x083, "v_cmpx_le_f16">; 1697defm V_CMPX_GT_F16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x084, "v_cmpx_gt_f16">; 1698defm V_CMPX_LG_F16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x085, "v_cmpx_lg_f16">; 1699defm V_CMPX_GE_F16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x086, "v_cmpx_ge_f16">; 1700defm V_CMPX_O_F16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x087, "v_cmpx_o_f16">; 1701defm V_CMPX_U_F16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x088, "v_cmpx_u_f16">; 1702defm V_CMPX_NGE_F16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x089, "v_cmpx_nge_f16">; 1703defm V_CMPX_NLG_F16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x08a, "v_cmpx_nlg_f16">; 1704defm V_CMPX_NGT_F16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x08b, "v_cmpx_ngt_f16">; 1705defm V_CMPX_NLE_F16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x08c, "v_cmpx_nle_f16">; 1706defm V_CMPX_NEQ_F16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x08d, "v_cmpx_neq_f16">; 1707defm V_CMPX_NLT_F16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x08e, "v_cmpx_nlt_f16">; 1708defm V_CMPX_T_F16_t16 : VOPCX_Real_with_name_gfx11<0x08f, "V_CMPX_TRU_F16_t16", "v_cmpx_t_f16", "v_cmpx_tru_f16">; 1709defm V_CMPX_F_F32 : VOPCX_Real_gfx11<0x090>; 1710defm V_CMPX_LT_F32 : VOPCX_Real_gfx11_gfx12<0x091>; 1711defm V_CMPX_EQ_F32 : VOPCX_Real_gfx11_gfx12<0x092>; 1712defm V_CMPX_LE_F32 : VOPCX_Real_gfx11_gfx12<0x093>; 1713defm V_CMPX_GT_F32 : VOPCX_Real_gfx11_gfx12<0x094>; 1714defm V_CMPX_LG_F32 : VOPCX_Real_gfx11_gfx12<0x095>; 1715defm V_CMPX_GE_F32 : VOPCX_Real_gfx11_gfx12<0x096>; 1716defm V_CMPX_O_F32 : VOPCX_Real_gfx11_gfx12<0x097>; 1717defm V_CMPX_U_F32 : VOPCX_Real_gfx11_gfx12<0x098>; 1718defm V_CMPX_NGE_F32 : VOPCX_Real_gfx11_gfx12<0x099>; 1719defm V_CMPX_NLG_F32 : VOPCX_Real_gfx11_gfx12<0x09a>; 1720defm V_CMPX_NGT_F32 : VOPCX_Real_gfx11_gfx12<0x09b>; 1721defm V_CMPX_NLE_F32 : VOPCX_Real_gfx11_gfx12<0x09c>; 1722defm V_CMPX_NEQ_F32 : VOPCX_Real_gfx11_gfx12<0x09d>; 1723defm V_CMPX_NLT_F32 : VOPCX_Real_gfx11_gfx12<0x09e>; 1724defm V_CMPX_T_F32 : VOPCX_Real_with_name_gfx11<0x09f, "V_CMPX_TRU_F32", "v_cmpx_t_f32">; 1725 1726defm V_CMPX_F_F64 : VOPCX_Real_gfx11<0x0a0>; 1727defm V_CMPX_LT_F64 : VOPCX_Real_gfx11_gfx12<0x0a1>; 1728defm V_CMPX_EQ_F64 : VOPCX_Real_gfx11_gfx12<0x0a2>; 1729defm V_CMPX_LE_F64 : VOPCX_Real_gfx11_gfx12<0x0a3>; 1730defm V_CMPX_GT_F64 : VOPCX_Real_gfx11_gfx12<0x0a4>; 1731defm V_CMPX_LG_F64 : VOPCX_Real_gfx11_gfx12<0x0a5>; 1732defm V_CMPX_GE_F64 : VOPCX_Real_gfx11_gfx12<0x0a6>; 1733defm V_CMPX_O_F64 : VOPCX_Real_gfx11_gfx12<0x0a7>; 1734defm V_CMPX_U_F64 : VOPCX_Real_gfx11_gfx12<0x0a8>; 1735defm V_CMPX_NGE_F64 : VOPCX_Real_gfx11_gfx12<0x0a9>; 1736defm V_CMPX_NLG_F64 : VOPCX_Real_gfx11_gfx12<0x0aa>; 1737defm V_CMPX_NGT_F64 : VOPCX_Real_gfx11_gfx12<0x0ab>; 1738defm V_CMPX_NLE_F64 : VOPCX_Real_gfx11_gfx12<0x0ac>; 1739defm V_CMPX_NEQ_F64 : VOPCX_Real_gfx11_gfx12<0x0ad>; 1740defm V_CMPX_NLT_F64 : VOPCX_Real_gfx11_gfx12<0x0ae>; 1741defm V_CMPX_T_F64 : VOPCX_Real_with_name_gfx11<0x0af, "V_CMPX_TRU_F64", "v_cmpx_t_f64">; 1742 1743defm V_CMPX_LT_I16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x0b1, "v_cmpx_lt_i16">; 1744defm V_CMPX_EQ_I16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x0b2, "v_cmpx_eq_i16">; 1745defm V_CMPX_LE_I16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x0b3, "v_cmpx_le_i16">; 1746defm V_CMPX_GT_I16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x0b4, "v_cmpx_gt_i16">; 1747defm V_CMPX_NE_I16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x0b5, "v_cmpx_ne_i16">; 1748defm V_CMPX_GE_I16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x0b6, "v_cmpx_ge_i16">; 1749defm V_CMPX_LT_U16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x0b9, "v_cmpx_lt_u16">; 1750defm V_CMPX_EQ_U16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x0ba, "v_cmpx_eq_u16">; 1751defm V_CMPX_LE_U16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x0bb, "v_cmpx_le_u16">; 1752defm V_CMPX_GT_U16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x0bc, "v_cmpx_gt_u16">; 1753defm V_CMPX_NE_U16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x0bd, "v_cmpx_ne_u16">; 1754defm V_CMPX_GE_U16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x0be, "v_cmpx_ge_u16">; 1755defm V_CMPX_F_I32 : VOPCX_Real_gfx11<0x0c0>; 1756defm V_CMPX_LT_I32 : VOPCX_Real_gfx11_gfx12<0x0c1>; 1757defm V_CMPX_EQ_I32 : VOPCX_Real_gfx11_gfx12<0x0c2>; 1758defm V_CMPX_LE_I32 : VOPCX_Real_gfx11_gfx12<0x0c3>; 1759defm V_CMPX_GT_I32 : VOPCX_Real_gfx11_gfx12<0x0c4>; 1760defm V_CMPX_NE_I32 : VOPCX_Real_gfx11_gfx12<0x0c5>; 1761defm V_CMPX_GE_I32 : VOPCX_Real_gfx11_gfx12<0x0c6>; 1762defm V_CMPX_T_I32 : VOPCX_Real_gfx11<0x0c7>; 1763defm V_CMPX_F_U32 : VOPCX_Real_gfx11<0x0c8>; 1764defm V_CMPX_LT_U32 : VOPCX_Real_gfx11_gfx12<0x0c9>; 1765defm V_CMPX_EQ_U32 : VOPCX_Real_gfx11_gfx12<0x0ca>; 1766defm V_CMPX_LE_U32 : VOPCX_Real_gfx11_gfx12<0x0cb>; 1767defm V_CMPX_GT_U32 : VOPCX_Real_gfx11_gfx12<0x0cc>; 1768defm V_CMPX_NE_U32 : VOPCX_Real_gfx11_gfx12<0x0cd>; 1769defm V_CMPX_GE_U32 : VOPCX_Real_gfx11_gfx12<0x0ce>; 1770defm V_CMPX_T_U32 : VOPCX_Real_gfx11<0x0cf>; 1771 1772defm V_CMPX_F_I64 : VOPCX_Real_gfx11<0x0d0>; 1773defm V_CMPX_LT_I64 : VOPCX_Real_gfx11_gfx12<0x0d1>; 1774defm V_CMPX_EQ_I64 : VOPCX_Real_gfx11_gfx12<0x0d2>; 1775defm V_CMPX_LE_I64 : VOPCX_Real_gfx11_gfx12<0x0d3>; 1776defm V_CMPX_GT_I64 : VOPCX_Real_gfx11_gfx12<0x0d4>; 1777defm V_CMPX_NE_I64 : VOPCX_Real_gfx11_gfx12<0x0d5>; 1778defm V_CMPX_GE_I64 : VOPCX_Real_gfx11_gfx12<0x0d6>; 1779defm V_CMPX_T_I64 : VOPCX_Real_gfx11<0x0d7>; 1780defm V_CMPX_F_U64 : VOPCX_Real_gfx11<0x0d8>; 1781defm V_CMPX_LT_U64 : VOPCX_Real_gfx11_gfx12<0x0d9>; 1782defm V_CMPX_EQ_U64 : VOPCX_Real_gfx11_gfx12<0x0da>; 1783defm V_CMPX_LE_U64 : VOPCX_Real_gfx11_gfx12<0x0db>; 1784defm V_CMPX_GT_U64 : VOPCX_Real_gfx11_gfx12<0x0dc>; 1785defm V_CMPX_NE_U64 : VOPCX_Real_gfx11_gfx12<0x0dd>; 1786defm V_CMPX_GE_U64 : VOPCX_Real_gfx11_gfx12<0x0de>; 1787defm V_CMPX_T_U64 : VOPCX_Real_gfx11<0x0df>; 1788defm V_CMPX_CLASS_F16_t16 : VOPCX_Real_t16_gfx11_gfx12<0x0fd, "v_cmpx_class_f16">; 1789defm V_CMPX_CLASS_F32 : VOPCX_Real_gfx11_gfx12<0x0fe>; 1790defm V_CMPX_CLASS_F64 : VOPCX_Real_gfx11_gfx12<0x0ff>; 1791 1792//===----------------------------------------------------------------------===// 1793// GFX10. 1794//===----------------------------------------------------------------------===// 1795 1796let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in { 1797 multiclass VOPC_Real_gfx10<bits<9> op> { 1798 def _e32_gfx10 : 1799 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>, 1800 VOPCe<op{7-0}>; 1801 def _e64_gfx10 : 1802 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 1803 VOP3a_gfx10<{0, op}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1804 // Encoding used for VOPC instructions encoded as VOP3 differs from 1805 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. 1806 bits<8> sdst; 1807 let Inst{7-0} = sdst; 1808 } 1809 1810 if !cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then 1811 def _sdwa_gfx10 : 1812 VOP_SDWA10_Real<!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>, 1813 VOPC_SDWA9e<op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 1814 1815 defm : VOPCInstAliases<NAME, "gfx10">; 1816 } 1817 1818 multiclass VOPCX_Real_gfx10<bits<9> op> { 1819 def _e32_gfx10 : 1820 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_nosdst_e32"), SIEncodingFamily.GFX10>, 1821 VOPCe<op{7-0}> { 1822 let AsmString = !subst("_nosdst", "", !cast<VOPC_Pseudo>(NAME#"_nosdst_e32").PseudoInstr) 1823 # " " # !cast<VOPC_Pseudo>(NAME#"_nosdst_e32").AsmOperands; 1824 } 1825 1826 def _e64_gfx10 : 1827 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_nosdst_e64"), SIEncodingFamily.GFX10>, 1828 VOP3a_gfx10<{0, op}, !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").Pfl> { 1829 let Inst{7-0} = ?; // sdst 1830 let AsmString = !subst("_nosdst", "", !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").Mnemonic) 1831 # "{_e64} " # !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").AsmOperands; 1832 } 1833 1834 if !cast<VOPC_Pseudo>(NAME#"_nosdst_e32").Pfl.HasExtSDWA9 then 1835 def _sdwa_gfx10 : 1836 VOP_SDWA10_Real<!cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa")>, 1837 VOPC_SDWA9e<op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").Pfl> { 1838 let AsmString = !subst("_nosdst", "", !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").Mnemonic) 1839 # "{_sdwa} " # !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").AsmOperands9; 1840 } 1841 1842 defm : VOPCXInstAliases<NAME, "gfx10">; 1843 } 1844} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" 1845 1846defm V_CMP_LT_I16 : VOPC_Real_gfx10<0x089>; 1847defm V_CMP_EQ_I16 : VOPC_Real_gfx10<0x08a>; 1848defm V_CMP_LE_I16 : VOPC_Real_gfx10<0x08b>; 1849defm V_CMP_GT_I16 : VOPC_Real_gfx10<0x08c>; 1850defm V_CMP_NE_I16 : VOPC_Real_gfx10<0x08d>; 1851defm V_CMP_GE_I16 : VOPC_Real_gfx10<0x08e>; 1852defm V_CMP_CLASS_F16 : VOPC_Real_gfx10<0x08f>; 1853defm V_CMPX_LT_I16 : VOPCX_Real_gfx10<0x099>; 1854defm V_CMPX_EQ_I16 : VOPCX_Real_gfx10<0x09a>; 1855defm V_CMPX_LE_I16 : VOPCX_Real_gfx10<0x09b>; 1856defm V_CMPX_GT_I16 : VOPCX_Real_gfx10<0x09c>; 1857defm V_CMPX_NE_I16 : VOPCX_Real_gfx10<0x09d>; 1858defm V_CMPX_GE_I16 : VOPCX_Real_gfx10<0x09e>; 1859defm V_CMPX_CLASS_F16 : VOPCX_Real_gfx10<0x09f>; 1860defm V_CMP_LT_U16 : VOPC_Real_gfx10<0x0a9>; 1861defm V_CMP_EQ_U16 : VOPC_Real_gfx10<0x0aa>; 1862defm V_CMP_LE_U16 : VOPC_Real_gfx10<0x0ab>; 1863defm V_CMP_GT_U16 : VOPC_Real_gfx10<0x0ac>; 1864defm V_CMP_NE_U16 : VOPC_Real_gfx10<0x0ad>; 1865defm V_CMP_GE_U16 : VOPC_Real_gfx10<0x0ae>; 1866defm V_CMPX_LT_U16 : VOPCX_Real_gfx10<0x0b9>; 1867defm V_CMPX_EQ_U16 : VOPCX_Real_gfx10<0x0ba>; 1868defm V_CMPX_LE_U16 : VOPCX_Real_gfx10<0x0bb>; 1869defm V_CMPX_GT_U16 : VOPCX_Real_gfx10<0x0bc>; 1870defm V_CMPX_NE_U16 : VOPCX_Real_gfx10<0x0bd>; 1871defm V_CMPX_GE_U16 : VOPCX_Real_gfx10<0x0be>; 1872defm V_CMP_F_F16 : VOPC_Real_gfx10<0x0c8>; 1873defm V_CMP_LT_F16 : VOPC_Real_gfx10<0x0c9>; 1874defm V_CMP_EQ_F16 : VOPC_Real_gfx10<0x0ca>; 1875defm V_CMP_LE_F16 : VOPC_Real_gfx10<0x0cb>; 1876defm V_CMP_GT_F16 : VOPC_Real_gfx10<0x0cc>; 1877defm V_CMP_LG_F16 : VOPC_Real_gfx10<0x0cd>; 1878defm V_CMP_GE_F16 : VOPC_Real_gfx10<0x0ce>; 1879defm V_CMP_O_F16 : VOPC_Real_gfx10<0x0cf>; 1880defm V_CMPX_F_F16 : VOPCX_Real_gfx10<0x0d8>; 1881defm V_CMPX_LT_F16 : VOPCX_Real_gfx10<0x0d9>; 1882defm V_CMPX_EQ_F16 : VOPCX_Real_gfx10<0x0da>; 1883defm V_CMPX_LE_F16 : VOPCX_Real_gfx10<0x0db>; 1884defm V_CMPX_GT_F16 : VOPCX_Real_gfx10<0x0dc>; 1885defm V_CMPX_LG_F16 : VOPCX_Real_gfx10<0x0dd>; 1886defm V_CMPX_GE_F16 : VOPCX_Real_gfx10<0x0de>; 1887defm V_CMPX_O_F16 : VOPCX_Real_gfx10<0x0df>; 1888defm V_CMP_U_F16 : VOPC_Real_gfx10<0x0e8>; 1889defm V_CMP_NGE_F16 : VOPC_Real_gfx10<0x0e9>; 1890defm V_CMP_NLG_F16 : VOPC_Real_gfx10<0x0ea>; 1891defm V_CMP_NGT_F16 : VOPC_Real_gfx10<0x0eb>; 1892defm V_CMP_NLE_F16 : VOPC_Real_gfx10<0x0ec>; 1893defm V_CMP_NEQ_F16 : VOPC_Real_gfx10<0x0ed>; 1894defm V_CMP_NLT_F16 : VOPC_Real_gfx10<0x0ee>; 1895defm V_CMP_TRU_F16 : VOPC_Real_gfx10<0x0ef>; 1896defm V_CMPX_U_F16 : VOPCX_Real_gfx10<0x0f8>; 1897defm V_CMPX_NGE_F16 : VOPCX_Real_gfx10<0x0f9>; 1898defm V_CMPX_NLG_F16 : VOPCX_Real_gfx10<0x0fa>; 1899defm V_CMPX_NGT_F16 : VOPCX_Real_gfx10<0x0fb>; 1900defm V_CMPX_NLE_F16 : VOPCX_Real_gfx10<0x0fc>; 1901defm V_CMPX_NEQ_F16 : VOPCX_Real_gfx10<0x0fd>; 1902defm V_CMPX_NLT_F16 : VOPCX_Real_gfx10<0x0fe>; 1903defm V_CMPX_TRU_F16 : VOPCX_Real_gfx10<0x0ff>; 1904 1905//===----------------------------------------------------------------------===// 1906// GFX6, GFX7, GFX10. 1907//===----------------------------------------------------------------------===// 1908 1909let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in { 1910 multiclass VOPC_Real_gfx6_gfx7<bits<9> op> { 1911 def _e32_gfx6_gfx7 : 1912 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>, 1913 VOPCe<op{7-0}>; 1914 def _e64_gfx6_gfx7 : 1915 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 1916 VOP3a_gfx6_gfx7<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1917 // Encoding used for VOPC instructions encoded as VOP3 differs from 1918 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst. 1919 bits<8> sdst; 1920 let Inst{7-0} = sdst; 1921 } 1922 1923 defm : VOPCInstAliases<NAME, "gfx6_gfx7">; 1924 } 1925} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" 1926 1927multiclass VOPC_Real_gfx6_gfx7_gfx10<bits<9> op> : 1928 VOPC_Real_gfx6_gfx7<op>, VOPC_Real_gfx10<op>; 1929 1930multiclass VOPCX_Real_gfx6_gfx7<bits<9> op> : 1931 VOPC_Real_gfx6_gfx7<op>; 1932 1933multiclass VOPCX_Real_gfx6_gfx7_gfx10 <bits<9> op> : 1934 VOPC_Real_gfx6_gfx7<op>, VOPCX_Real_gfx10<op>; 1935 1936multiclass VOPC_Real_gfx6_gfx7_gfx10_gfx11<bits<9> op> : 1937 VOPC_Real_gfx6_gfx7_gfx10<op>, VOPC_Real_Base<GFX11Gen, op>; 1938 1939multiclass VOPCX_Real_gfx6_gfx7_gfx10_gfx11<bits<9> op> : 1940 VOPCX_Real_gfx6_gfx7_gfx10<op>, VOPCX_Real<GFX11Gen, op>; 1941 1942multiclass VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<9> op> : 1943 VOPC_Real_gfx6_gfx7_gfx10_gfx11<op>, VOPC_Real_Base<GFX12Gen, op>; 1944 1945defm V_CMP_F_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x000>; 1946defm V_CMP_LT_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x001>; 1947defm V_CMP_EQ_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x002>; 1948defm V_CMP_LE_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x003>; 1949defm V_CMP_GT_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x004>; 1950defm V_CMP_LG_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x005>; 1951defm V_CMP_GE_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x006>; 1952defm V_CMP_O_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x007>; 1953defm V_CMP_U_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x008>; 1954defm V_CMP_NGE_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x009>; 1955defm V_CMP_NLG_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00a>; 1956defm V_CMP_NGT_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00b>; 1957defm V_CMP_NLE_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00c>; 1958defm V_CMP_NEQ_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00d>; 1959defm V_CMP_NLT_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00e>; 1960defm V_CMP_TRU_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x00f>; 1961defm V_CMPX_F_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x010>; 1962defm V_CMPX_LT_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x011>; 1963defm V_CMPX_EQ_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x012>; 1964defm V_CMPX_LE_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x013>; 1965defm V_CMPX_GT_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x014>; 1966defm V_CMPX_LG_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x015>; 1967defm V_CMPX_GE_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x016>; 1968defm V_CMPX_O_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x017>; 1969defm V_CMPX_U_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x018>; 1970defm V_CMPX_NGE_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x019>; 1971defm V_CMPX_NLG_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01a>; 1972defm V_CMPX_NGT_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01b>; 1973defm V_CMPX_NLE_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01c>; 1974defm V_CMPX_NEQ_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01d>; 1975defm V_CMPX_NLT_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01e>; 1976defm V_CMPX_TRU_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01f>; 1977defm V_CMP_F_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x020>; 1978defm V_CMP_LT_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x021>; 1979defm V_CMP_EQ_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x022>; 1980defm V_CMP_LE_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x023>; 1981defm V_CMP_GT_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x024>; 1982defm V_CMP_LG_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x025>; 1983defm V_CMP_GE_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x026>; 1984defm V_CMP_O_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x027>; 1985defm V_CMP_U_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x028>; 1986defm V_CMP_NGE_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x029>; 1987defm V_CMP_NLG_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02a>; 1988defm V_CMP_NGT_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02b>; 1989defm V_CMP_NLE_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02c>; 1990defm V_CMP_NEQ_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02d>; 1991defm V_CMP_NLT_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02e>; 1992defm V_CMP_TRU_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x02f>; 1993defm V_CMPX_F_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x030>; 1994defm V_CMPX_LT_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x031>; 1995defm V_CMPX_EQ_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x032>; 1996defm V_CMPX_LE_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x033>; 1997defm V_CMPX_GT_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x034>; 1998defm V_CMPX_LG_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x035>; 1999defm V_CMPX_GE_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x036>; 2000defm V_CMPX_O_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x037>; 2001defm V_CMPX_U_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x038>; 2002defm V_CMPX_NGE_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x039>; 2003defm V_CMPX_NLG_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03a>; 2004defm V_CMPX_NGT_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03b>; 2005defm V_CMPX_NLE_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03c>; 2006defm V_CMPX_NEQ_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03d>; 2007defm V_CMPX_NLT_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03e>; 2008defm V_CMPX_TRU_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x03f>; 2009defm V_CMPS_F_F32 : VOPC_Real_gfx6_gfx7<0x040>; 2010defm V_CMPS_LT_F32 : VOPC_Real_gfx6_gfx7<0x041>; 2011defm V_CMPS_EQ_F32 : VOPC_Real_gfx6_gfx7<0x042>; 2012defm V_CMPS_LE_F32 : VOPC_Real_gfx6_gfx7<0x043>; 2013defm V_CMPS_GT_F32 : VOPC_Real_gfx6_gfx7<0x044>; 2014defm V_CMPS_LG_F32 : VOPC_Real_gfx6_gfx7<0x045>; 2015defm V_CMPS_GE_F32 : VOPC_Real_gfx6_gfx7<0x046>; 2016defm V_CMPS_O_F32 : VOPC_Real_gfx6_gfx7<0x047>; 2017defm V_CMPS_U_F32 : VOPC_Real_gfx6_gfx7<0x048>; 2018defm V_CMPS_NGE_F32 : VOPC_Real_gfx6_gfx7<0x049>; 2019defm V_CMPS_NLG_F32 : VOPC_Real_gfx6_gfx7<0x04a>; 2020defm V_CMPS_NGT_F32 : VOPC_Real_gfx6_gfx7<0x04b>; 2021defm V_CMPS_NLE_F32 : VOPC_Real_gfx6_gfx7<0x04c>; 2022defm V_CMPS_NEQ_F32 : VOPC_Real_gfx6_gfx7<0x04d>; 2023defm V_CMPS_NLT_F32 : VOPC_Real_gfx6_gfx7<0x04e>; 2024defm V_CMPS_TRU_F32 : VOPC_Real_gfx6_gfx7<0x04f>; 2025defm V_CMPSX_F_F32 : VOPCX_Real_gfx6_gfx7<0x050>; 2026defm V_CMPSX_LT_F32 : VOPCX_Real_gfx6_gfx7<0x051>; 2027defm V_CMPSX_EQ_F32 : VOPCX_Real_gfx6_gfx7<0x052>; 2028defm V_CMPSX_LE_F32 : VOPCX_Real_gfx6_gfx7<0x053>; 2029defm V_CMPSX_GT_F32 : VOPCX_Real_gfx6_gfx7<0x054>; 2030defm V_CMPSX_LG_F32 : VOPCX_Real_gfx6_gfx7<0x055>; 2031defm V_CMPSX_GE_F32 : VOPCX_Real_gfx6_gfx7<0x056>; 2032defm V_CMPSX_O_F32 : VOPCX_Real_gfx6_gfx7<0x057>; 2033defm V_CMPSX_U_F32 : VOPCX_Real_gfx6_gfx7<0x058>; 2034defm V_CMPSX_NGE_F32 : VOPCX_Real_gfx6_gfx7<0x059>; 2035defm V_CMPSX_NLG_F32 : VOPCX_Real_gfx6_gfx7<0x05a>; 2036defm V_CMPSX_NGT_F32 : VOPCX_Real_gfx6_gfx7<0x05b>; 2037defm V_CMPSX_NLE_F32 : VOPCX_Real_gfx6_gfx7<0x05c>; 2038defm V_CMPSX_NEQ_F32 : VOPCX_Real_gfx6_gfx7<0x05d>; 2039defm V_CMPSX_NLT_F32 : VOPCX_Real_gfx6_gfx7<0x05e>; 2040defm V_CMPSX_TRU_F32 : VOPCX_Real_gfx6_gfx7<0x05f>; 2041defm V_CMPS_F_F64 : VOPC_Real_gfx6_gfx7<0x060>; 2042defm V_CMPS_LT_F64 : VOPC_Real_gfx6_gfx7<0x061>; 2043defm V_CMPS_EQ_F64 : VOPC_Real_gfx6_gfx7<0x062>; 2044defm V_CMPS_LE_F64 : VOPC_Real_gfx6_gfx7<0x063>; 2045defm V_CMPS_GT_F64 : VOPC_Real_gfx6_gfx7<0x064>; 2046defm V_CMPS_LG_F64 : VOPC_Real_gfx6_gfx7<0x065>; 2047defm V_CMPS_GE_F64 : VOPC_Real_gfx6_gfx7<0x066>; 2048defm V_CMPS_O_F64 : VOPC_Real_gfx6_gfx7<0x067>; 2049defm V_CMPS_U_F64 : VOPC_Real_gfx6_gfx7<0x068>; 2050defm V_CMPS_NGE_F64 : VOPC_Real_gfx6_gfx7<0x069>; 2051defm V_CMPS_NLG_F64 : VOPC_Real_gfx6_gfx7<0x06a>; 2052defm V_CMPS_NGT_F64 : VOPC_Real_gfx6_gfx7<0x06b>; 2053defm V_CMPS_NLE_F64 : VOPC_Real_gfx6_gfx7<0x06c>; 2054defm V_CMPS_NEQ_F64 : VOPC_Real_gfx6_gfx7<0x06d>; 2055defm V_CMPS_NLT_F64 : VOPC_Real_gfx6_gfx7<0x06e>; 2056defm V_CMPS_TRU_F64 : VOPC_Real_gfx6_gfx7<0x06f>; 2057defm V_CMPSX_F_F64 : VOPCX_Real_gfx6_gfx7<0x070>; 2058defm V_CMPSX_LT_F64 : VOPCX_Real_gfx6_gfx7<0x071>; 2059defm V_CMPSX_EQ_F64 : VOPCX_Real_gfx6_gfx7<0x072>; 2060defm V_CMPSX_LE_F64 : VOPCX_Real_gfx6_gfx7<0x073>; 2061defm V_CMPSX_GT_F64 : VOPCX_Real_gfx6_gfx7<0x074>; 2062defm V_CMPSX_LG_F64 : VOPCX_Real_gfx6_gfx7<0x075>; 2063defm V_CMPSX_GE_F64 : VOPCX_Real_gfx6_gfx7<0x076>; 2064defm V_CMPSX_O_F64 : VOPCX_Real_gfx6_gfx7<0x077>; 2065defm V_CMPSX_U_F64 : VOPCX_Real_gfx6_gfx7<0x078>; 2066defm V_CMPSX_NGE_F64 : VOPCX_Real_gfx6_gfx7<0x079>; 2067defm V_CMPSX_NLG_F64 : VOPCX_Real_gfx6_gfx7<0x07a>; 2068defm V_CMPSX_NGT_F64 : VOPCX_Real_gfx6_gfx7<0x07b>; 2069defm V_CMPSX_NLE_F64 : VOPCX_Real_gfx6_gfx7<0x07c>; 2070defm V_CMPSX_NEQ_F64 : VOPCX_Real_gfx6_gfx7<0x07d>; 2071defm V_CMPSX_NLT_F64 : VOPCX_Real_gfx6_gfx7<0x07e>; 2072defm V_CMPSX_TRU_F64 : VOPCX_Real_gfx6_gfx7<0x07f>; 2073defm V_CMP_F_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x080>; 2074defm V_CMP_LT_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x081>; 2075defm V_CMP_EQ_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x082>; 2076defm V_CMP_LE_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x083>; 2077defm V_CMP_GT_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x084>; 2078defm V_CMP_NE_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x085>; 2079defm V_CMP_GE_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x086>; 2080defm V_CMP_T_I32 : VOPC_Real_gfx6_gfx7_gfx10<0x087>; 2081defm V_CMP_CLASS_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x088>; 2082defm V_CMPX_F_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x090>; 2083defm V_CMPX_LT_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x091>; 2084defm V_CMPX_EQ_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x092>; 2085defm V_CMPX_LE_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x093>; 2086defm V_CMPX_GT_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x094>; 2087defm V_CMPX_NE_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x095>; 2088defm V_CMPX_GE_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x096>; 2089defm V_CMPX_T_I32 : VOPCX_Real_gfx6_gfx7_gfx10<0x097>; 2090defm V_CMPX_CLASS_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x098>; 2091defm V_CMP_F_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a0>; 2092defm V_CMP_LT_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a1>; 2093defm V_CMP_EQ_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a2>; 2094defm V_CMP_LE_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a3>; 2095defm V_CMP_GT_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a4>; 2096defm V_CMP_NE_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a5>; 2097defm V_CMP_GE_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a6>; 2098defm V_CMP_T_I64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a7>; 2099defm V_CMP_CLASS_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x0a8>; 2100defm V_CMPX_F_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b0>; 2101defm V_CMPX_LT_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b1>; 2102defm V_CMPX_EQ_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b2>; 2103defm V_CMPX_LE_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b3>; 2104defm V_CMPX_GT_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b4>; 2105defm V_CMPX_NE_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b5>; 2106defm V_CMPX_GE_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b6>; 2107defm V_CMPX_T_I64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b7>; 2108defm V_CMPX_CLASS_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b8>; 2109defm V_CMP_F_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c0>; 2110defm V_CMP_LT_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c1>; 2111defm V_CMP_EQ_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c2>; 2112defm V_CMP_LE_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c3>; 2113defm V_CMP_GT_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c4>; 2114defm V_CMP_NE_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c5>; 2115defm V_CMP_GE_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c6>; 2116defm V_CMP_T_U32 : VOPC_Real_gfx6_gfx7_gfx10<0x0c7>; 2117defm V_CMPX_F_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d0>; 2118defm V_CMPX_LT_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d1>; 2119defm V_CMPX_EQ_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d2>; 2120defm V_CMPX_LE_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d3>; 2121defm V_CMPX_GT_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d4>; 2122defm V_CMPX_NE_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d5>; 2123defm V_CMPX_GE_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d6>; 2124defm V_CMPX_T_U32 : VOPCX_Real_gfx6_gfx7_gfx10<0x0d7>; 2125defm V_CMP_F_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e0>; 2126defm V_CMP_LT_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e1>; 2127defm V_CMP_EQ_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e2>; 2128defm V_CMP_LE_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e3>; 2129defm V_CMP_GT_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e4>; 2130defm V_CMP_NE_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e5>; 2131defm V_CMP_GE_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e6>; 2132defm V_CMP_T_U64 : VOPC_Real_gfx6_gfx7_gfx10<0x0e7>; 2133defm V_CMPX_F_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f0>; 2134defm V_CMPX_LT_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f1>; 2135defm V_CMPX_EQ_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f2>; 2136defm V_CMPX_LE_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f3>; 2137defm V_CMPX_GT_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f4>; 2138defm V_CMPX_NE_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f5>; 2139defm V_CMPX_GE_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f6>; 2140defm V_CMPX_T_U64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0f7>; 2141 2142//===----------------------------------------------------------------------===// 2143// GFX8, GFX9 (VI). 2144//===----------------------------------------------------------------------===// 2145 2146multiclass VOPC_Real_vi <bits<10> op> { 2147 let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { 2148 def _e32_vi : 2149 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>, 2150 VOPCe<op{7-0}>; 2151 2152 def _e64_vi : 2153 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 2154 VOP3a_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 2155 // Encoding used for VOPC instructions encoded as VOP3 2156 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst 2157 bits<8> sdst; 2158 let Inst{7-0} = sdst; 2159 } 2160 } 2161 2162 if !cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA then 2163 def _sdwa_vi : 2164 VOP_SDWA_Real <!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>, 2165 VOPC_SDWAe <op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 2166 2167 if !cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then 2168 def _sdwa_gfx9 : 2169 VOP_SDWA9_Real <!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>, 2170 VOPC_SDWA9e <op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>; 2171 2172 let AssemblerPredicate = isGFX8GFX9 in { 2173 defm : VOPCInstAliases<NAME, "vi">; 2174 } 2175} 2176 2177defm V_CMP_CLASS_F32 : VOPC_Real_vi <0x10>; 2178defm V_CMPX_CLASS_F32 : VOPC_Real_vi <0x11>; 2179defm V_CMP_CLASS_F64 : VOPC_Real_vi <0x12>; 2180defm V_CMPX_CLASS_F64 : VOPC_Real_vi <0x13>; 2181defm V_CMP_CLASS_F16 : VOPC_Real_vi <0x14>; 2182defm V_CMPX_CLASS_F16 : VOPC_Real_vi <0x15>; 2183 2184defm V_CMP_F_F16 : VOPC_Real_vi <0x20>; 2185defm V_CMP_LT_F16 : VOPC_Real_vi <0x21>; 2186defm V_CMP_EQ_F16 : VOPC_Real_vi <0x22>; 2187defm V_CMP_LE_F16 : VOPC_Real_vi <0x23>; 2188defm V_CMP_GT_F16 : VOPC_Real_vi <0x24>; 2189defm V_CMP_LG_F16 : VOPC_Real_vi <0x25>; 2190defm V_CMP_GE_F16 : VOPC_Real_vi <0x26>; 2191defm V_CMP_O_F16 : VOPC_Real_vi <0x27>; 2192defm V_CMP_U_F16 : VOPC_Real_vi <0x28>; 2193defm V_CMP_NGE_F16 : VOPC_Real_vi <0x29>; 2194defm V_CMP_NLG_F16 : VOPC_Real_vi <0x2a>; 2195defm V_CMP_NGT_F16 : VOPC_Real_vi <0x2b>; 2196defm V_CMP_NLE_F16 : VOPC_Real_vi <0x2c>; 2197defm V_CMP_NEQ_F16 : VOPC_Real_vi <0x2d>; 2198defm V_CMP_NLT_F16 : VOPC_Real_vi <0x2e>; 2199defm V_CMP_TRU_F16 : VOPC_Real_vi <0x2f>; 2200 2201defm V_CMPX_F_F16 : VOPC_Real_vi <0x30>; 2202defm V_CMPX_LT_F16 : VOPC_Real_vi <0x31>; 2203defm V_CMPX_EQ_F16 : VOPC_Real_vi <0x32>; 2204defm V_CMPX_LE_F16 : VOPC_Real_vi <0x33>; 2205defm V_CMPX_GT_F16 : VOPC_Real_vi <0x34>; 2206defm V_CMPX_LG_F16 : VOPC_Real_vi <0x35>; 2207defm V_CMPX_GE_F16 : VOPC_Real_vi <0x36>; 2208defm V_CMPX_O_F16 : VOPC_Real_vi <0x37>; 2209defm V_CMPX_U_F16 : VOPC_Real_vi <0x38>; 2210defm V_CMPX_NGE_F16 : VOPC_Real_vi <0x39>; 2211defm V_CMPX_NLG_F16 : VOPC_Real_vi <0x3a>; 2212defm V_CMPX_NGT_F16 : VOPC_Real_vi <0x3b>; 2213defm V_CMPX_NLE_F16 : VOPC_Real_vi <0x3c>; 2214defm V_CMPX_NEQ_F16 : VOPC_Real_vi <0x3d>; 2215defm V_CMPX_NLT_F16 : VOPC_Real_vi <0x3e>; 2216defm V_CMPX_TRU_F16 : VOPC_Real_vi <0x3f>; 2217 2218defm V_CMP_F_F32 : VOPC_Real_vi <0x40>; 2219defm V_CMP_LT_F32 : VOPC_Real_vi <0x41>; 2220defm V_CMP_EQ_F32 : VOPC_Real_vi <0x42>; 2221defm V_CMP_LE_F32 : VOPC_Real_vi <0x43>; 2222defm V_CMP_GT_F32 : VOPC_Real_vi <0x44>; 2223defm V_CMP_LG_F32 : VOPC_Real_vi <0x45>; 2224defm V_CMP_GE_F32 : VOPC_Real_vi <0x46>; 2225defm V_CMP_O_F32 : VOPC_Real_vi <0x47>; 2226defm V_CMP_U_F32 : VOPC_Real_vi <0x48>; 2227defm V_CMP_NGE_F32 : VOPC_Real_vi <0x49>; 2228defm V_CMP_NLG_F32 : VOPC_Real_vi <0x4a>; 2229defm V_CMP_NGT_F32 : VOPC_Real_vi <0x4b>; 2230defm V_CMP_NLE_F32 : VOPC_Real_vi <0x4c>; 2231defm V_CMP_NEQ_F32 : VOPC_Real_vi <0x4d>; 2232defm V_CMP_NLT_F32 : VOPC_Real_vi <0x4e>; 2233defm V_CMP_TRU_F32 : VOPC_Real_vi <0x4f>; 2234 2235defm V_CMPX_F_F32 : VOPC_Real_vi <0x50>; 2236defm V_CMPX_LT_F32 : VOPC_Real_vi <0x51>; 2237defm V_CMPX_EQ_F32 : VOPC_Real_vi <0x52>; 2238defm V_CMPX_LE_F32 : VOPC_Real_vi <0x53>; 2239defm V_CMPX_GT_F32 : VOPC_Real_vi <0x54>; 2240defm V_CMPX_LG_F32 : VOPC_Real_vi <0x55>; 2241defm V_CMPX_GE_F32 : VOPC_Real_vi <0x56>; 2242defm V_CMPX_O_F32 : VOPC_Real_vi <0x57>; 2243defm V_CMPX_U_F32 : VOPC_Real_vi <0x58>; 2244defm V_CMPX_NGE_F32 : VOPC_Real_vi <0x59>; 2245defm V_CMPX_NLG_F32 : VOPC_Real_vi <0x5a>; 2246defm V_CMPX_NGT_F32 : VOPC_Real_vi <0x5b>; 2247defm V_CMPX_NLE_F32 : VOPC_Real_vi <0x5c>; 2248defm V_CMPX_NEQ_F32 : VOPC_Real_vi <0x5d>; 2249defm V_CMPX_NLT_F32 : VOPC_Real_vi <0x5e>; 2250defm V_CMPX_TRU_F32 : VOPC_Real_vi <0x5f>; 2251 2252defm V_CMP_F_F64 : VOPC_Real_vi <0x60>; 2253defm V_CMP_LT_F64 : VOPC_Real_vi <0x61>; 2254defm V_CMP_EQ_F64 : VOPC_Real_vi <0x62>; 2255defm V_CMP_LE_F64 : VOPC_Real_vi <0x63>; 2256defm V_CMP_GT_F64 : VOPC_Real_vi <0x64>; 2257defm V_CMP_LG_F64 : VOPC_Real_vi <0x65>; 2258defm V_CMP_GE_F64 : VOPC_Real_vi <0x66>; 2259defm V_CMP_O_F64 : VOPC_Real_vi <0x67>; 2260defm V_CMP_U_F64 : VOPC_Real_vi <0x68>; 2261defm V_CMP_NGE_F64 : VOPC_Real_vi <0x69>; 2262defm V_CMP_NLG_F64 : VOPC_Real_vi <0x6a>; 2263defm V_CMP_NGT_F64 : VOPC_Real_vi <0x6b>; 2264defm V_CMP_NLE_F64 : VOPC_Real_vi <0x6c>; 2265defm V_CMP_NEQ_F64 : VOPC_Real_vi <0x6d>; 2266defm V_CMP_NLT_F64 : VOPC_Real_vi <0x6e>; 2267defm V_CMP_TRU_F64 : VOPC_Real_vi <0x6f>; 2268 2269defm V_CMPX_F_F64 : VOPC_Real_vi <0x70>; 2270defm V_CMPX_LT_F64 : VOPC_Real_vi <0x71>; 2271defm V_CMPX_EQ_F64 : VOPC_Real_vi <0x72>; 2272defm V_CMPX_LE_F64 : VOPC_Real_vi <0x73>; 2273defm V_CMPX_GT_F64 : VOPC_Real_vi <0x74>; 2274defm V_CMPX_LG_F64 : VOPC_Real_vi <0x75>; 2275defm V_CMPX_GE_F64 : VOPC_Real_vi <0x76>; 2276defm V_CMPX_O_F64 : VOPC_Real_vi <0x77>; 2277defm V_CMPX_U_F64 : VOPC_Real_vi <0x78>; 2278defm V_CMPX_NGE_F64 : VOPC_Real_vi <0x79>; 2279defm V_CMPX_NLG_F64 : VOPC_Real_vi <0x7a>; 2280defm V_CMPX_NGT_F64 : VOPC_Real_vi <0x7b>; 2281defm V_CMPX_NLE_F64 : VOPC_Real_vi <0x7c>; 2282defm V_CMPX_NEQ_F64 : VOPC_Real_vi <0x7d>; 2283defm V_CMPX_NLT_F64 : VOPC_Real_vi <0x7e>; 2284defm V_CMPX_TRU_F64 : VOPC_Real_vi <0x7f>; 2285 2286defm V_CMP_F_I16 : VOPC_Real_vi <0xa0>; 2287defm V_CMP_LT_I16 : VOPC_Real_vi <0xa1>; 2288defm V_CMP_EQ_I16 : VOPC_Real_vi <0xa2>; 2289defm V_CMP_LE_I16 : VOPC_Real_vi <0xa3>; 2290defm V_CMP_GT_I16 : VOPC_Real_vi <0xa4>; 2291defm V_CMP_NE_I16 : VOPC_Real_vi <0xa5>; 2292defm V_CMP_GE_I16 : VOPC_Real_vi <0xa6>; 2293defm V_CMP_T_I16 : VOPC_Real_vi <0xa7>; 2294 2295defm V_CMP_F_U16 : VOPC_Real_vi <0xa8>; 2296defm V_CMP_LT_U16 : VOPC_Real_vi <0xa9>; 2297defm V_CMP_EQ_U16 : VOPC_Real_vi <0xaa>; 2298defm V_CMP_LE_U16 : VOPC_Real_vi <0xab>; 2299defm V_CMP_GT_U16 : VOPC_Real_vi <0xac>; 2300defm V_CMP_NE_U16 : VOPC_Real_vi <0xad>; 2301defm V_CMP_GE_U16 : VOPC_Real_vi <0xae>; 2302defm V_CMP_T_U16 : VOPC_Real_vi <0xaf>; 2303 2304defm V_CMPX_F_I16 : VOPC_Real_vi <0xb0>; 2305defm V_CMPX_LT_I16 : VOPC_Real_vi <0xb1>; 2306defm V_CMPX_EQ_I16 : VOPC_Real_vi <0xb2>; 2307defm V_CMPX_LE_I16 : VOPC_Real_vi <0xb3>; 2308defm V_CMPX_GT_I16 : VOPC_Real_vi <0xb4>; 2309defm V_CMPX_NE_I16 : VOPC_Real_vi <0xb5>; 2310defm V_CMPX_GE_I16 : VOPC_Real_vi <0xb6>; 2311defm V_CMPX_T_I16 : VOPC_Real_vi <0xb7>; 2312 2313defm V_CMPX_F_U16 : VOPC_Real_vi <0xb8>; 2314defm V_CMPX_LT_U16 : VOPC_Real_vi <0xb9>; 2315defm V_CMPX_EQ_U16 : VOPC_Real_vi <0xba>; 2316defm V_CMPX_LE_U16 : VOPC_Real_vi <0xbb>; 2317defm V_CMPX_GT_U16 : VOPC_Real_vi <0xbc>; 2318defm V_CMPX_NE_U16 : VOPC_Real_vi <0xbd>; 2319defm V_CMPX_GE_U16 : VOPC_Real_vi <0xbe>; 2320defm V_CMPX_T_U16 : VOPC_Real_vi <0xbf>; 2321 2322defm V_CMP_F_I32 : VOPC_Real_vi <0xc0>; 2323defm V_CMP_LT_I32 : VOPC_Real_vi <0xc1>; 2324defm V_CMP_EQ_I32 : VOPC_Real_vi <0xc2>; 2325defm V_CMP_LE_I32 : VOPC_Real_vi <0xc3>; 2326defm V_CMP_GT_I32 : VOPC_Real_vi <0xc4>; 2327defm V_CMP_NE_I32 : VOPC_Real_vi <0xc5>; 2328defm V_CMP_GE_I32 : VOPC_Real_vi <0xc6>; 2329defm V_CMP_T_I32 : VOPC_Real_vi <0xc7>; 2330 2331defm V_CMPX_F_I32 : VOPC_Real_vi <0xd0>; 2332defm V_CMPX_LT_I32 : VOPC_Real_vi <0xd1>; 2333defm V_CMPX_EQ_I32 : VOPC_Real_vi <0xd2>; 2334defm V_CMPX_LE_I32 : VOPC_Real_vi <0xd3>; 2335defm V_CMPX_GT_I32 : VOPC_Real_vi <0xd4>; 2336defm V_CMPX_NE_I32 : VOPC_Real_vi <0xd5>; 2337defm V_CMPX_GE_I32 : VOPC_Real_vi <0xd6>; 2338defm V_CMPX_T_I32 : VOPC_Real_vi <0xd7>; 2339 2340defm V_CMP_F_I64 : VOPC_Real_vi <0xe0>; 2341defm V_CMP_LT_I64 : VOPC_Real_vi <0xe1>; 2342defm V_CMP_EQ_I64 : VOPC_Real_vi <0xe2>; 2343defm V_CMP_LE_I64 : VOPC_Real_vi <0xe3>; 2344defm V_CMP_GT_I64 : VOPC_Real_vi <0xe4>; 2345defm V_CMP_NE_I64 : VOPC_Real_vi <0xe5>; 2346defm V_CMP_GE_I64 : VOPC_Real_vi <0xe6>; 2347defm V_CMP_T_I64 : VOPC_Real_vi <0xe7>; 2348 2349defm V_CMPX_F_I64 : VOPC_Real_vi <0xf0>; 2350defm V_CMPX_LT_I64 : VOPC_Real_vi <0xf1>; 2351defm V_CMPX_EQ_I64 : VOPC_Real_vi <0xf2>; 2352defm V_CMPX_LE_I64 : VOPC_Real_vi <0xf3>; 2353defm V_CMPX_GT_I64 : VOPC_Real_vi <0xf4>; 2354defm V_CMPX_NE_I64 : VOPC_Real_vi <0xf5>; 2355defm V_CMPX_GE_I64 : VOPC_Real_vi <0xf6>; 2356defm V_CMPX_T_I64 : VOPC_Real_vi <0xf7>; 2357 2358defm V_CMP_F_U32 : VOPC_Real_vi <0xc8>; 2359defm V_CMP_LT_U32 : VOPC_Real_vi <0xc9>; 2360defm V_CMP_EQ_U32 : VOPC_Real_vi <0xca>; 2361defm V_CMP_LE_U32 : VOPC_Real_vi <0xcb>; 2362defm V_CMP_GT_U32 : VOPC_Real_vi <0xcc>; 2363defm V_CMP_NE_U32 : VOPC_Real_vi <0xcd>; 2364defm V_CMP_GE_U32 : VOPC_Real_vi <0xce>; 2365defm V_CMP_T_U32 : VOPC_Real_vi <0xcf>; 2366 2367defm V_CMPX_F_U32 : VOPC_Real_vi <0xd8>; 2368defm V_CMPX_LT_U32 : VOPC_Real_vi <0xd9>; 2369defm V_CMPX_EQ_U32 : VOPC_Real_vi <0xda>; 2370defm V_CMPX_LE_U32 : VOPC_Real_vi <0xdb>; 2371defm V_CMPX_GT_U32 : VOPC_Real_vi <0xdc>; 2372defm V_CMPX_NE_U32 : VOPC_Real_vi <0xdd>; 2373defm V_CMPX_GE_U32 : VOPC_Real_vi <0xde>; 2374defm V_CMPX_T_U32 : VOPC_Real_vi <0xdf>; 2375 2376defm V_CMP_F_U64 : VOPC_Real_vi <0xe8>; 2377defm V_CMP_LT_U64 : VOPC_Real_vi <0xe9>; 2378defm V_CMP_EQ_U64 : VOPC_Real_vi <0xea>; 2379defm V_CMP_LE_U64 : VOPC_Real_vi <0xeb>; 2380defm V_CMP_GT_U64 : VOPC_Real_vi <0xec>; 2381defm V_CMP_NE_U64 : VOPC_Real_vi <0xed>; 2382defm V_CMP_GE_U64 : VOPC_Real_vi <0xee>; 2383defm V_CMP_T_U64 : VOPC_Real_vi <0xef>; 2384 2385defm V_CMPX_F_U64 : VOPC_Real_vi <0xf8>; 2386defm V_CMPX_LT_U64 : VOPC_Real_vi <0xf9>; 2387defm V_CMPX_EQ_U64 : VOPC_Real_vi <0xfa>; 2388defm V_CMPX_LE_U64 : VOPC_Real_vi <0xfb>; 2389defm V_CMPX_GT_U64 : VOPC_Real_vi <0xfc>; 2390defm V_CMPX_NE_U64 : VOPC_Real_vi <0xfd>; 2391defm V_CMPX_GE_U64 : VOPC_Real_vi <0xfe>; 2392defm V_CMPX_T_U64 : VOPC_Real_vi <0xff>; 2393