1//===-- VOP3Instructions.td - Vector Instruction Defintions ---------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// VOP3 Classes 11//===----------------------------------------------------------------------===// 12 13class getVOP3ModPat<VOPProfile P, SDPatternOperator node> { 14 dag src0 = !if(P.HasOMod, 15 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 16 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)); 17 18 list<dag> ret3 = [(set P.DstVT:$vdst, 19 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 20 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), 21 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))]; 22 23 list<dag> ret2 = [(set P.DstVT:$vdst, 24 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 25 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))]; 26 27 list<dag> ret1 = [(set P.DstVT:$vdst, 28 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))]; 29 30 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 31 !if(!eq(P.NumSrcArgs, 2), ret2, 32 ret1)); 33} 34 35class getVOP3PModPat<VOPProfile P, SDPatternOperator node> { 36 list<dag> ret3 = [(set P.DstVT:$vdst, 37 (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp), 38 (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))), 39 (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers)), 40 (P.Src2VT (VOP3PMods P.Src2VT:$src2, i32:$src2_modifiers))))]; 41 42 list<dag> ret2 = [(set P.DstVT:$vdst, 43 (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)), 44 (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))), 45 (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers))))]; 46 47 list<dag> ret1 = [(set P.DstVT:$vdst, 48 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))]; 49 50 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 51 !if(!eq(P.NumSrcArgs, 2), ret2, 52 ret1)); 53} 54 55class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> { 56 list<dag> ret3 = [(set P.DstVT:$vdst, 57 (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp), 58 (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))), 59 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)), 60 (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))]; 61 62 list<dag> ret2 = [(set P.DstVT:$vdst, 63 (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)), 64 (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))), 65 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))]; 66 67 list<dag> ret1 = [(set P.DstVT:$vdst, 68 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))]; 69 70 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 71 !if(!eq(P.NumSrcArgs, 2), ret2, 72 ret1)); 73} 74 75class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> { 76 list<dag> ret3 = [(set P.DstVT:$vdst, 77 (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp), 78 (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 79 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)), 80 (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))]; 81 82 list<dag> ret2 = [(set P.DstVT:$vdst, 83 (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)), 84 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 85 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))]; 86 87 list<dag> ret1 = [(set P.DstVT:$vdst, 88 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))]; 89 90 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 91 !if(!eq(P.NumSrcArgs, 2), ret2, 92 ret1)); 93} 94 95class getVOP3Pat<VOPProfile P, SDPatternOperator node> { 96 list<dag> ret3 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))]; 97 list<dag> ret2 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1))]; 98 list<dag> ret1 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0))]; 99 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 100 !if(!eq(P.NumSrcArgs, 2), ret2, 101 ret1)); 102} 103 104class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> { 105 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))]; 106 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))]; 107 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))]; 108 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 109 !if(!eq(P.NumSrcArgs, 2), ret2, 110 ret1)); 111} 112 113class getVOP3MAIPat<VOPProfile P, SDPatternOperator node> { 114 list<dag> ret = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, 115 timm:$cbsz, timm:$abid, timm:$blgp))]; 116} 117 118class VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit VOP3Only = 0> : 119 VOP3_Pseudo<OpName, P, 120 !if(P.HasOpSel, 121 !if(P.HasModifiers, 122 getVOP3OpSelModPat<P, node>.ret, 123 getVOP3OpSelPat<P, node>.ret), 124 !if(P.HasModifiers, 125 getVOP3ModPat<P, node>.ret, 126 !if(P.HasIntClamp, 127 getVOP3ClampPat<P, node>.ret, 128 !if (P.IsMAI, 129 getVOP3MAIPat<P, node>.ret, 130 getVOP3Pat<P, node>.ret)))), 131 VOP3Only, 0, P.HasOpSel> { 132 133 let IntClamp = P.HasIntClamp; 134 let AsmMatchConverter = 135 !if(P.HasOpSel, 136 "cvtVOP3OpSel", 137 !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)), 138 "cvtVOP3", 139 "")); 140} 141 142// Special case for v_div_fmas_{f32|f64}, since it seems to be the 143// only VOP instruction that implicitly reads VCC. 144let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in { 145def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> { 146 let Outs64 = (outs DstRC.RegClass:$vdst); 147} 148def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> { 149 let Outs64 = (outs DstRC.RegClass:$vdst); 150} 151} 152 153class VOP3Features<bit Clamp, bit OpSel, bit Packed, bit MAI> { 154 bit HasClamp = Clamp; 155 bit HasOpSel = OpSel; 156 bit IsPacked = Packed; 157 bit IsMAI = MAI; 158} 159 160def VOP3_REGULAR : VOP3Features<0, 0, 0, 0>; 161def VOP3_CLAMP : VOP3Features<1, 0, 0, 0>; 162def VOP3_OPSEL : VOP3Features<1, 1, 0, 0>; 163def VOP3_PACKED : VOP3Features<1, 1, 1, 0>; 164def VOP3_MAI : VOP3Features<0, 0, 0, 1>; 165 166class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProfile<P.ArgVT> { 167 168 let HasClamp = !if(Features.HasClamp, 1, P.HasClamp); 169 let HasOpSel = !if(Features.HasOpSel, 1, P.HasOpSel); 170 let IsMAI = !if(Features.IsMAI, 1, P.IsMAI); 171 let IsPacked = !if(Features.IsPacked, 1, P.IsPacked); 172 173 let HasModifiers = !if(Features.IsPacked, !if(Features.IsMAI, 0, 1), P.HasModifiers); 174 175 // FIXME: Hack to stop printing _e64 176 let Outs64 = (outs DstRC.RegClass:$vdst); 177 let Asm64 = 178 " " # !if(Features.HasOpSel, 179 getAsmVOP3OpSel<NumSrcArgs, 180 HasIntClamp, 181 HasSrc0FloatMods, 182 HasSrc1FloatMods, 183 HasSrc2FloatMods>.ret, 184 !if(Features.HasClamp, 185 getAsm64<HasDst, NumSrcArgs, HasIntClamp, 186 HasModifiers, HasOMod, DstVT>.ret, 187 P.Asm64)); 188 let NeedPatGen = P.NeedPatGen; 189} 190 191class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> { 192 // v_div_scale_{f32|f64} do not support input modifiers. 193 let HasModifiers = 0; 194 let HasClamp = 0; 195 let HasOMod = 0; 196 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 197 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2"; 198} 199 200def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> { 201 // FIXME: Hack to stop printing _e64 202 let DstRC = RegisterOperand<VGPR_32>; 203} 204 205def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> { 206 // FIXME: Hack to stop printing _e64 207 let DstRC = RegisterOperand<VReg_64>; 208} 209 210def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> { 211 let HasClamp = 1; 212 213 // FIXME: Hack to stop printing _e64 214 let DstRC = RegisterOperand<VReg_64>; 215 216 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 217 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2$clamp"; 218} 219 220//===----------------------------------------------------------------------===// 221// VOP3 INTERP 222//===----------------------------------------------------------------------===// 223 224class VOP3Interp<string OpName, VOPProfile P, list<dag> pattern = []> : 225 VOP3_Pseudo<OpName, P, pattern> { 226 let AsmMatchConverter = "cvtVOP3Interp"; 227} 228 229def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> { 230 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 231 Attr:$attr, AttrChan:$attrchan, 232 clampmod:$clamp, omod:$omod); 233 234 let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod"; 235} 236 237def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> { 238 let Ins64 = (ins InterpSlot:$src0, 239 Attr:$attr, AttrChan:$attrchan, 240 clampmod:$clamp, omod:$omod); 241 242 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod"; 243 244 let HasClamp = 1; 245} 246 247class getInterp16Asm <bit HasSrc2, bit HasOMod> { 248 string src2 = !if(HasSrc2, ", $src2_modifiers", ""); 249 string omod = !if(HasOMod, "$omod", ""); 250 string ret = 251 " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod; 252} 253 254class getInterp16Ins <bit HasSrc2, bit HasOMod, 255 Operand Src0Mod, Operand Src2Mod> { 256 dag ret = !if(HasSrc2, 257 !if(HasOMod, 258 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 259 Attr:$attr, AttrChan:$attrchan, 260 Src2Mod:$src2_modifiers, VRegSrc_32:$src2, 261 highmod:$high, clampmod:$clamp, omod:$omod), 262 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 263 Attr:$attr, AttrChan:$attrchan, 264 Src2Mod:$src2_modifiers, VRegSrc_32:$src2, 265 highmod:$high, clampmod:$clamp) 266 ), 267 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 268 Attr:$attr, AttrChan:$attrchan, 269 highmod:$high, clampmod:$clamp, omod:$omod) 270 ); 271} 272 273class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> { 274 275 let HasOMod = !if(!eq(DstVT.Value, f16.Value), 0, 1); 276 let HasHigh = 1; 277 278 let Outs64 = (outs VGPR_32:$vdst); 279 let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret; 280 let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret; 281} 282 283//===----------------------------------------------------------------------===// 284// VOP3 Instructions 285//===----------------------------------------------------------------------===// 286 287let isCommutable = 1 in { 288 289def V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 290def V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>; 291def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 292def V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 293def V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fma>; 294def V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>; 295 296let SchedRW = [WriteDoubleAdd] in { 297let FPDPRounding = 1 in { 298def V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, fma>; 299def V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, fadd, 1>; 300def V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul, 1>; 301} // End FPDPRounding = 1 302def V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum_like, 1>; 303def V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum_like, 1>; 304} // End SchedRW = [WriteDoubleAdd] 305 306let SchedRW = [WriteQuarterRate32] in { 307def V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile<VOP_I32_I32_I32>, mul>; 308def V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>; 309def V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile<VOP_I32_I32_I32>>; 310def V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile<VOP_I32_I32_I32>, mulhs>; 311} // End SchedRW = [WriteQuarterRate32] 312 313let Uses = [VCC, EXEC] in { 314// v_div_fmas_f32: 315// result = src0 * src1 + src2 316// if (vcc) 317// result *= 2^32 318// 319def V_DIV_FMAS_F32 : VOP3_Pseudo <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC, []> { 320 let SchedRW = [WriteFloatFMA]; 321} 322// v_div_fmas_f64: 323// result = src0 * src1 + src2 324// if (vcc) 325// result *= 2^64 326// 327def V_DIV_FMAS_F64 : VOP3_Pseudo <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC, []> { 328 let SchedRW = [WriteDouble]; 329 let FPDPRounding = 1; 330} 331} // End Uses = [VCC, EXEC] 332 333} // End isCommutable = 1 334 335def V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>; 336def V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>; 337def V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>; 338def V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>; 339def V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>; 340def V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>; 341def V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>; 342def V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbit>; 343def V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>; 344def V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>; 345def V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>; 346def V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>; 347def V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>; 348def V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>; 349def V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>; 350def V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>; 351def V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>; 352def V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>; 353def V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 354def V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 355def V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 356def V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 357def V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>; 358def V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>; 359 360let SchedRW = [WriteDoubleAdd], FPDPRounding = 1 in { 361def V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>; 362def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>; 363} // End SchedRW = [WriteDoubleAdd], FPDPRounding = 1 364 365def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> { 366 let SchedRW = [WriteFloatFMA, WriteSALU]; 367 let AsmMatchConverter = ""; 368} 369 370// Double precision division pre-scale. 371def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> { 372 let SchedRW = [WriteDouble, WriteSALU]; 373 let AsmMatchConverter = ""; 374 let FPDPRounding = 1; 375} 376 377def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 378 379let Constraints = "@earlyclobber $vdst" in { 380def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; 381} // End Constraints = "@earlyclobber $vdst" 382 383def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUtrig_preop> { 384 let SchedRW = [WriteDouble]; 385} 386 387let SchedRW = [Write64Bit] in { 388let SubtargetPredicate = isGFX6GFX7GFX10 in { 389def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>, shl>; 390def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>, srl>; 391def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>, sra>; 392def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 393} // End SubtargetPredicate = isGFX6GFX7GFX10 394 395let SubtargetPredicate = isGFX8Plus in { 396def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshl_rev>; 397def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshr_rev>; 398def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, ashr_rev>; 399} // End SubtargetPredicate = isGFX8Plus 400} // End SchedRW = [Write64Bit] 401 402 403let SchedRW = [Write32Bit] in { 404let SubtargetPredicate = isGFX8Plus in { 405def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUperm>; 406} // End SubtargetPredicate = isGFX8Plus 407} // End SchedRW = [Write32Bit] 408 409let SubtargetPredicate = isGFX7Plus in { 410 411let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in { 412def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; 413def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32, VOP3_CLAMP>>; 414} // End Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] 415 416let isCommutable = 1 in { 417let SchedRW = [WriteQuarterRate32, WriteSALU] in { 418def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>; 419def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>; 420} // End SchedRW = [WriteDouble, WriteSALU] 421} // End isCommutable = 1 422 423} // End SubtargetPredicate = isGFX7Plus 424 425 426def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup> { 427 let Predicates = [Has16BitInsts, isGFX8Only]; 428 let FPDPRounding = 1; 429} 430def V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9", 431 VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUdiv_fixup> { 432 let renamedInGFX9 = 1; 433 let Predicates = [Has16BitInsts, isGFX9Plus]; 434 let FPDPRounding = 1; 435} 436 437def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma> { 438 let Predicates = [Has16BitInsts, isGFX8Only]; 439 let FPDPRounding = 1; 440} 441def V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, fma> { 442 let renamedInGFX9 = 1; 443 let Predicates = [Has16BitInsts, isGFX9Plus]; 444 let FPDPRounding = 1; 445} 446 447let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in { 448 449let renamedInGFX9 = 1 in { 450def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; 451def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; 452let FPDPRounding = 1 in { 453def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>; 454let Uses = [M0, EXEC] in { 455def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>, 456 [(set f16:$vdst, (AMDGPUinterp_p2_f16 f32:$src0, (i32 timm:$attrchan), 457 (i32 timm:$attr), 458 (i32 timm:$src0_modifiers), 459 (f32 VRegSrc_32:$src2), 460 (i32 timm:$src2_modifiers), 461 (i1 timm:$high), 462 (i1 timm:$clamp)))]>; 463} // End Uses = [M0, EXEC] 464} // End FPDPRounding = 1 465} // End renamedInGFX9 = 1 466 467let SubtargetPredicate = isGFX9Only in { 468def V_MAD_F16_gfx9 : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>> { 469 let FPDPRounding = 1; 470} 471} // End SubtargetPredicate = isGFX9Only 472 473let SubtargetPredicate = isGFX9Plus in { 474def V_MAD_U16_gfx9 : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; 475def V_MAD_I16_gfx9 : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; 476def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>; 477} // End SubtargetPredicate = isGFX9Plus 478 479let Uses = [M0, EXEC], FPDPRounding = 1 in { 480def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>, 481 [(set f32:$vdst, (AMDGPUinterp_p1ll_f16 f32:$src0, (i32 timm:$attrchan), 482 (i32 timm:$attr), 483 (i32 timm:$src0_modifiers), 484 (i1 timm:$high), 485 (i1 timm:$clamp), 486 (i32 timm:$omod)))]>; 487def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>, 488 [(set f32:$vdst, (AMDGPUinterp_p1lv_f16 f32:$src0, (i32 timm:$attrchan), 489 (i32 timm:$attr), 490 (i32 timm:$src0_modifiers), 491 (f32 VRegSrc_32:$src2), 492 (i32 timm:$src2_modifiers), 493 (i1 timm:$high), 494 (i1 timm:$clamp), 495 (i32 timm:$omod)))]>; 496} // End Uses = [M0, EXEC], FPDPRounding = 1 497 498} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1 499 500let SubtargetPredicate = isGFX8GFX9 in { 501def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>; 502def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>; 503def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>; 504} // End SubtargetPredicate = isGFX8GFX9 505 506let Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] in { 507 508multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2, 509 Instruction inst, SDPatternOperator op3> { 510def : GCNPat < 511 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 512 (inst i16:$src0, i16:$src1, i16:$src2, (i1 0)) 513>; 514 515} 516 517defm: Ternary_i16_Pats<mul, add, V_MAD_U16, zext>; 518defm: Ternary_i16_Pats<mul, add, V_MAD_I16, sext>; 519 520} // End Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] 521 522let Predicates = [Has16BitInsts, isGFX10Plus] in { 523 524multiclass Ternary_i16_Pats_gfx9<SDPatternOperator op1, SDPatternOperator op2, 525 Instruction inst, SDPatternOperator op3> { 526def : GCNPat < 527 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 528 (inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1, SRCMODS.NONE, $src2, DSTCLAMP.NONE) 529>; 530 531} 532 533defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_U16_gfx9, zext>; 534defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_I16_gfx9, sext>; 535 536} // End Predicates = [Has16BitInsts, isGFX10Plus] 537 538class ThreeOpFrag<SDPatternOperator op1, SDPatternOperator op2> : PatFrag< 539 (ops node:$x, node:$y, node:$z), 540 // When the inner operation is used multiple times, selecting 3-op 541 // instructions may still be beneficial -- if the other users can be 542 // combined similarly. Let's be conservative for now. 543 (op2 (HasOneUseBinOp<op1> node:$x, node:$y), node:$z), 544 [{ 545 // Only use VALU ops when the result is divergent. 546 if (!N->isDivergent()) 547 return false; 548 549 // Check constant bus limitations. 550 // 551 // Note: Use !isDivergent as a conservative proxy for whether the value 552 // is in an SGPR (uniform values can end up in VGPRs as well). 553 unsigned ConstantBusUses = 0; 554 for (unsigned i = 0; i < 3; ++i) { 555 if (!Operands[i]->isDivergent() && 556 !isInlineImmediate(Operands[i].getNode())) { 557 ConstantBusUses++; 558 // This uses AMDGPU::V_ADD3_U32, but all three operand instructions 559 // have the same constant bus limit. 560 if (ConstantBusUses > Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32)) 561 return false; 562 } 563 } 564 565 return true; 566 }] 567> { 568 let PredicateCodeUsesOperands = 1; 569} 570 571let SubtargetPredicate = isGFX9Plus in { 572def V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 573def V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 574def V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 575def V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 576def V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 577def V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 578def V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 579 580def V_XAD_U32 : VOP3Inst <"v_xad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 581 582def V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmed3>; 583def V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmed3>; 584def V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumed3>; 585 586def V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmin3>; 587def V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmin3>; 588def V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumin3>; 589 590def V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmax3>; 591def V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmax3>; 592def V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumax3>; 593 594def V_ADD_I16 : VOP3Inst <"v_add_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; 595def V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; 596 597def V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; 598def V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; 599 600def V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 601def V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 602 603def V_ADD_I32_gfx9 : VOP3Inst <"v_add_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>; 604def V_SUB_I32_gfx9 : VOP3Inst <"v_sub_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>; 605 606 607class ThreeOp_i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst> : GCNPat < 608 // This matches (op2 (op1 i32:$src0, i32:$src1), i32:$src2) with conditions. 609 (ThreeOpFrag<op1, op2> i32:$src0, i32:$src1, i32:$src2), 610 (inst i32:$src0, i32:$src1, i32:$src2) 611>; 612 613def : ThreeOp_i32_Pats<shl, add, V_LSHL_ADD_U32>; 614def : ThreeOp_i32_Pats<add, shl, V_ADD_LSHL_U32>; 615def : ThreeOp_i32_Pats<add, add, V_ADD3_U32>; 616def : ThreeOp_i32_Pats<shl, or, V_LSHL_OR_B32>; 617def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32>; 618def : ThreeOp_i32_Pats<or, or, V_OR3_B32>; 619def : ThreeOp_i32_Pats<xor, add, V_XAD_U32>; 620 621} // End SubtargetPredicate = isGFX9Plus 622 623def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3_OPSEL> { 624 let Src0RC64 = VRegSrc_32; 625 let Src1RC64 = SCSrc_b32; 626 let Src2RC64 = SCSrc_b32; 627 let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0, 628 IntOpSelMods:$src1_modifiers, SCSrc_b32:$src1, 629 IntOpSelMods:$src2_modifiers, SCSrc_b32:$src2, 630 VGPR_32:$vdst_in, op_sel:$op_sel); 631 let HasClamp = 0; 632 let HasOMod = 0; 633} 634 635let SubtargetPredicate = isGFX10Plus in { 636 def V_XOR3_B32 : VOP3Inst <"v_xor3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 637 def : ThreeOp_i32_Pats<xor, xor, V_XOR3_B32>; 638 639 let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in { 640 def V_PERMLANE16_B32 : VOP3Inst <"v_permlane16_b32", VOP3_PERMLANE_Profile>; 641 def V_PERMLANEX16_B32 : VOP3Inst <"v_permlanex16_b32", VOP3_PERMLANE_Profile>; 642 } // End $vdst = $vdst_in, DisableEncoding $vdst_in 643 644 def : GCNPat< 645 (int_amdgcn_permlane16 i32:$vdst_in, i32:$src0, i32:$src1, i32:$src2, timm:$fi, timm:$bc), 646 (V_PERMLANE16_B32 (as_i1imm $fi), $src0, (as_i1imm $bc), $src1, 0, $src2, $vdst_in) 647 >; 648 def : GCNPat< 649 (int_amdgcn_permlanex16 i32:$vdst_in, i32:$src0, i32:$src1, i32:$src2, timm:$fi, timm:$bc), 650 (V_PERMLANEX16_B32 (as_i1imm $fi), $src0, (as_i1imm $bc), $src1, 0, $src2, $vdst_in) 651 >; 652} // End SubtargetPredicate = isGFX10Plus 653 654//===----------------------------------------------------------------------===// 655// Integer Clamp Patterns 656//===----------------------------------------------------------------------===// 657 658class getClampPat<VOPProfile P, SDPatternOperator node> { 659 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2)); 660 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1)); 661 dag ret1 = (P.DstVT (node P.Src0VT:$src0)); 662 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3, 663 !if(!eq(P.NumSrcArgs, 2), ret2, 664 ret1)); 665} 666 667class getClampRes<VOPProfile P, Instruction inst> { 668 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0)); 669 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0)); 670 dag ret1 = (inst P.Src0VT:$src0, (i1 0)); 671 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3, 672 !if(!eq(P.NumSrcArgs, 2), ret2, 673 ret1)); 674} 675 676class IntClampPat<VOP3Inst inst, SDPatternOperator node> : GCNPat< 677 getClampPat<inst.Pfl, node>.ret, 678 getClampRes<inst.Pfl, inst>.ret 679>; 680 681def : IntClampPat<V_MAD_I32_I24, AMDGPUmad_i24>; 682def : IntClampPat<V_MAD_U32_U24, AMDGPUmad_u24>; 683 684def : IntClampPat<V_SAD_U8, int_amdgcn_sad_u8>; 685def : IntClampPat<V_SAD_HI_U8, int_amdgcn_sad_hi_u8>; 686def : IntClampPat<V_SAD_U16, int_amdgcn_sad_u16>; 687 688def : IntClampPat<V_MSAD_U8, int_amdgcn_msad_u8>; 689def : IntClampPat<V_MQSAD_PK_U16_U8, int_amdgcn_mqsad_pk_u16_u8>; 690 691def : IntClampPat<V_QSAD_PK_U16_U8, int_amdgcn_qsad_pk_u16_u8>; 692def : IntClampPat<V_MQSAD_U32_U8, int_amdgcn_mqsad_u32_u8>; 693 694 695//===----------------------------------------------------------------------===// 696// Target-specific instruction encodings. 697//===----------------------------------------------------------------------===// 698 699//===----------------------------------------------------------------------===// 700// GFX10. 701//===----------------------------------------------------------------------===// 702 703let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in { 704 multiclass VOP3_Real_gfx10<bits<10> op> { 705 def _gfx10 : 706 VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX10>, 707 VOP3e_gfx10<op, !cast<VOP_Pseudo>(NAME).Pfl>; 708 } 709 multiclass VOP3_Real_gfx10_with_name<bits<10> op, string opName, 710 string asmName> { 711 def _gfx10 : 712 VOP3_Real<!cast<VOP3_Pseudo>(opName), SIEncodingFamily.GFX10>, 713 VOP3e_gfx10<op, !cast<VOP3_Pseudo>(opName).Pfl> { 714 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName); 715 let AsmString = asmName # ps.AsmOperands; 716 } 717 } 718 multiclass VOP3be_Real_gfx10<bits<10> op> { 719 def _gfx10 : 720 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>, 721 VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>; 722 } 723 multiclass VOP3Interp_Real_gfx10<bits<10> op> { 724 def _gfx10 : 725 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>, 726 VOP3Interp_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>; 727 } 728 multiclass VOP3OpSel_Real_gfx10<bits<10> op> { 729 def _gfx10 : 730 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>, 731 VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>; 732 } 733 multiclass VOP3OpSel_Real_gfx10_with_name<bits<10> op, string opName, 734 string asmName> { 735 def _gfx10 : 736 VOP3_Real<!cast<VOP3_Pseudo>(opName), SIEncodingFamily.GFX10>, 737 VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(opName).Pfl> { 738 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName); 739 let AsmString = asmName # ps.AsmOperands; 740 } 741 } 742} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" 743 744defm V_READLANE_B32 : VOP3_Real_gfx10<0x360>; 745 746let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) in { 747 defm V_WRITELANE_B32 : VOP3_Real_gfx10<0x361>; 748} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) 749 750defm V_XOR3_B32 : VOP3_Real_gfx10<0x178>; 751defm V_LSHLREV_B64 : VOP3_Real_gfx10<0x2ff>; 752defm V_LSHRREV_B64 : VOP3_Real_gfx10<0x300>; 753defm V_ASHRREV_I64 : VOP3_Real_gfx10<0x301>; 754defm V_PERM_B32 : VOP3_Real_gfx10<0x344>; 755defm V_XAD_U32 : VOP3_Real_gfx10<0x345>; 756defm V_LSHL_ADD_U32 : VOP3_Real_gfx10<0x346>; 757defm V_ADD_LSHL_U32 : VOP3_Real_gfx10<0x347>; 758defm V_ADD3_U32 : VOP3_Real_gfx10<0x36d>; 759defm V_LSHL_OR_B32 : VOP3_Real_gfx10<0x36f>; 760defm V_AND_OR_B32 : VOP3_Real_gfx10<0x371>; 761defm V_OR3_B32 : VOP3_Real_gfx10<0x372>; 762 763// TODO-GFX10: add MC tests for v_add/sub_nc_i16 764defm V_ADD_NC_I16 : 765 VOP3OpSel_Real_gfx10_with_name<0x30d, "V_ADD_I16", "v_add_nc_i16">; 766defm V_SUB_NC_I16 : 767 VOP3OpSel_Real_gfx10_with_name<0x30e, "V_SUB_I16", "v_sub_nc_i16">; 768defm V_SUB_NC_I32 : 769 VOP3_Real_gfx10_with_name<0x376, "V_SUB_I32_gfx9", "v_sub_nc_i32">; 770defm V_ADD_NC_I32 : 771 VOP3_Real_gfx10_with_name<0x37f, "V_ADD_I32_gfx9", "v_add_nc_i32">; 772 773defm V_INTERP_P1LL_F16 : VOP3Interp_Real_gfx10<0x342>; 774defm V_INTERP_P1LV_F16 : VOP3Interp_Real_gfx10<0x343>; 775defm V_INTERP_P2_F16 : VOP3Interp_Real_gfx10<0x35a>; 776 777defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx10<0x311>; 778defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx10<0x312>; 779defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx10<0x313>; 780 781defm V_MIN3_F16 : VOP3OpSel_Real_gfx10<0x351>; 782defm V_MIN3_I16 : VOP3OpSel_Real_gfx10<0x352>; 783defm V_MIN3_U16 : VOP3OpSel_Real_gfx10<0x353>; 784defm V_MAX3_F16 : VOP3OpSel_Real_gfx10<0x354>; 785defm V_MAX3_I16 : VOP3OpSel_Real_gfx10<0x355>; 786defm V_MAX3_U16 : VOP3OpSel_Real_gfx10<0x356>; 787defm V_MED3_F16 : VOP3OpSel_Real_gfx10<0x357>; 788defm V_MED3_I16 : VOP3OpSel_Real_gfx10<0x358>; 789defm V_MED3_U16 : VOP3OpSel_Real_gfx10<0x359>; 790defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx10<0x373>; 791defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx10<0x375>; 792 793defm V_MAD_U16 : 794 VOP3OpSel_Real_gfx10_with_name<0x340, "V_MAD_U16_gfx9", "v_mad_u16">; 795defm V_FMA_F16 : 796 VOP3OpSel_Real_gfx10_with_name<0x34b, "V_FMA_F16_gfx9", "v_fma_f16">; 797defm V_MAD_I16 : 798 VOP3OpSel_Real_gfx10_with_name<0x35e, "V_MAD_I16_gfx9", "v_mad_i16">; 799defm V_DIV_FIXUP_F16 : 800 VOP3OpSel_Real_gfx10_with_name<0x35f, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">; 801 802// FIXME-GFX10-OPSEL: Need to add "selective" opsel support to some of these 803// (they do not support SDWA or DPP). 804defm V_ADD_NC_U16 : VOP3_Real_gfx10_with_name<0x303, "V_ADD_U16_e64", "v_add_nc_u16">; 805defm V_SUB_NC_U16 : VOP3_Real_gfx10_with_name<0x304, "V_SUB_U16_e64", "v_sub_nc_u16">; 806defm V_MUL_LO_U16 : VOP3_Real_gfx10_with_name<0x305, "V_MUL_LO_U16_e64", "v_mul_lo_u16">; 807defm V_LSHRREV_B16 : VOP3_Real_gfx10_with_name<0x307, "V_LSHRREV_B16_e64", "v_lshrrev_b16">; 808defm V_ASHRREV_I16 : VOP3_Real_gfx10_with_name<0x308, "V_ASHRREV_I16_e64", "v_ashrrev_i16">; 809defm V_MAX_U16 : VOP3_Real_gfx10_with_name<0x309, "V_MAX_U16_e64", "v_max_u16">; 810defm V_MAX_I16 : VOP3_Real_gfx10_with_name<0x30a, "V_MAX_I16_e64", "v_max_i16">; 811defm V_MIN_U16 : VOP3_Real_gfx10_with_name<0x30b, "V_MIN_U16_e64", "v_min_u16">; 812defm V_MIN_I16 : VOP3_Real_gfx10_with_name<0x30c, "V_MIN_I16_e64", "v_min_i16">; 813defm V_LSHLREV_B16 : VOP3_Real_gfx10_with_name<0x314, "V_LSHLREV_B16_e64", "v_lshlrev_b16">; 814defm V_PERMLANE16_B32 : VOP3OpSel_Real_gfx10<0x377>; 815defm V_PERMLANEX16_B32 : VOP3OpSel_Real_gfx10<0x378>; 816 817//===----------------------------------------------------------------------===// 818// GFX7, GFX10. 819//===----------------------------------------------------------------------===// 820 821let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in { 822 multiclass VOP3_Real_gfx7<bits<10> op> { 823 def _gfx7 : 824 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>, 825 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME).Pfl>; 826 } 827 multiclass VOP3be_Real_gfx7<bits<10> op> { 828 def _gfx7 : 829 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>, 830 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME).Pfl>; 831 } 832} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" 833 834multiclass VOP3_Real_gfx7_gfx10<bits<10> op> : 835 VOP3_Real_gfx7<op>, VOP3_Real_gfx10<op>; 836 837multiclass VOP3be_Real_gfx7_gfx10<bits<10> op> : 838 VOP3be_Real_gfx7<op>, VOP3be_Real_gfx10<op>; 839 840defm V_QSAD_PK_U16_U8 : VOP3_Real_gfx7_gfx10<0x172>; 841defm V_MQSAD_U32_U8 : VOP3_Real_gfx7_gfx10<0x175>; 842defm V_MAD_U64_U32 : VOP3be_Real_gfx7_gfx10<0x176>; 843defm V_MAD_I64_I32 : VOP3be_Real_gfx7_gfx10<0x177>; 844 845//===----------------------------------------------------------------------===// 846// GFX6, GFX7, GFX10. 847//===----------------------------------------------------------------------===// 848 849let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in { 850 multiclass VOP3_Real_gfx6_gfx7<bits<10> op> { 851 def _gfx6_gfx7 : 852 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>, 853 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME).Pfl>; 854 } 855 multiclass VOP3be_Real_gfx6_gfx7<bits<10> op> { 856 def _gfx6_gfx7 : 857 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>, 858 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME).Pfl>; 859 } 860} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" 861 862multiclass VOP3_Real_gfx6_gfx7_gfx10<bits<10> op> : 863 VOP3_Real_gfx6_gfx7<op>, VOP3_Real_gfx10<op>; 864 865multiclass VOP3be_Real_gfx6_gfx7_gfx10<bits<10> op> : 866 VOP3be_Real_gfx6_gfx7<op>, VOP3be_Real_gfx10<op>; 867 868defm V_LSHL_B64 : VOP3_Real_gfx6_gfx7<0x161>; 869defm V_LSHR_B64 : VOP3_Real_gfx6_gfx7<0x162>; 870defm V_ASHR_I64 : VOP3_Real_gfx6_gfx7<0x163>; 871 872defm V_MAD_LEGACY_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x140>; 873defm V_MAD_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x141>; 874defm V_MAD_I32_I24 : VOP3_Real_gfx6_gfx7_gfx10<0x142>; 875defm V_MAD_U32_U24 : VOP3_Real_gfx6_gfx7_gfx10<0x143>; 876defm V_CUBEID_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x144>; 877defm V_CUBESC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x145>; 878defm V_CUBETC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x146>; 879defm V_CUBEMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x147>; 880defm V_BFE_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x148>; 881defm V_BFE_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x149>; 882defm V_BFI_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14a>; 883defm V_FMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x14b>; 884defm V_FMA_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x14c>; 885defm V_LERP_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x14d>; 886defm V_ALIGNBIT_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14e>; 887defm V_ALIGNBYTE_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14f>; 888defm V_MULLIT_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x150>; 889defm V_MIN3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x151>; 890defm V_MIN3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x152>; 891defm V_MIN3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x153>; 892defm V_MAX3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x154>; 893defm V_MAX3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x155>; 894defm V_MAX3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x156>; 895defm V_MED3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x157>; 896defm V_MED3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x158>; 897defm V_MED3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x159>; 898defm V_SAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15a>; 899defm V_SAD_HI_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15b>; 900defm V_SAD_U16 : VOP3_Real_gfx6_gfx7_gfx10<0x15c>; 901defm V_SAD_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x15d>; 902defm V_CVT_PK_U8_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15e>; 903defm V_DIV_FIXUP_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15f>; 904defm V_DIV_FIXUP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x160>; 905defm V_ADD_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x164>; 906defm V_MUL_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x165>; 907defm V_MIN_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x166>; 908defm V_MAX_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x167>; 909defm V_LDEXP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x168>; 910defm V_MUL_LO_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x169>; 911defm V_MUL_HI_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x16a>; 912defm V_MUL_LO_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16b>; 913defm V_MUL_HI_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16c>; 914defm V_DIV_FMAS_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x16f>; 915defm V_DIV_FMAS_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x170>; 916defm V_MSAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x171>; 917defm V_MQSAD_PK_U16_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x173>; 918defm V_TRIG_PREOP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x174>; 919defm V_DIV_SCALE_F32 : VOP3be_Real_gfx6_gfx7_gfx10<0x16d>; 920defm V_DIV_SCALE_F64 : VOP3be_Real_gfx6_gfx7_gfx10<0x16e>; 921 922//===----------------------------------------------------------------------===// 923// GFX8, GFX9 (VI). 924//===----------------------------------------------------------------------===// 925 926let AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" in { 927 928multiclass VOP3_Real_vi<bits<10> op> { 929 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 930 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 931} 932 933multiclass VOP3be_Real_vi<bits<10> op> { 934 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 935 VOP3be_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 936} 937 938multiclass VOP3OpSel_Real_gfx9<bits<10> op> { 939 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 940 VOP3OpSel_gfx9 <op, !cast<VOP_Pseudo>(NAME).Pfl>; 941} 942 943multiclass VOP3Interp_Real_vi<bits<10> op> { 944 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 945 VOP3Interp_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 946} 947 948} // End AssemblerPredicates = [isGFX8GFX9], DecoderNamespace = "GFX8" 949 950let AssemblerPredicates = [isGFX8Only], DecoderNamespace = "GFX8" in { 951 952multiclass VOP3_F16_Real_vi<bits<10> op> { 953 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, 954 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>; 955} 956 957multiclass VOP3Interp_F16_Real_vi<bits<10> op> { 958 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, 959 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>; 960} 961 962} // End AssemblerPredicates = [isGFX8Only], DecoderNamespace = "GFX8" 963 964let AssemblerPredicates = [isGFX9Only], DecoderNamespace = "GFX9" in { 965 966multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { 967 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>, 968 VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> { 969 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName); 970 let AsmString = AsmName # ps.AsmOperands; 971 } 972} 973 974multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> { 975 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>, 976 VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl> { 977 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME); 978 let AsmString = AsmName # ps.AsmOperands; 979 } 980} 981 982multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { 983 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>, 984 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> { 985 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName); 986 let AsmString = AsmName # ps.AsmOperands; 987 } 988} 989 990multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> { 991 def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX9>, 992 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl> { 993 VOP_Pseudo ps = !cast<VOP_Pseudo>(NAME); 994 let AsmString = AsmName # ps.AsmOperands; 995 } 996} 997 998} // End AssemblerPredicates = [isGFX9Only], DecoderNamespace = "GFX9" 999 1000defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>; 1001defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>; 1002 1003defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>; 1004defm V_MAD_F32 : VOP3_Real_vi <0x1c1>; 1005defm V_MAD_I32_I24 : VOP3_Real_vi <0x1c2>; 1006defm V_MAD_U32_U24 : VOP3_Real_vi <0x1c3>; 1007defm V_CUBEID_F32 : VOP3_Real_vi <0x1c4>; 1008defm V_CUBESC_F32 : VOP3_Real_vi <0x1c5>; 1009defm V_CUBETC_F32 : VOP3_Real_vi <0x1c6>; 1010defm V_CUBEMA_F32 : VOP3_Real_vi <0x1c7>; 1011defm V_BFE_U32 : VOP3_Real_vi <0x1c8>; 1012defm V_BFE_I32 : VOP3_Real_vi <0x1c9>; 1013defm V_BFI_B32 : VOP3_Real_vi <0x1ca>; 1014defm V_FMA_F32 : VOP3_Real_vi <0x1cb>; 1015defm V_FMA_F64 : VOP3_Real_vi <0x1cc>; 1016defm V_LERP_U8 : VOP3_Real_vi <0x1cd>; 1017defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>; 1018defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>; 1019defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>; 1020defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>; 1021defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>; 1022defm V_MAX3_F32 : VOP3_Real_vi <0x1d3>; 1023defm V_MAX3_I32 : VOP3_Real_vi <0x1d4>; 1024defm V_MAX3_U32 : VOP3_Real_vi <0x1d5>; 1025defm V_MED3_F32 : VOP3_Real_vi <0x1d6>; 1026defm V_MED3_I32 : VOP3_Real_vi <0x1d7>; 1027defm V_MED3_U32 : VOP3_Real_vi <0x1d8>; 1028defm V_SAD_U8 : VOP3_Real_vi <0x1d9>; 1029defm V_SAD_HI_U8 : VOP3_Real_vi <0x1da>; 1030defm V_SAD_U16 : VOP3_Real_vi <0x1db>; 1031defm V_SAD_U32 : VOP3_Real_vi <0x1dc>; 1032defm V_CVT_PK_U8_F32 : VOP3_Real_vi <0x1dd>; 1033defm V_DIV_FIXUP_F32 : VOP3_Real_vi <0x1de>; 1034defm V_DIV_FIXUP_F64 : VOP3_Real_vi <0x1df>; 1035defm V_DIV_SCALE_F32 : VOP3be_Real_vi <0x1e0>; 1036defm V_DIV_SCALE_F64 : VOP3be_Real_vi <0x1e1>; 1037defm V_DIV_FMAS_F32 : VOP3_Real_vi <0x1e2>; 1038defm V_DIV_FMAS_F64 : VOP3_Real_vi <0x1e3>; 1039defm V_MSAD_U8 : VOP3_Real_vi <0x1e4>; 1040defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>; 1041defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>; 1042defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>; 1043 1044defm V_PERM_B32 : VOP3_Real_vi <0x1ed>; 1045 1046defm V_MAD_F16 : VOP3_F16_Real_vi <0x1ea>; 1047defm V_MAD_U16 : VOP3_F16_Real_vi <0x1eb>; 1048defm V_MAD_I16 : VOP3_F16_Real_vi <0x1ec>; 1049defm V_FMA_F16 : VOP3_F16_Real_vi <0x1ee>; 1050defm V_DIV_FIXUP_F16 : VOP3_F16_Real_vi <0x1ef>; 1051defm V_INTERP_P2_F16 : VOP3Interp_F16_Real_vi <0x276>; 1052 1053let FPDPRounding = 1 in { 1054defm V_MAD_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16", "v_mad_legacy_f16">; 1055defm V_FMA_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16", "v_fma_legacy_f16">; 1056defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">; 1057defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16", "v_interp_p2_legacy_f16">; 1058} // End FPDPRounding = 1 1059 1060defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">; 1061defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">; 1062 1063defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">; 1064defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">; 1065defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">; 1066defm V_FMA_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">; 1067defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">; 1068defm V_INTERP_P2_F16_gfx9 : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2_f16">; 1069 1070defm V_ADD_I32_gfx9 : VOP3_Real_gfx9 <0x29c, "v_add_i32">; 1071defm V_SUB_I32_gfx9 : VOP3_Real_gfx9 <0x29d, "v_sub_i32">; 1072 1073defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>; 1074defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>; 1075defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>; 1076 1077defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>; 1078defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>; 1079defm V_ADD_F64 : VOP3_Real_vi <0x280>; 1080defm V_MUL_F64 : VOP3_Real_vi <0x281>; 1081defm V_MIN_F64 : VOP3_Real_vi <0x282>; 1082defm V_MAX_F64 : VOP3_Real_vi <0x283>; 1083defm V_LDEXP_F64 : VOP3_Real_vi <0x284>; 1084defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>; 1085 1086// removed from VI as identical to V_MUL_LO_U32 1087let isAsmParserOnly = 1 in { 1088defm V_MUL_LO_I32 : VOP3_Real_vi <0x285>; 1089} 1090 1091defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>; 1092defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>; 1093 1094defm V_READLANE_B32 : VOP3_Real_vi <0x289>; 1095defm V_WRITELANE_B32 : VOP3_Real_vi <0x28a>; 1096 1097defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>; 1098defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>; 1099defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>; 1100defm V_TRIG_PREOP_F64 : VOP3_Real_vi <0x292>; 1101 1102defm V_LSHL_ADD_U32 : VOP3_Real_vi <0x1fd>; 1103defm V_ADD_LSHL_U32 : VOP3_Real_vi <0x1fe>; 1104defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>; 1105defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>; 1106defm V_AND_OR_B32 : VOP3_Real_vi <0x201>; 1107defm V_OR3_B32 : VOP3_Real_vi <0x202>; 1108defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>; 1109 1110defm V_XAD_U32 : VOP3_Real_vi <0x1f3>; 1111 1112defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>; 1113defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>; 1114defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>; 1115 1116defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>; 1117defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>; 1118defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>; 1119 1120defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>; 1121defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>; 1122defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>; 1123 1124defm V_ADD_I16 : VOP3OpSel_Real_gfx9 <0x29e>; 1125defm V_SUB_I16 : VOP3OpSel_Real_gfx9 <0x29f>; 1126 1127defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>; 1128defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>; 1129 1130defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>; 1131defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>; 1132