1//===-- VOP3Instructions.td - Vector Instruction Definitions --------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// Special case for v_div_fmas_{f32|f64}, since it seems to be the 10// only VOP instruction that implicitly reads VCC. 11let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in { 12def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> { 13 let Outs64 = (outs DstRC.RegClass:$vdst); 14 let HasExtVOP3DPP = 0; 15 let HasExtDPP = 0; 16} 17def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> { 18 let Outs64 = (outs DstRC.RegClass:$vdst); 19} 20} 21 22class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> { 23 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 24 let Asm64 = "$vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod"; 25 let IsSingle = 1; 26 let HasExtVOP3DPP = 0; 27 let HasExtDPP = 0; 28} 29 30def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32>; 31def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64>; 32 33def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> { 34 let HasClamp = 1; 35 36 let IsSingle = 1; 37 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 38 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp"; 39} 40 41class V_MUL_PROF<VOPProfile P> : VOP3_Profile<P> { 42 let HasExtVOP3DPP = 0; 43 let HasExtDPP = 0; 44} 45 46def DIV_FIXUP_F32_PROF : VOP3_Profile<VOP_F32_F32_F32_F32> { 47 let HasExtVOP3DPP = 0; 48 let HasExtDPP = 0; 49} 50 51//===----------------------------------------------------------------------===// 52// VOP3 INTERP 53//===----------------------------------------------------------------------===// 54 55class VOP3Interp<string OpName, VOPProfile P, list<dag> pattern = []> : 56 VOP3_Pseudo<OpName, P, pattern> { 57 let AsmMatchConverter = "cvtVOP3Interp"; 58 let mayRaiseFPException = 0; 59} 60 61def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> { 62 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 63 Attr:$attr, AttrChan:$attrchan, 64 clampmod0:$clamp, omod0:$omod); 65 66 let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod"; 67} 68 69def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> { 70 let Ins64 = (ins InterpSlot:$src0, 71 Attr:$attr, AttrChan:$attrchan, 72 clampmod0:$clamp, omod0:$omod); 73 74 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod"; 75 76 let HasClamp = 1; 77 let HasSrc0Mods = 0; 78} 79 80class getInterp16Asm <bit HasSrc2, bit HasOMod> { 81 string src2 = !if(HasSrc2, ", $src2_modifiers", ""); 82 string omod = !if(HasOMod, "$omod", ""); 83 string ret = 84 " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod; 85} 86 87class getInterp16Ins <bit HasSrc2, bit HasOMod, 88 Operand Src0Mod, Operand Src2Mod> { 89 dag ret = !if(HasSrc2, 90 !if(HasOMod, 91 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 92 Attr:$attr, AttrChan:$attrchan, 93 Src2Mod:$src2_modifiers, VRegSrc_32:$src2, 94 highmod:$high, clampmod0:$clamp, omod0:$omod), 95 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 96 Attr:$attr, AttrChan:$attrchan, 97 Src2Mod:$src2_modifiers, VRegSrc_32:$src2, 98 highmod:$high, clampmod0:$clamp) 99 ), 100 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 101 Attr:$attr, AttrChan:$attrchan, 102 highmod:$high, clampmod0:$clamp, omod0:$omod) 103 ); 104} 105 106class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> { 107 108 let HasOMod = !ne(DstVT.Value, f16.Value); 109 let HasHigh = 1; 110 111 let Outs64 = (outs DstRC.RegClass:$vdst); 112 let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret; 113 let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret; 114} 115 116//===----------------------------------------------------------------------===// 117// VOP3 Instructions 118//===----------------------------------------------------------------------===// 119 120let isCommutable = 1 in { 121 122let isReMaterializable = 1 in { 123let mayRaiseFPException = 0 in { 124let SubtargetPredicate = HasMadMacF32Insts in { 125defm V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 126defm V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>; 127} // End SubtargetPredicate = HasMadMacInsts 128 129let SubtargetPredicate = HasFmaLegacy32 in 130defm V_FMA_LEGACY_F32 : VOP3Inst <"v_fma_legacy_f32", 131 VOP3_Profile<VOP_F32_F32_F32_F32>, 132 int_amdgcn_fma_legacy>; 133} 134 135defm V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 136defm V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 137defm V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, any_fma>; 138defm V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>; 139 140let SchedRW = [WriteDoubleAdd] in { 141let FPDPRounding = 1 in { 142defm V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, any_fma>; 143defm V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, any_fadd>; 144defm V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul>; 145} // End FPDPRounding = 1 146defm V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum_like>; 147defm V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum_like>; 148} // End SchedRW = [WriteDoubleAdd] 149 150let SchedRW = [WriteIntMul] in { 151defm V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", V_MUL_PROF<VOP_I32_I32_I32>, DivergentBinFrag<mul>>; 152defm V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", V_MUL_PROF<VOP_I32_I32_I32>, mulhu>; 153defm V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", V_MUL_PROF<VOP_I32_I32_I32>>; 154defm V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", V_MUL_PROF<VOP_I32_I32_I32>, mulhs>; 155} // End SchedRW = [WriteIntMul] 156} // End isReMaterializable = 1 157 158let Uses = [MODE, VCC, EXEC] in { 159// v_div_fmas_f32: 160// result = src0 * src1 + src2 161// if (vcc) 162// result *= 2^32 163// 164let SchedRW = [WriteFloatFMA] in 165defm V_DIV_FMAS_F32 : VOP3Inst_Pseudo_Wrapper <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC, []>; 166// v_div_fmas_f64: 167// result = src0 * src1 + src2 168// if (vcc) 169// result *= 2^64 170// 171let SchedRW = [WriteDouble], FPDPRounding = 1 in 172defm V_DIV_FMAS_F64 : VOP3Inst_Pseudo_Wrapper <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC, []>; 173} // End Uses = [MODE, VCC, EXEC] 174 175} // End isCommutable = 1 176 177let isReMaterializable = 1 in { 178let mayRaiseFPException = 0 in { 179defm V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>; 180defm V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>; 181defm V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>; 182defm V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>; 183} // End mayRaiseFPException 184 185defm V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>; 186defm V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>; 187defm V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>; 188defm V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, fshr>; 189defm V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>; 190 191// XXX - No FPException seems suspect but manual doesn't say it does 192let mayRaiseFPException = 0 in { 193 let isCommutable = 1 in { 194 defm V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>; 195 defm V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>; 196 defm V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>; 197 defm V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>; 198 defm V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>; 199 defm V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>; 200 } // End isCommutable = 1 201 defm V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>; 202 defm V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>; 203 defm V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>; 204} // End mayRaiseFPException = 0 205 206let isCommutable = 1 in { 207 defm V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 208 defm V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 209 defm V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 210 defm V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 211} // End isCommutable = 1 212defm V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>; 213 214defm V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", DIV_FIXUP_F32_PROF, AMDGPUdiv_fixup>; 215 216let SchedRW = [WriteDoubleAdd], FPDPRounding = 1 in { 217 defm V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>; 218 defm V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp>; 219} // End SchedRW = [WriteDoubleAdd], FPDPRounding = 1 220} // End isReMaterializable = 1 221 222 223let mayRaiseFPException = 0 in { // Seems suspicious but manual doesn't say it does. 224 let SchedRW = [WriteFloatFMA, WriteSALU] in 225 defm V_DIV_SCALE_F32 : VOP3Inst_Pseudo_Wrapper <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32> ; 226 227 // Double precision division pre-scale. 228 let SchedRW = [WriteDouble, WriteSALU], FPDPRounding = 1 in 229 defm V_DIV_SCALE_F64 : VOP3Inst_Pseudo_Wrapper <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64>; 230} // End mayRaiseFPException = 0 231 232let isReMaterializable = 1 in 233defm V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 234 235let Constraints = "@earlyclobber $vdst" in { 236defm V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; 237} // End Constraints = "@earlyclobber $vdst" 238 239 240let isReMaterializable = 1 in { 241let SchedRW = [WriteDouble] in { 242defm V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, int_amdgcn_trig_preop>; 243} // End SchedRW = [WriteDouble] 244 245let SchedRW = [Write64Bit] in { 246 let SubtargetPredicate = isGFX6GFX7 in { 247 defm V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>, cshl_64>; 248 defm V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>, csrl_64>; 249 defm V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>, csra_64>; 250 } // End SubtargetPredicate = isGFX6GFX7 251 252 let SubtargetPredicate = isGFX8Plus in { 253 defm V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, clshl_rev_64>; 254 defm V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>, clshr_rev_64>; 255 defm V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, cashr_rev_64>; 256 } // End SubtargetPredicate = isGFX8Plus 257} // End SchedRW = [Write64Bit] 258} // End isReMaterializable = 1 259 260def : GCNPat< 261 (i32 (getDivergentFrag<sext>.ret i16:$src)), 262 (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))) 263>; 264 265let isReMaterializable = 1 in { 266let SubtargetPredicate = isGFX6GFX7GFX10Plus in { 267defm V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 268} // End SubtargetPredicate = isGFX6GFX7GFX10Plus 269 270let SchedRW = [Write32Bit] in { 271let SubtargetPredicate = isGFX8Plus in { 272defm V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUperm>; 273} // End SubtargetPredicate = isGFX8Plus 274} // End SchedRW = [Write32Bit] 275} // End isReMaterializable = 1 276 277def VOPProfileMQSAD : VOP3_Profile<VOP_V4I32_I64_I32_V4I32, VOP3_CLAMP> { 278 let HasModifiers = 0; 279} 280 281let SubtargetPredicate = isGFX7Plus in { 282let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in { 283defm V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; 284defm V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOPProfileMQSAD>; 285} // End Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] 286} // End SubtargetPredicate = isGFX7Plus 287 288let isCommutable = 1 in { 289let SchedRW = [WriteIntMul, WriteSALU] in { 290let SubtargetPredicate = isGFX7GFX8GFX9GFX10 in { 291defm V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>; 292defm V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>; 293} 294let SubtargetPredicate = isGFX11Only, Constraints = "@earlyclobber $vdst" in { 295defm V_MAD_U64_U32_gfx11 : VOP3Inst <"v_mad_u64_u32_gfx11", VOP3b_I64_I1_I32_I32_I64>; 296defm V_MAD_I64_I32_gfx11 : VOP3Inst <"v_mad_i64_i32_gfx11", VOP3b_I64_I1_I32_I32_I64>; 297} // End SubtargetPredicate = isGFX11Only, Constraints = "@earlyclobber $vdst" 298} // End SchedRW = [WriteIntMul, WriteSALU] 299} // End isCommutable = 1 300 301 302let FPDPRounding = 1 in { 303 let Predicates = [Has16BitInsts, isGFX8Only] in { 304 defm V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>; 305 defm V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, any_fma>; 306 } // End Predicates = [Has16BitInsts, isGFX8Only] 307 308 let renamedInGFX9 = 1, Predicates = [Has16BitInsts, isGFX9Plus] in { 309 defm V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9", 310 VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUdiv_fixup>; 311 defm V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, any_fma>; 312 } // End renamedInGFX9 = 1, Predicates = [Has16BitInsts, isGFX9Plus] 313} // End FPDPRounding = 1 314 315let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in { 316 317let renamedInGFX9 = 1 in { 318 defm V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; 319 defm V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; 320 let FPDPRounding = 1 in { 321 defm V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>; 322 let Uses = [MODE, M0, EXEC] in { 323 let OtherPredicates = [isNotGFX90APlus] in 324 // For some reason the intrinsic operands are in a different order 325 // from the instruction operands. 326 def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>, 327 [(set f16:$vdst, 328 (int_amdgcn_interp_p2_f16 (VOP3Mods f32:$src2, i32:$src2_modifiers), 329 (VOP3Mods f32:$src0, i32:$src0_modifiers), 330 (i32 timm:$attrchan), 331 (i32 timm:$attr), 332 (i1 timm:$high), 333 M0))]>; 334 } // End Uses = [M0, MODE, EXEC] 335 } // End FPDPRounding = 1 336} // End renamedInGFX9 = 1 337 338let SubtargetPredicate = isGFX9Only, FPDPRounding = 1 in { 339 defm V_MAD_F16_gfx9 : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>> ; 340} // End SubtargetPredicate = isGFX9Only, FPDPRounding = 1 341 342let SubtargetPredicate = isGFX9Plus in { 343defm V_MAD_U16_gfx9 : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; 344defm V_MAD_I16_gfx9 : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; 345let OtherPredicates = [isNotGFX90APlus] in 346def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>; 347} // End SubtargetPredicate = isGFX9Plus 348 349// This predicate should only apply to the selection pattern. The 350// instruction still exists and should decode on subtargets with 351// other bank counts. 352let OtherPredicates = [isNotGFX90APlus, has32BankLDS], Uses = [MODE, M0, EXEC], FPDPRounding = 1 in { 353def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>, 354 [(set f32:$vdst, (int_amdgcn_interp_p1_f16 (VOP3Mods f32:$src0, i32:$src0_modifiers), 355 (i32 timm:$attrchan), 356 (i32 timm:$attr), 357 (i1 timm:$high), M0))]>; 358} // End OtherPredicates = [isNotGFX90APlus, has32BankLDS], Uses = [MODE, M0, EXEC], FPDPRounding = 1 359 360let OtherPredicates = [isNotGFX90APlus], Uses = [MODE, M0, EXEC], FPDPRounding = 1 in { 361def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>; 362} // End OtherPredicates = [isNotGFX90APlus], Uses = [MODE, M0, EXEC], FPDPRounding = 1 363 364} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1 365 366def : GCNPat< 367 (i64 (getDivergentFrag<sext>.ret i16:$src)), 368 (REG_SEQUENCE VReg_64, 369 (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))), sub0, 370 (i32 (COPY_TO_REGCLASS 371 (V_ASHRREV_I32_e32 (S_MOV_B32 (i32 0x1f)), (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))) 372 ), VGPR_32)), sub1) 373>; 374 375let SubtargetPredicate = isGFX8Plus, Uses = [MODE, M0, EXEC], OtherPredicates = [isNotGFX90APlus] in { 376def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>; 377def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>; 378def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>; 379} // End SubtargetPredicate = isGFX8Plus, Uses = [MODE, M0, EXEC], OtherPredicates = [isNotGFX90APlus] 380 381let Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] in { 382 383multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2, 384 Instruction inst> { 385def : GCNPat < 386 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 387 (inst i16:$src0, i16:$src1, i16:$src2, (i1 0)) 388>; 389 390} 391 392defm: Ternary_i16_Pats<mul, add, V_MAD_U16_e64>; 393defm: Ternary_i16_Pats<mul, add, V_MAD_I16_e64>; 394 395} // End Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] 396 397let Predicates = [Has16BitInsts, isGFX10Plus] in { 398 399multiclass Ternary_i16_Pats_gfx9<SDPatternOperator op1, SDPatternOperator op2, 400 Instruction inst> { 401def : GCNPat < 402 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 403 (inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1, SRCMODS.NONE, $src2, DSTCLAMP.NONE) 404>; 405 406} 407 408defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_U16_gfx9_e64>; 409defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_I16_gfx9_e64>; 410 411} // End Predicates = [Has16BitInsts, isGFX10Plus] 412 413class ThreeOpFragSDAG<SDPatternOperator op1, SDPatternOperator op2> : PatFrag< 414 (ops node:$x, node:$y, node:$z), 415 // When the inner operation is used multiple times, selecting 3-op 416 // instructions may still be beneficial -- if the other users can be 417 // combined similarly. Let's be conservative for now. 418 (op2 (HasOneUseBinOp<op1> node:$x, node:$y), node:$z), 419 [{ 420 // Only use VALU ops when the result is divergent. 421 if (!N->isDivergent()) 422 return false; 423 424 // Check constant bus limitations. 425 // 426 // Note: Use !isDivergent as a conservative proxy for whether the value 427 // is in an SGPR (uniform values can end up in VGPRs as well). 428 unsigned ConstantBusUses = 0; 429 for (unsigned i = 0; i < 3; ++i) { 430 if (!Operands[i]->isDivergent() && 431 !isInlineImmediate(Operands[i].getNode())) { 432 ConstantBusUses++; 433 // This uses AMDGPU::V_ADD3_U32_e64, but all three operand instructions 434 // have the same constant bus limit. 435 if (ConstantBusUses > Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64)) 436 return false; 437 } 438 } 439 440 return true; 441 }]> { 442 let PredicateCodeUsesOperands = 1; 443} 444 445class ThreeOpFrag<SDPatternOperator op1, SDPatternOperator op2> : ThreeOpFragSDAG<op1, op2> { 446 // The divergence predicate is irrelevant in GlobalISel, as we have 447 // proper register bank checks. We just need to verify the constant 448 // bus restriction when all the sources are considered. 449 // 450 // FIXME: With unlucky SGPR operands, we could penalize code by 451 // blocking folding SGPR->VGPR copies later. 452 // FIXME: There's no register bank verifier 453 let GISelPredicateCode = [{ 454 const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64); 455 int ConstantBusUses = 0; 456 for (unsigned i = 0; i < 3; ++i) { 457 const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI); 458 if (RegBank->getID() == AMDGPU::SGPRRegBankID) { 459 if (++ConstantBusUses > ConstantBusLimit) 460 return false; 461 } 462 } 463 return true; 464 }]; 465} 466 467def shl_0_to_4 : PatFrag< 468 (ops node:$src0, node:$src1), (shl node:$src0, node:$src1), 469 [{ 470 if (auto *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 471 return C->getZExtValue() <= 4; 472 } 473 return false; 474 }]> { 475 let GISelPredicateCode = [{ 476 int64_t Imm = 0; 477 if (!mi_match(MI.getOperand(2).getReg(), MRI, m_ICst(Imm)) && 478 !mi_match(MI.getOperand(2).getReg(), MRI, m_Copy(m_ICst(Imm)))) 479 return false; 480 return (uint64_t)Imm <= 4; 481 }]; 482} 483 484def VOP3_CVT_PK_F8_F32_Profile : VOP3_Profile<VOP_I32_F32_F32, VOP3_OPSEL> { 485 let InsVOP3OpSel = (ins FP32InputMods:$src0_modifiers, Src0RC64:$src0, 486 FP32InputMods:$src1_modifiers, Src1RC64:$src1, 487 VGPR_32:$vdst_in, op_sel0:$op_sel); 488 let HasClamp = 0; 489 let HasExtVOP3DPP = 0; 490} 491 492def VOP3_CVT_SR_F8_F32_Profile : VOP3_Profile<VOPProfile<[i32, f32, i32, f32]>, 493 VOP3_OPSEL> { 494 let InsVOP3OpSel = (ins FP32InputMods:$src0_modifiers, Src0RC64:$src0, 495 FP32InputMods:$src1_modifiers, Src1RC64:$src1, 496 FP32InputMods:$src2_modifiers, VGPR_32:$src2, 497 op_sel0:$op_sel); 498 let HasClamp = 0; 499 let HasSrc2 = 0; 500 let HasSrc2Mods = 1; 501 let AsmVOP3OpSel = !subst(", $src2_modifiers", "", 502 getAsmVOP3OpSel<3, HasClamp, 503 HasSrc0FloatMods, HasSrc1FloatMods, 504 HasSrc2FloatMods>.ret); 505 let HasExtVOP3DPP = 0; 506} 507 508let SubtargetPredicate = isGFX9Plus in { 509let isCommutable = 1, isReMaterializable = 1 in { 510 defm V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 511 defm V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 512 defm V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 513 defm V_XAD_U32 : VOP3Inst <"v_xad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 514 defm V_ADD_I32 : VOP3Inst <"v_add_i32", VOP3_Profile<VOP_I32_I32_I32_ARITH>>; 515 defm V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 516} // End isCommutable = 1, isReMaterializable = 1 517// TODO src0 contains the opsel bit for dst, so if we commute, need to mask and swap this 518// to the new src0. 519defm V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmed3>; 520defm V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmed3>; 521defm V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumed3>; 522 523defm V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmin3>; 524defm V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmin3>; 525defm V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumin3>; 526 527defm V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmax3>; 528defm V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmax3>; 529defm V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumax3>; 530 531defm V_ADD_I16 : VOP3Inst <"v_add_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; 532defm V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; 533 534defm V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; 535defm V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; 536 537defm V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 538defm V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 539 540defm V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 541 542let isReMaterializable = 1 in { 543defm V_SUB_I32 : VOP3Inst <"v_sub_i32", VOP3_Profile<VOP_I32_I32_I32_ARITH>>; 544defm V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 545defm V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 546} // End isReMaterializable = 1 547 548// V_LSHL_ADD_U64: D0.u64 = (S0.u64 << S1.u[2:0]) + S2.u64 549// src0 is shifted left by 0-4 (use “0” to get ADD_U64). 550let SubtargetPredicate = isGFX940Plus in 551defm V_LSHL_ADD_U64 : VOP3Inst <"v_lshl_add_u64", VOP3_Profile<VOP_I64_I64_I32_I64>>; 552 553let SubtargetPredicate = HasFP8Insts, mayRaiseFPException = 0, 554 SchedRW = [WriteFloatCvt] in { 555 let Constraints = "$vdst = $vdst_in", DisableEncoding = "$vdst_in" in { 556 defm V_CVT_PK_FP8_F32 : VOP3Inst<"v_cvt_pk_fp8_f32", VOP3_CVT_PK_F8_F32_Profile>; 557 defm V_CVT_PK_BF8_F32 : VOP3Inst<"v_cvt_pk_bf8_f32", VOP3_CVT_PK_F8_F32_Profile>; 558 } 559 560 // These instructions have non-standard use of op_sel. In particular they are 561 // using op_sel bits 2 and 3 while only having two sources. Therefore dummy 562 // src2 is used to hold the op_sel value. 563 let Constraints = "$vdst = $src2", DisableEncoding = "$src2" in { 564 defm V_CVT_SR_FP8_F32 : VOP3Inst<"v_cvt_sr_fp8_f32", VOP3_CVT_SR_F8_F32_Profile>; 565 defm V_CVT_SR_BF8_F32 : VOP3Inst<"v_cvt_sr_bf8_f32", VOP3_CVT_SR_F8_F32_Profile>; 566 } 567} 568 569class Cvt_PK_F8_F32_Pat<SDPatternOperator node, int index, VOP3_Pseudo inst> : GCNPat< 570 (i32 (node f32:$src0, f32:$src1, i32:$old, index)), 571 (inst !if(index, SRCMODS.DST_OP_SEL, 0), $src0, 0, $src1, $old, !if(index, SRCMODS.OP_SEL_0, 0)) 572>; 573 574class Cvt_SR_F8_F32_Pat<SDPatternOperator node, bits<2> index, VOP3_Pseudo inst> : GCNPat< 575 (i32 (node f32:$src0, i32:$src1, i32:$old, index)), 576 (inst !if(index{1}, SRCMODS.DST_OP_SEL, 0), $src0, 0, $src1, 577 !if(index{0}, SRCMODS.OP_SEL_0, 0), $old, !if(index{1}, SRCMODS.OP_SEL_0, 0)) 578>; 579 580foreach Index = [0, -1] in { 581 def : Cvt_PK_F8_F32_Pat<int_amdgcn_cvt_pk_fp8_f32, Index, V_CVT_PK_FP8_F32_e64>; 582 def : Cvt_PK_F8_F32_Pat<int_amdgcn_cvt_pk_bf8_f32, Index, V_CVT_PK_BF8_F32_e64>; 583} 584 585foreach Index = [0, 1, 2, 3] in { 586 def : Cvt_SR_F8_F32_Pat<int_amdgcn_cvt_sr_fp8_f32, Index, V_CVT_SR_FP8_F32_e64>; 587 def : Cvt_SR_F8_F32_Pat<int_amdgcn_cvt_sr_bf8_f32, Index, V_CVT_SR_BF8_F32_e64>; 588} 589 590class ThreeOp_i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst> : GCNPat < 591 // This matches (op2 (op1 i32:$src0, i32:$src1), i32:$src2) with conditions. 592 (ThreeOpFrag<op1, op2> i32:$src0, i32:$src1, i32:$src2), 593 (inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2) 594>; 595 596def : ThreeOp_i32_Pats<cshl_32, add, V_LSHL_ADD_U32_e64>; 597def : ThreeOp_i32_Pats<add, cshl_32, V_ADD_LSHL_U32_e64>; 598def : ThreeOp_i32_Pats<add, add, V_ADD3_U32_e64>; 599def : ThreeOp_i32_Pats<cshl_32, or, V_LSHL_OR_B32_e64>; 600def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32_e64>; 601def : ThreeOp_i32_Pats<or, or, V_OR3_B32_e64>; 602def : ThreeOp_i32_Pats<xor, add, V_XAD_U32_e64>; 603 604let SubtargetPredicate = isGFX940Plus in 605def : GCNPat< 606 (ThreeOpFrag<shl_0_to_4, add> i64:$src0, i32:$src1, i64:$src2), 607 (V_LSHL_ADD_U64_e64 VSrc_b64:$src0, VSrc_b32:$src1, VSrc_b64:$src2) 608>; 609 610def : VOPBinOpClampPat<saddsat, V_ADD_I32_e64, i32>; 611def : VOPBinOpClampPat<ssubsat, V_SUB_I32_e64, i32>; 612 613def : GCNPat<(getDivergentFrag<or>.ret (or_oneuse i64:$src0, i64:$src1), i64:$src2), 614 (REG_SEQUENCE VReg_64, 615 (V_OR3_B32_e64 (i32 (EXTRACT_SUBREG $src0, sub0)), 616 (i32 (EXTRACT_SUBREG $src1, sub0)), 617 (i32 (EXTRACT_SUBREG $src2, sub0))), sub0, 618 (V_OR3_B32_e64 (i32 (EXTRACT_SUBREG $src0, sub1)), 619 (i32 (EXTRACT_SUBREG $src1, sub1)), 620 (i32 (EXTRACT_SUBREG $src2, sub1))), sub1)>; 621 622// FIXME: Probably should hardcode clamp bit in pseudo and avoid this. 623class OpSelBinOpClampPat<SDPatternOperator node, 624 Instruction inst> : GCNPat< 625 (node (i16 (VOP3OpSel i16:$src0, i32:$src0_modifiers)), 626 (i16 (VOP3OpSel i16:$src1, i32:$src1_modifiers))), 627 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE, 0) 628>; 629 630def : OpSelBinOpClampPat<saddsat, V_ADD_I16_e64>; 631def : OpSelBinOpClampPat<ssubsat, V_SUB_I16_e64>; 632} // End SubtargetPredicate = isGFX9Plus 633 634// FIXME: GlobalISel in general does not handle instructions with 2 results, 635// so it cannot use these patterns. 636multiclass IMAD32_Pats <VOP3_Pseudo inst> { 637 def : GCNPat < 638 (ThreeOpFrag<mul, add> i32:$src0, i32:$src1, i32:$src2), 639 (EXTRACT_SUBREG (inst $src0, $src1, 640 (REG_SEQUENCE SReg_64, // Use scalar and let it be legalized 641 $src2, sub0, 642 (i32 (IMPLICIT_DEF)), sub1), 643 0 /* clamp */), 644 sub0) 645 >; 646 // Immediate src2 in the pattern above will not fold because it would be partially 647 // undef. Hence define specialized pattern for this case. 648 // FIXME: GlobalISel pattern exporter fails to export a pattern like this and asserts, 649 // make it SDAG only. 650 def : GCNPat < 651 (ThreeOpFragSDAG<mul, add> i32:$src0, i32:$src1, (i32 imm:$src2)), 652 (EXTRACT_SUBREG (inst $src0, $src1, (i64 (as_i64imm $src2)), 0 /* clamp */), sub0) 653 >; 654} 655 656let SubtargetPredicate = isGFX9GFX10 in // exclude pre-GFX9 where it was slow 657defm : IMAD32_Pats<V_MAD_U64_U32_e64>; 658let SubtargetPredicate = isGFX11Only in 659defm : IMAD32_Pats<V_MAD_U64_U32_gfx11_e64>; 660 661def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3_OPSEL> { 662 let Src0RC64 = VRegSrc_32; 663 let Src1RC64 = SCSrc_b32; 664 let Src2RC64 = SCSrc_b32; 665 let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0, 666 IntOpSelMods:$src1_modifiers, SCSrc_b32:$src1, 667 IntOpSelMods:$src2_modifiers, SCSrc_b32:$src2, 668 VGPR_32:$vdst_in, op_sel0:$op_sel); 669 let HasClamp = 0; 670 let HasExtVOP3DPP = 0; 671 let HasExtDPP = 0; 672} 673 674class PermlanePat<SDPatternOperator permlane, 675 Instruction inst> : GCNPat< 676 (permlane i32:$vdst_in, i32:$src0, i32:$src1, i32:$src2, 677 timm:$fi, timm:$bc), 678 (inst (as_i1timm $fi), VGPR_32:$src0, (as_i1timm $bc), 679 SCSrc_b32:$src1, 0, SCSrc_b32:$src2, VGPR_32:$vdst_in) 680>; 681 682// Permlane intrinsic that has either fetch invalid or bound control 683// fields enabled. 684class BoundControlOrFetchInvalidPermlane<SDPatternOperator permlane> : 685 PatFrag<(ops node:$vdst_in, node:$src0, node:$src1, node:$src2, 686 node:$fi, node:$bc), 687 (permlane node:$vdst_in, node:$src0, node: 688 $src1, node:$src2, node:$fi, node:$bc)> { 689 let PredicateCode = [{ return N->getConstantOperandVal(5) != 0 || 690 N->getConstantOperandVal(6) != 0; }]; 691 let GISelPredicateCode = [{ 692 return MI.getOperand(6).getImm() != 0 || 693 MI.getOperand(7).getImm() != 0; 694 }]; 695} 696 697// Drop the input value if it won't be read. 698class PermlaneDiscardVDstIn<SDPatternOperator permlane, 699 Instruction inst> : GCNPat< 700 (permlane srcvalue, i32:$src0, i32:$src1, i32:$src2, 701 timm:$fi, timm:$bc), 702 (inst (as_i1timm $fi), VGPR_32:$src0, (as_i1timm $bc), 703 SCSrc_b32:$src1, 0, SCSrc_b32:$src2, 704 (IMPLICIT_DEF)) 705>; 706 707 708let SubtargetPredicate = isGFX10Plus in { 709 let isCommutable = 1, isReMaterializable = 1 in { 710 defm V_XOR3_B32 : VOP3Inst <"v_xor3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 711 } // End isCommutable = 1, isReMaterializable = 1 712 def : ThreeOp_i32_Pats<xor, xor, V_XOR3_B32_e64>; 713 714 let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in { 715 defm V_PERMLANE16_B32 : VOP3Inst<"v_permlane16_b32", VOP3_PERMLANE_Profile>; 716 defm V_PERMLANEX16_B32 : VOP3Inst<"v_permlanex16_b32", VOP3_PERMLANE_Profile>; 717 } // End $vdst = $vdst_in, DisableEncoding $vdst_in 718 719 def : PermlanePat<int_amdgcn_permlane16, V_PERMLANE16_B32_e64>; 720 def : PermlanePat<int_amdgcn_permlanex16, V_PERMLANEX16_B32_e64>; 721 722 def : PermlaneDiscardVDstIn< 723 BoundControlOrFetchInvalidPermlane<int_amdgcn_permlane16>, 724 V_PERMLANE16_B32_e64>; 725 def : PermlaneDiscardVDstIn< 726 BoundControlOrFetchInvalidPermlane<int_amdgcn_permlanex16>, 727 V_PERMLANEX16_B32_e64>; 728 729 defm V_ADD_NC_U16 : VOP3Inst <"v_add_nc_u16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>, add>; 730 defm V_SUB_NC_U16 : VOP3Inst <"v_sub_nc_u16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>, sub>; 731 732 def : OpSelBinOpClampPat<uaddsat, V_ADD_NC_U16_e64>; 733 def : OpSelBinOpClampPat<usubsat, V_SUB_NC_U16_e64>; 734 735 // Undo sub x, c -> add x, -c canonicalization since c is more likely 736 // an inline immediate than -c. 737 def : GCNPat< 738 (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)), 739 (V_SUB_NC_U16_e64 0, VSrc_b16:$src0, 0, NegSubInlineIntConst16:$src1, 0, 0) 740 >; 741 742} // End SubtargetPredicate = isGFX10Plus 743 744class DivFmasPat<ValueType vt, Instruction inst, Register CondReg> : GCNPat< 745 (AMDGPUdiv_fmas (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), 746 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), 747 (vt (VOP3Mods vt:$src2, i32:$src2_modifiers)), 748 (i1 CondReg)), 749 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, $src2_modifiers, $src2) 750>; 751 752let WaveSizePredicate = isWave64 in { 753def : DivFmasPat<f32, V_DIV_FMAS_F32_e64, VCC>; 754def : DivFmasPat<f64, V_DIV_FMAS_F64_e64, VCC>; 755} 756 757let WaveSizePredicate = isWave32 in { 758def : DivFmasPat<f32, V_DIV_FMAS_F32_e64, VCC_LO>; 759def : DivFmasPat<f64, V_DIV_FMAS_F64_e64, VCC_LO>; 760} 761 762class VOP3_DOT_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOP3_Profile<P, Features> { 763 let HasClamp = 0; 764 let HasOMod = 0; 765 // Override modifiers for bf16(i16) (same as float modifiers). 766 let HasSrc0Mods = 1; 767 let HasSrc1Mods = 1; 768 let HasSrc2Mods = 1; 769 let Src0ModDPP = FPVRegInputMods; 770 let Src1ModDPP = FPVRegInputMods; 771 let Src2ModVOP3DPP = FPVRegInputMods; 772 let InsVOP3OpSel = getInsVOP3OpSel<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs, 773 HasClamp, HasOMod, FPVRegInputMods, 774 FPVRegInputMods, FPVRegInputMods>.ret; 775 let AsmVOP3OpSel = getAsmVOP3OpSel<NumSrcArgs, HasClamp, 1, 1, 1>.ret; 776} 777 778let SubtargetPredicate = isGFX11Plus in { 779 defm V_MAXMIN_F32 : VOP3Inst<"v_maxmin_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 780 defm V_MINMAX_F32 : VOP3Inst<"v_minmax_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 781 defm V_MAXMIN_F16 : VOP3Inst<"v_maxmin_f16", VOP3_Profile<VOP_F16_F16_F16_F16>>; 782 defm V_MINMAX_F16 : VOP3Inst<"v_minmax_f16", VOP3_Profile<VOP_F16_F16_F16_F16>>; 783 defm V_MAXMIN_U32 : VOP3Inst<"v_maxmin_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 784 defm V_MINMAX_U32 : VOP3Inst<"v_minmax_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 785 defm V_MAXMIN_I32 : VOP3Inst<"v_maxmin_i32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 786 defm V_MINMAX_I32 : VOP3Inst<"v_minmax_i32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 787 defm V_CVT_PK_I16_F32 : VOP3Inst<"v_cvt_pk_i16_f32", VOP3_Profile<VOP_V2I16_F32_F32>>; 788 defm V_CVT_PK_U16_F32 : VOP3Inst<"v_cvt_pk_u16_f32", VOP3_Profile<VOP_V2I16_F32_F32>>; 789} // End SubtargetPredicate = isGFX11Plus 790 791let SubtargetPredicate = HasDot8Insts, IsDOT=1 in { 792 defm V_DOT2_F16_F16 : VOP3Inst<"v_dot2_f16_f16", VOP3_DOT_Profile<VOP_F16_V2F16_V2F16_F16>, int_amdgcn_fdot2_f16_f16>; 793 defm V_DOT2_BF16_BF16 : VOP3Inst<"v_dot2_bf16_bf16", VOP3_DOT_Profile<VOP_I16_V2I16_V2I16_I16>, int_amdgcn_fdot2_bf16_bf16>; 794} 795 796//===----------------------------------------------------------------------===// 797// Integer Clamp Patterns 798//===----------------------------------------------------------------------===// 799 800class getClampPat<VOPProfile P, SDPatternOperator node> { 801 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2)); 802 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1)); 803 dag ret1 = (P.DstVT (node P.Src0VT:$src0)); 804 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3, 805 !if(!eq(P.NumSrcArgs, 2), ret2, 806 ret1)); 807} 808 809class getClampRes<VOPProfile P, Instruction inst> { 810 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0)); 811 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0)); 812 dag ret1 = (inst P.Src0VT:$src0, (i1 0)); 813 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3, 814 !if(!eq(P.NumSrcArgs, 2), ret2, 815 ret1)); 816} 817 818class IntClampPat<VOP3InstBase inst, SDPatternOperator node> : GCNPat< 819 getClampPat<inst.Pfl, node>.ret, 820 getClampRes<inst.Pfl, inst>.ret 821>; 822 823def : IntClampPat<V_MAD_I32_I24_e64, AMDGPUmad_i24>; 824def : IntClampPat<V_MAD_U32_U24_e64, AMDGPUmad_u24>; 825 826def : IntClampPat<V_SAD_U8_e64, int_amdgcn_sad_u8>; 827def : IntClampPat<V_SAD_HI_U8_e64, int_amdgcn_sad_hi_u8>; 828def : IntClampPat<V_SAD_U16_e64, int_amdgcn_sad_u16>; 829 830def : IntClampPat<V_MSAD_U8_e64, int_amdgcn_msad_u8>; 831def : IntClampPat<V_MQSAD_PK_U16_U8_e64, int_amdgcn_mqsad_pk_u16_u8>; 832 833def : IntClampPat<V_QSAD_PK_U16_U8_e64, int_amdgcn_qsad_pk_u16_u8>; 834def : IntClampPat<V_MQSAD_U32_U8_e64, int_amdgcn_mqsad_u32_u8>; 835 836//===----------------------------------------------------------------------===// 837// Target-specific instruction encodings. 838//===----------------------------------------------------------------------===// 839 840//===----------------------------------------------------------------------===// 841// GFX11. 842//===----------------------------------------------------------------------===// 843 844defm V_FMA_DX9_ZERO_F32 : VOP3_Real_with_name_gfx11<0x209, "V_FMA_LEGACY_F32", "v_fma_dx9_zero_f32">; 845defm V_MAD_I32_I24 : VOP3_Realtriple_gfx11<0x20a>; 846defm V_MAD_U32_U24 : VOP3_Realtriple_gfx11<0x20b>; 847defm V_CUBEID_F32 : VOP3_Realtriple_gfx11<0x20c>; 848defm V_CUBESC_F32 : VOP3_Realtriple_gfx11<0x20d>; 849defm V_CUBETC_F32 : VOP3_Realtriple_gfx11<0x20e>; 850defm V_CUBEMA_F32 : VOP3_Realtriple_gfx11<0x20f>; 851defm V_BFE_U32 : VOP3_Realtriple_gfx11<0x210>; 852defm V_BFE_I32 : VOP3_Realtriple_gfx11<0x211>; 853defm V_BFI_B32 : VOP3_Realtriple_gfx11<0x212>; 854defm V_FMA_F32 : VOP3_Realtriple_gfx11<0x213>; 855defm V_FMA_F64 : VOP3_Real_Base_gfx11<0x214>; 856defm V_LERP_U8 : VOP3_Realtriple_gfx11<0x215>; 857defm V_ALIGNBIT_B32 : VOP3_Realtriple_gfx11<0x216>; 858defm V_ALIGNBYTE_B32 : VOP3_Realtriple_gfx11<0x217>; 859defm V_MULLIT_F32 : VOP3_Realtriple_gfx11<0x218>; 860defm V_MIN3_F32 : VOP3_Realtriple_gfx11<0x219>; 861defm V_MIN3_I32 : VOP3_Realtriple_gfx11<0x21a>; 862defm V_MIN3_U32 : VOP3_Realtriple_gfx11<0x21b>; 863defm V_MAX3_F32 : VOP3_Realtriple_gfx11<0x21c>; 864defm V_MAX3_I32 : VOP3_Realtriple_gfx11<0x21d>; 865defm V_MAX3_U32 : VOP3_Realtriple_gfx11<0x21e>; 866defm V_MED3_F32 : VOP3_Realtriple_gfx11<0x21f>; 867defm V_MED3_I32 : VOP3_Realtriple_gfx11<0x220>; 868defm V_MED3_U32 : VOP3_Realtriple_gfx11<0x221>; 869defm V_SAD_U8 : VOP3_Realtriple_gfx11<0x222>; 870defm V_SAD_HI_U8 : VOP3_Realtriple_gfx11<0x223>; 871defm V_SAD_U16 : VOP3_Realtriple_gfx11<0x224>; 872defm V_SAD_U32 : VOP3_Realtriple_gfx11<0x225>; 873defm V_CVT_PK_U8_F32 : VOP3_Realtriple_gfx11<0x226>; 874defm V_DIV_FIXUP_F32 : VOP3_Real_Base_gfx11<0x227>; 875defm V_DIV_FIXUP_F64 : VOP3_Real_Base_gfx11<0x228>; 876defm V_DIV_FMAS_F32 : VOP3_Real_Base_gfx11<0x237>; 877defm V_DIV_FMAS_F64 : VOP3_Real_Base_gfx11<0x238>; 878defm V_MSAD_U8 : VOP3_Realtriple_gfx11<0x239>; 879defm V_QSAD_PK_U16_U8 : VOP3_Real_Base_gfx11<0x23a>; 880defm V_MQSAD_PK_U16_U8 : VOP3_Real_Base_gfx11<0x23b>; 881defm V_MQSAD_U32_U8 : VOP3_Real_Base_gfx11<0x23d>; 882defm V_XOR3_B32 : VOP3_Realtriple_gfx11<0x240>; 883defm V_MAD_U16 : VOP3_Realtriple_with_name_gfx11<0x241, "V_MAD_U16_gfx9", "v_mad_u16">; 884defm V_PERM_B32 : VOP3_Realtriple_gfx11<0x244>; 885defm V_XAD_U32 : VOP3_Realtriple_gfx11<0x245>; 886defm V_LSHL_ADD_U32 : VOP3_Realtriple_gfx11<0x246>; 887defm V_ADD_LSHL_U32 : VOP3_Realtriple_gfx11<0x247>; 888defm V_FMA_F16 : VOP3_Realtriple_with_name_gfx11<0x248, "V_FMA_F16_gfx9", "v_fma_f16">; 889defm V_MIN3_F16 : VOP3_Realtriple_gfx11<0x249>; 890defm V_MIN3_I16 : VOP3_Realtriple_gfx11<0x24a>; 891defm V_MIN3_U16 : VOP3_Realtriple_gfx11<0x24b>; 892defm V_MAX3_F16 : VOP3_Realtriple_gfx11<0x24c>; 893defm V_MAX3_I16 : VOP3_Realtriple_gfx11<0x24d>; 894defm V_MAX3_U16 : VOP3_Realtriple_gfx11<0x24e>; 895defm V_MED3_F16 : VOP3_Realtriple_gfx11<0x24f>; 896defm V_MED3_I16 : VOP3_Realtriple_gfx11<0x250>; 897defm V_MED3_U16 : VOP3_Realtriple_gfx11<0x251>; 898defm V_MAD_I16 : VOP3_Realtriple_with_name_gfx11<0x253, "V_MAD_I16_gfx9", "v_mad_i16">; 899defm V_DIV_FIXUP_F16 : VOP3_Realtriple_with_name_gfx11<0x254, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">; 900defm V_ADD3_U32 : VOP3_Realtriple_gfx11<0x255>; 901defm V_LSHL_OR_B32 : VOP3_Realtriple_gfx11<0x256>; 902defm V_AND_OR_B32 : VOP3_Realtriple_gfx11<0x257>; 903defm V_OR3_B32 : VOP3_Realtriple_gfx11<0x258>; 904defm V_MAD_U32_U16 : VOP3_Realtriple_gfx11<0x259>; 905defm V_MAD_I32_I16 : VOP3_Realtriple_gfx11<0x25a>; 906defm V_PERMLANE16_B32 : VOP3_Real_Base_gfx11<0x25b>; 907defm V_PERMLANEX16_B32 : VOP3_Real_Base_gfx11<0x25c>; 908defm V_MAXMIN_F32 : VOP3_Realtriple_gfx11<0x25e>; 909defm V_MINMAX_F32 : VOP3_Realtriple_gfx11<0x25f>; 910defm V_MAXMIN_F16 : VOP3_Realtriple_gfx11<0x260>; 911defm V_MINMAX_F16 : VOP3_Realtriple_gfx11<0x261>; 912defm V_MAXMIN_U32 : VOP3_Realtriple_gfx11<0x262>; 913defm V_MINMAX_U32 : VOP3_Realtriple_gfx11<0x263>; 914defm V_MAXMIN_I32 : VOP3_Realtriple_gfx11<0x264>; 915defm V_MINMAX_I32 : VOP3_Realtriple_gfx11<0x265>; 916defm V_DOT2_F16_F16 : VOP3Dot_Realtriple_gfx11<0x266>; 917defm V_DOT2_BF16_BF16 : VOP3Dot_Realtriple_gfx11<0x267>; 918defm V_DIV_SCALE_F32 : VOP3be_Real_gfx11<0x2fc, "V_DIV_SCALE_F32", "v_div_scale_f32">; 919defm V_DIV_SCALE_F64 : VOP3be_Real_gfx11<0x2fd, "V_DIV_SCALE_F64", "v_div_scale_f64">; 920defm V_MAD_U64_U32_gfx11 : VOP3be_Real_gfx11<0x2fe, "V_MAD_U64_U32_gfx11", "v_mad_u64_u32">; 921defm V_MAD_I64_I32_gfx11 : VOP3be_Real_gfx11<0x2ff, "V_MAD_I64_I32_gfx11", "v_mad_i64_i32">; 922defm V_ADD_NC_U16 : VOP3Only_Realtriple_gfx11<0x303>; 923defm V_SUB_NC_U16 : VOP3Only_Realtriple_gfx11<0x304>; 924defm V_MUL_LO_U16 : VOP3Only_Realtriple_gfx11<0x305>; 925defm V_CVT_PK_I16_F32 : VOP3_Realtriple_gfx11<0x306>; 926defm V_CVT_PK_U16_F32 : VOP3_Realtriple_gfx11<0x307>; 927defm V_MAX_U16 : VOP3Only_Realtriple_gfx11<0x309>; 928defm V_MAX_I16 : VOP3Only_Realtriple_gfx11<0x30a>; 929defm V_MIN_U16 : VOP3Only_Realtriple_gfx11<0x30b>; 930defm V_MIN_I16 : VOP3Only_Realtriple_gfx11<0x30c>; 931defm V_ADD_NC_I16 : VOP3_Realtriple_with_name_gfx11<0x30d, "V_ADD_I16", "v_add_nc_i16">; 932defm V_SUB_NC_I16 : VOP3_Realtriple_with_name_gfx11<0x30e, "V_SUB_I16", "v_sub_nc_i16">; 933defm V_PACK_B32_F16 : VOP3_Realtriple_gfx11<0x311>; 934defm V_CVT_PK_NORM_I16_F16 : VOP3_Realtriple_with_name_gfx11<0x312, "V_CVT_PKNORM_I16_F16" , "v_cvt_pk_norm_i16_f16" >; 935defm V_CVT_PK_NORM_U16_F16 : VOP3_Realtriple_with_name_gfx11<0x313, "V_CVT_PKNORM_U16_F16" , "v_cvt_pk_norm_u16_f16" >; 936defm V_SUB_NC_I32 : VOP3_Realtriple_with_name_gfx11<0x325, "V_SUB_I32", "v_sub_nc_i32">; 937defm V_ADD_NC_I32 : VOP3_Realtriple_with_name_gfx11<0x326, "V_ADD_I32", "v_add_nc_i32">; 938defm V_ADD_F64 : VOP3_Real_Base_gfx11<0x327>; 939defm V_MUL_F64 : VOP3_Real_Base_gfx11<0x328>; 940defm V_MIN_F64 : VOP3_Real_Base_gfx11<0x329>; 941defm V_MAX_F64 : VOP3_Real_Base_gfx11<0x32a>; 942defm V_LDEXP_F64 : VOP3_Real_Base_gfx11<0x32b>; 943defm V_MUL_LO_U32 : VOP3_Real_Base_gfx11<0x32c>; 944defm V_MUL_HI_U32 : VOP3_Real_Base_gfx11<0x32d>; 945defm V_MUL_HI_I32 : VOP3_Real_Base_gfx11<0x32e>; 946defm V_TRIG_PREOP_F64 : VOP3_Real_Base_gfx11<0x32f>; 947defm V_LSHLREV_B16 : VOP3Only_Realtriple_gfx11<0x338>; 948defm V_LSHRREV_B16 : VOP3Only_Realtriple_gfx11<0x339>; 949defm V_ASHRREV_I16 : VOP3Only_Realtriple_gfx11<0x33a>; 950defm V_LSHLREV_B64 : VOP3_Real_Base_gfx11<0x33c>; 951defm V_LSHRREV_B64 : VOP3_Real_Base_gfx11<0x33d>; 952defm V_ASHRREV_I64 : VOP3_Real_Base_gfx11<0x33e>; 953defm V_READLANE_B32 : VOP3_Real_No_Suffix_gfx11<0x360>; // Pseudo in VOP2 954let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in { 955 defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_gfx11<0x361>; // Pseudo in VOP2 956} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) 957defm V_AND_B16 : VOP3Only_Realtriple_gfx11<0x362>; 958defm V_OR_B16 : VOP3Only_Realtriple_gfx11<0x363>; 959defm V_XOR_B16 : VOP3Only_Realtriple_gfx11<0x364>; 960 961//===----------------------------------------------------------------------===// 962// GFX10. 963//===----------------------------------------------------------------------===// 964 965let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in { 966 multiclass VOP3_Real_gfx10<bits<10> op> { 967 def _gfx10 : 968 VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 969 VOP3e_gfx10<op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 970 } 971 multiclass VOP3_Real_No_Suffix_gfx10<bits<10> op> { 972 def _gfx10 : 973 VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX10>, 974 VOP3e_gfx10<op, !cast<VOP_Pseudo>(NAME).Pfl>; 975 } 976 multiclass VOP3_Real_gfx10_with_name<bits<10> op, string opName, 977 string asmName> { 978 def _gfx10 : 979 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 980 VOP3e_gfx10<op, !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 981 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64"); 982 let AsmString = asmName # ps.AsmOperands; 983 let IsSingle = 1; 984 } 985 } 986 multiclass VOP3be_Real_gfx10<bits<10> op> { 987 def _gfx10 : 988 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 989 VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 990 } 991 multiclass VOP3Interp_Real_gfx10<bits<10> op> { 992 def _gfx10 : 993 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>, 994 VOP3Interp_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>; 995 } 996 multiclass VOP3OpSel_Real_gfx10<bits<10> op> { 997 def _gfx10 : 998 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 999 VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1000 } 1001 multiclass VOP3OpSel_Real_gfx10_with_name<bits<10> op, string opName, 1002 string asmName> { 1003 def _gfx10 : 1004 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 1005 VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 1006 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1007 let AsmString = asmName # ps.AsmOperands; 1008 } 1009 } 1010} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" 1011 1012defm V_READLANE_B32 : VOP3_Real_No_Suffix_gfx10<0x360>; 1013 1014let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in { 1015 defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_gfx10<0x361>; 1016} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) 1017 1018let SubtargetPredicate = isGFX10Before1030 in { 1019 defm V_MUL_LO_I32 : VOP3_Real_gfx10<0x16b>; 1020} 1021 1022defm V_XOR3_B32 : VOP3_Real_gfx10<0x178>; 1023defm V_LSHLREV_B64 : VOP3_Real_gfx10<0x2ff>; 1024defm V_LSHRREV_B64 : VOP3_Real_gfx10<0x300>; 1025defm V_ASHRREV_I64 : VOP3_Real_gfx10<0x301>; 1026defm V_PERM_B32 : VOP3_Real_gfx10<0x344>; 1027defm V_XAD_U32 : VOP3_Real_gfx10<0x345>; 1028defm V_LSHL_ADD_U32 : VOP3_Real_gfx10<0x346>; 1029defm V_ADD_LSHL_U32 : VOP3_Real_gfx10<0x347>; 1030defm V_ADD3_U32 : VOP3_Real_gfx10<0x36d>; 1031defm V_LSHL_OR_B32 : VOP3_Real_gfx10<0x36f>; 1032defm V_AND_OR_B32 : VOP3_Real_gfx10<0x371>; 1033defm V_OR3_B32 : VOP3_Real_gfx10<0x372>; 1034 1035// TODO-GFX10: add MC tests for v_add/sub_nc_i16 1036defm V_ADD_NC_I16 : 1037 VOP3OpSel_Real_gfx10_with_name<0x30d, "V_ADD_I16", "v_add_nc_i16">; 1038defm V_SUB_NC_I16 : 1039 VOP3OpSel_Real_gfx10_with_name<0x30e, "V_SUB_I16", "v_sub_nc_i16">; 1040defm V_SUB_NC_I32 : 1041 VOP3_Real_gfx10_with_name<0x376, "V_SUB_I32", "v_sub_nc_i32">; 1042defm V_ADD_NC_I32 : 1043 VOP3_Real_gfx10_with_name<0x37f, "V_ADD_I32", "v_add_nc_i32">; 1044 1045defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_gfx10<0x200>; 1046defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_gfx10<0x201>; 1047defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_gfx10<0x202>; 1048 1049defm V_INTERP_P1LL_F16 : VOP3Interp_Real_gfx10<0x342>; 1050defm V_INTERP_P1LV_F16 : VOP3Interp_Real_gfx10<0x343>; 1051defm V_INTERP_P2_F16 : VOP3Interp_Real_gfx10<0x35a>; 1052 1053defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx10<0x311>; 1054defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx10<0x312>; 1055defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx10<0x313>; 1056 1057defm V_MIN3_F16 : VOP3OpSel_Real_gfx10<0x351>; 1058defm V_MIN3_I16 : VOP3OpSel_Real_gfx10<0x352>; 1059defm V_MIN3_U16 : VOP3OpSel_Real_gfx10<0x353>; 1060defm V_MAX3_F16 : VOP3OpSel_Real_gfx10<0x354>; 1061defm V_MAX3_I16 : VOP3OpSel_Real_gfx10<0x355>; 1062defm V_MAX3_U16 : VOP3OpSel_Real_gfx10<0x356>; 1063defm V_MED3_F16 : VOP3OpSel_Real_gfx10<0x357>; 1064defm V_MED3_I16 : VOP3OpSel_Real_gfx10<0x358>; 1065defm V_MED3_U16 : VOP3OpSel_Real_gfx10<0x359>; 1066defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx10<0x373>; 1067defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx10<0x375>; 1068 1069defm V_MAD_U16 : 1070 VOP3OpSel_Real_gfx10_with_name<0x340, "V_MAD_U16_gfx9", "v_mad_u16">; 1071defm V_FMA_F16 : 1072 VOP3OpSel_Real_gfx10_with_name<0x34b, "V_FMA_F16_gfx9", "v_fma_f16">; 1073defm V_MAD_I16 : 1074 VOP3OpSel_Real_gfx10_with_name<0x35e, "V_MAD_I16_gfx9", "v_mad_i16">; 1075defm V_DIV_FIXUP_F16 : 1076 VOP3OpSel_Real_gfx10_with_name<0x35f, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">; 1077 1078defm V_ADD_NC_U16 : VOP3OpSel_Real_gfx10<0x303>; 1079defm V_SUB_NC_U16 : VOP3OpSel_Real_gfx10<0x304>; 1080 1081// FIXME-GFX10-OPSEL: Need to add "selective" opsel support to some of these 1082// (they do not support SDWA or DPP). 1083defm V_MUL_LO_U16 : VOP3_Real_gfx10_with_name<0x305, "V_MUL_LO_U16", "v_mul_lo_u16">; 1084defm V_LSHRREV_B16 : VOP3_Real_gfx10_with_name<0x307, "V_LSHRREV_B16", "v_lshrrev_b16">; 1085defm V_ASHRREV_I16 : VOP3_Real_gfx10_with_name<0x308, "V_ASHRREV_I16", "v_ashrrev_i16">; 1086defm V_MAX_U16 : VOP3_Real_gfx10_with_name<0x309, "V_MAX_U16", "v_max_u16">; 1087defm V_MAX_I16 : VOP3_Real_gfx10_with_name<0x30a, "V_MAX_I16", "v_max_i16">; 1088defm V_MIN_U16 : VOP3_Real_gfx10_with_name<0x30b, "V_MIN_U16", "v_min_u16">; 1089defm V_MIN_I16 : VOP3_Real_gfx10_with_name<0x30c, "V_MIN_I16", "v_min_i16">; 1090defm V_LSHLREV_B16 : VOP3_Real_gfx10_with_name<0x314, "V_LSHLREV_B16", "v_lshlrev_b16">; 1091defm V_PERMLANE16_B32 : VOP3OpSel_Real_gfx10<0x377>; 1092defm V_PERMLANEX16_B32 : VOP3OpSel_Real_gfx10<0x378>; 1093 1094//===----------------------------------------------------------------------===// 1095// GFX7, GFX10. 1096//===----------------------------------------------------------------------===// 1097 1098let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in { 1099 multiclass VOP3_Real_gfx7<bits<10> op> { 1100 def _gfx7 : 1101 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 1102 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1103 } 1104 multiclass VOP3be_Real_gfx7<bits<10> op> { 1105 def _gfx7 : 1106 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 1107 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1108 } 1109} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" 1110 1111multiclass VOP3_Real_gfx7_gfx10<bits<10> op> : 1112 VOP3_Real_gfx7<op>, VOP3_Real_gfx10<op>; 1113 1114multiclass VOP3be_Real_gfx7_gfx10<bits<10> op> : 1115 VOP3be_Real_gfx7<op>, VOP3be_Real_gfx10<op>; 1116 1117defm V_QSAD_PK_U16_U8 : VOP3_Real_gfx7_gfx10<0x172>; 1118defm V_MQSAD_U32_U8 : VOP3_Real_gfx7_gfx10<0x175>; 1119defm V_MAD_U64_U32 : VOP3be_Real_gfx7_gfx10<0x176>; 1120defm V_MAD_I64_I32 : VOP3be_Real_gfx7_gfx10<0x177>; 1121 1122//===----------------------------------------------------------------------===// 1123// GFX6, GFX7, GFX10. 1124//===----------------------------------------------------------------------===// 1125 1126let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in { 1127 multiclass VOP3_Real_gfx6_gfx7<bits<10> op> { 1128 def _gfx6_gfx7 : 1129 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 1130 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1131 } 1132 multiclass VOP3be_Real_gfx6_gfx7<bits<10> op> { 1133 def _gfx6_gfx7 : 1134 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 1135 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1136 } 1137} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" 1138 1139multiclass VOP3_Real_gfx6_gfx7_gfx10<bits<10> op> : 1140 VOP3_Real_gfx6_gfx7<op>, VOP3_Real_gfx10<op>; 1141 1142multiclass VOP3be_Real_gfx6_gfx7_gfx10<bits<10> op> : 1143 VOP3be_Real_gfx6_gfx7<op>, VOP3be_Real_gfx10<op>; 1144 1145defm V_LSHL_B64 : VOP3_Real_gfx6_gfx7<0x161>; 1146defm V_LSHR_B64 : VOP3_Real_gfx6_gfx7<0x162>; 1147defm V_ASHR_I64 : VOP3_Real_gfx6_gfx7<0x163>; 1148defm V_MUL_LO_I32 : VOP3_Real_gfx6_gfx7<0x16b>; 1149 1150defm V_MAD_LEGACY_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x140>; 1151defm V_MAD_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x141>; 1152defm V_MAD_I32_I24 : VOP3_Real_gfx6_gfx7_gfx10<0x142>; 1153defm V_MAD_U32_U24 : VOP3_Real_gfx6_gfx7_gfx10<0x143>; 1154defm V_CUBEID_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x144>; 1155defm V_CUBESC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x145>; 1156defm V_CUBETC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x146>; 1157defm V_CUBEMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x147>; 1158defm V_BFE_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x148>; 1159defm V_BFE_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x149>; 1160defm V_BFI_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14a>; 1161defm V_FMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x14b>; 1162defm V_FMA_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x14c>; 1163defm V_LERP_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x14d>; 1164defm V_ALIGNBIT_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14e>; 1165defm V_ALIGNBYTE_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14f>; 1166defm V_MULLIT_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x150>; 1167defm V_MIN3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x151>; 1168defm V_MIN3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x152>; 1169defm V_MIN3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x153>; 1170defm V_MAX3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x154>; 1171defm V_MAX3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x155>; 1172defm V_MAX3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x156>; 1173defm V_MED3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x157>; 1174defm V_MED3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x158>; 1175defm V_MED3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x159>; 1176defm V_SAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15a>; 1177defm V_SAD_HI_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15b>; 1178defm V_SAD_U16 : VOP3_Real_gfx6_gfx7_gfx10<0x15c>; 1179defm V_SAD_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x15d>; 1180defm V_CVT_PK_U8_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15e>; 1181defm V_DIV_FIXUP_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15f>; 1182defm V_DIV_FIXUP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x160>; 1183defm V_ADD_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x164>; 1184defm V_MUL_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x165>; 1185defm V_MIN_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x166>; 1186defm V_MAX_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x167>; 1187defm V_LDEXP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x168>; 1188defm V_MUL_LO_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x169>; 1189defm V_MUL_HI_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x16a>; 1190defm V_MUL_HI_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16c>; 1191defm V_DIV_FMAS_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x16f>; 1192defm V_DIV_FMAS_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x170>; 1193defm V_MSAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x171>; 1194defm V_MQSAD_PK_U16_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x173>; 1195defm V_TRIG_PREOP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x174>; 1196defm V_DIV_SCALE_F32 : VOP3be_Real_gfx6_gfx7_gfx10<0x16d>; 1197defm V_DIV_SCALE_F64 : VOP3be_Real_gfx6_gfx7_gfx10<0x16e>; 1198 1199// NB: Same opcode as v_mad_legacy_f32 1200let DecoderNamespace = "GFX10_B" in 1201defm V_FMA_LEGACY_F32 : VOP3_Real_gfx10<0x140>; 1202 1203//===----------------------------------------------------------------------===// 1204// GFX8, GFX9 (VI). 1205//===----------------------------------------------------------------------===// 1206 1207let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { 1208 1209multiclass VOP3_Real_vi<bits<10> op> { 1210 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1211 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 1212} 1213multiclass VOP3_Real_No_Suffix_vi<bits<10> op> { 1214 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 1215 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 1216} 1217 1218multiclass VOP3be_Real_vi<bits<10> op> { 1219 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1220 VOP3be_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 1221} 1222 1223multiclass VOP3OpSel_Real_gfx9<bits<10> op> { 1224 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1225 VOP3OpSel_gfx9 <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 1226} 1227 1228multiclass VOP3OpSel_Real_gfx9_forced_opsel2<bits<10> op> { 1229 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1230 VOP3OpSel_gfx9 <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl> { 1231 let Inst{13} = src2_modifiers{2}; // op_sel(2) 1232 } 1233} 1234 1235multiclass VOP3Interp_Real_vi<bits<10> op> { 1236 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 1237 VOP3Interp_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 1238} 1239 1240} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" 1241 1242let AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" in { 1243 1244multiclass VOP3_F16_Real_vi<bits<10> op> { 1245 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1246 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1247} 1248 1249multiclass VOP3Interp_F16_Real_vi<bits<10> op> { 1250 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, 1251 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>; 1252} 1253 1254} // End AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" 1255 1256let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in { 1257 1258multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { 1259 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>, 1260 VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 1261 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 1262 let AsmString = AsmName # ps.AsmOperands; 1263 } 1264} 1265 1266multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> { 1267 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>, 1268 VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1269 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME#"_e64"); 1270 let AsmString = AsmName # ps.AsmOperands; 1271 } 1272} 1273 1274multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { 1275 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>, 1276 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> { 1277 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName); 1278 let AsmString = AsmName # ps.AsmOperands; 1279 } 1280} 1281 1282multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> { 1283 def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>, 1284 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl> { 1285 VOP_Pseudo ps = !cast<VOP_Pseudo>(NAME#"_e64"); 1286 let AsmString = AsmName # ps.AsmOperands; 1287 } 1288} 1289 1290} // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" 1291 1292defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>; 1293defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>; 1294 1295defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>; 1296defm V_MAD_F32 : VOP3_Real_vi <0x1c1>; 1297defm V_MAD_I32_I24 : VOP3_Real_vi <0x1c2>; 1298defm V_MAD_U32_U24 : VOP3_Real_vi <0x1c3>; 1299defm V_CUBEID_F32 : VOP3_Real_vi <0x1c4>; 1300defm V_CUBESC_F32 : VOP3_Real_vi <0x1c5>; 1301defm V_CUBETC_F32 : VOP3_Real_vi <0x1c6>; 1302defm V_CUBEMA_F32 : VOP3_Real_vi <0x1c7>; 1303defm V_BFE_U32 : VOP3_Real_vi <0x1c8>; 1304defm V_BFE_I32 : VOP3_Real_vi <0x1c9>; 1305defm V_BFI_B32 : VOP3_Real_vi <0x1ca>; 1306defm V_FMA_F32 : VOP3_Real_vi <0x1cb>; 1307defm V_FMA_F64 : VOP3_Real_vi <0x1cc>; 1308defm V_LERP_U8 : VOP3_Real_vi <0x1cd>; 1309defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>; 1310defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>; 1311defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>; 1312defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>; 1313defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>; 1314defm V_MAX3_F32 : VOP3_Real_vi <0x1d3>; 1315defm V_MAX3_I32 : VOP3_Real_vi <0x1d4>; 1316defm V_MAX3_U32 : VOP3_Real_vi <0x1d5>; 1317defm V_MED3_F32 : VOP3_Real_vi <0x1d6>; 1318defm V_MED3_I32 : VOP3_Real_vi <0x1d7>; 1319defm V_MED3_U32 : VOP3_Real_vi <0x1d8>; 1320defm V_SAD_U8 : VOP3_Real_vi <0x1d9>; 1321defm V_SAD_HI_U8 : VOP3_Real_vi <0x1da>; 1322defm V_SAD_U16 : VOP3_Real_vi <0x1db>; 1323defm V_SAD_U32 : VOP3_Real_vi <0x1dc>; 1324defm V_CVT_PK_U8_F32 : VOP3_Real_vi <0x1dd>; 1325defm V_DIV_FIXUP_F32 : VOP3_Real_vi <0x1de>; 1326defm V_DIV_FIXUP_F64 : VOP3_Real_vi <0x1df>; 1327defm V_DIV_SCALE_F32 : VOP3be_Real_vi <0x1e0>; 1328defm V_DIV_SCALE_F64 : VOP3be_Real_vi <0x1e1>; 1329defm V_DIV_FMAS_F32 : VOP3_Real_vi <0x1e2>; 1330defm V_DIV_FMAS_F64 : VOP3_Real_vi <0x1e3>; 1331defm V_MSAD_U8 : VOP3_Real_vi <0x1e4>; 1332defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>; 1333defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>; 1334defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>; 1335 1336defm V_PERM_B32 : VOP3_Real_vi <0x1ed>; 1337 1338defm V_MAD_F16 : VOP3_F16_Real_vi <0x1ea>; 1339defm V_MAD_U16 : VOP3_F16_Real_vi <0x1eb>; 1340defm V_MAD_I16 : VOP3_F16_Real_vi <0x1ec>; 1341defm V_FMA_F16 : VOP3_F16_Real_vi <0x1ee>; 1342defm V_DIV_FIXUP_F16 : VOP3_F16_Real_vi <0x1ef>; 1343defm V_INTERP_P2_F16 : VOP3Interp_F16_Real_vi <0x276>; 1344 1345let FPDPRounding = 1 in { 1346defm V_MAD_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16", "v_mad_legacy_f16">; 1347defm V_FMA_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16", "v_fma_legacy_f16">; 1348defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">; 1349defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16", "v_interp_p2_legacy_f16">; 1350} // End FPDPRounding = 1 1351 1352defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">; 1353defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">; 1354 1355defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">; 1356defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">; 1357defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">; 1358defm V_FMA_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">; 1359defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">; 1360defm V_INTERP_P2_F16_gfx9 : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2_f16">; 1361 1362defm V_ADD_I32 : VOP3_Real_vi <0x29c>; 1363defm V_SUB_I32 : VOP3_Real_vi <0x29d>; 1364 1365defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>; 1366defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>; 1367defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>; 1368 1369defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>; 1370defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>; 1371defm V_ADD_F64 : VOP3_Real_vi <0x280>; 1372defm V_MUL_F64 : VOP3_Real_vi <0x281>; 1373defm V_MIN_F64 : VOP3_Real_vi <0x282>; 1374defm V_MAX_F64 : VOP3_Real_vi <0x283>; 1375defm V_LDEXP_F64 : VOP3_Real_vi <0x284>; 1376defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>; 1377 1378// removed from VI as identical to V_MUL_LO_U32 1379let isAsmParserOnly = 1 in { 1380defm V_MUL_LO_I32 : VOP3_Real_vi <0x285>; 1381} 1382 1383defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>; 1384defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>; 1385 1386defm V_READLANE_B32 : VOP3_Real_No_Suffix_vi <0x289>; 1387defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_vi <0x28a>; 1388 1389defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>; 1390defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>; 1391defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>; 1392defm V_TRIG_PREOP_F64 : VOP3_Real_vi <0x292>; 1393 1394defm V_LSHL_ADD_U32 : VOP3_Real_vi <0x1fd>; 1395defm V_ADD_LSHL_U32 : VOP3_Real_vi <0x1fe>; 1396defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>; 1397defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>; 1398defm V_AND_OR_B32 : VOP3_Real_vi <0x201>; 1399defm V_OR3_B32 : VOP3_Real_vi <0x202>; 1400defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>; 1401 1402defm V_XAD_U32 : VOP3_Real_vi <0x1f3>; 1403 1404defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>; 1405defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>; 1406defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>; 1407 1408defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>; 1409defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>; 1410defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>; 1411 1412defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>; 1413defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>; 1414defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>; 1415 1416defm V_ADD_I16 : VOP3OpSel_Real_gfx9 <0x29e>; 1417defm V_SUB_I16 : VOP3OpSel_Real_gfx9 <0x29f>; 1418 1419defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>; 1420defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>; 1421 1422defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>; 1423defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>; 1424 1425defm V_LSHL_ADD_U64 : VOP3_Real_vi <0x208>; 1426 1427let OtherPredicates = [HasFP8Insts] in { 1428defm V_CVT_PK_FP8_F32 : VOP3OpSel_Real_gfx9 <0x2a2>; 1429defm V_CVT_PK_BF8_F32 : VOP3OpSel_Real_gfx9 <0x2a3>; 1430defm V_CVT_SR_FP8_F32 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x2a4>; 1431defm V_CVT_SR_BF8_F32 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x2a5>; 1432} 1433