1//===-- VOP3Instructions.td - Vector Instruction Definitions --------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// Special case for v_div_fmas_{f32|f64}, since it seems to be the 10// only VOP instruction that implicitly reads VCC. 11let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in { 12def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> { 13 let Outs64 = (outs DstRC.RegClass:$vdst); 14 let HasExtVOP3DPP = 0; 15 let HasExtDPP = 0; 16} 17def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> { 18 let Outs64 = (outs DstRC.RegClass:$vdst); 19} 20} 21 22class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> { 23 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 24 let Asm64 = "$vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod"; 25 let IsSingle = 1; 26 let HasExtVOP3DPP = 0; 27 let HasExtDPP = 0; 28} 29 30def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32>; 31def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64>; 32 33def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> { 34 let HasClamp = 1; 35 36 let IsSingle = 1; 37 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst); 38 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp"; 39} 40 41class V_MUL_PROF<VOPProfile P> : VOP3_Profile<P> { 42 let HasExtVOP3DPP = 0; 43 let HasExtDPP = 0; 44} 45 46def DIV_FIXUP_F32_PROF : VOP3_Profile<VOP_F32_F32_F32_F32> { 47 let HasExtVOP3DPP = 0; 48 let HasExtDPP = 0; 49} 50 51//===----------------------------------------------------------------------===// 52// VOP3 INTERP 53//===----------------------------------------------------------------------===// 54 55class VOP3Interp<string OpName, VOPProfile P, list<dag> pattern = []> : 56 VOP3_Pseudo<OpName, P, pattern> { 57 let AsmMatchConverter = "cvtVOP3Interp"; 58 let mayRaiseFPException = 0; 59} 60 61def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> { 62 let Src0Mod = FPVRegInputMods; 63 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 64 Attr:$attr, AttrChan:$attrchan, 65 clampmod0:$clamp, omod0:$omod); 66 67 let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod"; 68} 69 70def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> { 71 let Ins64 = (ins InterpSlot:$src0, 72 Attr:$attr, AttrChan:$attrchan, 73 clampmod0:$clamp, omod0:$omod); 74 75 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod"; 76 77 let HasClamp = 1; 78 let HasSrc0Mods = 0; 79} 80 81class getInterp16Asm <bit HasSrc2, bit HasOMod> { 82 string src2 = !if(HasSrc2, ", $src2_modifiers", ""); 83 string omod = !if(HasOMod, "$omod", ""); 84 string ret = 85 " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod; 86} 87 88class getInterp16Ins <bit HasSrc2, bit HasOMod, 89 Operand Src0Mod, Operand Src2Mod> { 90 dag ret = !if(HasSrc2, 91 !if(HasOMod, 92 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 93 Attr:$attr, AttrChan:$attrchan, 94 Src2Mod:$src2_modifiers, VRegSrc_32:$src2, 95 highmod:$high, clampmod0:$clamp, omod0:$omod), 96 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 97 Attr:$attr, AttrChan:$attrchan, 98 Src2Mod:$src2_modifiers, VRegSrc_32:$src2, 99 highmod:$high, clampmod0:$clamp) 100 ), 101 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0, 102 Attr:$attr, AttrChan:$attrchan, 103 highmod:$high, clampmod0:$clamp, omod0:$omod) 104 ); 105} 106 107class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> { 108 109 let HasOMod = !ne(DstVT.Value, f16.Value); 110 let HasHigh = 1; 111 112 let Src0Mod = FPVRegInputMods; 113 let Src2Mod = FPVRegInputMods; 114 115 let Outs64 = (outs DstRC.RegClass:$vdst); 116 let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret; 117 let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret; 118} 119 120//===----------------------------------------------------------------------===// 121// VOP3 Instructions 122//===----------------------------------------------------------------------===// 123 124let isCommutable = 1 in { 125 126let isReMaterializable = 1 in { 127let mayRaiseFPException = 0 in { 128let SubtargetPredicate = HasMadMacF32Insts in { 129defm V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 130defm V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, any_fmad>; 131} // End SubtargetPredicate = HasMadMacInsts 132 133let SubtargetPredicate = HasFmaLegacy32 in 134defm V_FMA_LEGACY_F32 : VOP3Inst <"v_fma_legacy_f32", 135 VOP3_Profile<VOP_F32_F32_F32_F32>, 136 int_amdgcn_fma_legacy>; 137} 138 139defm V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 140defm V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 141defm V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, any_fma>; 142defm V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>; 143 144let SchedRW = [WriteDoubleAdd] in { 145let FPDPRounding = 1 in { 146defm V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, any_fma>; 147defm V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, any_fadd>; 148defm V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, any_fmul>; 149} // End FPDPRounding = 1 150defm V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum_like>; 151defm V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum_like>; 152} // End SchedRW = [WriteDoubleAdd] 153 154let SchedRW = [WriteIntMul] in { 155defm V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", V_MUL_PROF<VOP_I32_I32_I32>, DivergentBinFrag<mul>>; 156defm V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", V_MUL_PROF<VOP_I32_I32_I32>, mulhu>; 157defm V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", V_MUL_PROF<VOP_I32_I32_I32>>; 158defm V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", V_MUL_PROF<VOP_I32_I32_I32>, mulhs>; 159} // End SchedRW = [WriteIntMul] 160} // End isReMaterializable = 1 161 162let Uses = [MODE, VCC, EXEC] in { 163// v_div_fmas_f32: 164// result = src0 * src1 + src2 165// if (vcc) 166// result *= 2^32 167// 168let SchedRW = [WriteFloatFMA] in 169defm V_DIV_FMAS_F32 : VOP3Inst_Pseudo_Wrapper <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC, []>; 170// v_div_fmas_f64: 171// result = src0 * src1 + src2 172// if (vcc) 173// result *= 2^64 174// 175let SchedRW = [WriteDouble], FPDPRounding = 1 in 176defm V_DIV_FMAS_F64 : VOP3Inst_Pseudo_Wrapper <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC, []>; 177} // End Uses = [MODE, VCC, EXEC] 178 179} // End isCommutable = 1 180 181let isReMaterializable = 1 in { 182let mayRaiseFPException = 0 in { 183defm V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>; 184defm V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>; 185defm V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>; 186defm V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>; 187} // End mayRaiseFPException 188 189defm V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>; 190defm V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>; 191defm V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>; 192defm V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, fshr>; 193defm V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>; 194 195// XXX - No FPException seems suspect but manual doesn't say it does 196let mayRaiseFPException = 0 in { 197 let isCommutable = 1 in { 198 defm V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>; 199 defm V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>; 200 defm V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>; 201 defm V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>; 202 defm V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>; 203 defm V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>; 204 } // End isCommutable = 1 205 defm V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>; 206 defm V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>; 207 defm V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>; 208} // End mayRaiseFPException = 0 209 210let isCommutable = 1 in { 211 defm V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 212 defm V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 213 defm V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 214 defm V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 215} // End isCommutable = 1 216defm V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>; 217 218defm V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", DIV_FIXUP_F32_PROF, AMDGPUdiv_fixup>; 219 220let SchedRW = [WriteDoubleAdd], FPDPRounding = 1 in { 221 defm V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>; 222 defm V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp>; 223} // End SchedRW = [WriteDoubleAdd], FPDPRounding = 1 224} // End isReMaterializable = 1 225 226 227let mayRaiseFPException = 0 in { // Seems suspicious but manual doesn't say it does. 228 let SchedRW = [WriteFloatFMA, WriteSALU] in 229 defm V_DIV_SCALE_F32 : VOP3Inst_Pseudo_Wrapper <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32> ; 230 231 // Double precision division pre-scale. 232 let SchedRW = [WriteDouble, WriteSALU], FPDPRounding = 1 in 233 defm V_DIV_SCALE_F64 : VOP3Inst_Pseudo_Wrapper <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64>; 234} // End mayRaiseFPException = 0 235 236let isReMaterializable = 1 in 237defm V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; 238 239let Constraints = "@earlyclobber $vdst" in { 240defm V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; 241} // End Constraints = "@earlyclobber $vdst" 242 243 244let isReMaterializable = 1 in { 245let SchedRW = [WriteDouble] in { 246defm V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, int_amdgcn_trig_preop>; 247} // End SchedRW = [WriteDouble] 248 249let SchedRW = [Write64Bit] in { 250 let SubtargetPredicate = isGFX6GFX7 in { 251 defm V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>, cshl_64>; 252 defm V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>, csrl_64>; 253 defm V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>, csra_64>; 254 } // End SubtargetPredicate = isGFX6GFX7 255 256 let SubtargetPredicate = isGFX8Plus in { 257 defm V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, clshl_rev_64>; 258 defm V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>, clshr_rev_64>; 259 defm V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, cashr_rev_64>; 260 } // End SubtargetPredicate = isGFX8Plus 261} // End SchedRW = [Write64Bit] 262} // End isReMaterializable = 1 263 264def : GCNPat< 265 (i32 (DivergentUnaryFrag<sext> i16:$src)), 266 (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))) 267>; 268 269let isReMaterializable = 1 in { 270let SubtargetPredicate = isGFX6GFX7GFX10Plus in { 271defm V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 272} // End SubtargetPredicate = isGFX6GFX7GFX10Plus 273 274let SchedRW = [Write32Bit] in { 275let SubtargetPredicate = isGFX8Plus in { 276defm V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUperm>; 277} // End SubtargetPredicate = isGFX8Plus 278} // End SchedRW = [Write32Bit] 279} // End isReMaterializable = 1 280 281def VOPProfileMQSAD : VOP3_Profile<VOP_V4I32_I64_I32_V4I32, VOP3_CLAMP> { 282 let HasModifiers = 0; 283} 284 285let SubtargetPredicate = isGFX7Plus in { 286let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in { 287defm V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; 288defm V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOPProfileMQSAD>; 289} // End Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] 290} // End SubtargetPredicate = isGFX7Plus 291 292let isCommutable = 1, SchedRW = [WriteIntMul, WriteSALU] in { 293 let SubtargetPredicate = isGFX7Plus, OtherPredicates = [HasNotMADIntraFwdBug] in { 294 defm V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>; 295 defm V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>; 296 } 297 let SubtargetPredicate = isGFX11Only, OtherPredicates = [HasMADIntraFwdBug], 298 Constraints = "@earlyclobber $vdst" in { 299 defm V_MAD_U64_U32_gfx11 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>; 300 defm V_MAD_I64_I32_gfx11 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>; 301 } 302} // End isCommutable = 1, SchedRW = [WriteIntMul, WriteSALU] 303 304 305let FPDPRounding = 1 in { 306 let Predicates = [Has16BitInsts, isGFX8Only] in { 307 defm V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>; 308 defm V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, any_fma>; 309 } // End Predicates = [Has16BitInsts, isGFX8Only] 310 311 let renamedInGFX9 = 1, Predicates = [Has16BitInsts, isGFX9Plus] in { 312 defm V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9", 313 VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUdiv_fixup>; 314 defm V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, any_fma>; 315 } // End renamedInGFX9 = 1, Predicates = [Has16BitInsts, isGFX9Plus] 316} // End FPDPRounding = 1 317 318let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in { 319 320let renamedInGFX9 = 1 in { 321 defm V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; 322 defm V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; 323 let FPDPRounding = 1 in { 324 defm V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, any_fmad>; 325 let Uses = [MODE, M0, EXEC] in { 326 let OtherPredicates = [isNotGFX90APlus] in 327 // For some reason the intrinsic operands are in a different order 328 // from the instruction operands. 329 def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>, 330 [(set f16:$vdst, 331 (int_amdgcn_interp_p2_f16 (VOP3Mods f32:$src2, i32:$src2_modifiers), 332 (VOP3Mods f32:$src0, i32:$src0_modifiers), 333 (i32 timm:$attrchan), 334 (i32 timm:$attr), 335 (i1 timm:$high), 336 M0))]>; 337 } // End Uses = [M0, MODE, EXEC] 338 } // End FPDPRounding = 1 339} // End renamedInGFX9 = 1 340 341let SubtargetPredicate = isGFX9Only, FPDPRounding = 1 in { 342 defm V_MAD_F16_gfx9 : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>> ; 343} // End SubtargetPredicate = isGFX9Only, FPDPRounding = 1 344 345let SubtargetPredicate = isGFX9Plus in { 346defm V_MAD_U16_gfx9 : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; 347defm V_MAD_I16_gfx9 : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; 348let OtherPredicates = [isNotGFX90APlus] in 349def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>; 350} // End SubtargetPredicate = isGFX9Plus 351 352// This predicate should only apply to the selection pattern. The 353// instruction still exists and should decode on subtargets with 354// other bank counts. 355let OtherPredicates = [isNotGFX90APlus, has32BankLDS], Uses = [MODE, M0, EXEC], FPDPRounding = 1 in { 356def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>, 357 [(set f32:$vdst, (int_amdgcn_interp_p1_f16 (VOP3Mods f32:$src0, i32:$src0_modifiers), 358 (i32 timm:$attrchan), 359 (i32 timm:$attr), 360 (i1 timm:$high), M0))]>; 361} // End OtherPredicates = [isNotGFX90APlus, has32BankLDS], Uses = [MODE, M0, EXEC], FPDPRounding = 1 362 363let OtherPredicates = [isNotGFX90APlus], Uses = [MODE, M0, EXEC], FPDPRounding = 1 in { 364def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>; 365} // End OtherPredicates = [isNotGFX90APlus], Uses = [MODE, M0, EXEC], FPDPRounding = 1 366 367} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1 368 369def : GCNPat< 370 (i64 (DivergentUnaryFrag<sext> i16:$src)), 371 (REG_SEQUENCE VReg_64, 372 (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))), sub0, 373 (i32 (COPY_TO_REGCLASS 374 (V_ASHRREV_I32_e32 (S_MOV_B32 (i32 0x1f)), (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))) 375 ), VGPR_32)), sub1) 376>; 377 378let SubtargetPredicate = isGFX8Plus, Uses = [MODE, M0, EXEC], OtherPredicates = [isNotGFX90APlus] in { 379def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>; 380def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>; 381def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>; 382} // End SubtargetPredicate = isGFX8Plus, Uses = [MODE, M0, EXEC], OtherPredicates = [isNotGFX90APlus] 383 384let Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] in { 385 386multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2, 387 Instruction inst> { 388def : GCNPat < 389 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 390 (inst i16:$src0, i16:$src1, i16:$src2, (i1 0)) 391>; 392 393} 394 395defm: Ternary_i16_Pats<mul, add, V_MAD_U16_e64>; 396defm: Ternary_i16_Pats<mul, add, V_MAD_I16_e64>; 397 398} // End Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] 399 400let Predicates = [Has16BitInsts, isGFX10Plus] in { 401 402multiclass Ternary_i16_Pats_gfx9<SDPatternOperator op1, SDPatternOperator op2, 403 Instruction inst> { 404def : GCNPat < 405 (op2 (op1 i16:$src0, i16:$src1), i16:$src2), 406 (inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1, SRCMODS.NONE, $src2, DSTCLAMP.NONE) 407>; 408 409} 410 411defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_U16_gfx9_e64>; 412defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_I16_gfx9_e64>; 413 414} // End Predicates = [Has16BitInsts, isGFX10Plus] 415 416class ThreeOpFragSDAG<SDPatternOperator op1, SDPatternOperator op2> : PatFrag< 417 (ops node:$x, node:$y, node:$z), 418 // When the inner operation is used multiple times, selecting 3-op 419 // instructions may still be beneficial -- if the other users can be 420 // combined similarly. Let's be conservative for now. 421 (op2 (HasOneUseBinOp<op1> node:$x, node:$y), node:$z), 422 [{ 423 // Only use VALU ops when the result is divergent. 424 if (!N->isDivergent()) 425 return false; 426 427 // Check constant bus limitations. 428 // 429 // Note: Use !isDivergent as a conservative proxy for whether the value 430 // is in an SGPR (uniform values can end up in VGPRs as well). 431 unsigned ConstantBusUses = 0; 432 for (unsigned i = 0; i < 3; ++i) { 433 if (!Operands[i]->isDivergent() && 434 !isInlineImmediate(Operands[i].getNode())) { 435 ConstantBusUses++; 436 // This uses AMDGPU::V_ADD3_U32_e64, but all three operand instructions 437 // have the same constant bus limit. 438 if (ConstantBusUses > Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64)) 439 return false; 440 } 441 } 442 443 return true; 444 }]> { 445 let PredicateCodeUsesOperands = 1; 446} 447 448class ThreeOpFrag<SDPatternOperator op1, SDPatternOperator op2> : ThreeOpFragSDAG<op1, op2> { 449 // The divergence predicate is irrelevant in GlobalISel, as we have 450 // proper register bank checks. We just need to verify the constant 451 // bus restriction when all the sources are considered. 452 // 453 // FIXME: With unlucky SGPR operands, we could penalize code by 454 // blocking folding SGPR->VGPR copies later. 455 // FIXME: There's no register bank verifier 456 let GISelPredicateCode = [{ 457 const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64); 458 int ConstantBusUses = 0; 459 for (unsigned i = 0; i < 3; ++i) { 460 const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI); 461 if (RegBank->getID() == AMDGPU::SGPRRegBankID) { 462 if (++ConstantBusUses > ConstantBusLimit) 463 return false; 464 } 465 } 466 return true; 467 }]; 468} 469 470def shl_0_to_4 : PatFrag< 471 (ops node:$src0, node:$src1), (shl node:$src0, node:$src1), 472 [{ 473 if (auto *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 474 return C->getZExtValue() <= 4; 475 } 476 return false; 477 }]> { 478 let GISelPredicateCode = [{ 479 int64_t Imm = 0; 480 if (!mi_match(MI.getOperand(2).getReg(), MRI, m_ICst(Imm)) && 481 !mi_match(MI.getOperand(2).getReg(), MRI, m_Copy(m_ICst(Imm)))) 482 return false; 483 return (uint64_t)Imm <= 4; 484 }]; 485} 486 487def VOP3_CVT_PK_F8_F32_Profile : VOP3_Profile<VOP_I32_F32_F32, VOP3_OPSEL> { 488 let InsVOP3OpSel = (ins FP32InputMods:$src0_modifiers, Src0RC64:$src0, 489 FP32InputMods:$src1_modifiers, Src1RC64:$src1, 490 VGPR_32:$vdst_in, op_sel0:$op_sel); 491 let HasClamp = 0; 492 let HasExtVOP3DPP = 0; 493} 494 495def VOP3_CVT_SR_F8_F32_Profile : VOP3_Profile<VOPProfile<[i32, f32, i32, f32]>, 496 VOP3_OPSEL> { 497 let InsVOP3OpSel = (ins FP32InputMods:$src0_modifiers, Src0RC64:$src0, 498 FP32InputMods:$src1_modifiers, Src1RC64:$src1, 499 FP32InputMods:$src2_modifiers, VGPR_32:$src2, 500 op_sel0:$op_sel); 501 let HasClamp = 0; 502 let HasSrc2 = 0; 503 let HasSrc2Mods = 1; 504 let AsmVOP3OpSel = !subst(", $src2_modifiers", "", 505 getAsmVOP3OpSel<3, HasClamp, HasOMod, 506 HasSrc0FloatMods, HasSrc1FloatMods, 507 HasSrc2FloatMods>.ret); 508 let HasExtVOP3DPP = 0; 509} 510 511let SubtargetPredicate = isGFX9Plus in { 512let isCommutable = 1, isReMaterializable = 1 in { 513 defm V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 514 defm V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 515 defm V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 516 defm V_XAD_U32 : VOP3Inst <"v_xad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 517 defm V_ADD_I32 : VOP3Inst <"v_add_i32", VOP3_Profile<VOP_I32_I32_I32_ARITH>>; 518 defm V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 519} // End isCommutable = 1, isReMaterializable = 1 520// TODO src0 contains the opsel bit for dst, so if we commute, need to mask and swap this 521// to the new src0. 522defm V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmed3>; 523defm V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmed3>; 524defm V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumed3>; 525 526defm V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmin3>; 527defm V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmin3>; 528defm V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumin3>; 529 530defm V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmax3>; 531defm V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmax3>; 532defm V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumax3>; 533 534defm V_ADD_I16 : VOP3Inst <"v_add_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; 535defm V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; 536 537defm V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; 538defm V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; 539 540defm V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 541defm V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 542 543defm V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; 544 545let isReMaterializable = 1 in { 546defm V_SUB_I32 : VOP3Inst <"v_sub_i32", VOP3_Profile<VOP_I32_I32_I32_ARITH>>; 547defm V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 548defm V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 549} // End isReMaterializable = 1 550 551// V_LSHL_ADD_U64: D0.u64 = (S0.u64 << S1.u[2:0]) + S2.u64 552// src0 is shifted left by 0-4 (use “0” to get ADD_U64). 553let SubtargetPredicate = isGFX940Plus in 554defm V_LSHL_ADD_U64 : VOP3Inst <"v_lshl_add_u64", VOP3_Profile<VOP_I64_I64_I32_I64>>; 555 556let SubtargetPredicate = HasFP8Insts, mayRaiseFPException = 0, 557 SchedRW = [WriteFloatCvt] in { 558 let Constraints = "$vdst = $vdst_in", DisableEncoding = "$vdst_in" in { 559 defm V_CVT_PK_FP8_F32 : VOP3Inst<"v_cvt_pk_fp8_f32", VOP3_CVT_PK_F8_F32_Profile>; 560 defm V_CVT_PK_BF8_F32 : VOP3Inst<"v_cvt_pk_bf8_f32", VOP3_CVT_PK_F8_F32_Profile>; 561 } 562 563 // These instructions have non-standard use of op_sel. In particular they are 564 // using op_sel bits 2 and 3 while only having two sources. Therefore dummy 565 // src2 is used to hold the op_sel value. 566 let Constraints = "$vdst = $src2", DisableEncoding = "$src2" in { 567 defm V_CVT_SR_FP8_F32 : VOP3Inst<"v_cvt_sr_fp8_f32", VOP3_CVT_SR_F8_F32_Profile>; 568 defm V_CVT_SR_BF8_F32 : VOP3Inst<"v_cvt_sr_bf8_f32", VOP3_CVT_SR_F8_F32_Profile>; 569 } 570} 571 572class Cvt_PK_F8_F32_Pat<SDPatternOperator node, int index, VOP3_Pseudo inst> : GCNPat< 573 (i32 (node f32:$src0, f32:$src1, i32:$old, index)), 574 (inst !if(index, SRCMODS.DST_OP_SEL, 0), $src0, 0, $src1, $old, !if(index, SRCMODS.OP_SEL_0, 0)) 575>; 576 577class Cvt_SR_F8_F32_Pat<SDPatternOperator node, bits<2> index, VOP3_Pseudo inst> : GCNPat< 578 (i32 (node f32:$src0, i32:$src1, i32:$old, index)), 579 (inst !if(index{1}, SRCMODS.DST_OP_SEL, 0), $src0, 0, $src1, 580 !if(index{0}, SRCMODS.OP_SEL_0, 0), $old, !if(index{1}, SRCMODS.OP_SEL_0, 0)) 581>; 582 583foreach Index = [0, -1] in { 584 def : Cvt_PK_F8_F32_Pat<int_amdgcn_cvt_pk_fp8_f32, Index, V_CVT_PK_FP8_F32_e64>; 585 def : Cvt_PK_F8_F32_Pat<int_amdgcn_cvt_pk_bf8_f32, Index, V_CVT_PK_BF8_F32_e64>; 586} 587 588foreach Index = [0, 1, 2, 3] in { 589 def : Cvt_SR_F8_F32_Pat<int_amdgcn_cvt_sr_fp8_f32, Index, V_CVT_SR_FP8_F32_e64>; 590 def : Cvt_SR_F8_F32_Pat<int_amdgcn_cvt_sr_bf8_f32, Index, V_CVT_SR_BF8_F32_e64>; 591} 592 593class ThreeOp_i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst> : GCNPat < 594 // This matches (op2 (op1 i32:$src0, i32:$src1), i32:$src2) with conditions. 595 (ThreeOpFrag<op1, op2> i32:$src0, i32:$src1, i32:$src2), 596 (inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2) 597>; 598 599def : ThreeOp_i32_Pats<cshl_32, add, V_LSHL_ADD_U32_e64>; 600def : ThreeOp_i32_Pats<add, cshl_32, V_ADD_LSHL_U32_e64>; 601def : ThreeOp_i32_Pats<add, add, V_ADD3_U32_e64>; 602def : ThreeOp_i32_Pats<ptradd, ptradd, V_ADD3_U32_e64>; 603def : ThreeOp_i32_Pats<cshl_32, or, V_LSHL_OR_B32_e64>; 604def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32_e64>; 605def : ThreeOp_i32_Pats<or, or, V_OR3_B32_e64>; 606def : ThreeOp_i32_Pats<xor, add, V_XAD_U32_e64>; 607 608let SubtargetPredicate = isGFX940Plus in 609def : GCNPat< 610 (ThreeOpFrag<shl_0_to_4, add> i64:$src0, i32:$src1, i64:$src2), 611 (V_LSHL_ADD_U64_e64 VSrc_b64:$src0, VSrc_b32:$src1, VSrc_b64:$src2) 612>; 613 614def : VOPBinOpClampPat<saddsat, V_ADD_I32_e64, i32>; 615def : VOPBinOpClampPat<ssubsat, V_SUB_I32_e64, i32>; 616 617def : GCNPat<(DivergentBinFrag<or> (or_oneuse i64:$src0, i64:$src1), i64:$src2), 618 (REG_SEQUENCE VReg_64, 619 (V_OR3_B32_e64 (i32 (EXTRACT_SUBREG $src0, sub0)), 620 (i32 (EXTRACT_SUBREG $src1, sub0)), 621 (i32 (EXTRACT_SUBREG $src2, sub0))), sub0, 622 (V_OR3_B32_e64 (i32 (EXTRACT_SUBREG $src0, sub1)), 623 (i32 (EXTRACT_SUBREG $src1, sub1)), 624 (i32 (EXTRACT_SUBREG $src2, sub1))), sub1)>; 625 626// FIXME: Probably should hardcode clamp bit in pseudo and avoid this. 627class OpSelBinOpClampPat<SDPatternOperator node, 628 Instruction inst> : GCNPat< 629 (node (i16 (VOP3OpSel i16:$src0, i32:$src0_modifiers)), 630 (i16 (VOP3OpSel i16:$src1, i32:$src1_modifiers))), 631 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE, 0) 632>; 633 634def : OpSelBinOpClampPat<saddsat, V_ADD_I16_e64>; 635def : OpSelBinOpClampPat<ssubsat, V_SUB_I16_e64>; 636} // End SubtargetPredicate = isGFX9Plus 637 638// FIXME: GlobalISel in general does not handle instructions with 2 results, 639// so it cannot use these patterns. 640multiclass IMAD32_Pats <VOP3_Pseudo inst> { 641 def : GCNPat < 642 (ThreeOpFrag<mul, add> i32:$src0, i32:$src1, i32:$src2), 643 (EXTRACT_SUBREG (inst $src0, $src1, 644 (REG_SEQUENCE SReg_64, // Use scalar and let it be legalized 645 $src2, sub0, 646 (i32 (IMPLICIT_DEF)), sub1), 647 0 /* clamp */), 648 sub0) 649 >; 650 // Immediate src2 in the pattern above will not fold because it would be partially 651 // undef. Hence define specialized pattern for this case. 652 // FIXME: GlobalISel pattern exporter fails to export a pattern like this and asserts, 653 // make it SDAG only. 654 def : GCNPat < 655 (ThreeOpFragSDAG<mul, add> i32:$src0, i32:$src1, (i32 imm:$src2)), 656 (EXTRACT_SUBREG (inst $src0, $src1, (i64 (as_i64imm $src2)), 0 /* clamp */), sub0) 657 >; 658} 659 660// exclude pre-GFX9 where it was slow 661let OtherPredicates = [HasNotMADIntraFwdBug], SubtargetPredicate = isGFX9Plus in 662 defm : IMAD32_Pats<V_MAD_U64_U32_e64>; 663let OtherPredicates = [HasMADIntraFwdBug], SubtargetPredicate = isGFX11Only in 664 defm : IMAD32_Pats<V_MAD_U64_U32_gfx11_e64>; 665 666def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3_OPSEL> { 667 let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0, 668 IntOpSelMods:$src1_modifiers, SSrc_b32:$src1, 669 IntOpSelMods:$src2_modifiers, SSrc_b32:$src2, 670 VGPR_32:$vdst_in, op_sel0:$op_sel); 671 let HasClamp = 0; 672 let HasExtVOP3DPP = 0; 673 let HasExtDPP = 0; 674} 675 676class PermlanePat<SDPatternOperator permlane, 677 Instruction inst> : GCNPat< 678 (permlane i32:$vdst_in, i32:$src0, i32:$src1, i32:$src2, 679 timm:$fi, timm:$bc), 680 (inst (as_i1timm $fi), VGPR_32:$src0, (as_i1timm $bc), 681 SCSrc_b32:$src1, 0, SCSrc_b32:$src2, VGPR_32:$vdst_in) 682>; 683 684 685let SubtargetPredicate = isGFX10Plus in { 686 let isCommutable = 1, isReMaterializable = 1 in { 687 defm V_XOR3_B32 : VOP3Inst <"v_xor3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 688 } // End isCommutable = 1, isReMaterializable = 1 689 def : ThreeOp_i32_Pats<xor, xor, V_XOR3_B32_e64>; 690 691 let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in { 692 defm V_PERMLANE16_B32 : VOP3Inst<"v_permlane16_b32", VOP3_PERMLANE_Profile>; 693 defm V_PERMLANEX16_B32 : VOP3Inst<"v_permlanex16_b32", VOP3_PERMLANE_Profile>; 694 } // End $vdst = $vdst_in, DisableEncoding $vdst_in 695 696 def : PermlanePat<int_amdgcn_permlane16, V_PERMLANE16_B32_e64>; 697 def : PermlanePat<int_amdgcn_permlanex16, V_PERMLANEX16_B32_e64>; 698 699 defm V_ADD_NC_U16 : VOP3Inst <"v_add_nc_u16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>, add>; 700 defm V_SUB_NC_U16 : VOP3Inst <"v_sub_nc_u16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>, sub>; 701 702 def : OpSelBinOpClampPat<uaddsat, V_ADD_NC_U16_e64>; 703 def : OpSelBinOpClampPat<usubsat, V_SUB_NC_U16_e64>; 704 705 // Undo sub x, c -> add x, -c canonicalization since c is more likely 706 // an inline immediate than -c. 707 def : GCNPat< 708 (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)), 709 (V_SUB_NC_U16_e64 0, VSrc_b16:$src0, 0, NegSubInlineIntConst16:$src1, 0, 0) 710 >; 711 712} // End SubtargetPredicate = isGFX10Plus 713 714class DivFmasPat<ValueType vt, Instruction inst, Register CondReg> : GCNPat< 715 (AMDGPUdiv_fmas (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), 716 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), 717 (vt (VOP3Mods vt:$src2, i32:$src2_modifiers)), 718 (i1 CondReg)), 719 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, $src2_modifiers, $src2) 720>; 721 722let WaveSizePredicate = isWave64 in { 723def : DivFmasPat<f32, V_DIV_FMAS_F32_e64, VCC>; 724def : DivFmasPat<f64, V_DIV_FMAS_F64_e64, VCC>; 725} 726 727let WaveSizePredicate = isWave32 in { 728def : DivFmasPat<f32, V_DIV_FMAS_F32_e64, VCC_LO>; 729def : DivFmasPat<f64, V_DIV_FMAS_F64_e64, VCC_LO>; 730} 731 732class VOP3_DOT_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOP3_Profile<P, Features> { 733 let HasClamp = 0; 734 let HasOMod = 0; 735 // Override modifiers for bf16(i16) (same as float modifiers). 736 let HasSrc0Mods = 1; 737 let HasSrc1Mods = 1; 738 let HasSrc2Mods = 1; 739 let Src0ModVOP3DPP = FPVRegInputMods; 740 let Src1ModVOP3DPP = FPVRegInputMods; 741 let Src2ModVOP3DPP = FP16InputMods; 742 let InsVOP3OpSel = getInsVOP3OpSel<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs, 743 HasClamp, HasOMod, FP16InputMods, 744 FP16InputMods, FP16InputMods>.ret; 745 let AsmVOP3OpSel = getAsmVOP3OpSel<NumSrcArgs, HasClamp, HasOMod, 1, 1, 1>.ret; 746} 747 748let SubtargetPredicate = isGFX11Plus in { 749 defm V_MAXMIN_F32 : VOP3Inst<"v_maxmin_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 750 defm V_MINMAX_F32 : VOP3Inst<"v_minmax_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; 751 defm V_MAXMIN_F16 : VOP3Inst<"v_maxmin_f16", VOP3_Profile<VOP_F16_F16_F16_F16>>; 752 defm V_MINMAX_F16 : VOP3Inst<"v_minmax_f16", VOP3_Profile<VOP_F16_F16_F16_F16>>; 753 defm V_MAXMIN_U32 : VOP3Inst<"v_maxmin_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 754 defm V_MINMAX_U32 : VOP3Inst<"v_minmax_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 755 defm V_MAXMIN_I32 : VOP3Inst<"v_maxmin_i32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 756 defm V_MINMAX_I32 : VOP3Inst<"v_minmax_i32", VOP3_Profile<VOP_I32_I32_I32_I32>>; 757 defm V_CVT_PK_I16_F32 : VOP3Inst<"v_cvt_pk_i16_f32", VOP3_Profile<VOP_V2I16_F32_F32>>; 758 defm V_CVT_PK_U16_F32 : VOP3Inst<"v_cvt_pk_u16_f32", VOP3_Profile<VOP_V2I16_F32_F32>>; 759} // End SubtargetPredicate = isGFX11Plus 760 761let SubtargetPredicate = HasDot9Insts, IsDOT=1 in { 762 defm V_DOT2_F16_F16 : VOP3Inst<"v_dot2_f16_f16", VOP3_DOT_Profile<VOP_F16_V2F16_V2F16_F16>, int_amdgcn_fdot2_f16_f16>; 763 defm V_DOT2_BF16_BF16 : VOP3Inst<"v_dot2_bf16_bf16", VOP3_DOT_Profile<VOP_I16_V2I16_V2I16_I16>, int_amdgcn_fdot2_bf16_bf16>; 764} 765 766//===----------------------------------------------------------------------===// 767// Integer Clamp Patterns 768//===----------------------------------------------------------------------===// 769 770class getClampPat<VOPProfile P, SDPatternOperator node> { 771 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2)); 772 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1)); 773 dag ret1 = (P.DstVT (node P.Src0VT:$src0)); 774 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3, 775 !if(!eq(P.NumSrcArgs, 2), ret2, 776 ret1)); 777} 778 779class getClampRes<VOPProfile P, Instruction inst> { 780 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0)); 781 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0)); 782 dag ret1 = (inst P.Src0VT:$src0, (i1 0)); 783 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3, 784 !if(!eq(P.NumSrcArgs, 2), ret2, 785 ret1)); 786} 787 788class IntClampPat<VOP3InstBase inst, SDPatternOperator node> : GCNPat< 789 getClampPat<inst.Pfl, node>.ret, 790 getClampRes<inst.Pfl, inst>.ret 791>; 792 793def : IntClampPat<V_MAD_I32_I24_e64, AMDGPUmad_i24>; 794def : IntClampPat<V_MAD_U32_U24_e64, AMDGPUmad_u24>; 795 796def : IntClampPat<V_SAD_U8_e64, int_amdgcn_sad_u8>; 797def : IntClampPat<V_SAD_HI_U8_e64, int_amdgcn_sad_hi_u8>; 798def : IntClampPat<V_SAD_U16_e64, int_amdgcn_sad_u16>; 799 800def : IntClampPat<V_MSAD_U8_e64, int_amdgcn_msad_u8>; 801def : IntClampPat<V_MQSAD_PK_U16_U8_e64, int_amdgcn_mqsad_pk_u16_u8>; 802 803def : IntClampPat<V_QSAD_PK_U16_U8_e64, int_amdgcn_qsad_pk_u16_u8>; 804def : IntClampPat<V_MQSAD_U32_U8_e64, int_amdgcn_mqsad_u32_u8>; 805 806//===----------------------------------------------------------------------===// 807// Target-specific instruction encodings. 808//===----------------------------------------------------------------------===// 809 810//===----------------------------------------------------------------------===// 811// GFX11. 812//===----------------------------------------------------------------------===// 813 814defm V_FMA_DX9_ZERO_F32 : VOP3_Real_with_name_gfx11<0x209, "V_FMA_LEGACY_F32", "v_fma_dx9_zero_f32">; 815defm V_MAD_I32_I24 : VOP3_Realtriple_gfx11<0x20a>; 816defm V_MAD_U32_U24 : VOP3_Realtriple_gfx11<0x20b>; 817defm V_CUBEID_F32 : VOP3_Realtriple_gfx11<0x20c>; 818defm V_CUBESC_F32 : VOP3_Realtriple_gfx11<0x20d>; 819defm V_CUBETC_F32 : VOP3_Realtriple_gfx11<0x20e>; 820defm V_CUBEMA_F32 : VOP3_Realtriple_gfx11<0x20f>; 821defm V_BFE_U32 : VOP3_Realtriple_gfx11<0x210>; 822defm V_BFE_I32 : VOP3_Realtriple_gfx11<0x211>; 823defm V_BFI_B32 : VOP3_Realtriple_gfx11<0x212>; 824defm V_FMA_F32 : VOP3_Realtriple_gfx11<0x213>; 825defm V_FMA_F64 : VOP3_Real_Base_gfx11<0x214>; 826defm V_LERP_U8 : VOP3_Realtriple_gfx11<0x215>; 827defm V_ALIGNBIT_B32 : VOP3_Realtriple_gfx11<0x216>; 828defm V_ALIGNBYTE_B32 : VOP3_Realtriple_gfx11<0x217>; 829defm V_MULLIT_F32 : VOP3_Realtriple_gfx11<0x218>; 830defm V_MIN3_F32 : VOP3_Realtriple_gfx11<0x219>; 831defm V_MIN3_I32 : VOP3_Realtriple_gfx11<0x21a>; 832defm V_MIN3_U32 : VOP3_Realtriple_gfx11<0x21b>; 833defm V_MAX3_F32 : VOP3_Realtriple_gfx11<0x21c>; 834defm V_MAX3_I32 : VOP3_Realtriple_gfx11<0x21d>; 835defm V_MAX3_U32 : VOP3_Realtriple_gfx11<0x21e>; 836defm V_MED3_F32 : VOP3_Realtriple_gfx11<0x21f>; 837defm V_MED3_I32 : VOP3_Realtriple_gfx11<0x220>; 838defm V_MED3_U32 : VOP3_Realtriple_gfx11<0x221>; 839defm V_SAD_U8 : VOP3_Realtriple_gfx11<0x222>; 840defm V_SAD_HI_U8 : VOP3_Realtriple_gfx11<0x223>; 841defm V_SAD_U16 : VOP3_Realtriple_gfx11<0x224>; 842defm V_SAD_U32 : VOP3_Realtriple_gfx11<0x225>; 843defm V_CVT_PK_U8_F32 : VOP3_Realtriple_gfx11<0x226>; 844defm V_DIV_FIXUP_F32 : VOP3_Real_Base_gfx11<0x227>; 845defm V_DIV_FIXUP_F64 : VOP3_Real_Base_gfx11<0x228>; 846defm V_DIV_FMAS_F32 : VOP3_Real_Base_gfx11<0x237>; 847defm V_DIV_FMAS_F64 : VOP3_Real_Base_gfx11<0x238>; 848defm V_MSAD_U8 : VOP3_Realtriple_gfx11<0x239>; 849defm V_QSAD_PK_U16_U8 : VOP3_Real_Base_gfx11<0x23a>; 850defm V_MQSAD_PK_U16_U8 : VOP3_Real_Base_gfx11<0x23b>; 851defm V_MQSAD_U32_U8 : VOP3_Real_Base_gfx11<0x23d>; 852defm V_XOR3_B32 : VOP3_Realtriple_gfx11<0x240>; 853defm V_MAD_U16 : VOP3_Realtriple_with_name_gfx11<0x241, "V_MAD_U16_gfx9", "v_mad_u16">; 854defm V_PERM_B32 : VOP3_Realtriple_gfx11<0x244>; 855defm V_XAD_U32 : VOP3_Realtriple_gfx11<0x245>; 856defm V_LSHL_ADD_U32 : VOP3_Realtriple_gfx11<0x246>; 857defm V_ADD_LSHL_U32 : VOP3_Realtriple_gfx11<0x247>; 858defm V_FMA_F16 : VOP3_Realtriple_with_name_gfx11<0x248, "V_FMA_F16_gfx9", "v_fma_f16">; 859defm V_MIN3_F16 : VOP3_Realtriple_gfx11<0x249>; 860defm V_MIN3_I16 : VOP3_Realtriple_gfx11<0x24a>; 861defm V_MIN3_U16 : VOP3_Realtriple_gfx11<0x24b>; 862defm V_MAX3_F16 : VOP3_Realtriple_gfx11<0x24c>; 863defm V_MAX3_I16 : VOP3_Realtriple_gfx11<0x24d>; 864defm V_MAX3_U16 : VOP3_Realtriple_gfx11<0x24e>; 865defm V_MED3_F16 : VOP3_Realtriple_gfx11<0x24f>; 866defm V_MED3_I16 : VOP3_Realtriple_gfx11<0x250>; 867defm V_MED3_U16 : VOP3_Realtriple_gfx11<0x251>; 868defm V_MAD_I16 : VOP3_Realtriple_with_name_gfx11<0x253, "V_MAD_I16_gfx9", "v_mad_i16">; 869defm V_DIV_FIXUP_F16 : VOP3_Realtriple_with_name_gfx11<0x254, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">; 870defm V_ADD3_U32 : VOP3_Realtriple_gfx11<0x255>; 871defm V_LSHL_OR_B32 : VOP3_Realtriple_gfx11<0x256>; 872defm V_AND_OR_B32 : VOP3_Realtriple_gfx11<0x257>; 873defm V_OR3_B32 : VOP3_Realtriple_gfx11<0x258>; 874defm V_MAD_U32_U16 : VOP3_Realtriple_gfx11<0x259>; 875defm V_MAD_I32_I16 : VOP3_Realtriple_gfx11<0x25a>; 876defm V_PERMLANE16_B32 : VOP3_Real_Base_gfx11<0x25b>; 877defm V_PERMLANEX16_B32 : VOP3_Real_Base_gfx11<0x25c>; 878defm V_MAXMIN_F32 : VOP3_Realtriple_gfx11<0x25e>; 879defm V_MINMAX_F32 : VOP3_Realtriple_gfx11<0x25f>; 880defm V_MAXMIN_F16 : VOP3_Realtriple_gfx11<0x260>; 881defm V_MINMAX_F16 : VOP3_Realtriple_gfx11<0x261>; 882defm V_MAXMIN_U32 : VOP3_Realtriple_gfx11<0x262>; 883defm V_MINMAX_U32 : VOP3_Realtriple_gfx11<0x263>; 884defm V_MAXMIN_I32 : VOP3_Realtriple_gfx11<0x264>; 885defm V_MINMAX_I32 : VOP3_Realtriple_gfx11<0x265>; 886defm V_DOT2_F16_F16 : VOP3Dot_Realtriple_gfx11<0x266>; 887defm V_DOT2_BF16_BF16 : VOP3Dot_Realtriple_gfx11<0x267>; 888defm V_DIV_SCALE_F32 : VOP3be_Real_gfx11<0x2fc, "V_DIV_SCALE_F32", "v_div_scale_f32">; 889defm V_DIV_SCALE_F64 : VOP3be_Real_gfx11<0x2fd, "V_DIV_SCALE_F64", "v_div_scale_f64">; 890defm V_MAD_U64_U32_gfx11 : VOP3be_Real_gfx11<0x2fe, "V_MAD_U64_U32_gfx11", "v_mad_u64_u32">; 891defm V_MAD_I64_I32_gfx11 : VOP3be_Real_gfx11<0x2ff, "V_MAD_I64_I32_gfx11", "v_mad_i64_i32">; 892defm V_ADD_NC_U16 : VOP3Only_Realtriple_gfx11<0x303>; 893defm V_SUB_NC_U16 : VOP3Only_Realtriple_gfx11<0x304>; 894defm V_MUL_LO_U16_t16 : VOP3Only_Realtriple_t16_gfx11<0x305, "v_mul_lo_u16">; 895defm V_CVT_PK_I16_F32 : VOP3_Realtriple_gfx11<0x306>; 896defm V_CVT_PK_U16_F32 : VOP3_Realtriple_gfx11<0x307>; 897defm V_MAX_U16_t16 : VOP3Only_Realtriple_t16_gfx11<0x309, "v_max_u16">; 898defm V_MAX_I16_t16 : VOP3Only_Realtriple_t16_gfx11<0x30a, "v_max_i16">; 899defm V_MIN_U16_t16 : VOP3Only_Realtriple_t16_gfx11<0x30b, "v_min_u16">; 900defm V_MIN_I16_t16 : VOP3Only_Realtriple_t16_gfx11<0x30c, "v_min_i16">; 901defm V_ADD_NC_I16 : VOP3_Realtriple_with_name_gfx11<0x30d, "V_ADD_I16", "v_add_nc_i16">; 902defm V_SUB_NC_I16 : VOP3_Realtriple_with_name_gfx11<0x30e, "V_SUB_I16", "v_sub_nc_i16">; 903defm V_PACK_B32_F16 : VOP3_Realtriple_gfx11<0x311>; 904defm V_CVT_PK_NORM_I16_F16 : VOP3_Realtriple_with_name_gfx11<0x312, "V_CVT_PKNORM_I16_F16" , "v_cvt_pk_norm_i16_f16" >; 905defm V_CVT_PK_NORM_U16_F16 : VOP3_Realtriple_with_name_gfx11<0x313, "V_CVT_PKNORM_U16_F16" , "v_cvt_pk_norm_u16_f16" >; 906defm V_SUB_NC_I32 : VOP3_Realtriple_with_name_gfx11<0x325, "V_SUB_I32", "v_sub_nc_i32">; 907defm V_ADD_NC_I32 : VOP3_Realtriple_with_name_gfx11<0x326, "V_ADD_I32", "v_add_nc_i32">; 908defm V_ADD_F64 : VOP3_Real_Base_gfx11<0x327>; 909defm V_MUL_F64 : VOP3_Real_Base_gfx11<0x328>; 910defm V_MIN_F64 : VOP3_Real_Base_gfx11<0x329>; 911defm V_MAX_F64 : VOP3_Real_Base_gfx11<0x32a>; 912defm V_LDEXP_F64 : VOP3_Real_Base_gfx11<0x32b>; 913defm V_MUL_LO_U32 : VOP3_Real_Base_gfx11<0x32c>; 914defm V_MUL_HI_U32 : VOP3_Real_Base_gfx11<0x32d>; 915defm V_MUL_HI_I32 : VOP3_Real_Base_gfx11<0x32e>; 916defm V_TRIG_PREOP_F64 : VOP3_Real_Base_gfx11<0x32f>; 917defm V_LSHLREV_B16_t16 : VOP3Only_Realtriple_t16_gfx11<0x338, "v_lshlrev_b16">; 918defm V_LSHRREV_B16_t16 : VOP3Only_Realtriple_t16_gfx11<0x339, "v_lshrrev_b16">; 919defm V_ASHRREV_I16_t16 : VOP3Only_Realtriple_t16_gfx11<0x33a, "v_ashrrev_i16">; 920defm V_LSHLREV_B64 : VOP3_Real_Base_gfx11<0x33c>; 921defm V_LSHRREV_B64 : VOP3_Real_Base_gfx11<0x33d>; 922defm V_ASHRREV_I64 : VOP3_Real_Base_gfx11<0x33e>; 923defm V_READLANE_B32 : VOP3_Real_No_Suffix_gfx11<0x360>; // Pseudo in VOP2 924let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in { 925 defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_gfx11<0x361>; // Pseudo in VOP2 926} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) 927defm V_AND_B16_t16 : VOP3Only_Realtriple_t16_gfx11<0x362, "v_and_b16">; 928defm V_OR_B16_t16 : VOP3Only_Realtriple_t16_gfx11<0x363, "v_or_b16">; 929defm V_XOR_B16_t16 : VOP3Only_Realtriple_t16_gfx11<0x364, "v_xor_b16">; 930 931//===----------------------------------------------------------------------===// 932// GFX10. 933//===----------------------------------------------------------------------===// 934 935let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in { 936 multiclass VOP3_Real_gfx10<bits<10> op> { 937 def _gfx10 : 938 VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 939 VOP3e_gfx10<op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 940 } 941 multiclass VOP3_Real_No_Suffix_gfx10<bits<10> op> { 942 def _gfx10 : 943 VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX10>, 944 VOP3e_gfx10<op, !cast<VOP_Pseudo>(NAME).Pfl>; 945 } 946 multiclass VOP3_Real_gfx10_with_name<bits<10> op, string opName, 947 string asmName> { 948 def _gfx10 : 949 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 950 VOP3e_gfx10<op, !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 951 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64"); 952 let AsmString = asmName # ps.AsmOperands; 953 let IsSingle = 1; 954 } 955 } 956 multiclass VOP3be_Real_gfx10<bits<10> op> { 957 def _gfx10 : 958 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 959 VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 960 } 961 multiclass VOP3Interp_Real_gfx10<bits<10> op> { 962 def _gfx10 : 963 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>, 964 VOP3Interp_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>; 965 } 966 multiclass VOP3OpSel_Real_gfx10<bits<10> op> { 967 def _gfx10 : 968 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>, 969 VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 970 } 971 multiclass VOP3OpSel_Real_gfx10_with_name<bits<10> op, string opName, 972 string asmName> { 973 def _gfx10 : 974 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>, 975 VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(opName#"_e64").Pfl> { 976 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64"); 977 let AsmString = asmName # ps.AsmOperands; 978 } 979 } 980} // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" 981 982defm V_READLANE_B32 : VOP3_Real_No_Suffix_gfx10<0x360>; 983 984let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in { 985 defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_gfx10<0x361>; 986} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) 987 988let SubtargetPredicate = isGFX10Before1030 in { 989 defm V_MUL_LO_I32 : VOP3_Real_gfx10<0x16b>; 990} 991 992defm V_XOR3_B32 : VOP3_Real_gfx10<0x178>; 993defm V_LSHLREV_B64 : VOP3_Real_gfx10<0x2ff>; 994defm V_LSHRREV_B64 : VOP3_Real_gfx10<0x300>; 995defm V_ASHRREV_I64 : VOP3_Real_gfx10<0x301>; 996defm V_PERM_B32 : VOP3_Real_gfx10<0x344>; 997defm V_XAD_U32 : VOP3_Real_gfx10<0x345>; 998defm V_LSHL_ADD_U32 : VOP3_Real_gfx10<0x346>; 999defm V_ADD_LSHL_U32 : VOP3_Real_gfx10<0x347>; 1000defm V_ADD3_U32 : VOP3_Real_gfx10<0x36d>; 1001defm V_LSHL_OR_B32 : VOP3_Real_gfx10<0x36f>; 1002defm V_AND_OR_B32 : VOP3_Real_gfx10<0x371>; 1003defm V_OR3_B32 : VOP3_Real_gfx10<0x372>; 1004 1005// TODO-GFX10: add MC tests for v_add/sub_nc_i16 1006defm V_ADD_NC_I16 : 1007 VOP3OpSel_Real_gfx10_with_name<0x30d, "V_ADD_I16", "v_add_nc_i16">; 1008defm V_SUB_NC_I16 : 1009 VOP3OpSel_Real_gfx10_with_name<0x30e, "V_SUB_I16", "v_sub_nc_i16">; 1010defm V_SUB_NC_I32 : 1011 VOP3_Real_gfx10_with_name<0x376, "V_SUB_I32", "v_sub_nc_i32">; 1012defm V_ADD_NC_I32 : 1013 VOP3_Real_gfx10_with_name<0x37f, "V_ADD_I32", "v_add_nc_i32">; 1014 1015defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_gfx10<0x200>; 1016defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_gfx10<0x201>; 1017defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_gfx10<0x202>; 1018 1019defm V_INTERP_P1LL_F16 : VOP3Interp_Real_gfx10<0x342>; 1020defm V_INTERP_P1LV_F16 : VOP3Interp_Real_gfx10<0x343>; 1021defm V_INTERP_P2_F16 : VOP3Interp_Real_gfx10<0x35a>; 1022 1023defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx10<0x311>; 1024defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx10<0x312>; 1025defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx10<0x313>; 1026 1027defm V_MIN3_F16 : VOP3OpSel_Real_gfx10<0x351>; 1028defm V_MIN3_I16 : VOP3OpSel_Real_gfx10<0x352>; 1029defm V_MIN3_U16 : VOP3OpSel_Real_gfx10<0x353>; 1030defm V_MAX3_F16 : VOP3OpSel_Real_gfx10<0x354>; 1031defm V_MAX3_I16 : VOP3OpSel_Real_gfx10<0x355>; 1032defm V_MAX3_U16 : VOP3OpSel_Real_gfx10<0x356>; 1033defm V_MED3_F16 : VOP3OpSel_Real_gfx10<0x357>; 1034defm V_MED3_I16 : VOP3OpSel_Real_gfx10<0x358>; 1035defm V_MED3_U16 : VOP3OpSel_Real_gfx10<0x359>; 1036defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx10<0x373>; 1037defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx10<0x375>; 1038 1039defm V_MAD_U16 : 1040 VOP3OpSel_Real_gfx10_with_name<0x340, "V_MAD_U16_gfx9", "v_mad_u16">; 1041defm V_FMA_F16 : 1042 VOP3OpSel_Real_gfx10_with_name<0x34b, "V_FMA_F16_gfx9", "v_fma_f16">; 1043defm V_MAD_I16 : 1044 VOP3OpSel_Real_gfx10_with_name<0x35e, "V_MAD_I16_gfx9", "v_mad_i16">; 1045defm V_DIV_FIXUP_F16 : 1046 VOP3OpSel_Real_gfx10_with_name<0x35f, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">; 1047 1048defm V_ADD_NC_U16 : VOP3OpSel_Real_gfx10<0x303>; 1049defm V_SUB_NC_U16 : VOP3OpSel_Real_gfx10<0x304>; 1050 1051// FIXME-GFX10-OPSEL: Need to add "selective" opsel support to some of these 1052// (they do not support SDWA or DPP). 1053defm V_MUL_LO_U16 : VOP3_Real_gfx10_with_name<0x305, "V_MUL_LO_U16", "v_mul_lo_u16">; 1054defm V_LSHRREV_B16 : VOP3_Real_gfx10_with_name<0x307, "V_LSHRREV_B16", "v_lshrrev_b16">; 1055defm V_ASHRREV_I16 : VOP3_Real_gfx10_with_name<0x308, "V_ASHRREV_I16", "v_ashrrev_i16">; 1056defm V_MAX_U16 : VOP3_Real_gfx10_with_name<0x309, "V_MAX_U16", "v_max_u16">; 1057defm V_MAX_I16 : VOP3_Real_gfx10_with_name<0x30a, "V_MAX_I16", "v_max_i16">; 1058defm V_MIN_U16 : VOP3_Real_gfx10_with_name<0x30b, "V_MIN_U16", "v_min_u16">; 1059defm V_MIN_I16 : VOP3_Real_gfx10_with_name<0x30c, "V_MIN_I16", "v_min_i16">; 1060defm V_LSHLREV_B16 : VOP3_Real_gfx10_with_name<0x314, "V_LSHLREV_B16", "v_lshlrev_b16">; 1061defm V_PERMLANE16_B32 : VOP3OpSel_Real_gfx10<0x377>; 1062defm V_PERMLANEX16_B32 : VOP3OpSel_Real_gfx10<0x378>; 1063 1064//===----------------------------------------------------------------------===// 1065// GFX7, GFX10. 1066//===----------------------------------------------------------------------===// 1067 1068let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in { 1069 multiclass VOP3_Real_gfx7<bits<10> op> { 1070 def _gfx7 : 1071 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 1072 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1073 } 1074 multiclass VOP3be_Real_gfx7<bits<10> op> { 1075 def _gfx7 : 1076 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 1077 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1078 } 1079} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" 1080 1081multiclass VOP3_Real_gfx7_gfx10<bits<10> op> : 1082 VOP3_Real_gfx7<op>, VOP3_Real_gfx10<op>; 1083 1084multiclass VOP3be_Real_gfx7_gfx10<bits<10> op> : 1085 VOP3be_Real_gfx7<op>, VOP3be_Real_gfx10<op>; 1086 1087defm V_QSAD_PK_U16_U8 : VOP3_Real_gfx7_gfx10<0x172>; 1088defm V_MQSAD_U32_U8 : VOP3_Real_gfx7_gfx10<0x175>; 1089defm V_MAD_U64_U32 : VOP3be_Real_gfx7_gfx10<0x176>; 1090defm V_MAD_I64_I32 : VOP3be_Real_gfx7_gfx10<0x177>; 1091 1092//===----------------------------------------------------------------------===// 1093// GFX6, GFX7, GFX10. 1094//===----------------------------------------------------------------------===// 1095 1096let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in { 1097 multiclass VOP3_Real_gfx6_gfx7<bits<10> op> { 1098 def _gfx6_gfx7 : 1099 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 1100 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1101 } 1102 multiclass VOP3be_Real_gfx6_gfx7<bits<10> op> { 1103 def _gfx6_gfx7 : 1104 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, 1105 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1106 } 1107} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" 1108 1109multiclass VOP3_Real_gfx6_gfx7_gfx10<bits<10> op> : 1110 VOP3_Real_gfx6_gfx7<op>, VOP3_Real_gfx10<op>; 1111 1112multiclass VOP3be_Real_gfx6_gfx7_gfx10<bits<10> op> : 1113 VOP3be_Real_gfx6_gfx7<op>, VOP3be_Real_gfx10<op>; 1114 1115defm V_LSHL_B64 : VOP3_Real_gfx6_gfx7<0x161>; 1116defm V_LSHR_B64 : VOP3_Real_gfx6_gfx7<0x162>; 1117defm V_ASHR_I64 : VOP3_Real_gfx6_gfx7<0x163>; 1118defm V_MUL_LO_I32 : VOP3_Real_gfx6_gfx7<0x16b>; 1119 1120defm V_MAD_LEGACY_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x140>; 1121defm V_MAD_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x141>; 1122defm V_MAD_I32_I24 : VOP3_Real_gfx6_gfx7_gfx10<0x142>; 1123defm V_MAD_U32_U24 : VOP3_Real_gfx6_gfx7_gfx10<0x143>; 1124defm V_CUBEID_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x144>; 1125defm V_CUBESC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x145>; 1126defm V_CUBETC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x146>; 1127defm V_CUBEMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x147>; 1128defm V_BFE_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x148>; 1129defm V_BFE_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x149>; 1130defm V_BFI_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14a>; 1131defm V_FMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x14b>; 1132defm V_FMA_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x14c>; 1133defm V_LERP_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x14d>; 1134defm V_ALIGNBIT_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14e>; 1135defm V_ALIGNBYTE_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14f>; 1136defm V_MULLIT_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x150>; 1137defm V_MIN3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x151>; 1138defm V_MIN3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x152>; 1139defm V_MIN3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x153>; 1140defm V_MAX3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x154>; 1141defm V_MAX3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x155>; 1142defm V_MAX3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x156>; 1143defm V_MED3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x157>; 1144defm V_MED3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x158>; 1145defm V_MED3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x159>; 1146defm V_SAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15a>; 1147defm V_SAD_HI_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15b>; 1148defm V_SAD_U16 : VOP3_Real_gfx6_gfx7_gfx10<0x15c>; 1149defm V_SAD_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x15d>; 1150defm V_CVT_PK_U8_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15e>; 1151defm V_DIV_FIXUP_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15f>; 1152defm V_DIV_FIXUP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x160>; 1153defm V_ADD_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x164>; 1154defm V_MUL_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x165>; 1155defm V_MIN_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x166>; 1156defm V_MAX_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x167>; 1157defm V_LDEXP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x168>; 1158defm V_MUL_LO_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x169>; 1159defm V_MUL_HI_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x16a>; 1160defm V_MUL_HI_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16c>; 1161defm V_DIV_FMAS_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x16f>; 1162defm V_DIV_FMAS_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x170>; 1163defm V_MSAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x171>; 1164defm V_MQSAD_PK_U16_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x173>; 1165defm V_TRIG_PREOP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x174>; 1166defm V_DIV_SCALE_F32 : VOP3be_Real_gfx6_gfx7_gfx10<0x16d>; 1167defm V_DIV_SCALE_F64 : VOP3be_Real_gfx6_gfx7_gfx10<0x16e>; 1168 1169// NB: Same opcode as v_mad_legacy_f32 1170let DecoderNamespace = "GFX10_B" in 1171defm V_FMA_LEGACY_F32 : VOP3_Real_gfx10<0x140>; 1172 1173//===----------------------------------------------------------------------===// 1174// GFX8, GFX9 (VI). 1175//===----------------------------------------------------------------------===// 1176 1177let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in { 1178 1179multiclass VOP3_Real_vi<bits<10> op> { 1180 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1181 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 1182} 1183multiclass VOP3_Real_No_Suffix_vi<bits<10> op> { 1184 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 1185 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 1186} 1187 1188multiclass VOP3be_Real_vi<bits<10> op> { 1189 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1190 VOP3be_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 1191} 1192 1193multiclass VOP3OpSel_Real_gfx9<bits<10> op> { 1194 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1195 VOP3OpSel_gfx9 <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl>; 1196} 1197 1198multiclass VOP3OpSel_Real_gfx9_forced_opsel2<bits<10> op> { 1199 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1200 VOP3OpSel_gfx9 <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl> { 1201 let Inst{13} = src2_modifiers{2}; // op_sel(2) 1202 } 1203} 1204 1205multiclass VOP3Interp_Real_vi<bits<10> op> { 1206 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>, 1207 VOP3Interp_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>; 1208} 1209 1210} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" 1211 1212let AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" in { 1213 1214multiclass VOP3_F16_Real_vi<bits<10> op> { 1215 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, 1216 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>; 1217} 1218 1219multiclass VOP3Interp_F16_Real_vi<bits<10> op> { 1220 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, 1221 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>; 1222} 1223 1224} // End AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" 1225 1226let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in { 1227 1228multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { 1229 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>, 1230 VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> { 1231 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64"); 1232 let AsmString = AsmName # ps.AsmOperands; 1233 } 1234} 1235 1236multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> { 1237 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>, 1238 VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { 1239 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME#"_e64"); 1240 let AsmString = AsmName # ps.AsmOperands; 1241 } 1242} 1243 1244multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { 1245 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>, 1246 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> { 1247 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName); 1248 let AsmString = AsmName # ps.AsmOperands; 1249 } 1250} 1251 1252multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> { 1253 def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>, 1254 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME#"_e64").Pfl> { 1255 VOP_Pseudo ps = !cast<VOP_Pseudo>(NAME#"_e64"); 1256 let AsmString = AsmName # ps.AsmOperands; 1257 } 1258} 1259 1260} // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" 1261 1262defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>; 1263defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>; 1264 1265defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>; 1266defm V_MAD_F32 : VOP3_Real_vi <0x1c1>; 1267defm V_MAD_I32_I24 : VOP3_Real_vi <0x1c2>; 1268defm V_MAD_U32_U24 : VOP3_Real_vi <0x1c3>; 1269defm V_CUBEID_F32 : VOP3_Real_vi <0x1c4>; 1270defm V_CUBESC_F32 : VOP3_Real_vi <0x1c5>; 1271defm V_CUBETC_F32 : VOP3_Real_vi <0x1c6>; 1272defm V_CUBEMA_F32 : VOP3_Real_vi <0x1c7>; 1273defm V_BFE_U32 : VOP3_Real_vi <0x1c8>; 1274defm V_BFE_I32 : VOP3_Real_vi <0x1c9>; 1275defm V_BFI_B32 : VOP3_Real_vi <0x1ca>; 1276defm V_FMA_F32 : VOP3_Real_vi <0x1cb>; 1277defm V_FMA_F64 : VOP3_Real_vi <0x1cc>; 1278defm V_LERP_U8 : VOP3_Real_vi <0x1cd>; 1279defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>; 1280defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>; 1281defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>; 1282defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>; 1283defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>; 1284defm V_MAX3_F32 : VOP3_Real_vi <0x1d3>; 1285defm V_MAX3_I32 : VOP3_Real_vi <0x1d4>; 1286defm V_MAX3_U32 : VOP3_Real_vi <0x1d5>; 1287defm V_MED3_F32 : VOP3_Real_vi <0x1d6>; 1288defm V_MED3_I32 : VOP3_Real_vi <0x1d7>; 1289defm V_MED3_U32 : VOP3_Real_vi <0x1d8>; 1290defm V_SAD_U8 : VOP3_Real_vi <0x1d9>; 1291defm V_SAD_HI_U8 : VOP3_Real_vi <0x1da>; 1292defm V_SAD_U16 : VOP3_Real_vi <0x1db>; 1293defm V_SAD_U32 : VOP3_Real_vi <0x1dc>; 1294defm V_CVT_PK_U8_F32 : VOP3_Real_vi <0x1dd>; 1295defm V_DIV_FIXUP_F32 : VOP3_Real_vi <0x1de>; 1296defm V_DIV_FIXUP_F64 : VOP3_Real_vi <0x1df>; 1297defm V_DIV_SCALE_F32 : VOP3be_Real_vi <0x1e0>; 1298defm V_DIV_SCALE_F64 : VOP3be_Real_vi <0x1e1>; 1299defm V_DIV_FMAS_F32 : VOP3_Real_vi <0x1e2>; 1300defm V_DIV_FMAS_F64 : VOP3_Real_vi <0x1e3>; 1301defm V_MSAD_U8 : VOP3_Real_vi <0x1e4>; 1302defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>; 1303defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>; 1304defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>; 1305 1306defm V_PERM_B32 : VOP3_Real_vi <0x1ed>; 1307 1308defm V_MAD_F16 : VOP3_F16_Real_vi <0x1ea>; 1309defm V_MAD_U16 : VOP3_F16_Real_vi <0x1eb>; 1310defm V_MAD_I16 : VOP3_F16_Real_vi <0x1ec>; 1311defm V_FMA_F16 : VOP3_F16_Real_vi <0x1ee>; 1312defm V_DIV_FIXUP_F16 : VOP3_F16_Real_vi <0x1ef>; 1313defm V_INTERP_P2_F16 : VOP3Interp_F16_Real_vi <0x276>; 1314 1315let FPDPRounding = 1 in { 1316defm V_MAD_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16", "v_mad_legacy_f16">; 1317defm V_FMA_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16", "v_fma_legacy_f16">; 1318defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">; 1319defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16", "v_interp_p2_legacy_f16">; 1320} // End FPDPRounding = 1 1321 1322defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">; 1323defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">; 1324 1325defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">; 1326defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">; 1327defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">; 1328defm V_FMA_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">; 1329defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">; 1330defm V_INTERP_P2_F16_gfx9 : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2_f16">; 1331 1332defm V_ADD_I32 : VOP3_Real_vi <0x29c>; 1333defm V_SUB_I32 : VOP3_Real_vi <0x29d>; 1334 1335defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>; 1336defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>; 1337defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>; 1338 1339defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>; 1340defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>; 1341defm V_ADD_F64 : VOP3_Real_vi <0x280>; 1342defm V_MUL_F64 : VOP3_Real_vi <0x281>; 1343defm V_MIN_F64 : VOP3_Real_vi <0x282>; 1344defm V_MAX_F64 : VOP3_Real_vi <0x283>; 1345defm V_LDEXP_F64 : VOP3_Real_vi <0x284>; 1346defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>; 1347 1348// removed from VI as identical to V_MUL_LO_U32 1349let isAsmParserOnly = 1 in { 1350defm V_MUL_LO_I32 : VOP3_Real_vi <0x285>; 1351} 1352 1353defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>; 1354defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>; 1355 1356defm V_READLANE_B32 : VOP3_Real_No_Suffix_vi <0x289>; 1357defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_vi <0x28a>; 1358 1359defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>; 1360defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>; 1361defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>; 1362defm V_TRIG_PREOP_F64 : VOP3_Real_vi <0x292>; 1363 1364defm V_LSHL_ADD_U32 : VOP3_Real_vi <0x1fd>; 1365defm V_ADD_LSHL_U32 : VOP3_Real_vi <0x1fe>; 1366defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>; 1367defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>; 1368defm V_AND_OR_B32 : VOP3_Real_vi <0x201>; 1369defm V_OR3_B32 : VOP3_Real_vi <0x202>; 1370defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>; 1371 1372defm V_XAD_U32 : VOP3_Real_vi <0x1f3>; 1373 1374defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>; 1375defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>; 1376defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>; 1377 1378defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>; 1379defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>; 1380defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>; 1381 1382defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>; 1383defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>; 1384defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>; 1385 1386defm V_ADD_I16 : VOP3OpSel_Real_gfx9 <0x29e>; 1387defm V_SUB_I16 : VOP3OpSel_Real_gfx9 <0x29f>; 1388 1389defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>; 1390defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>; 1391 1392defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>; 1393defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>; 1394 1395defm V_LSHL_ADD_U64 : VOP3_Real_vi <0x208>; 1396 1397let OtherPredicates = [HasFP8Insts] in { 1398defm V_CVT_PK_FP8_F32 : VOP3OpSel_Real_gfx9 <0x2a2>; 1399defm V_CVT_PK_BF8_F32 : VOP3OpSel_Real_gfx9 <0x2a3>; 1400defm V_CVT_SR_FP8_F32 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x2a4>; 1401defm V_CVT_SR_BF8_F32 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x2a5>; 1402} 1403