xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/VOP3Instructions.td (revision 32100375a661c1e16588ddfa7b90ca8d26cb9786) 
1//===-- VOP3Instructions.td - Vector Instruction Defintions ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// VOP3 Classes
11//===----------------------------------------------------------------------===//
12
13class getVOP3ModPat<VOPProfile P, SDPatternOperator node> {
14  dag src0 = !if(P.HasOMod,
15    (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
16    (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp));
17
18  list<dag> ret3 = [(set P.DstVT:$vdst,
19    (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
20          (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
21          (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))];
22
23  list<dag> ret2 = [(set P.DstVT:$vdst,
24    (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
25          (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))];
26
27  list<dag> ret1 = [(set P.DstVT:$vdst,
28    (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))];
29
30  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
31                  !if(!eq(P.NumSrcArgs, 2), ret2,
32                  ret1));
33}
34
35class getVOP3PModPat<VOPProfile P, SDPatternOperator node> {
36  list<dag> ret3 = [(set P.DstVT:$vdst,
37    (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
38                                    (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))),
39          (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers)),
40          (P.Src2VT (VOP3PMods P.Src2VT:$src2, i32:$src2_modifiers))))];
41
42  list<dag> ret2 = [(set P.DstVT:$vdst,
43    (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
44                          (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))),
45          (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers))))];
46
47  list<dag> ret1 = [(set P.DstVT:$vdst,
48    (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
49
50  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
51                  !if(!eq(P.NumSrcArgs, 2), ret2,
52                  ret1));
53}
54
55class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> {
56  list<dag> ret3 = [(set P.DstVT:$vdst,
57    (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
58                                    (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))),
59          (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)),
60          (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))];
61
62  list<dag> ret2 = [(set P.DstVT:$vdst,
63    (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
64                          (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))),
65          (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))];
66
67  list<dag> ret1 = [(set P.DstVT:$vdst,
68    (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
69
70  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
71                  !if(!eq(P.NumSrcArgs, 2), ret2,
72                  ret1));
73}
74
75class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> {
76  list<dag> ret3 = [(set P.DstVT:$vdst,
77    (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
78                                    (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
79          (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)),
80          (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))];
81
82  list<dag> ret2 = [(set P.DstVT:$vdst,
83    (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
84                          (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
85          (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))];
86
87  list<dag> ret1 = [(set P.DstVT:$vdst,
88    (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
89
90  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
91                  !if(!eq(P.NumSrcArgs, 2), ret2,
92                  ret1));
93}
94
95class getVOP3Pat<VOPProfile P, SDPatternOperator node> {
96  list<dag> ret3 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))];
97  list<dag> ret2 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1))];
98  list<dag> ret1 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0))];
99  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
100                  !if(!eq(P.NumSrcArgs, 2), ret2,
101                  ret1));
102}
103
104class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> {
105  list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))];
106  list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))];
107  list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))];
108  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
109                  !if(!eq(P.NumSrcArgs, 2), ret2,
110                  ret1));
111}
112
113class getVOP3MAIPat<VOPProfile P, SDPatternOperator node> {
114  list<dag> ret = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2,
115                                        timm:$cbsz, timm:$abid, timm:$blgp))];
116}
117
118class VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit VOP3Only = 0> :
119  VOP3_Pseudo<OpName, P,
120    !if(P.HasOpSel,
121        !if(P.HasModifiers,
122            getVOP3OpSelModPat<P, node>.ret,
123            getVOP3OpSelPat<P, node>.ret),
124        !if(P.HasModifiers,
125            getVOP3ModPat<P, node>.ret,
126            !if(P.HasIntClamp,
127                getVOP3ClampPat<P, node>.ret,
128                !if (P.IsMAI,
129                    getVOP3MAIPat<P, node>.ret,
130                    getVOP3Pat<P, node>.ret)))),
131    VOP3Only, 0, P.HasOpSel> {
132
133  let IntClamp = P.HasIntClamp;
134  let AsmMatchConverter =
135    !if(P.HasOpSel,
136        "cvtVOP3OpSel",
137        !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),
138            "cvtVOP3",
139            ""));
140}
141
142// Special case for v_div_fmas_{f32|f64}, since it seems to be the
143// only VOP instruction that implicitly reads VCC.
144let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in {
145def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> {
146  let Outs64 = (outs DstRC.RegClass:$vdst);
147}
148def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> {
149  let Outs64 = (outs DstRC.RegClass:$vdst);
150}
151}
152
153class VOP3Features<bit Clamp, bit OpSel, bit Packed, bit MAI> {
154  bit HasClamp = Clamp;
155  bit HasOpSel = OpSel;
156  bit IsPacked = Packed;
157  bit IsMAI = MAI;
158}
159
160def VOP3_REGULAR : VOP3Features<0, 0, 0, 0>;
161def VOP3_CLAMP   : VOP3Features<1, 0, 0, 0>;
162def VOP3_OPSEL   : VOP3Features<1, 1, 0, 0>;
163def VOP3_PACKED  : VOP3Features<1, 1, 1, 0>;
164def VOP3_MAI     : VOP3Features<0, 0, 0, 1>;
165
166class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProfile<P.ArgVT> {
167
168  let HasClamp = !if(Features.HasClamp, 1, P.HasClamp);
169  let HasOpSel = !if(Features.HasOpSel, 1, P.HasOpSel);
170  let IsMAI    = !if(Features.IsMAI,    1, P.IsMAI);
171  let IsPacked = !if(Features.IsPacked, 1, P.IsPacked);
172
173  let HasModifiers = !if(Features.IsPacked, !if(Features.IsMAI, 0, 1), P.HasModifiers);
174
175  // FIXME: Hack to stop printing _e64
176  let Outs64 = (outs DstRC.RegClass:$vdst);
177  let Asm64 =
178    " " # !if(Features.HasOpSel,
179              getAsmVOP3OpSel<NumSrcArgs,
180                              HasIntClamp,
181                              HasSrc0FloatMods,
182                              HasSrc1FloatMods,
183                              HasSrc2FloatMods>.ret,
184              !if(Features.HasClamp,
185                  getAsm64<HasDst, NumSrcArgs, HasIntClamp,
186                           HasModifiers, HasOMod, DstVT>.ret,
187                  P.Asm64));
188  let NeedPatGen = P.NeedPatGen;
189}
190
191class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> {
192  // v_div_scale_{f32|f64} do not support input modifiers.
193  let HasModifiers = 0;
194  let HasClamp = 0;
195  let HasOMod = 0;
196  let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
197  let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
198}
199
200def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> {
201  // FIXME: Hack to stop printing _e64
202  let DstRC = RegisterOperand<VGPR_32>;
203}
204
205def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> {
206  // FIXME: Hack to stop printing _e64
207  let DstRC = RegisterOperand<VReg_64>;
208}
209
210def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> {
211  let HasClamp = 1;
212
213  // FIXME: Hack to stop printing _e64
214  let DstRC = RegisterOperand<VReg_64>;
215
216  let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
217  let Asm64 = " $vdst, $sdst, $src0, $src1, $src2$clamp";
218}
219
220//===----------------------------------------------------------------------===//
221// VOP3 INTERP
222//===----------------------------------------------------------------------===//
223
224class VOP3Interp<string OpName, VOPProfile P, list<dag> pattern = []> :
225                 VOP3_Pseudo<OpName, P, pattern> {
226  let AsmMatchConverter = "cvtVOP3Interp";
227}
228
229def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
230  let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
231                   Attr:$attr, AttrChan:$attrchan,
232                   clampmod:$clamp, omod:$omod);
233
234  let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
235}
236
237def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> {
238  let Ins64 = (ins InterpSlot:$src0,
239                   Attr:$attr, AttrChan:$attrchan,
240                   clampmod:$clamp, omod:$omod);
241
242  let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
243
244  let HasClamp = 1;
245}
246
247class getInterp16Asm <bit HasSrc2, bit HasOMod> {
248  string src2 = !if(HasSrc2, ", $src2_modifiers", "");
249  string omod = !if(HasOMod, "$omod", "");
250  string ret =
251    " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod;
252}
253
254class getInterp16Ins <bit HasSrc2, bit HasOMod,
255                      Operand Src0Mod, Operand Src2Mod> {
256  dag ret = !if(HasSrc2,
257                !if(HasOMod,
258                    (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
259                         Attr:$attr, AttrChan:$attrchan,
260                         Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
261                         highmod:$high, clampmod0:$clamp, omod0:$omod),
262                    (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
263                         Attr:$attr, AttrChan:$attrchan,
264                         Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
265                         highmod:$high, clampmod0:$clamp)
266                ),
267                (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
268                     Attr:$attr, AttrChan:$attrchan,
269                     highmod:$high, clampmod0:$clamp, omod0:$omod)
270            );
271}
272
273class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
274
275  let HasOMod = !if(!eq(DstVT.Value, f16.Value), 0, 1);
276  let HasHigh = 1;
277
278  let Outs64 = (outs VGPR_32:$vdst);
279  let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret;
280  let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret;
281}
282
283//===----------------------------------------------------------------------===//
284// VOP3 Instructions
285//===----------------------------------------------------------------------===//
286
287let isCommutable = 1 in {
288
289def V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
290def V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>;
291def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
292def V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
293def V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fma>;
294def V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>;
295
296let SchedRW = [WriteDoubleAdd] in {
297let FPDPRounding = 1 in {
298def V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, fma>;
299def V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, fadd, 1>;
300def V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul, 1>;
301} // End FPDPRounding = 1
302def V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum_like, 1>;
303def V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum_like, 1>;
304} // End SchedRW = [WriteDoubleAdd]
305
306let SchedRW = [WriteQuarterRate32] in {
307def V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile<VOP_I32_I32_I32>, mul>;
308def V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>;
309def V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile<VOP_I32_I32_I32>>;
310def V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile<VOP_I32_I32_I32>, mulhs>;
311} // End SchedRW = [WriteQuarterRate32]
312
313let Uses = [VCC, EXEC] in {
314// v_div_fmas_f32:
315//   result = src0 * src1 + src2
316//   if (vcc)
317//     result *= 2^32
318//
319def V_DIV_FMAS_F32 : VOP3_Pseudo <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC, []> {
320  let SchedRW = [WriteFloatFMA];
321}
322// v_div_fmas_f64:
323//   result = src0 * src1 + src2
324//   if (vcc)
325//     result *= 2^64
326//
327def V_DIV_FMAS_F64 : VOP3_Pseudo <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC, []> {
328  let SchedRW = [WriteDouble];
329  let FPDPRounding = 1;
330}
331} // End Uses = [VCC, EXEC]
332
333} // End isCommutable = 1
334
335def V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>;
336def V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>;
337def V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>;
338def V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>;
339def V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>;
340def V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>;
341def V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>;
342def V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbit>;
343def V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>;
344def V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>;
345def V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>;
346def V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>;
347def V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>;
348def V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>;
349def V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>;
350def V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>;
351def V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>;
352def V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>;
353def V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
354def V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
355def V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
356def V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
357def V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>;
358def V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>;
359
360let SchedRW = [WriteDoubleAdd], FPDPRounding = 1 in {
361def V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>;
362def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>;
363} // End SchedRW = [WriteDoubleAdd], FPDPRounding = 1
364
365def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> {
366  let SchedRW = [WriteFloatFMA, WriteSALU];
367  let AsmMatchConverter = "";
368}
369
370// Double precision division pre-scale.
371def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> {
372  let SchedRW = [WriteDouble, WriteSALU];
373  let AsmMatchConverter = "";
374  let FPDPRounding = 1;
375}
376
377def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
378
379let Constraints = "@earlyclobber $vdst" in {
380def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>;
381} // End Constraints = "@earlyclobber $vdst"
382
383def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUtrig_preop> {
384  let SchedRW = [WriteDouble];
385}
386
387let SchedRW = [Write64Bit] in {
388let SubtargetPredicate = isGFX6GFX7GFX10 in {
389def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>, shl>;
390def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>, srl>;
391def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>, sra>;
392def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
393} // End SubtargetPredicate = isGFX6GFX7GFX10
394
395let SubtargetPredicate = isGFX8Plus in {
396def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshl_rev>;
397def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshr_rev>;
398def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, ashr_rev>;
399} // End SubtargetPredicate = isGFX8Plus
400} // End SchedRW = [Write64Bit]
401
402
403let SchedRW = [Write32Bit] in {
404let SubtargetPredicate = isGFX8Plus in {
405def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUperm>;
406} // End SubtargetPredicate = isGFX8Plus
407} // End SchedRW = [Write32Bit]
408
409let SubtargetPredicate = isGFX7Plus in {
410
411let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in {
412def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>;
413def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32, VOP3_CLAMP>>;
414} // End Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32]
415
416let isCommutable = 1 in {
417let SchedRW = [WriteQuarterRate32, WriteSALU] in {
418def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>;
419def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>;
420} // End SchedRW = [WriteDouble, WriteSALU]
421} // End isCommutable = 1
422
423} // End SubtargetPredicate = isGFX7Plus
424
425
426def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup> {
427  let Predicates = [Has16BitInsts, isGFX8Only];
428  let FPDPRounding = 1;
429}
430def V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9",
431                                      VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUdiv_fixup> {
432  let renamedInGFX9 = 1;
433  let Predicates = [Has16BitInsts, isGFX9Plus];
434  let FPDPRounding = 1;
435}
436
437def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma> {
438  let Predicates = [Has16BitInsts, isGFX8Only];
439  let FPDPRounding = 1;
440}
441def V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, fma> {
442  let renamedInGFX9 = 1;
443  let Predicates = [Has16BitInsts, isGFX9Plus];
444  let FPDPRounding = 1;
445}
446
447let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in {
448
449let renamedInGFX9 = 1 in {
450def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
451def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
452let FPDPRounding = 1 in {
453def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
454let Uses = [M0, EXEC] in {
455// For some reason the intrinsic operands are in a different order
456// from the instruction operands.
457def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>,
458       [(set f16:$vdst,
459         (int_amdgcn_interp_p2_f16 (VOP3Mods f32:$src2, i32:$src2_modifiers),
460                                   (VOP3Mods f32:$src0, i32:$src0_modifiers),
461                                   (i32 timm:$attrchan),
462                                   (i32 timm:$attr),
463                                   (i1 timm:$high),
464                                   M0))]>;
465} // End Uses = [M0, EXEC]
466} // End FPDPRounding = 1
467} // End renamedInGFX9 = 1
468
469let SubtargetPredicate = isGFX9Only in {
470def V_MAD_F16_gfx9   : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>> {
471  let FPDPRounding = 1;
472}
473} // End SubtargetPredicate = isGFX9Only
474
475let SubtargetPredicate = isGFX9Plus in {
476def V_MAD_U16_gfx9   : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
477def V_MAD_I16_gfx9   : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
478def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>;
479} // End SubtargetPredicate = isGFX9Plus
480
481let Uses = [M0, EXEC], FPDPRounding = 1 in {
482def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>,
483       [(set f32:$vdst, (AMDGPUinterp_p1ll_f16 f32:$src0, (i32 timm:$attrchan),
484                                                          (i32 timm:$attr),
485                                                          (i32 timm:$src0_modifiers),
486                                                          (i1 timm:$high),
487                                                          (i1 timm:$clamp),
488                                                          (i32 timm:$omod)))]>;
489def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>,
490       [(set f32:$vdst, (AMDGPUinterp_p1lv_f16 f32:$src0, (i32 timm:$attrchan),
491                                                          (i32 timm:$attr),
492                                                          (i32 timm:$src0_modifiers),
493                                                          (f32 VRegSrc_32:$src2),
494                                                          (i32 timm:$src2_modifiers),
495                                                          (i1 timm:$high),
496                                                          (i1 timm:$clamp),
497                                                          (i32 timm:$omod)))]>;
498} // End Uses = [M0, EXEC], FPDPRounding = 1
499
500} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1
501
502let SubtargetPredicate = isGFX8Plus, Uses = [M0, EXEC] in {
503def V_INTERP_P1_F32_e64  : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
504def V_INTERP_P2_F32_e64  : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
505def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
506} // End SubtargetPredicate = isGFX8Plus, Uses = [M0, EXEC]
507
508let Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] in {
509
510multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2,
511                             Instruction inst, SDPatternOperator op3> {
512def : GCNPat <
513  (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
514  (inst i16:$src0, i16:$src1, i16:$src2, (i1 0))
515>;
516
517}
518
519defm: Ternary_i16_Pats<mul, add, V_MAD_U16, zext>;
520defm: Ternary_i16_Pats<mul, add, V_MAD_I16, sext>;
521
522} // End Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9]
523
524let Predicates = [Has16BitInsts, isGFX10Plus] in {
525
526multiclass Ternary_i16_Pats_gfx9<SDPatternOperator op1, SDPatternOperator op2,
527                                 Instruction inst, SDPatternOperator op3> {
528def : GCNPat <
529  (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
530  (inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1, SRCMODS.NONE, $src2, DSTCLAMP.NONE)
531>;
532
533}
534
535defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_U16_gfx9, zext>;
536defm: Ternary_i16_Pats_gfx9<mul, add, V_MAD_I16_gfx9, sext>;
537
538} // End Predicates = [Has16BitInsts, isGFX10Plus]
539
540class ThreeOpFrag<SDPatternOperator op1, SDPatternOperator op2> : PatFrag<
541  (ops node:$x, node:$y, node:$z),
542  // When the inner operation is used multiple times, selecting 3-op
543  // instructions may still be beneficial -- if the other users can be
544  // combined similarly. Let's be conservative for now.
545  (op2 (HasOneUseBinOp<op1> node:$x, node:$y), node:$z),
546  [{
547    // Only use VALU ops when the result is divergent.
548    if (!N->isDivergent())
549      return false;
550
551    // Check constant bus limitations.
552    //
553    // Note: Use !isDivergent as a conservative proxy for whether the value
554    //       is in an SGPR (uniform values can end up in VGPRs as well).
555    unsigned ConstantBusUses = 0;
556    for (unsigned i = 0; i < 3; ++i) {
557      if (!Operands[i]->isDivergent() &&
558          !isInlineImmediate(Operands[i].getNode())) {
559        ConstantBusUses++;
560        // This uses AMDGPU::V_ADD3_U32, but all three operand instructions
561        // have the same constant bus limit.
562        if (ConstantBusUses > Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32))
563          return false;
564      }
565    }
566
567    return true;
568  }]
569> {
570  let PredicateCodeUsesOperands = 1;
571}
572
573let SubtargetPredicate = isGFX9Plus in {
574def V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
575def V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
576def V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
577def V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
578def V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
579def V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
580def V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
581
582def V_XAD_U32 : VOP3Inst <"v_xad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
583
584def V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmed3>;
585def V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmed3>;
586def V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumed3>;
587
588def V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmin3>;
589def V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmin3>;
590def V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumin3>;
591
592def V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmax3>;
593def V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmax3>;
594def V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumax3>;
595
596def V_ADD_I16 : VOP3Inst <"v_add_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>;
597def V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>;
598
599def V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>;
600def V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>;
601
602def V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
603def V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
604
605def V_ADD_I32_gfx9 : VOP3Inst <"v_add_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>;
606def V_SUB_I32_gfx9 : VOP3Inst <"v_sub_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>;
607
608
609class ThreeOp_i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst> : GCNPat <
610  // This matches (op2 (op1 i32:$src0, i32:$src1), i32:$src2) with conditions.
611  (ThreeOpFrag<op1, op2> i32:$src0, i32:$src1, i32:$src2),
612  (inst i32:$src0, i32:$src1, i32:$src2)
613>;
614
615def : ThreeOp_i32_Pats<shl, add, V_LSHL_ADD_U32>;
616def : ThreeOp_i32_Pats<add, shl, V_ADD_LSHL_U32>;
617def : ThreeOp_i32_Pats<add, add, V_ADD3_U32>;
618def : ThreeOp_i32_Pats<shl, or, V_LSHL_OR_B32>;
619def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32>;
620def : ThreeOp_i32_Pats<or, or, V_OR3_B32>;
621def : ThreeOp_i32_Pats<xor, add, V_XAD_U32>;
622
623} // End SubtargetPredicate = isGFX9Plus
624
625def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3_OPSEL> {
626  let Src0RC64 = VRegSrc_32;
627  let Src1RC64 = SCSrc_b32;
628  let Src2RC64 = SCSrc_b32;
629  let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0,
630                          IntOpSelMods:$src1_modifiers, SCSrc_b32:$src1,
631                          IntOpSelMods:$src2_modifiers, SCSrc_b32:$src2,
632                          VGPR_32:$vdst_in, op_sel:$op_sel);
633  let HasClamp = 0;
634  let HasOMod = 0;
635}
636
637let SubtargetPredicate = isGFX10Plus in {
638  def V_XOR3_B32 : VOP3Inst <"v_xor3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
639  def : ThreeOp_i32_Pats<xor, xor, V_XOR3_B32>;
640
641  let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in {
642    def V_PERMLANE16_B32 : VOP3Inst <"v_permlane16_b32", VOP3_PERMLANE_Profile>;
643    def V_PERMLANEX16_B32 : VOP3Inst <"v_permlanex16_b32", VOP3_PERMLANE_Profile>;
644  } // End $vdst = $vdst_in, DisableEncoding $vdst_in
645
646  def : GCNPat<
647    (int_amdgcn_permlane16 i32:$vdst_in, i32:$src0, i32:$src1, i32:$src2, timm:$fi, timm:$bc),
648    (V_PERMLANE16_B32 (as_i1imm $fi), $src0, (as_i1imm $bc), $src1, 0, $src2, $vdst_in)
649  >;
650  def : GCNPat<
651    (int_amdgcn_permlanex16 i32:$vdst_in, i32:$src0, i32:$src1, i32:$src2, timm:$fi, timm:$bc),
652    (V_PERMLANEX16_B32 (as_i1imm $fi), $src0, (as_i1imm $bc), $src1, 0, $src2, $vdst_in)
653  >;
654} // End SubtargetPredicate = isGFX10Plus
655
656//===----------------------------------------------------------------------===//
657// Integer Clamp Patterns
658//===----------------------------------------------------------------------===//
659
660class getClampPat<VOPProfile P, SDPatternOperator node> {
661  dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
662  dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
663  dag ret1 = (P.DstVT (node P.Src0VT:$src0));
664  dag ret = !if(!eq(P.NumSrcArgs, 3), ret3,
665            !if(!eq(P.NumSrcArgs, 2), ret2,
666            ret1));
667}
668
669class getClampRes<VOPProfile P, Instruction inst> {
670  dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0));
671  dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0));
672  dag ret1 = (inst P.Src0VT:$src0, (i1 0));
673  dag ret = !if(!eq(P.NumSrcArgs, 3), ret3,
674            !if(!eq(P.NumSrcArgs, 2), ret2,
675            ret1));
676}
677
678class IntClampPat<VOP3Inst inst, SDPatternOperator node> : GCNPat<
679  getClampPat<inst.Pfl, node>.ret,
680  getClampRes<inst.Pfl, inst>.ret
681>;
682
683def : IntClampPat<V_MAD_I32_I24, AMDGPUmad_i24>;
684def : IntClampPat<V_MAD_U32_U24, AMDGPUmad_u24>;
685
686def : IntClampPat<V_SAD_U8, int_amdgcn_sad_u8>;
687def : IntClampPat<V_SAD_HI_U8, int_amdgcn_sad_hi_u8>;
688def : IntClampPat<V_SAD_U16, int_amdgcn_sad_u16>;
689
690def : IntClampPat<V_MSAD_U8, int_amdgcn_msad_u8>;
691def : IntClampPat<V_MQSAD_PK_U16_U8, int_amdgcn_mqsad_pk_u16_u8>;
692
693def : IntClampPat<V_QSAD_PK_U16_U8, int_amdgcn_qsad_pk_u16_u8>;
694def : IntClampPat<V_MQSAD_U32_U8, int_amdgcn_mqsad_u32_u8>;
695
696
697//===----------------------------------------------------------------------===//
698// Target-specific instruction encodings.
699//===----------------------------------------------------------------------===//
700
701//===----------------------------------------------------------------------===//
702// GFX10.
703//===----------------------------------------------------------------------===//
704
705let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
706  multiclass VOP3_Real_gfx10<bits<10> op> {
707    def _gfx10 :
708      VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX10>,
709      VOP3e_gfx10<op, !cast<VOP_Pseudo>(NAME).Pfl>;
710  }
711  multiclass VOP3_Real_gfx10_with_name<bits<10> op, string opName,
712                                       string asmName> {
713    def _gfx10 :
714      VOP3_Real<!cast<VOP3_Pseudo>(opName), SIEncodingFamily.GFX10>,
715      VOP3e_gfx10<op, !cast<VOP3_Pseudo>(opName).Pfl> {
716        VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName);
717        let AsmString = asmName # ps.AsmOperands;
718      }
719  }
720  multiclass VOP3be_Real_gfx10<bits<10> op> {
721    def _gfx10 :
722      VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>,
723      VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>;
724  }
725  multiclass VOP3Interp_Real_gfx10<bits<10> op> {
726    def _gfx10 :
727      VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>,
728      VOP3Interp_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>;
729  }
730  multiclass VOP3OpSel_Real_gfx10<bits<10> op> {
731    def _gfx10 :
732      VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>,
733      VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(NAME).Pfl>;
734  }
735  multiclass VOP3OpSel_Real_gfx10_with_name<bits<10> op, string opName,
736                                            string asmName> {
737    def _gfx10 :
738      VOP3_Real<!cast<VOP3_Pseudo>(opName), SIEncodingFamily.GFX10>,
739      VOP3OpSel_gfx10<op, !cast<VOP3_Pseudo>(opName).Pfl> {
740        VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName);
741        let AsmString = asmName # ps.AsmOperands;
742      }
743  }
744} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
745
746defm V_READLANE_B32  : VOP3_Real_gfx10<0x360>;
747
748let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) in {
749  defm V_WRITELANE_B32 : VOP3_Real_gfx10<0x361>;
750} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in)
751
752defm V_XOR3_B32           : VOP3_Real_gfx10<0x178>;
753defm V_LSHLREV_B64        : VOP3_Real_gfx10<0x2ff>;
754defm V_LSHRREV_B64        : VOP3_Real_gfx10<0x300>;
755defm V_ASHRREV_I64        : VOP3_Real_gfx10<0x301>;
756defm V_PERM_B32           : VOP3_Real_gfx10<0x344>;
757defm V_XAD_U32            : VOP3_Real_gfx10<0x345>;
758defm V_LSHL_ADD_U32       : VOP3_Real_gfx10<0x346>;
759defm V_ADD_LSHL_U32       : VOP3_Real_gfx10<0x347>;
760defm V_ADD3_U32           : VOP3_Real_gfx10<0x36d>;
761defm V_LSHL_OR_B32        : VOP3_Real_gfx10<0x36f>;
762defm V_AND_OR_B32         : VOP3_Real_gfx10<0x371>;
763defm V_OR3_B32            : VOP3_Real_gfx10<0x372>;
764
765// TODO-GFX10: add MC tests for v_add/sub_nc_i16
766defm V_ADD_NC_I16 :
767  VOP3OpSel_Real_gfx10_with_name<0x30d, "V_ADD_I16", "v_add_nc_i16">;
768defm V_SUB_NC_I16 :
769  VOP3OpSel_Real_gfx10_with_name<0x30e, "V_SUB_I16", "v_sub_nc_i16">;
770defm V_SUB_NC_I32 :
771  VOP3_Real_gfx10_with_name<0x376, "V_SUB_I32_gfx9", "v_sub_nc_i32">;
772defm V_ADD_NC_I32 :
773  VOP3_Real_gfx10_with_name<0x37f, "V_ADD_I32_gfx9", "v_add_nc_i32">;
774
775defm V_INTERP_P1_F32_e64  : VOP3Interp_Real_gfx10<0x200>;
776defm V_INTERP_P2_F32_e64  : VOP3Interp_Real_gfx10<0x201>;
777defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_gfx10<0x202>;
778
779defm V_INTERP_P1LL_F16    : VOP3Interp_Real_gfx10<0x342>;
780defm V_INTERP_P1LV_F16    : VOP3Interp_Real_gfx10<0x343>;
781defm V_INTERP_P2_F16      : VOP3Interp_Real_gfx10<0x35a>;
782
783defm V_PACK_B32_F16       : VOP3OpSel_Real_gfx10<0x311>;
784defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx10<0x312>;
785defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx10<0x313>;
786
787defm V_MIN3_F16           : VOP3OpSel_Real_gfx10<0x351>;
788defm V_MIN3_I16           : VOP3OpSel_Real_gfx10<0x352>;
789defm V_MIN3_U16           : VOP3OpSel_Real_gfx10<0x353>;
790defm V_MAX3_F16           : VOP3OpSel_Real_gfx10<0x354>;
791defm V_MAX3_I16           : VOP3OpSel_Real_gfx10<0x355>;
792defm V_MAX3_U16           : VOP3OpSel_Real_gfx10<0x356>;
793defm V_MED3_F16           : VOP3OpSel_Real_gfx10<0x357>;
794defm V_MED3_I16           : VOP3OpSel_Real_gfx10<0x358>;
795defm V_MED3_U16           : VOP3OpSel_Real_gfx10<0x359>;
796defm V_MAD_U32_U16        : VOP3OpSel_Real_gfx10<0x373>;
797defm V_MAD_I32_I16        : VOP3OpSel_Real_gfx10<0x375>;
798
799defm V_MAD_U16 :
800  VOP3OpSel_Real_gfx10_with_name<0x340, "V_MAD_U16_gfx9", "v_mad_u16">;
801defm V_FMA_F16 :
802  VOP3OpSel_Real_gfx10_with_name<0x34b, "V_FMA_F16_gfx9", "v_fma_f16">;
803defm V_MAD_I16 :
804  VOP3OpSel_Real_gfx10_with_name<0x35e, "V_MAD_I16_gfx9", "v_mad_i16">;
805defm V_DIV_FIXUP_F16 :
806  VOP3OpSel_Real_gfx10_with_name<0x35f, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">;
807
808// FIXME-GFX10-OPSEL: Need to add "selective" opsel support to some of these
809// (they do not support SDWA or DPP).
810defm V_ADD_NC_U16      : VOP3_Real_gfx10_with_name<0x303, "V_ADD_U16_e64", "v_add_nc_u16">;
811defm V_SUB_NC_U16      : VOP3_Real_gfx10_with_name<0x304, "V_SUB_U16_e64", "v_sub_nc_u16">;
812defm V_MUL_LO_U16      : VOP3_Real_gfx10_with_name<0x305, "V_MUL_LO_U16_e64", "v_mul_lo_u16">;
813defm V_LSHRREV_B16     : VOP3_Real_gfx10_with_name<0x307, "V_LSHRREV_B16_e64", "v_lshrrev_b16">;
814defm V_ASHRREV_I16     : VOP3_Real_gfx10_with_name<0x308, "V_ASHRREV_I16_e64", "v_ashrrev_i16">;
815defm V_MAX_U16         : VOP3_Real_gfx10_with_name<0x309, "V_MAX_U16_e64", "v_max_u16">;
816defm V_MAX_I16         : VOP3_Real_gfx10_with_name<0x30a, "V_MAX_I16_e64", "v_max_i16">;
817defm V_MIN_U16         : VOP3_Real_gfx10_with_name<0x30b, "V_MIN_U16_e64", "v_min_u16">;
818defm V_MIN_I16         : VOP3_Real_gfx10_with_name<0x30c, "V_MIN_I16_e64", "v_min_i16">;
819defm V_LSHLREV_B16     : VOP3_Real_gfx10_with_name<0x314, "V_LSHLREV_B16_e64", "v_lshlrev_b16">;
820defm V_PERMLANE16_B32  : VOP3OpSel_Real_gfx10<0x377>;
821defm V_PERMLANEX16_B32 : VOP3OpSel_Real_gfx10<0x378>;
822
823//===----------------------------------------------------------------------===//
824// GFX7, GFX10.
825//===----------------------------------------------------------------------===//
826
827let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {
828  multiclass VOP3_Real_gfx7<bits<10> op> {
829    def _gfx7 :
830      VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
831      VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME).Pfl>;
832  }
833  multiclass VOP3be_Real_gfx7<bits<10> op> {
834    def _gfx7 :
835      VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
836      VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME).Pfl>;
837  }
838} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7"
839
840multiclass VOP3_Real_gfx7_gfx10<bits<10> op> :
841  VOP3_Real_gfx7<op>, VOP3_Real_gfx10<op>;
842
843multiclass VOP3be_Real_gfx7_gfx10<bits<10> op> :
844  VOP3be_Real_gfx7<op>, VOP3be_Real_gfx10<op>;
845
846defm V_QSAD_PK_U16_U8   : VOP3_Real_gfx7_gfx10<0x172>;
847defm V_MQSAD_U32_U8     : VOP3_Real_gfx7_gfx10<0x175>;
848defm V_MAD_U64_U32      : VOP3be_Real_gfx7_gfx10<0x176>;
849defm V_MAD_I64_I32      : VOP3be_Real_gfx7_gfx10<0x177>;
850
851//===----------------------------------------------------------------------===//
852// GFX6, GFX7, GFX10.
853//===----------------------------------------------------------------------===//
854
855let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
856  multiclass VOP3_Real_gfx6_gfx7<bits<10> op> {
857    def _gfx6_gfx7 :
858      VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
859      VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME).Pfl>;
860  }
861  multiclass VOP3be_Real_gfx6_gfx7<bits<10> op> {
862    def _gfx6_gfx7 :
863      VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
864      VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME).Pfl>;
865  }
866} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
867
868multiclass VOP3_Real_gfx6_gfx7_gfx10<bits<10> op> :
869  VOP3_Real_gfx6_gfx7<op>, VOP3_Real_gfx10<op>;
870
871multiclass VOP3be_Real_gfx6_gfx7_gfx10<bits<10> op> :
872  VOP3be_Real_gfx6_gfx7<op>, VOP3be_Real_gfx10<op>;
873
874defm V_LSHL_B64        : VOP3_Real_gfx6_gfx7<0x161>;
875defm V_LSHR_B64        : VOP3_Real_gfx6_gfx7<0x162>;
876defm V_ASHR_I64        : VOP3_Real_gfx6_gfx7<0x163>;
877
878defm V_MAD_LEGACY_F32  : VOP3_Real_gfx6_gfx7_gfx10<0x140>;
879defm V_MAD_F32         : VOP3_Real_gfx6_gfx7_gfx10<0x141>;
880defm V_MAD_I32_I24     : VOP3_Real_gfx6_gfx7_gfx10<0x142>;
881defm V_MAD_U32_U24     : VOP3_Real_gfx6_gfx7_gfx10<0x143>;
882defm V_CUBEID_F32      : VOP3_Real_gfx6_gfx7_gfx10<0x144>;
883defm V_CUBESC_F32      : VOP3_Real_gfx6_gfx7_gfx10<0x145>;
884defm V_CUBETC_F32      : VOP3_Real_gfx6_gfx7_gfx10<0x146>;
885defm V_CUBEMA_F32      : VOP3_Real_gfx6_gfx7_gfx10<0x147>;
886defm V_BFE_U32         : VOP3_Real_gfx6_gfx7_gfx10<0x148>;
887defm V_BFE_I32         : VOP3_Real_gfx6_gfx7_gfx10<0x149>;
888defm V_BFI_B32         : VOP3_Real_gfx6_gfx7_gfx10<0x14a>;
889defm V_FMA_F32         : VOP3_Real_gfx6_gfx7_gfx10<0x14b>;
890defm V_FMA_F64         : VOP3_Real_gfx6_gfx7_gfx10<0x14c>;
891defm V_LERP_U8         : VOP3_Real_gfx6_gfx7_gfx10<0x14d>;
892defm V_ALIGNBIT_B32    : VOP3_Real_gfx6_gfx7_gfx10<0x14e>;
893defm V_ALIGNBYTE_B32   : VOP3_Real_gfx6_gfx7_gfx10<0x14f>;
894defm V_MULLIT_F32      : VOP3_Real_gfx6_gfx7_gfx10<0x150>;
895defm V_MIN3_F32        : VOP3_Real_gfx6_gfx7_gfx10<0x151>;
896defm V_MIN3_I32        : VOP3_Real_gfx6_gfx7_gfx10<0x152>;
897defm V_MIN3_U32        : VOP3_Real_gfx6_gfx7_gfx10<0x153>;
898defm V_MAX3_F32        : VOP3_Real_gfx6_gfx7_gfx10<0x154>;
899defm V_MAX3_I32        : VOP3_Real_gfx6_gfx7_gfx10<0x155>;
900defm V_MAX3_U32        : VOP3_Real_gfx6_gfx7_gfx10<0x156>;
901defm V_MED3_F32        : VOP3_Real_gfx6_gfx7_gfx10<0x157>;
902defm V_MED3_I32        : VOP3_Real_gfx6_gfx7_gfx10<0x158>;
903defm V_MED3_U32        : VOP3_Real_gfx6_gfx7_gfx10<0x159>;
904defm V_SAD_U8          : VOP3_Real_gfx6_gfx7_gfx10<0x15a>;
905defm V_SAD_HI_U8       : VOP3_Real_gfx6_gfx7_gfx10<0x15b>;
906defm V_SAD_U16         : VOP3_Real_gfx6_gfx7_gfx10<0x15c>;
907defm V_SAD_U32         : VOP3_Real_gfx6_gfx7_gfx10<0x15d>;
908defm V_CVT_PK_U8_F32   : VOP3_Real_gfx6_gfx7_gfx10<0x15e>;
909defm V_DIV_FIXUP_F32   : VOP3_Real_gfx6_gfx7_gfx10<0x15f>;
910defm V_DIV_FIXUP_F64   : VOP3_Real_gfx6_gfx7_gfx10<0x160>;
911defm V_ADD_F64         : VOP3_Real_gfx6_gfx7_gfx10<0x164>;
912defm V_MUL_F64         : VOP3_Real_gfx6_gfx7_gfx10<0x165>;
913defm V_MIN_F64         : VOP3_Real_gfx6_gfx7_gfx10<0x166>;
914defm V_MAX_F64         : VOP3_Real_gfx6_gfx7_gfx10<0x167>;
915defm V_LDEXP_F64       : VOP3_Real_gfx6_gfx7_gfx10<0x168>;
916defm V_MUL_LO_U32      : VOP3_Real_gfx6_gfx7_gfx10<0x169>;
917defm V_MUL_HI_U32      : VOP3_Real_gfx6_gfx7_gfx10<0x16a>;
918defm V_MUL_LO_I32      : VOP3_Real_gfx6_gfx7_gfx10<0x16b>;
919defm V_MUL_HI_I32      : VOP3_Real_gfx6_gfx7_gfx10<0x16c>;
920defm V_DIV_FMAS_F32    : VOP3_Real_gfx6_gfx7_gfx10<0x16f>;
921defm V_DIV_FMAS_F64    : VOP3_Real_gfx6_gfx7_gfx10<0x170>;
922defm V_MSAD_U8         : VOP3_Real_gfx6_gfx7_gfx10<0x171>;
923defm V_MQSAD_PK_U16_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x173>;
924defm V_TRIG_PREOP_F64  : VOP3_Real_gfx6_gfx7_gfx10<0x174>;
925defm V_DIV_SCALE_F32   : VOP3be_Real_gfx6_gfx7_gfx10<0x16d>;
926defm V_DIV_SCALE_F64   : VOP3be_Real_gfx6_gfx7_gfx10<0x16e>;
927
928//===----------------------------------------------------------------------===//
929// GFX8, GFX9 (VI).
930//===----------------------------------------------------------------------===//
931
932let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
933
934multiclass VOP3_Real_vi<bits<10> op> {
935  def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>,
936            VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>;
937}
938
939multiclass VOP3be_Real_vi<bits<10> op> {
940  def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>,
941            VOP3be_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>;
942}
943
944multiclass VOP3OpSel_Real_gfx9<bits<10> op> {
945  def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>,
946            VOP3OpSel_gfx9 <op, !cast<VOP_Pseudo>(NAME).Pfl>;
947}
948
949multiclass VOP3Interp_Real_vi<bits<10> op> {
950  def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>,
951            VOP3Interp_vi <op, !cast<VOP_Pseudo>(NAME).Pfl>;
952}
953
954} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8"
955
956let AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8" in {
957
958multiclass VOP3_F16_Real_vi<bits<10> op> {
959  def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
960            VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
961}
962
963multiclass VOP3Interp_F16_Real_vi<bits<10> op> {
964  def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
965            VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
966}
967
968} // End AssemblerPredicate = isGFX8Only, DecoderNamespace = "GFX8"
969
970let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in {
971
972multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
973  def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
974            VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
975              VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
976              let AsmString = AsmName # ps.AsmOperands;
977            }
978}
979
980multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> {
981  def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>,
982            VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
983              VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME);
984              let AsmString = AsmName # ps.AsmOperands;
985            }
986}
987
988multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
989  def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
990            VOP3Interp_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
991              VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
992              let AsmString = AsmName # ps.AsmOperands;
993            }
994}
995
996multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> {
997  def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX9>,
998              VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl> {
999              VOP_Pseudo ps = !cast<VOP_Pseudo>(NAME);
1000              let AsmString = AsmName # ps.AsmOperands;
1001            }
1002}
1003
1004} // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9"
1005
1006defm V_MAD_U64_U32      : VOP3be_Real_vi <0x1E8>;
1007defm V_MAD_I64_I32      : VOP3be_Real_vi <0x1E9>;
1008
1009defm V_MAD_LEGACY_F32   : VOP3_Real_vi <0x1c0>;
1010defm V_MAD_F32          : VOP3_Real_vi <0x1c1>;
1011defm V_MAD_I32_I24      : VOP3_Real_vi <0x1c2>;
1012defm V_MAD_U32_U24      : VOP3_Real_vi <0x1c3>;
1013defm V_CUBEID_F32       : VOP3_Real_vi <0x1c4>;
1014defm V_CUBESC_F32       : VOP3_Real_vi <0x1c5>;
1015defm V_CUBETC_F32       : VOP3_Real_vi <0x1c6>;
1016defm V_CUBEMA_F32       : VOP3_Real_vi <0x1c7>;
1017defm V_BFE_U32          : VOP3_Real_vi <0x1c8>;
1018defm V_BFE_I32          : VOP3_Real_vi <0x1c9>;
1019defm V_BFI_B32          : VOP3_Real_vi <0x1ca>;
1020defm V_FMA_F32          : VOP3_Real_vi <0x1cb>;
1021defm V_FMA_F64          : VOP3_Real_vi <0x1cc>;
1022defm V_LERP_U8          : VOP3_Real_vi <0x1cd>;
1023defm V_ALIGNBIT_B32     : VOP3_Real_vi <0x1ce>;
1024defm V_ALIGNBYTE_B32    : VOP3_Real_vi <0x1cf>;
1025defm V_MIN3_F32         : VOP3_Real_vi <0x1d0>;
1026defm V_MIN3_I32         : VOP3_Real_vi <0x1d1>;
1027defm V_MIN3_U32         : VOP3_Real_vi <0x1d2>;
1028defm V_MAX3_F32         : VOP3_Real_vi <0x1d3>;
1029defm V_MAX3_I32         : VOP3_Real_vi <0x1d4>;
1030defm V_MAX3_U32         : VOP3_Real_vi <0x1d5>;
1031defm V_MED3_F32         : VOP3_Real_vi <0x1d6>;
1032defm V_MED3_I32         : VOP3_Real_vi <0x1d7>;
1033defm V_MED3_U32         : VOP3_Real_vi <0x1d8>;
1034defm V_SAD_U8           : VOP3_Real_vi <0x1d9>;
1035defm V_SAD_HI_U8        : VOP3_Real_vi <0x1da>;
1036defm V_SAD_U16          : VOP3_Real_vi <0x1db>;
1037defm V_SAD_U32          : VOP3_Real_vi <0x1dc>;
1038defm V_CVT_PK_U8_F32    : VOP3_Real_vi <0x1dd>;
1039defm V_DIV_FIXUP_F32    : VOP3_Real_vi <0x1de>;
1040defm V_DIV_FIXUP_F64    : VOP3_Real_vi <0x1df>;
1041defm V_DIV_SCALE_F32    : VOP3be_Real_vi <0x1e0>;
1042defm V_DIV_SCALE_F64    : VOP3be_Real_vi <0x1e1>;
1043defm V_DIV_FMAS_F32     : VOP3_Real_vi <0x1e2>;
1044defm V_DIV_FMAS_F64     : VOP3_Real_vi <0x1e3>;
1045defm V_MSAD_U8          : VOP3_Real_vi <0x1e4>;
1046defm V_QSAD_PK_U16_U8   : VOP3_Real_vi <0x1e5>;
1047defm V_MQSAD_PK_U16_U8  : VOP3_Real_vi <0x1e6>;
1048defm V_MQSAD_U32_U8     : VOP3_Real_vi <0x1e7>;
1049
1050defm V_PERM_B32         : VOP3_Real_vi <0x1ed>;
1051
1052defm V_MAD_F16          : VOP3_F16_Real_vi <0x1ea>;
1053defm V_MAD_U16          : VOP3_F16_Real_vi <0x1eb>;
1054defm V_MAD_I16          : VOP3_F16_Real_vi <0x1ec>;
1055defm V_FMA_F16          : VOP3_F16_Real_vi <0x1ee>;
1056defm V_DIV_FIXUP_F16    : VOP3_F16_Real_vi <0x1ef>;
1057defm V_INTERP_P2_F16    : VOP3Interp_F16_Real_vi <0x276>;
1058
1059let FPDPRounding = 1 in {
1060defm V_MAD_LEGACY_F16       : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16",       "v_mad_legacy_f16">;
1061defm V_FMA_LEGACY_F16       : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16",       "v_fma_legacy_f16">;
1062defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">;
1063defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16", "v_interp_p2_legacy_f16">;
1064} // End FPDPRounding = 1
1065
1066defm V_MAD_LEGACY_U16       : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16",       "v_mad_legacy_u16">;
1067defm V_MAD_LEGACY_I16       : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16",       "v_mad_legacy_i16">;
1068
1069defm V_MAD_F16_gfx9         : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">;
1070defm V_MAD_U16_gfx9         : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">;
1071defm V_MAD_I16_gfx9         : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">;
1072defm V_FMA_F16_gfx9         : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">;
1073defm V_DIV_FIXUP_F16_gfx9   : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">;
1074defm V_INTERP_P2_F16_gfx9   : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2_f16">;
1075
1076defm V_ADD_I32_gfx9         : VOP3_Real_gfx9 <0x29c, "v_add_i32">;
1077defm V_SUB_I32_gfx9         : VOP3_Real_gfx9 <0x29d, "v_sub_i32">;
1078
1079defm V_INTERP_P1_F32_e64  : VOP3Interp_Real_vi <0x270>;
1080defm V_INTERP_P2_F32_e64  : VOP3Interp_Real_vi <0x271>;
1081defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>;
1082
1083defm V_INTERP_P1LL_F16  : VOP3Interp_Real_vi <0x274>;
1084defm V_INTERP_P1LV_F16  : VOP3Interp_Real_vi <0x275>;
1085defm V_ADD_F64          : VOP3_Real_vi <0x280>;
1086defm V_MUL_F64          : VOP3_Real_vi <0x281>;
1087defm V_MIN_F64          : VOP3_Real_vi <0x282>;
1088defm V_MAX_F64          : VOP3_Real_vi <0x283>;
1089defm V_LDEXP_F64        : VOP3_Real_vi <0x284>;
1090defm V_MUL_LO_U32       : VOP3_Real_vi <0x285>;
1091
1092// removed from VI as identical to V_MUL_LO_U32
1093let isAsmParserOnly = 1 in {
1094defm V_MUL_LO_I32       : VOP3_Real_vi <0x285>;
1095}
1096
1097defm V_MUL_HI_U32       : VOP3_Real_vi <0x286>;
1098defm V_MUL_HI_I32       : VOP3_Real_vi <0x287>;
1099
1100defm V_READLANE_B32     : VOP3_Real_vi <0x289>;
1101defm V_WRITELANE_B32    : VOP3_Real_vi <0x28a>;
1102
1103defm V_LSHLREV_B64      : VOP3_Real_vi <0x28f>;
1104defm V_LSHRREV_B64      : VOP3_Real_vi <0x290>;
1105defm V_ASHRREV_I64      : VOP3_Real_vi <0x291>;
1106defm V_TRIG_PREOP_F64   : VOP3_Real_vi <0x292>;
1107
1108defm V_LSHL_ADD_U32 : VOP3_Real_vi <0x1fd>;
1109defm V_ADD_LSHL_U32 : VOP3_Real_vi <0x1fe>;
1110defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>;
1111defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>;
1112defm V_AND_OR_B32 : VOP3_Real_vi <0x201>;
1113defm V_OR3_B32 : VOP3_Real_vi <0x202>;
1114defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>;
1115
1116defm V_XAD_U32 : VOP3_Real_vi <0x1f3>;
1117
1118defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>;
1119defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>;
1120defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>;
1121
1122defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>;
1123defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>;
1124defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>;
1125
1126defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>;
1127defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>;
1128defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>;
1129
1130defm V_ADD_I16  : VOP3OpSel_Real_gfx9 <0x29e>;
1131defm V_SUB_I16  : VOP3OpSel_Real_gfx9 <0x29f>;
1132
1133defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>;
1134defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>;
1135
1136defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>;
1137defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>;
1138