xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/VOP2Instructions.td (revision a3266ba2697a383d2ede56803320d941866c7e76) 
1//===-- VOP2Instructions.td - Vector Instruction Definitions --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// VOP2 Classes
11//===----------------------------------------------------------------------===//
12
13class VOP2e <bits<6> op, VOPProfile P> : Enc32 {
14  bits<8> vdst;
15  bits<9> src0;
16  bits<8> src1;
17
18  let Inst{8-0}   = !if(P.HasSrc0, src0, 0);
19  let Inst{16-9}  = !if(P.HasSrc1, src1, 0);
20  let Inst{24-17} = !if(P.EmitDst, vdst, 0);
21  let Inst{30-25} = op;
22  let Inst{31}    = 0x0; //encoding
23}
24
25class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 {
26  bits<8>  vdst;
27  bits<9>  src0;
28  bits<8>  src1;
29  bits<32> imm;
30
31  let Inst{8-0}   = !if(P.HasSrc0, src0, 0);
32  let Inst{16-9}  = !if(P.HasSrc1, src1, 0);
33  let Inst{24-17} = !if(P.EmitDst, vdst, 0);
34  let Inst{30-25} = op;
35  let Inst{31}    = 0x0; // encoding
36  let Inst{63-32} = imm;
37}
38
39class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> {
40  bits<8> vdst;
41  bits<8> src1;
42
43  let Inst{8-0}   = 0xf9; // sdwa
44  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
45  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
46  let Inst{30-25} = op;
47  let Inst{31}    = 0x0; // encoding
48}
49
50class VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> {
51  bits<8> vdst;
52  bits<9> src1;
53
54  let Inst{8-0}   = 0xf9; // sdwa
55  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
56  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
57  let Inst{30-25} = op;
58  let Inst{31}    = 0x0; // encoding
59  let Inst{63}    = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
60}
61
62class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> :
63  VOP_Pseudo <opName, suffix, P, P.Outs32, P.Ins32, "", pattern> {
64
65  let AsmOperands = P.Asm32;
66
67  let Size = 4;
68  let mayLoad = 0;
69  let mayStore = 0;
70  let hasSideEffects = 0;
71
72  let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
73
74  let mayRaiseFPException = ReadsModeReg;
75
76  let VOP2 = 1;
77  let VALU = 1;
78  let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
79
80  let AsmVariantName = AMDGPUAsmVariants.Default;
81}
82
83class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :
84  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
85  SIMCInstr <ps.PseudoInstr, EncodingFamily> {
86
87  let isPseudo = 0;
88  let isCodeGenOnly = 0;
89
90  let Constraints     = ps.Constraints;
91  let DisableEncoding = ps.DisableEncoding;
92
93  // copy relevant pseudo op flags
94  let SubtargetPredicate = ps.SubtargetPredicate;
95  let OtherPredicates    = ps.OtherPredicates;
96  let AsmMatchConverter  = ps.AsmMatchConverter;
97  let AsmVariantName     = ps.AsmVariantName;
98  let Constraints        = ps.Constraints;
99  let DisableEncoding    = ps.DisableEncoding;
100  let TSFlags            = ps.TSFlags;
101  let UseNamedOperandTable = ps.UseNamedOperandTable;
102  let Uses                 = ps.Uses;
103  let Defs                 = ps.Defs;
104}
105
106class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
107  VOP_SDWA_Pseudo <OpName, P, pattern> {
108  let AsmMatchConverter = "cvtSdwaVOP2";
109}
110
111class VOP2_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
112  VOP_DPP_Pseudo <OpName, P, pattern> {
113}
114
115
116class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {
117  list<dag> ret = !if(P.HasModifiers,
118    [(set P.DstVT:$vdst,
119      (node (P.Src0VT
120              !if(P.HasOMod,
121                  (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
122                  (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
123            (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
124    [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
125}
126
127multiclass VOP2Inst_e32<string opName,
128                        VOPProfile P,
129                        SDPatternOperator node = null_frag,
130                        string revOp = opName,
131                        bit GFX9Renamed = 0> {
132  let renamedInGFX9 = GFX9Renamed in {
133    def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
134               Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
135  } // End renamedInGFX9 = GFX9Renamed
136}
137
138multiclass VOP2Inst_e64<string opName,
139                        VOPProfile P,
140                        SDPatternOperator node = null_frag,
141                        string revOp = opName,
142                        bit GFX9Renamed = 0> {
143  let renamedInGFX9 = GFX9Renamed in {
144    def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
145               Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
146  } // End renamedInGFX9 = GFX9Renamed
147}
148
149multiclass VOP2Inst_sdwa<string opName,
150                         VOPProfile P,
151                         SDPatternOperator node = null_frag,
152                         string revOp = opName,
153                         bit GFX9Renamed = 0> {
154  let renamedInGFX9 = GFX9Renamed in {
155    foreach _ = BoolToList<P.HasExtSDWA>.ret in
156      def _sdwa : VOP2_SDWA_Pseudo <opName, P>;
157  } // End renamedInGFX9 = GFX9Renamed
158}
159
160multiclass VOP2Inst<string opName,
161                    VOPProfile P,
162                    SDPatternOperator node = null_frag,
163                    string revOp = opName,
164                    bit GFX9Renamed = 0> :
165    VOP2Inst_e32<opName, P, node, revOp, GFX9Renamed>,
166    VOP2Inst_e64<opName, P, node, revOp, GFX9Renamed>,
167    VOP2Inst_sdwa<opName, P, node, revOp, GFX9Renamed> {
168  let renamedInGFX9 = GFX9Renamed in {
169    foreach _ = BoolToList<P.HasExtDPP>.ret in
170      def _dpp  : VOP2_DPP_Pseudo <opName, P>;
171  }
172}
173
174multiclass VOP2bInst <string opName,
175                      VOPProfile P,
176                      SDPatternOperator node = null_frag,
177                      string revOp = opName,
178                      bit GFX9Renamed = 0,
179                      bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
180  let renamedInGFX9 = GFX9Renamed in {
181    let SchedRW = [Write32Bit, WriteSALU] in {
182      let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
183        def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
184                   Commutable_REV<revOp#"_e32", !eq(revOp, opName)> {
185          let usesCustomInserter = !eq(P.NumSrcArgs, 2);
186        }
187
188        foreach _ = BoolToList<P.HasExtSDWA>.ret in
189          def _sdwa  : VOP2_SDWA_Pseudo <opName, P> {
190            let AsmMatchConverter = "cvtSdwaVOP2b";
191          }
192        foreach _ = BoolToList<P.HasExtDPP>.ret in
193          def _dpp  : VOP2_DPP_Pseudo <opName, P>;
194      }
195
196      def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
197                 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
198    }
199  }
200}
201
202class VOP2bInstAlias <VOP2_Pseudo ps, Instruction inst,
203                      string OpName, string opnd> :
204  InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32),
205             (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
206                   ps.Pfl.Src1RC32:$src1)>,
207  PredicateControl {
208}
209
210multiclass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> {
211  let WaveSizePredicate = isWave32 in {
212    def : VOP2bInstAlias<ps, inst, OpName, "vcc_lo">;
213  }
214  let WaveSizePredicate = isWave64 in {
215    def : VOP2bInstAlias<ps, inst, OpName, "vcc">;
216  }
217}
218
219multiclass VOP2eInst <string opName,
220                      VOPProfile P,
221                      SDPatternOperator node = null_frag,
222                      string revOp = opName,
223                      bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
224
225  let SchedRW = [Write32Bit] in {
226    let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in {
227      def _e32 : VOP2_Pseudo <opName, P>,
228                 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
229
230      foreach _ = BoolToList<P.HasExtSDWA>.ret in
231        def _sdwa : VOP2_SDWA_Pseudo <opName, P> {
232          let AsmMatchConverter = "cvtSdwaVOP2e";
233        }
234
235      foreach _ = BoolToList<P.HasExtDPP>.ret in
236        def _dpp  : VOP2_DPP_Pseudo <opName, P>;
237    }
238
239    def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
240               Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
241  }
242}
243
244class VOP2eInstAlias <VOP2_Pseudo ps, Instruction inst, string opnd = ""> :
245  InstAlias <ps.OpName#" "#ps.Pfl.Asm32#", "#opnd,
246             (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
247                   ps.Pfl.Src1RC32:$src1)>, PredicateControl;
248
249class VOP2e64InstAlias <VOP3_Pseudo ps, Instruction inst> :
250  InstAlias <ps.OpName#" "#ps.Pfl.Asm64,
251             (inst ps.Pfl.DstRC:$vdst, VOPDstS64orS32:$sdst,
252                   ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, clampmod:$clamp)>,
253  PredicateControl;
254
255multiclass VOP2eInstAliases<VOP2_Pseudo ps, VOP2_Real inst> {
256  let WaveSizePredicate = isWave32 in {
257    def : VOP2eInstAlias<ps, inst, "vcc_lo">;
258  }
259  let WaveSizePredicate = isWave64 in {
260    def : VOP2eInstAlias<ps, inst, "vcc">;
261  }
262}
263
264class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
265  field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
266  field dag Ins32 = !if(!eq(vt.Size, 32),
267                        (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm),
268                        (ins VCSrc_f16:$src0, VGPR_32:$src1, ImmOpType:$imm));
269  field bit HasExt = 0;
270
271  // Hack to stop printing _e64
272  let DstRC = RegisterOperand<VGPR_32>;
273  field string Asm32 = " $vdst, $src0, $src1, $imm";
274}
275
276def VOP_MADAK_F16 : VOP_MADAK <f16>;
277def VOP_MADAK_F32 : VOP_MADAK <f32>;
278
279class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
280  field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
281  field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1);
282  field bit HasExt = 0;
283
284  // Hack to stop printing _e64
285  let DstRC = RegisterOperand<VGPR_32>;
286  field string Asm32 = " $vdst, $src0, $imm, $src1";
287}
288
289def VOP_MADMK_F16 : VOP_MADMK <f16>;
290def VOP_MADMK_F32 : VOP_MADMK <f32>;
291
292// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory
293// and processing time but it makes it easier to convert to mad.
294class VOP_MAC <ValueType vt0, ValueType vt1=vt0> : VOPProfile <[vt0, vt1, vt1, vt0]> {
295  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
296  let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
297                       0, HasModifiers, HasModifiers, HasOMod,
298                       Src0Mod, Src1Mod, Src2Mod>.ret;
299  let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
300                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
301                    VGPR_32:$src2, // stub argument
302                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
303                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
304  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
305
306  let InsDPP8 = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
307                     Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
308                     VGPR_32:$src2, // stub argument
309                     dpp8:$dpp8, FI:$fi);
310
311  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
312                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
313                     VGPR_32:$src2, // stub argument
314                     clampmod:$clamp, omod:$omod,
315                     dst_sel:$dst_sel, dst_unused:$dst_unused,
316                     src0_sel:$src0_sel, src1_sel:$src1_sel);
317  let Asm32 = getAsm32<1, 2, vt0>.ret;
318  let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, vt0>.ret;
319  let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt0>.ret;
320  let AsmDPP16 = getAsmDPP16<1, 2, HasModifiers, vt0>.ret;
321  let AsmDPP8 = getAsmDPP8<1, 2, 0, vt0>.ret;
322  let AsmSDWA = getAsmSDWA<1, 2, vt0>.ret;
323  let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt0>.ret;
324  let HasSrc2 = 0;
325  let HasSrc2Mods = 0;
326
327  let HasExt = 1;
328  let HasExtDPP = 1;
329  let HasExtSDWA = 1;
330  let HasExtSDWA9 = 0;
331  let TieRegDPP = "$src2";
332}
333
334def VOP_MAC_F16 : VOP_MAC <f16>;
335def VOP_MAC_F32 : VOP_MAC <f32>;
336let HasExtDPP = 0 in
337def VOP_MAC_LEGACY_F32 : VOP_MAC <f32>;
338
339class VOP_DOT_ACC<ValueType vt0, ValueType vt1> : VOP_MAC<vt0, vt1> {
340  let HasClamp = 0;
341  let HasExtSDWA = 0;
342  let HasOpSel = 0;
343  let IsPacked = 0;
344}
345
346def VOP_DOT_ACC_F32_V2F16 : VOP_DOT_ACC<f32, v2f16> {
347  let Src0ModDPP = FPVRegInputMods;
348  let Src1ModDPP = FPVRegInputMods;
349}
350
351def VOP_DOT_ACC_I32_I32   : VOP_DOT_ACC<i32, i32> {
352  let HasSrc0Mods = 1;
353  let HasSrc1Mods = 1;
354}
355
356// Write out to vcc or arbitrary SGPR.
357def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], 0, /*EnableClamp=*/1> {
358  let Asm32 = "$vdst, vcc, $src0, $src1";
359  let Asm64 = "$vdst, $sdst, $src0, $src1$clamp";
360  let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
361  let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
362  let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
363  let AsmDPP8 = "$vdst, vcc, $src0, $src1 $dpp8$fi";
364  let AsmDPP16 = AsmDPP#"$fi";
365  let Outs32 = (outs DstRC:$vdst);
366  let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
367}
368
369// Write out to vcc or arbitrary SGPR and read in from vcc or
370// arbitrary SGPR.
371def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], 0, /*EnableClamp=*/1> {
372  let Asm32 = "$vdst, vcc, $src0, $src1, vcc";
373  let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
374  let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
375  let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
376  let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
377  let AsmDPP8 = "$vdst, vcc, $src0, $src1, vcc $dpp8$fi";
378  let AsmDPP16 = AsmDPP#"$fi";
379  let Outs32 = (outs DstRC:$vdst);
380  let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
381
382  // Suppress src2 implied by type since the 32-bit encoding uses an
383  // implicit VCC use.
384  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
385
386  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
387                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
388                     clampmod:$clamp,
389                     dst_sel:$dst_sel, dst_unused:$dst_unused,
390                     src0_sel:$src0_sel, src1_sel:$src1_sel);
391
392  let InsDPP = (ins DstRCDPP:$old,
393                    Src0DPP:$src0,
394                    Src1DPP:$src1,
395                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
396                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
397  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
398
399  let HasExt = 1;
400  let HasExtDPP = 1;
401  let HasExtSDWA = 1;
402  let HasExtSDWA9 = 1;
403}
404
405// Read in from vcc or arbitrary SGPR.
406def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableF32SrcMods=*/1> {
407  let Asm32 = "$vdst, $src0, $src1";
408  let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2";
409  let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
410  let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
411  let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
412  let AsmDPP8 = "$vdst, $src0, $src1, vcc $dpp8$fi";
413  let AsmDPP16 = AsmDPP#"$fi";
414
415  let Outs32 = (outs DstRC:$vdst);
416  let Outs64 = (outs DstRC:$vdst);
417
418  // Suppress src2 implied by type since the 32-bit encoding uses an
419  // implicit VCC use.
420  let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
421
422  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
423                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
424                     clampmod:$clamp,
425                     dst_sel:$dst_sel, dst_unused:$dst_unused,
426                     src0_sel:$src0_sel, src1_sel:$src1_sel);
427
428  let InsDPP = (ins DstRCDPP:$old,
429                    Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
430                    Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
431                    dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
432                    bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
433  let InsDPP16 = !con(InsDPP, (ins FI:$fi));
434
435  let HasExt = 1;
436  let HasExtDPP = 1;
437  let HasExtSDWA = 1;
438  let HasExtSDWA9 = 1;
439}
440
441def VOP_READLANE : VOPProfile<[i32, i32, i32]> {
442  let Outs32 = (outs SReg_32:$vdst);
443  let Outs64 = Outs32;
444  let Ins32 = (ins VRegOrLds_32:$src0, SCSrc_b32:$src1);
445  let Ins64 = Ins32;
446  let Asm32 = " $vdst, $src0, $src1";
447  let Asm64 = Asm32;
448
449  let HasExt = 0;
450  let HasExtDPP = 0;
451  let HasExtSDWA = 0;
452  let HasExtSDWA9 = 0;
453}
454
455def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> {
456  let Outs32 = (outs VGPR_32:$vdst);
457  let Outs64 = Outs32;
458  let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in);
459  let Ins64 = Ins32;
460  let Asm32 = " $vdst, $src0, $src1";
461  let Asm64 = Asm32;
462  let HasSrc2 = 0;
463  let HasSrc2Mods = 0;
464
465  let HasExt = 0;
466  let HasExtDPP = 0;
467  let HasExtSDWA = 0;
468  let HasExtSDWA9 = 0;
469}
470
471//===----------------------------------------------------------------------===//
472// VOP2 Instructions
473//===----------------------------------------------------------------------===//
474
475defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>;
476let SubtargetPredicate = HasMadMacF32Insts in
477def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>;
478
479let isCommutable = 1 in {
480defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, any_fadd>;
481defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, any_fsub>;
482defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">;
483defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>;
484defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, any_fmul>;
485defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32_ARITH, AMDGPUmul_i24>;
486defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_i24>;
487defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32_ARITH, AMDGPUmul_u24>;
488defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_u24>;
489defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum_like>;
490defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum_like>;
491defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smin>;
492defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smax>;
493defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umin>;
494defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>;
495defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, lshr_rev, "v_lshr_b32">;
496defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, ashr_rev, "v_ashr_i32">;
497defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, lshl_rev, "v_lshl_b32">;
498defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, and>;
499defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>;
500defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, xor>;
501
502let mayRaiseFPException = 0 in {
503let OtherPredicates = [HasMadMacF32Insts] in {
504let Constraints = "$vdst = $src2", DisableEncoding="$src2",
505    isConvertibleToThreeAddress = 1 in {
506defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>;
507
508let SubtargetPredicate = isGFX6GFX7GFX10 in
509defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_MAC_LEGACY_F32>;
510} // End Constraints = "$vdst = $src2", DisableEncoding="$src2",
511  //     isConvertibleToThreeAddress = 1
512
513def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, []>;
514} // End OtherPredicates = [HasMadMacF32Insts]
515} // End mayRaiseFPException = 0
516
517// No patterns so that the scalar instructions are always selected.
518// The scalar versions will be replaced with vector when needed later.
519defm V_ADD_CO_U32 : VOP2bInst <"v_add_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_add_co_u32", 1>;
520defm V_SUB_CO_U32 : VOP2bInst <"v_sub_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
521defm V_SUBREV_CO_U32 : VOP2bInst <"v_subrev_co_u32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_co_u32", 1>;
522defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32", 1>;
523defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;
524defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32", 1>;
525
526
527let SubtargetPredicate = HasAddNoCarryInsts in {
528defm V_ADD_U32 : VOP2Inst <"v_add_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_add_u32", 1>;
529defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>;
530defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32_ARITH, null_frag, "v_sub_u32", 1>;
531}
532
533} // End isCommutable = 1
534
535// These are special and do not read the exec mask.
536let isConvergent = 1, Uses = []<Register> in {
537def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE,
538  [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))]>;
539
540let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in {
541def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE,
542  [(set i32:$vdst, (int_amdgcn_writelane i32:$src0, i32:$src1, i32:$vdst_in))]>;
543} // End $vdst = $vdst_in, DisableEncoding $vdst_in
544} // End isConvergent = 1
545
546defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_NO_EXT<VOP_I32_I32_I32>>;
547defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, add_ctpop>;
548defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_lo>;
549defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_hi>;
550defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_NO_EXT<VOP_F32_F32_I32>, AMDGPUldexp>;
551defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst"
552
553let ReadsModeReg = 0, mayRaiseFPException = 0 in {
554defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_i16_f32>;
555defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_u16_f32>;
556}
557
558defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT<VOP_V2F16_F32_F32>, AMDGPUpkrtz_f16_f32>;
559defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_u16_u32>;
560defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_i16_i32>;
561
562
563let SubtargetPredicate = isGFX6GFX7 in {
564defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;
565defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;
566} // End SubtargetPredicate = isGFX6GFX7
567
568let isCommutable = 1 in {
569let SubtargetPredicate = isGFX6GFX7 in {
570defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, srl>;
571defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, sra>;
572defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, shl>;
573} // End SubtargetPredicate = isGFX6GFX7
574} // End isCommutable = 1
575
576
577class DivergentBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
578  GCNPat<
579      (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
580      !if(!cast<Commutable_REV>(Inst).IsOrig,
581        (Inst $src0, $src1),
582        (Inst $src1, $src0)
583      )
584  >;
585
586class DivergentClampingBinOp<SDPatternOperator Op, VOP_Pseudo Inst> :
587  GCNPat<
588      (getDivergentFrag<Op>.ret Inst.Pfl.Src0VT:$src0, Inst.Pfl.Src1VT:$src1),
589      !if(!cast<Commutable_REV>(Inst).IsOrig,
590        (Inst $src0, $src1, 0),
591        (Inst $src1, $src0, 0)
592      )
593  >;
594
595def : DivergentBinOp<srl, V_LSHRREV_B32_e64>;
596def : DivergentBinOp<sra, V_ASHRREV_I32_e64>;
597def : DivergentBinOp<shl, V_LSHLREV_B32_e64>;
598
599let SubtargetPredicate = HasAddNoCarryInsts in {
600  def : DivergentClampingBinOp<add, V_ADD_U32_e64>;
601  def : DivergentClampingBinOp<sub, V_SUB_U32_e64>;
602}
603
604let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] in {
605def : DivergentClampingBinOp<add, V_ADD_CO_U32_e64>;
606def : DivergentClampingBinOp<sub, V_SUB_CO_U32_e64>;
607}
608
609def : DivergentBinOp<adde, V_ADDC_U32_e32>;
610def : DivergentBinOp<sube, V_SUBB_U32_e32>;
611
612class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> :
613  GCNPat<
614      (getDivergentFrag<Op>.ret i64:$src0, i64:$src1),
615      (REG_SEQUENCE VReg_64,
616        (Inst
617          (i32 (EXTRACT_SUBREG $src0, sub0)),
618          (i32 (EXTRACT_SUBREG $src1, sub0))
619        ), sub0,
620        (Inst
621          (i32 (EXTRACT_SUBREG $src0, sub1)),
622          (i32 (EXTRACT_SUBREG $src1, sub1))
623        ), sub1
624      )
625  >;
626
627def :  divergent_i64_BinOp <and, V_AND_B32_e32>;
628def :  divergent_i64_BinOp <or,  V_OR_B32_e32>;
629def :  divergent_i64_BinOp <xor, V_XOR_B32_e32>;
630
631let SubtargetPredicate = Has16BitInsts in {
632
633let FPDPRounding = 1 in {
634def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">;
635defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>;
636} // End FPDPRounding = 1
637
638defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16, lshl_rev>;
639defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16, lshr_rev>;
640defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16, ashr_rev>;
641
642let isCommutable = 1 in {
643let FPDPRounding = 1 in {
644defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, any_fadd>;
645defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, any_fsub>;
646defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">;
647defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, any_fmul>;
648
649let mayRaiseFPException = 0 in {
650def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">;
651}
652
653} // End FPDPRounding = 1
654defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>;
655defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16_ARITH, sub>;
656defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16_ARITH, null_frag, "v_sub_u16">;
657defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16, mul>;
658defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum_like>;
659defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum_like>;
660defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16, umax>;
661defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16, smax>;
662defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16, umin>;
663defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16, smin>;
664
665let Constraints = "$vdst = $src2", DisableEncoding="$src2",
666    isConvertibleToThreeAddress = 1 in {
667defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>;
668}
669} // End isCommutable = 1
670
671} // End SubtargetPredicate = Has16BitInsts
672
673let SubtargetPredicate = HasDLInsts in {
674
675defm V_XNOR_B32 : VOP2Inst <"v_xnor_b32", VOP_I32_I32_I32>;
676
677let Constraints = "$vdst = $src2",
678    DisableEncoding = "$src2",
679    isConvertibleToThreeAddress = 1,
680    isCommutable = 1 in
681defm V_FMAC_F32 : VOP2Inst <"v_fmac_f32", VOP_MAC_F32>;
682
683} // End SubtargetPredicate = HasDLInsts
684
685let SubtargetPredicate = HasFmaLegacy32 in {
686
687let Constraints = "$vdst = $src2",
688    DisableEncoding = "$src2",
689    isConvertibleToThreeAddress = 1,
690    isCommutable = 1 in
691defm V_FMAC_LEGACY_F32 : VOP2Inst <"v_fmac_legacy_f32", VOP_MAC_LEGACY_F32>;
692
693} // End SubtargetPredicate = HasFmaLegacy32
694
695let Constraints = "$vdst = $src2",
696      DisableEncoding="$src2",
697      isConvertibleToThreeAddress = 1,
698      isCommutable = 1,
699      IsDOT = 1 in {
700  let SubtargetPredicate = HasDot5Insts in
701    defm V_DOT2C_F32_F16 : VOP2Inst<"v_dot2c_f32_f16", VOP_DOT_ACC_F32_V2F16>;
702  let SubtargetPredicate = HasDot6Insts in
703    defm V_DOT4C_I32_I8  : VOP2Inst<"v_dot4c_i32_i8",  VOP_DOT_ACC_I32_I32>;
704
705  let SubtargetPredicate = HasDot4Insts in
706    defm V_DOT2C_I32_I16 : VOP2Inst<"v_dot2c_i32_i16", VOP_DOT_ACC_I32_I32>;
707  let SubtargetPredicate = HasDot3Insts in
708    defm V_DOT8C_I32_I4  : VOP2Inst<"v_dot8c_i32_i4",  VOP_DOT_ACC_I32_I32>;
709}
710
711let AddedComplexity = 30 in {
712  def : GCNPat<
713    (f32 (AMDGPUfdot2 v2f16:$src0, v2f16:$src1, f32:$src2, (i1 DSTCLAMP.NONE))),
714    (f32 (V_DOT2C_F32_F16_e32 $src0, $src1, $src2))
715  > {
716    let SubtargetPredicate = HasDot5Insts;
717  }
718  def : GCNPat<
719    (i32 (int_amdgcn_sdot4 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
720    (i32 (V_DOT4C_I32_I8_e32 $src0, $src1, $src2))
721  > {
722    let SubtargetPredicate = HasDot6Insts;
723  }
724  def : GCNPat<
725    (i32 (int_amdgcn_sdot2 v2i16:$src0, v2i16:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
726    (i32 (V_DOT2C_I32_I16_e32 $src0, $src1, $src2))
727  > {
728    let SubtargetPredicate = HasDot4Insts;
729  }
730  def : GCNPat<
731    (i32 (int_amdgcn_sdot8 i32:$src0, i32:$src1, i32:$src2, (i1 DSTCLAMP.NONE))),
732    (i32 (V_DOT8C_I32_I4_e32 $src0, $src1, $src2))
733  > {
734    let SubtargetPredicate = HasDot3Insts;
735  }
736} // End AddedComplexity = 30
737
738let SubtargetPredicate = isGFX10Plus in {
739
740def V_FMAMK_F32 : VOP2_Pseudo<"v_fmamk_f32", VOP_MADMK_F32, [], "">;
741let FPDPRounding = 1 in
742def V_FMAMK_F16 : VOP2_Pseudo <"v_fmamk_f16", VOP_MADMK_F16, [], "">;
743
744let isCommutable = 1 in {
745def V_FMAAK_F32 : VOP2_Pseudo<"v_fmaak_f32", VOP_MADAK_F32, [], "">;
746let FPDPRounding = 1 in
747def V_FMAAK_F16 : VOP2_Pseudo <"v_fmaak_f16", VOP_MADAK_F16, [], "">;
748} // End isCommutable = 1
749
750let Constraints = "$vdst = $src2",
751    DisableEncoding="$src2",
752    isConvertibleToThreeAddress = 1,
753    isCommutable = 1 in {
754defm V_FMAC_F16 : VOP2Inst <"v_fmac_f16", VOP_MAC_F16>;
755}
756
757} // End SubtargetPredicate = isGFX10Plus
758
759let SubtargetPredicate = HasPkFmacF16Inst in {
760defm V_PK_FMAC_F16 : VOP2Inst<"v_pk_fmac_f16", VOP_V2F16_V2F16_V2F16>;
761} // End SubtargetPredicate = HasPkFmacF16Inst
762
763// Note: 16-bit instructions produce a 0 result in the high 16-bits
764// on GFX8 and GFX9 and preserve high 16 bits on GFX10+
765multiclass Arithmetic_i16_0Hi_Pats <SDPatternOperator op, Instruction inst> {
766
767def : GCNPat<
768  (i32 (zext (op i16:$src0, i16:$src1))),
769  (inst VSrc_b16:$src0, VSrc_b16:$src1)
770>;
771
772def : GCNPat<
773  (i64 (zext (op i16:$src0, i16:$src1))),
774   (REG_SEQUENCE VReg_64,
775     (inst $src0, $src1), sub0,
776     (V_MOV_B32_e32 (i32 0)), sub1)
777>;
778}
779
780class ZExt_i16_i1_Pat <SDNode ext> : GCNPat <
781  (i16 (ext i1:$src)),
782  (V_CNDMASK_B32_e64 (i32 0/*src0mod*/), (i32 0/*src0*/),
783                     (i32 0/*src1mod*/), (i32 1/*src1*/),
784                     $src)
785>;
786
787foreach vt = [i16, v2i16] in {
788def : GCNPat <
789  (and vt:$src0, vt:$src1),
790  (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
791>;
792
793def : GCNPat <
794  (or vt:$src0, vt:$src1),
795  (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
796>;
797
798def : GCNPat <
799  (xor vt:$src0, vt:$src1),
800  (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
801>;
802}
803
804let Predicates = [Has16BitInsts] in {
805
806// Undo sub x, c -> add x, -c canonicalization since c is more likely
807// an inline immediate than -c.
808// TODO: Also do for 64-bit.
809def : GCNPat<
810  (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)),
811  (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
812>;
813
814
815let Predicates = [Has16BitInsts, isGFX7GFX8GFX9] in {
816
817def : GCNPat<
818  (i32 (zext (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)))),
819  (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
820>;
821
822defm : Arithmetic_i16_0Hi_Pats<add, V_ADD_U16_e64>;
823defm : Arithmetic_i16_0Hi_Pats<mul, V_MUL_LO_U16_e64>;
824defm : Arithmetic_i16_0Hi_Pats<sub, V_SUB_U16_e64>;
825defm : Arithmetic_i16_0Hi_Pats<smin, V_MIN_I16_e64>;
826defm : Arithmetic_i16_0Hi_Pats<smax, V_MAX_I16_e64>;
827defm : Arithmetic_i16_0Hi_Pats<umin, V_MIN_U16_e64>;
828defm : Arithmetic_i16_0Hi_Pats<umax, V_MAX_U16_e64>;
829defm : Arithmetic_i16_0Hi_Pats<lshl_rev, V_LSHLREV_B16_e64>;
830defm : Arithmetic_i16_0Hi_Pats<lshr_rev, V_LSHRREV_B16_e64>;
831defm : Arithmetic_i16_0Hi_Pats<ashr_rev, V_ASHRREV_I16_e64>;
832}  // End Predicates = [Has16BitInsts, isGFX7GFX8GFX9]
833
834def : ZExt_i16_i1_Pat<zext>;
835def : ZExt_i16_i1_Pat<anyext>;
836
837def : GCNPat <
838  (i16 (sext i1:$src)),
839  (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
840                     /*src1mod*/(i32 0), /*src1*/(i32 -1), $src)
841>;
842
843} // End Predicates = [Has16BitInsts]
844
845
846let SubtargetPredicate = HasIntClamp in {
847// Set clamp bit for saturation.
848def : VOPBinOpClampPat<uaddsat, V_ADD_CO_U32_e64, i32>;
849def : VOPBinOpClampPat<usubsat, V_SUB_CO_U32_e64, i32>;
850}
851
852let SubtargetPredicate = HasAddNoCarryInsts, OtherPredicates = [HasIntClamp] in {
853let AddedComplexity = 1 in { // Prefer over form with carry-out.
854def : VOPBinOpClampPat<uaddsat, V_ADD_U32_e64, i32>;
855def : VOPBinOpClampPat<usubsat, V_SUB_U32_e64, i32>;
856}
857}
858
859let SubtargetPredicate = Has16BitInsts, OtherPredicates = [HasIntClamp] in {
860def : VOPBinOpClampPat<uaddsat, V_ADD_U16_e64, i16>;
861def : VOPBinOpClampPat<usubsat, V_SUB_U16_e64, i16>;
862}
863
864//===----------------------------------------------------------------------===//
865// Target-specific instruction encodings.
866//===----------------------------------------------------------------------===//
867
868class VOP2_DPP<bits<6> op, VOP2_DPP_Pseudo ps,
869               string opName = ps.OpName, VOPProfile p = ps.Pfl,
870               bit IsDPP16 = 0> :
871    VOP_DPP<opName, p, IsDPP16> {
872  let hasSideEffects = ps.hasSideEffects;
873  let Defs = ps.Defs;
874  let SchedRW = ps.SchedRW;
875  let Uses = ps.Uses;
876
877  bits<8> vdst;
878  bits<8> src1;
879  let Inst{8-0}   = 0xfa;
880  let Inst{16-9}  = !if(p.HasSrc1, src1{7-0}, 0);
881  let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
882  let Inst{30-25} = op;
883  let Inst{31}    = 0x0;
884}
885
886class Base_VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,
887                 string opName = ps.OpName, VOPProfile p = ps.Pfl> :
888    VOP2_DPP<op, ps, opName, p, 1> {
889  let AssemblerPredicate = HasDPP16;
890  let SubtargetPredicate = HasDPP16;
891  let OtherPredicates = ps.OtherPredicates;
892}
893
894class VOP2_DPP16<bits<6> op, VOP2_DPP_Pseudo ps,
895                 string opName = ps.OpName, VOPProfile p = ps.Pfl> :
896    Base_VOP2_DPP16<op, ps, opName, p>,
897    SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX10>;
898
899class VOP2_DPP8<bits<6> op, VOP2_Pseudo ps,
900                string opName = ps.OpName, VOPProfile p = ps.Pfl> :
901    VOP_DPP8<ps.OpName, p> {
902  let hasSideEffects = ps.hasSideEffects;
903  let Defs = ps.Defs;
904  let SchedRW = ps.SchedRW;
905  let Uses = ps.Uses;
906
907  bits<8> vdst;
908  bits<8> src1;
909
910  let Inst{8-0}   = fi;
911  let Inst{16-9}  = !if(p.HasSrc1, src1{7-0}, 0);
912  let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
913  let Inst{30-25} = op;
914  let Inst{31}    = 0x0;
915
916  let AssemblerPredicate = HasDPP8;
917  let SubtargetPredicate = HasDPP8;
918  let OtherPredicates = ps.OtherPredicates;
919}
920
921//===----------------------------------------------------------------------===//
922// GFX10.
923//===----------------------------------------------------------------------===//
924
925let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
926  //===------------------------------- VOP2 -------------------------------===//
927  multiclass VOP2Only_Real_MADK_gfx10<bits<6> op> {
928    def _gfx10 :
929      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>,
930      VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
931  }
932  multiclass VOP2Only_Real_MADK_gfx10_with_name<bits<6> op, string opName,
933                                                string asmName> {
934    def _gfx10 :
935        VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX10>,
936        VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> {
937      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName);
938      let AsmString = asmName # ps.AsmOperands;
939    }
940  }
941  multiclass VOP2_Real_e32_gfx10<bits<6> op> {
942    def _e32_gfx10 :
943      VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
944      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
945  }
946  multiclass VOP2_Real_e64_gfx10<bits<6> op> {
947    def _e64_gfx10 :
948      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
949      VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
950  }
951  multiclass VOP2_Real_sdwa_gfx10<bits<6> op> {
952    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
953    def _sdwa_gfx10 :
954      VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
955      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
956      let DecoderNamespace = "SDWA10";
957    }
958  }
959  multiclass VOP2_Real_dpp_gfx10<bits<6> op> {
960    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
961    def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
962      let DecoderNamespace = "SDWA10";
963    }
964  }
965  multiclass VOP2_Real_dpp8_gfx10<bits<6> op> {
966    foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
967    def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")> {
968      let DecoderNamespace = "DPP8";
969    }
970  }
971
972  //===------------------------- VOP2 (with name) -------------------------===//
973  multiclass VOP2_Real_e32_gfx10_with_name<bits<6> op, string opName,
974                                           string asmName> {
975    def _e32_gfx10 :
976      VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
977      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
978        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
979        let AsmString = asmName # ps.AsmOperands;
980      }
981  }
982  multiclass VOP2_Real_e64_gfx10_with_name<bits<6> op, string opName,
983                                           string asmName> {
984    def _e64_gfx10 :
985      VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
986      VOP3e_gfx10<{0, 1, 0, 0, op{5-0}},
987                  !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
988        VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64");
989        let AsmString = asmName # ps.AsmOperands;
990      }
991  }
992  let DecoderNamespace = "SDWA10" in {
993    multiclass VOP2_Real_sdwa_gfx10_with_name<bits<6> op, string opName,
994                                              string asmName> {
995      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
996      def _sdwa_gfx10 :
997        VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
998        VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
999          VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1000          let AsmString = asmName # ps.AsmOperands;
1001        }
1002    }
1003    multiclass VOP2_Real_dpp_gfx10_with_name<bits<6> op, string opName,
1004                                             string asmName> {
1005      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1006      def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp")> {
1007        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
1008        let AsmString = asmName # ps.Pfl.AsmDPP16;
1009      }
1010    }
1011    multiclass VOP2_Real_dpp8_gfx10_with_name<bits<6> op, string opName,
1012                                              string asmName> {
1013      foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1014      def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
1015        VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
1016        let AsmString = asmName # ps.Pfl.AsmDPP8;
1017        let DecoderNamespace = "DPP8";
1018      }
1019    }
1020  } // End DecoderNamespace = "SDWA10"
1021
1022  //===------------------------------ VOP2be ------------------------------===//
1023  multiclass VOP2be_Real_e32_gfx10<bits<6> op, string opName, string asmName> {
1024    def _e32_gfx10 :
1025      VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
1026      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
1027        VOP2_Pseudo Ps = !cast<VOP2_Pseudo>(opName#"_e32");
1028        let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
1029      }
1030  }
1031  multiclass VOP2be_Real_e64_gfx10<bits<6> op, string opName, string asmName> {
1032    def _e64_gfx10 :
1033      VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
1034      VOP3be_gfx10<{0, 1, 0, 0, op{5-0}},
1035                   !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
1036        VOP3_Pseudo Ps = !cast<VOP3_Pseudo>(opName#"_e64");
1037        let AsmString = asmName # Ps.AsmOperands;
1038      }
1039  }
1040  multiclass VOP2be_Real_sdwa_gfx10<bits<6> op, string opName, string asmName> {
1041    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1042    def _sdwa_gfx10 :
1043      VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1044      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1045        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1046        let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
1047        let DecoderNamespace = "SDWA10";
1048      }
1049    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1050    def _sdwa_w32_gfx10 :
1051      Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1052      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1053        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1054        let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands);
1055        let isAsmParserOnly = 1;
1056        let DecoderNamespace = "SDWA10";
1057        let WaveSizePredicate = isWave32;
1058      }
1059    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9>.ret in
1060    def _sdwa_w64_gfx10 :
1061      Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1062      VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1063        VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1064        let AsmString = asmName # Ps.AsmOperands;
1065        let isAsmParserOnly = 1;
1066        let DecoderNamespace = "SDWA10";
1067        let WaveSizePredicate = isWave64;
1068      }
1069  }
1070  multiclass VOP2be_Real_dpp_gfx10<bits<6> op, string opName, string asmName> {
1071    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1072    def _dpp_gfx10 :
1073      VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1074        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1075        let AsmString = asmName # !subst(", vcc", "", AsmDPP);
1076        let DecoderNamespace = "SDWA10";
1077      }
1078    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1079    def _dpp_w32_gfx10 :
1080      Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1081        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1082        let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP);
1083        let isAsmParserOnly = 1;
1084        let WaveSizePredicate = isWave32;
1085      }
1086    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1087    def _dpp_w64_gfx10 :
1088      Base_VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), asmName> {
1089        string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
1090        let AsmString = asmName # AsmDPP;
1091        let isAsmParserOnly = 1;
1092        let WaveSizePredicate = isWave64;
1093      }
1094  }
1095  multiclass VOP2be_Real_dpp8_gfx10<bits<6> op, string opName, string asmName> {
1096    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1097    def _dpp8_gfx10 :
1098      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1099        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1100        let AsmString = asmName # !subst(", vcc", "", AsmDPP8);
1101        let DecoderNamespace = "DPP8";
1102      }
1103    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1104    def _dpp8_w32_gfx10 :
1105      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1106        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1107        let AsmString = asmName # !subst("vcc", "vcc_lo", AsmDPP8);
1108        let isAsmParserOnly = 1;
1109        let WaveSizePredicate = isWave32;
1110      }
1111    foreach _ = BoolToList<!cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtDPP>.ret in
1112    def _dpp8_w64_gfx10 :
1113      VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32"), asmName> {
1114        string AsmDPP8 = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP8;
1115        let AsmString = asmName # AsmDPP8;
1116        let isAsmParserOnly = 1;
1117        let WaveSizePredicate = isWave64;
1118      }
1119  }
1120
1121  //===----------------------------- VOP3Only -----------------------------===//
1122  multiclass VOP3Only_Real_gfx10<bits<10> op> {
1123    def _e64_gfx10 :
1124      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1125      VOP3e_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1126  }
1127
1128  //===---------------------------- VOP3beOnly ----------------------------===//
1129  multiclass VOP3beOnly_Real_gfx10<bits<10> op> {
1130    def _e64_gfx10 :
1131      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1132      VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1133  }
1134} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
1135
1136multiclass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> :
1137  VOP2be_Real_e32_gfx10<op, opName, asmName>,
1138  VOP2be_Real_e64_gfx10<op, opName, asmName>,
1139  VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
1140  VOP2be_Real_dpp_gfx10<op, opName, asmName>,
1141  VOP2be_Real_dpp8_gfx10<op, opName, asmName>;
1142
1143multiclass VOP2e_Real_gfx10<bits<6> op, string opName, string asmName> :
1144  VOP2_Real_e32_gfx10<op>,
1145  VOP2_Real_e64_gfx10<op>,
1146  VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
1147  VOP2be_Real_dpp_gfx10<op, opName, asmName>,
1148  VOP2be_Real_dpp8_gfx10<op, opName, asmName>;
1149
1150multiclass VOP2_Real_gfx10<bits<6> op> :
1151  VOP2_Real_e32_gfx10<op>, VOP2_Real_e64_gfx10<op>,
1152  VOP2_Real_sdwa_gfx10<op>, VOP2_Real_dpp_gfx10<op>, VOP2_Real_dpp8_gfx10<op>;
1153
1154multiclass VOP2_Real_gfx10_with_name<bits<6> op, string opName,
1155                                     string asmName> :
1156  VOP2_Real_e32_gfx10_with_name<op, opName, asmName>,
1157  VOP2_Real_e64_gfx10_with_name<op, opName, asmName>,
1158  VOP2_Real_sdwa_gfx10_with_name<op, opName, asmName>,
1159  VOP2_Real_dpp_gfx10_with_name<op, opName, asmName>,
1160  VOP2_Real_dpp8_gfx10_with_name<op, opName, asmName>;
1161
1162// NB: Same opcode as v_mac_legacy_f32
1163let DecoderNamespace = "GFX10_B" in
1164defm V_FMAC_LEGACY_F32 : VOP2_Real_gfx10<0x006>;
1165
1166defm V_XNOR_B32        : VOP2_Real_gfx10<0x01e>;
1167defm V_FMAC_F32        : VOP2_Real_gfx10<0x02b>;
1168defm V_FMAMK_F32       : VOP2Only_Real_MADK_gfx10<0x02c>;
1169defm V_FMAAK_F32       : VOP2Only_Real_MADK_gfx10<0x02d>;
1170defm V_ADD_F16         : VOP2_Real_gfx10<0x032>;
1171defm V_SUB_F16         : VOP2_Real_gfx10<0x033>;
1172defm V_SUBREV_F16      : VOP2_Real_gfx10<0x034>;
1173defm V_MUL_F16         : VOP2_Real_gfx10<0x035>;
1174defm V_FMAC_F16        : VOP2_Real_gfx10<0x036>;
1175defm V_FMAMK_F16       : VOP2Only_Real_MADK_gfx10<0x037>;
1176defm V_FMAAK_F16       : VOP2Only_Real_MADK_gfx10<0x038>;
1177defm V_MAX_F16         : VOP2_Real_gfx10<0x039>;
1178defm V_MIN_F16         : VOP2_Real_gfx10<0x03a>;
1179defm V_LDEXP_F16       : VOP2_Real_gfx10<0x03b>;
1180defm V_PK_FMAC_F16     : VOP2_Real_e32_gfx10<0x03c>;
1181
1182// VOP2 no carry-in, carry-out.
1183defm V_ADD_NC_U32 :
1184  VOP2_Real_gfx10_with_name<0x025, "V_ADD_U32", "v_add_nc_u32">;
1185defm V_SUB_NC_U32 :
1186  VOP2_Real_gfx10_with_name<0x026, "V_SUB_U32", "v_sub_nc_u32">;
1187defm V_SUBREV_NC_U32 :
1188  VOP2_Real_gfx10_with_name<0x027, "V_SUBREV_U32", "v_subrev_nc_u32">;
1189
1190// VOP2 carry-in, carry-out.
1191defm V_ADD_CO_CI_U32 :
1192  VOP2be_Real_gfx10<0x028, "V_ADDC_U32", "v_add_co_ci_u32">;
1193defm V_SUB_CO_CI_U32 :
1194  VOP2be_Real_gfx10<0x029, "V_SUBB_U32", "v_sub_co_ci_u32">;
1195defm V_SUBREV_CO_CI_U32 :
1196  VOP2be_Real_gfx10<0x02a, "V_SUBBREV_U32", "v_subrev_co_ci_u32">;
1197
1198defm V_CNDMASK_B32 :
1199  VOP2e_Real_gfx10<0x001, "V_CNDMASK_B32", "v_cndmask_b32">;
1200
1201// VOP3 only.
1202defm V_BFM_B32            : VOP3Only_Real_gfx10<0x363>;
1203defm V_BCNT_U32_B32       : VOP3Only_Real_gfx10<0x364>;
1204defm V_MBCNT_LO_U32_B32   : VOP3Only_Real_gfx10<0x365>;
1205defm V_MBCNT_HI_U32_B32   : VOP3Only_Real_gfx10<0x366>;
1206defm V_LDEXP_F32          : VOP3Only_Real_gfx10<0x362>;
1207defm V_CVT_PKNORM_I16_F32 : VOP3Only_Real_gfx10<0x368>;
1208defm V_CVT_PKNORM_U16_F32 : VOP3Only_Real_gfx10<0x369>;
1209defm V_CVT_PK_U16_U32     : VOP3Only_Real_gfx10<0x36a>;
1210defm V_CVT_PK_I16_I32     : VOP3Only_Real_gfx10<0x36b>;
1211
1212// VOP3 carry-out.
1213defm V_ADD_CO_U32 : VOP3beOnly_Real_gfx10<0x30f>;
1214defm V_SUB_CO_U32 : VOP3beOnly_Real_gfx10<0x310>;
1215defm V_SUBREV_CO_U32 : VOP3beOnly_Real_gfx10<0x319>;
1216
1217let SubtargetPredicate = isGFX10Plus in {
1218  defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx10>;
1219
1220  defm : VOP2bInstAliases<
1221    V_ADDC_U32_e32, V_ADD_CO_CI_U32_e32_gfx10, "v_add_co_ci_u32">;
1222  defm : VOP2bInstAliases<
1223    V_SUBB_U32_e32, V_SUB_CO_CI_U32_e32_gfx10, "v_sub_co_ci_u32">;
1224  defm : VOP2bInstAliases<
1225    V_SUBBREV_U32_e32, V_SUBREV_CO_CI_U32_e32_gfx10, "v_subrev_co_ci_u32">;
1226} // End SubtargetPredicate = isGFX10Plus
1227
1228//===----------------------------------------------------------------------===//
1229// GFX6, GFX7, GFX10.
1230//===----------------------------------------------------------------------===//
1231
1232class VOP2_DPPe <bits<6> op, VOP2_DPP_Pseudo ps, VOPProfile P = ps.Pfl> :
1233  VOP_DPPe <P> {
1234  bits<8> vdst;
1235  bits<8> src1;
1236  let Inst{8-0}   = 0xfa; //dpp
1237  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
1238  let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
1239  let Inst{30-25} = op;
1240  let Inst{31}    = 0x0; //encoding
1241}
1242
1243let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
1244  multiclass VOP2_Lane_Real_gfx6_gfx7<bits<6> op> {
1245    def _gfx6_gfx7 :
1246      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1247      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1248  }
1249  multiclass VOP2Only_Real_MADK_gfx6_gfx7<bits<6> op> {
1250    def _gfx6_gfx7 :
1251      VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1252      VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1253  }
1254  multiclass VOP2_Real_e32_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1255    def _e32_gfx6_gfx7 :
1256      VOP2_Real<!cast<VOP2_Pseudo>(PseudoName#"_e32"), SIEncodingFamily.SI>,
1257      VOP2e<op{5-0}, !cast<VOP2_Pseudo>(PseudoName#"_e32").Pfl>;
1258  }
1259  multiclass VOP2_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1260    def _e64_gfx6_gfx7 :
1261      VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>,
1262      VOP3e_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>;
1263  }
1264  multiclass VOP2be_Real_e64_gfx6_gfx7<bits<6> op, string PseudoName = NAME> {
1265    def _e64_gfx6_gfx7 :
1266      VOP3_Real<!cast<VOP3_Pseudo>(PseudoName#"_e64"), SIEncodingFamily.SI>,
1267      VOP3be_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(PseudoName#"_e64").Pfl>;
1268  }
1269} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
1270
1271multiclass VOP2Only_Real_MADK_gfx6_gfx7_gfx10<bits<6> op> :
1272  VOP2Only_Real_MADK_gfx6_gfx7<op>, VOP2Only_Real_MADK_gfx10<op>;
1273
1274multiclass VOP2_Real_gfx6_gfx7<bits<6> op> :
1275  VOP2_Real_e32_gfx6_gfx7<op>, VOP2_Real_e64_gfx6_gfx7<op>;
1276
1277multiclass VOP2_Real_gfx6_gfx7_gfx10<bits<6> op> :
1278  VOP2_Real_gfx6_gfx7<op>, VOP2_Real_gfx10<op>;
1279
1280multiclass VOP2be_Real_gfx6_gfx7<bits<6> op> :
1281  VOP2_Real_e32_gfx6_gfx7<op>, VOP2be_Real_e64_gfx6_gfx7<op>;
1282
1283multiclass VOP2be_Real_gfx6_gfx7_with_name<bits<6> op,
1284  string PseudoName, string asmName>  {
1285  defvar ps32 = !cast<VOP2_Pseudo>(PseudoName#"_e32");
1286  defvar ps64 = !cast<VOP3_Pseudo>(PseudoName#"_e64");
1287
1288  let AsmString = asmName # ps32.AsmOperands in {
1289    defm "" : VOP2_Real_e32_gfx6_gfx7<op, PseudoName>;
1290  }
1291
1292   let AsmString = asmName # ps64.AsmOperands in {
1293    defm "" : VOP2be_Real_e64_gfx6_gfx7<op, PseudoName>;
1294  }
1295}
1296
1297defm V_CNDMASK_B32        : VOP2_Real_gfx6_gfx7<0x000>;
1298defm V_MIN_LEGACY_F32     : VOP2_Real_gfx6_gfx7<0x00d>;
1299defm V_MAX_LEGACY_F32     : VOP2_Real_gfx6_gfx7<0x00e>;
1300defm V_LSHR_B32           : VOP2_Real_gfx6_gfx7<0x015>;
1301defm V_ASHR_I32           : VOP2_Real_gfx6_gfx7<0x017>;
1302defm V_LSHL_B32           : VOP2_Real_gfx6_gfx7<0x019>;
1303defm V_BFM_B32            : VOP2_Real_gfx6_gfx7<0x01e>;
1304defm V_BCNT_U32_B32       : VOP2_Real_gfx6_gfx7<0x022>;
1305defm V_MBCNT_LO_U32_B32   : VOP2_Real_gfx6_gfx7<0x023>;
1306defm V_MBCNT_HI_U32_B32   : VOP2_Real_gfx6_gfx7<0x024>;
1307defm V_LDEXP_F32          : VOP2_Real_gfx6_gfx7<0x02b>;
1308defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_gfx6_gfx7<0x02c>;
1309defm V_CVT_PKNORM_I16_F32 : VOP2_Real_gfx6_gfx7<0x02d>;
1310defm V_CVT_PKNORM_U16_F32 : VOP2_Real_gfx6_gfx7<0x02e>;
1311defm V_CVT_PK_U16_U32     : VOP2_Real_gfx6_gfx7<0x030>;
1312defm V_CVT_PK_I16_I32     : VOP2_Real_gfx6_gfx7<0x031>;
1313
1314// V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in
1315// VI, but the VI instructions behave the same as the SI versions.
1316defm V_ADD_I32            : VOP2be_Real_gfx6_gfx7_with_name<0x025, "V_ADD_CO_U32", "v_add_i32">;
1317defm V_SUB_I32            : VOP2be_Real_gfx6_gfx7_with_name<0x026, "V_SUB_CO_U32", "v_sub_i32">;
1318defm V_SUBREV_I32         : VOP2be_Real_gfx6_gfx7_with_name<0x027, "V_SUBREV_CO_U32", "v_subrev_i32">;
1319defm V_ADDC_U32           : VOP2be_Real_gfx6_gfx7<0x028>;
1320defm V_SUBB_U32           : VOP2be_Real_gfx6_gfx7<0x029>;
1321defm V_SUBBREV_U32        : VOP2be_Real_gfx6_gfx7<0x02a>;
1322
1323defm V_READLANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x001>;
1324
1325let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
1326  defm V_WRITELANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x002>;
1327} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
1328
1329let SubtargetPredicate = isGFX6GFX7 in {
1330  defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx6_gfx7>;
1331  defm : VOP2eInstAliases<V_ADD_CO_U32_e32, V_ADD_I32_e32_gfx6_gfx7>;
1332  defm : VOP2eInstAliases<V_SUB_CO_U32_e32, V_SUB_I32_e32_gfx6_gfx7>;
1333  defm : VOP2eInstAliases<V_SUBREV_CO_U32_e32, V_SUBREV_I32_e32_gfx6_gfx7>;
1334
1335  def : VOP2e64InstAlias<V_ADD_CO_U32_e64, V_ADD_I32_e64_gfx6_gfx7>;
1336  def : VOP2e64InstAlias<V_SUB_CO_U32_e64, V_SUB_I32_e64_gfx6_gfx7>;
1337  def : VOP2e64InstAlias<V_SUBREV_CO_U32_e64, V_SUBREV_I32_e64_gfx6_gfx7>;
1338} // End SubtargetPredicate = isGFX6GFX7
1339
1340defm V_ADD_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x003>;
1341defm V_SUB_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x004>;
1342defm V_SUBREV_F32         : VOP2_Real_gfx6_gfx7_gfx10<0x005>;
1343defm V_MAC_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x006>;
1344defm V_MUL_LEGACY_F32     : VOP2_Real_gfx6_gfx7_gfx10<0x007>;
1345defm V_MUL_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x008>;
1346defm V_MUL_I32_I24        : VOP2_Real_gfx6_gfx7_gfx10<0x009>;
1347defm V_MUL_HI_I32_I24     : VOP2_Real_gfx6_gfx7_gfx10<0x00a>;
1348defm V_MUL_U32_U24        : VOP2_Real_gfx6_gfx7_gfx10<0x00b>;
1349defm V_MUL_HI_U32_U24     : VOP2_Real_gfx6_gfx7_gfx10<0x00c>;
1350defm V_MIN_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x00f>;
1351defm V_MAX_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x010>;
1352defm V_MIN_I32            : VOP2_Real_gfx6_gfx7_gfx10<0x011>;
1353defm V_MAX_I32            : VOP2_Real_gfx6_gfx7_gfx10<0x012>;
1354defm V_MIN_U32            : VOP2_Real_gfx6_gfx7_gfx10<0x013>;
1355defm V_MAX_U32            : VOP2_Real_gfx6_gfx7_gfx10<0x014>;
1356defm V_LSHRREV_B32        : VOP2_Real_gfx6_gfx7_gfx10<0x016>;
1357defm V_ASHRREV_I32        : VOP2_Real_gfx6_gfx7_gfx10<0x018>;
1358defm V_LSHLREV_B32        : VOP2_Real_gfx6_gfx7_gfx10<0x01a>;
1359defm V_AND_B32            : VOP2_Real_gfx6_gfx7_gfx10<0x01b>;
1360defm V_OR_B32             : VOP2_Real_gfx6_gfx7_gfx10<0x01c>;
1361defm V_XOR_B32            : VOP2_Real_gfx6_gfx7_gfx10<0x01d>;
1362defm V_MAC_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x01f>;
1363defm V_CVT_PKRTZ_F16_F32  : VOP2_Real_gfx6_gfx7_gfx10<0x02f>;
1364defm V_MADMK_F32          : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x020>;
1365defm V_MADAK_F32          : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x021>;
1366
1367//===----------------------------------------------------------------------===//
1368// GFX8, GFX9 (VI).
1369//===----------------------------------------------------------------------===//
1370
1371let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
1372
1373multiclass VOP2_Real_MADK_vi <bits<6> op> {
1374  def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
1375            VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1376}
1377
1378multiclass VOP2_Real_e32_vi <bits<6> op> {
1379  def _e32_vi :
1380    VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
1381    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
1382}
1383
1384multiclass VOP2_Real_e64_vi <bits<10> op> {
1385  def _e64_vi :
1386    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1387    VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1388}
1389
1390multiclass VOP2_Real_e64only_vi <bits<10> op> {
1391  def _e64_vi :
1392    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1393    VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1394      // Hack to stop printing _e64
1395      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME#"_e64");
1396      let OutOperandList = (outs VGPR_32:$vdst);
1397      let AsmString = ps.Mnemonic # " " # ps.AsmOperands;
1398    }
1399}
1400
1401multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> :
1402  VOP2_Real_e32_vi<op>,
1403  VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;
1404
1405} // End AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8"
1406
1407multiclass VOP2_SDWA_Real <bits<6> op> {
1408  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA>.ret in
1409  def _sdwa_vi :
1410    VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1411    VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1412}
1413
1414multiclass VOP2_SDWA9_Real <bits<6> op> {
1415  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
1416  def _sdwa_gfx9 :
1417    VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1418    VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1419}
1420
1421let AssemblerPredicate = isGFX8Only in {
1422
1423multiclass VOP2be_Real_e32e64_vi_only <bits<6> op, string OpName, string AsmName> {
1424  def _e32_vi :
1425    VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.VI>,
1426    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
1427      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
1428      let AsmString = AsmName # ps.AsmOperands;
1429      let DecoderNamespace = "GFX8";
1430    }
1431  def _e64_vi :
1432    VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.VI>,
1433    VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
1434      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");
1435      let AsmString = AsmName # ps.AsmOperands;
1436      let DecoderNamespace = "GFX8";
1437    }
1438  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA>.ret in
1439    def _sdwa_vi :
1440      VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,
1441      VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
1442        VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");
1443        let AsmString = AsmName # ps.AsmOperands;
1444      }
1445  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in
1446    def _dpp_vi :
1447      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.VI>,
1448      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
1449        VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
1450        let AsmString = AsmName # ps.AsmOperands;
1451      }
1452}
1453}
1454
1455let AssemblerPredicate = isGFX9Only in {
1456
1457multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> {
1458  def _e32_gfx9 :
1459    VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>,
1460    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
1461      VOP2_Pseudo ps = !cast<VOP2_Pseudo>(OpName#"_e32");
1462      let AsmString = AsmName # ps.AsmOperands;
1463      let DecoderNamespace = "GFX9";
1464    }
1465  def _e64_gfx9 :
1466    VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>,
1467    VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
1468      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName#"_e64");
1469      let AsmString = AsmName # ps.AsmOperands;
1470      let DecoderNamespace = "GFX9";
1471    }
1472  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtSDWA9>.ret in
1473    def _sdwa_gfx9 :
1474      VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa")>,
1475      VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
1476        VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa");
1477        let AsmString = AsmName # ps.AsmOperands;
1478      }
1479  foreach _ = BoolToList<!cast<VOP2_Pseudo>(OpName#"_e32").Pfl.HasExtDPP>.ret in
1480    def _dpp_gfx9 :
1481      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.GFX9>,
1482      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
1483        VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
1484        let AsmString = AsmName # ps.AsmOperands;
1485        let DecoderNamespace = "SDWA9";
1486      }
1487}
1488
1489multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> {
1490  def _e32_gfx9 :
1491    VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>,
1492    VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>{
1493      let DecoderNamespace = "GFX9";
1494    }
1495  def _e64_gfx9 :
1496    VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
1497    VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
1498      let DecoderNamespace = "GFX9";
1499    }
1500  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
1501    def _sdwa_gfx9 :
1502      VOP_SDWA9_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1503      VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
1504      }
1505  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1506    def _dpp_gfx9 :
1507      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
1508      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
1509        let DecoderNamespace = "SDWA9";
1510      }
1511}
1512
1513} // AssemblerPredicate = isGFX9Only
1514
1515multiclass VOP2_Real_e32e64_vi <bits<6> op> :
1516  Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> {
1517
1518  foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
1519    def _dpp_vi :
1520      VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.VI>,
1521      VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
1522}
1523
1524defm V_CNDMASK_B32        : VOP2_Real_e32e64_vi <0x0>;
1525defm V_ADD_F32            : VOP2_Real_e32e64_vi <0x1>;
1526defm V_SUB_F32            : VOP2_Real_e32e64_vi <0x2>;
1527defm V_SUBREV_F32         : VOP2_Real_e32e64_vi <0x3>;
1528defm V_MUL_LEGACY_F32     : VOP2_Real_e32e64_vi <0x4>;
1529defm V_MUL_F32            : VOP2_Real_e32e64_vi <0x5>;
1530defm V_MUL_I32_I24        : VOP2_Real_e32e64_vi <0x6>;
1531defm V_MUL_HI_I32_I24     : VOP2_Real_e32e64_vi <0x7>;
1532defm V_MUL_U32_U24        : VOP2_Real_e32e64_vi <0x8>;
1533defm V_MUL_HI_U32_U24     : VOP2_Real_e32e64_vi <0x9>;
1534defm V_MIN_F32            : VOP2_Real_e32e64_vi <0xa>;
1535defm V_MAX_F32            : VOP2_Real_e32e64_vi <0xb>;
1536defm V_MIN_I32            : VOP2_Real_e32e64_vi <0xc>;
1537defm V_MAX_I32            : VOP2_Real_e32e64_vi <0xd>;
1538defm V_MIN_U32            : VOP2_Real_e32e64_vi <0xe>;
1539defm V_MAX_U32            : VOP2_Real_e32e64_vi <0xf>;
1540defm V_LSHRREV_B32        : VOP2_Real_e32e64_vi <0x10>;
1541defm V_ASHRREV_I32        : VOP2_Real_e32e64_vi <0x11>;
1542defm V_LSHLREV_B32        : VOP2_Real_e32e64_vi <0x12>;
1543defm V_AND_B32            : VOP2_Real_e32e64_vi <0x13>;
1544defm V_OR_B32             : VOP2_Real_e32e64_vi <0x14>;
1545defm V_XOR_B32            : VOP2_Real_e32e64_vi <0x15>;
1546defm V_MAC_F32            : VOP2_Real_e32e64_vi <0x16>;
1547defm V_MADMK_F32          : VOP2_Real_MADK_vi <0x17>;
1548defm V_MADAK_F32          : VOP2_Real_MADK_vi <0x18>;
1549
1550defm V_ADD_U32            : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_CO_U32",     "v_add_u32">;
1551defm V_SUB_U32            : VOP2be_Real_e32e64_vi_only <0x1a, "V_SUB_CO_U32",     "v_sub_u32">;
1552defm V_SUBREV_U32         : VOP2be_Real_e32e64_vi_only <0x1b, "V_SUBREV_CO_U32",  "v_subrev_u32">;
1553defm V_ADDC_U32           : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32",    "v_addc_u32">;
1554defm V_SUBB_U32           : VOP2be_Real_e32e64_vi_only <0x1d, "V_SUBB_U32",    "v_subb_u32">;
1555defm V_SUBBREV_U32        : VOP2be_Real_e32e64_vi_only <0x1e, "V_SUBBREV_U32", "v_subbrev_u32">;
1556
1557defm V_ADD_CO_U32         : VOP2be_Real_e32e64_gfx9 <0x19, "V_ADD_CO_U32",     "v_add_co_u32">;
1558defm V_SUB_CO_U32         : VOP2be_Real_e32e64_gfx9 <0x1a, "V_SUB_CO_U32",     "v_sub_co_u32">;
1559defm V_SUBREV_CO_U32      : VOP2be_Real_e32e64_gfx9 <0x1b, "V_SUBREV_CO_U32",  "v_subrev_co_u32">;
1560defm V_ADDC_CO_U32        : VOP2be_Real_e32e64_gfx9 <0x1c, "V_ADDC_U32",    "v_addc_co_u32">;
1561defm V_SUBB_CO_U32        : VOP2be_Real_e32e64_gfx9 <0x1d, "V_SUBB_U32",    "v_subb_co_u32">;
1562defm V_SUBBREV_CO_U32     : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_subbrev_co_u32">;
1563
1564defm V_ADD_U32            : VOP2_Real_e32e64_gfx9 <0x34>;
1565defm V_SUB_U32            : VOP2_Real_e32e64_gfx9 <0x35>;
1566defm V_SUBREV_U32         : VOP2_Real_e32e64_gfx9 <0x36>;
1567
1568defm V_BFM_B32            : VOP2_Real_e64only_vi <0x293>;
1569defm V_BCNT_U32_B32       : VOP2_Real_e64only_vi <0x28b>;
1570defm V_MBCNT_LO_U32_B32   : VOP2_Real_e64only_vi <0x28c>;
1571defm V_MBCNT_HI_U32_B32   : VOP2_Real_e64only_vi <0x28d>;
1572defm V_LDEXP_F32          : VOP2_Real_e64only_vi <0x288>;
1573defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>;
1574defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>;
1575defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>;
1576defm V_CVT_PKRTZ_F16_F32  : VOP2_Real_e64only_vi <0x296>;
1577defm V_CVT_PK_U16_U32     : VOP2_Real_e64only_vi <0x297>;
1578defm V_CVT_PK_I16_I32     : VOP2_Real_e64only_vi <0x298>;
1579
1580defm V_ADD_F16            : VOP2_Real_e32e64_vi <0x1f>;
1581defm V_SUB_F16            : VOP2_Real_e32e64_vi <0x20>;
1582defm V_SUBREV_F16         : VOP2_Real_e32e64_vi <0x21>;
1583defm V_MUL_F16            : VOP2_Real_e32e64_vi <0x22>;
1584defm V_MAC_F16            : VOP2_Real_e32e64_vi <0x23>;
1585defm V_MADMK_F16          : VOP2_Real_MADK_vi <0x24>;
1586defm V_MADAK_F16          : VOP2_Real_MADK_vi <0x25>;
1587defm V_ADD_U16            : VOP2_Real_e32e64_vi <0x26>;
1588defm V_SUB_U16            : VOP2_Real_e32e64_vi <0x27>;
1589defm V_SUBREV_U16         : VOP2_Real_e32e64_vi <0x28>;
1590defm V_MUL_LO_U16         : VOP2_Real_e32e64_vi <0x29>;
1591defm V_LSHLREV_B16        : VOP2_Real_e32e64_vi <0x2a>;
1592defm V_LSHRREV_B16        : VOP2_Real_e32e64_vi <0x2b>;
1593defm V_ASHRREV_I16        : VOP2_Real_e32e64_vi <0x2c>;
1594defm V_MAX_F16            : VOP2_Real_e32e64_vi <0x2d>;
1595defm V_MIN_F16            : VOP2_Real_e32e64_vi <0x2e>;
1596defm V_MAX_U16            : VOP2_Real_e32e64_vi <0x2f>;
1597defm V_MAX_I16            : VOP2_Real_e32e64_vi <0x30>;
1598defm V_MIN_U16            : VOP2_Real_e32e64_vi <0x31>;
1599defm V_MIN_I16            : VOP2_Real_e32e64_vi <0x32>;
1600defm V_LDEXP_F16          : VOP2_Real_e32e64_vi <0x33>;
1601
1602let SubtargetPredicate = isGFX8GFX9 in {
1603
1604// Aliases to simplify matching of floating-point instructions that
1605// are VOP2 on SI and VOP3 on VI.
1606class SI2_VI3Alias <string name, VOP3_Real inst> : InstAlias <
1607  name#" $dst, $src0, $src1",
1608  !if(inst.Pfl.HasOMod,
1609      (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0),
1610      (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0))
1611>, PredicateControl {
1612  let UseInstAsmMatchConverter = 0;
1613  let AsmVariantName = AMDGPUAsmVariants.VOP3;
1614}
1615
1616def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;
1617def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;
1618def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
1619def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
1620def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
1621
1622defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_vi>;
1623
1624} // End SubtargetPredicate = isGFX8GFX9
1625
1626let SubtargetPredicate = isGFX9Only in {
1627
1628defm : VOP2bInstAliases<V_ADD_U32_e32,     V_ADD_CO_U32_e32_gfx9,     "v_add_co_u32">;
1629defm : VOP2bInstAliases<V_ADDC_U32_e32,    V_ADDC_CO_U32_e32_gfx9,    "v_addc_co_u32">;
1630defm : VOP2bInstAliases<V_SUB_U32_e32,     V_SUB_CO_U32_e32_gfx9,     "v_sub_co_u32">;
1631defm : VOP2bInstAliases<V_SUBB_U32_e32,    V_SUBB_CO_U32_e32_gfx9,    "v_subb_co_u32">;
1632defm : VOP2bInstAliases<V_SUBREV_U32_e32,  V_SUBREV_CO_U32_e32_gfx9,  "v_subrev_co_u32">;
1633defm : VOP2bInstAliases<V_SUBBREV_U32_e32, V_SUBBREV_CO_U32_e32_gfx9, "v_subbrev_co_u32">;
1634
1635} // End SubtargetPredicate = isGFX9Only
1636
1637let SubtargetPredicate = HasDLInsts in {
1638
1639defm V_FMAC_F32 : VOP2_Real_e32e64_vi <0x3b>;
1640defm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>;
1641
1642} // End SubtargetPredicate = HasDLInsts
1643
1644multiclass VOP2_Real_DOT_ACC_gfx9<bits<6> op> : VOP2_Real_e32_vi<op> {
1645  def _dpp_vi : VOP2_DPP<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
1646}
1647
1648multiclass VOP2_Real_DOT_ACC_gfx10<bits<6> op> :
1649  VOP2_Real_e32_gfx10<op>,
1650  VOP2_Real_dpp_gfx10<op>,
1651  VOP2_Real_dpp8_gfx10<op>;
1652
1653let SubtargetPredicate = HasDot5Insts in {
1654  defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx9<0x37>;
1655  // NB: Opcode conflicts with V_DOT8C_I32_I4
1656  // This opcode exists in gfx 10.1* only
1657  defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx10<0x02>;
1658}
1659
1660let SubtargetPredicate = HasDot6Insts in {
1661  defm V_DOT4C_I32_I8  : VOP2_Real_DOT_ACC_gfx9<0x39>;
1662  defm V_DOT4C_I32_I8  : VOP2_Real_DOT_ACC_gfx10<0x0d>;
1663}
1664
1665let SubtargetPredicate = HasDot4Insts in {
1666  defm V_DOT2C_I32_I16 : VOP2_Real_DOT_ACC_gfx9<0x38>;
1667}
1668let SubtargetPredicate = HasDot3Insts in {
1669  defm V_DOT8C_I32_I4  : VOP2_Real_DOT_ACC_gfx9<0x3a>;
1670}
1671
1672let SubtargetPredicate = HasPkFmacF16Inst in {
1673defm V_PK_FMAC_F16 : VOP2_Real_e32_vi<0x3c>;
1674} // End SubtargetPredicate = HasPkFmacF16Inst
1675
1676let SubtargetPredicate = HasDot3Insts in {
1677  // NB: Opcode conflicts with V_DOT2C_F32_F16
1678  let DecoderNamespace = "GFX10_B" in
1679  defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx10<0x02>;
1680}
1681