xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/VINTERPInstructions.td (revision 43e29d03f416d7dda52112a29600a7c82ee1a91e) 
1//===-- VINTERPInstructions.td - VINTERP Instruction Definitions ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// VINTERP encoding
11//===----------------------------------------------------------------------===//
12
13class VINTERPe_gfx11 <bits<7> op, VOPProfile P> : Enc64 {
14  bits<8> vdst;
15  bits<4> src0_modifiers;
16  bits<9> src0;
17  bits<3> src1_modifiers;
18  bits<9> src1;
19  bits<3> src2_modifiers;
20  bits<9> src2;
21  bits<1> clamp;
22  bits<3> waitexp;
23
24  let Inst{31-26} = 0x33; // VOP3P encoding
25  let Inst{25-24} = 0x1; // VINTERP sub-encoding
26  let Inst{23}    = 0; // reserved
27
28  let Inst{7-0}   = vdst;
29  let Inst{10-8}  = waitexp;
30  let Inst{11}    = !if(P.HasOpSel, src0_modifiers{2}, 0); // op_sel(0)
31  let Inst{12}    = !if(P.HasOpSel, src1_modifiers{2}, 0); // op_sel(1)
32  let Inst{13}    = !if(P.HasOpSel, src2_modifiers{2}, 0); // op_sel(2)
33  let Inst{14}    = !if(P.HasOpSel, src0_modifiers{3}, 0); // op_sel(3)
34  let Inst{15}    = clamp;
35  let Inst{22-16} = op;
36  let Inst{40-32} = src0;
37  let Inst{49-41} = src1;
38  let Inst{58-50} = src2;
39  let Inst{61}    = src0_modifiers{0}; // neg(0)
40  let Inst{62}    = src1_modifiers{0}; // neg(1)
41  let Inst{63}    = src2_modifiers{0}; // neg(2)
42}
43
44//===----------------------------------------------------------------------===//
45// VOP3 VINTERP
46//===----------------------------------------------------------------------===//
47
48class VINTERP_Pseudo <string OpName, VOPProfile P, list<dag> pattern = []> :
49  VOP3_Pseudo<OpName, P, pattern, 0, 0> {
50  let AsmMatchConverter = "cvtVINTERP";
51  let mayRaiseFPException = 0;
52
53  let VOP3_OPSEL = 1;
54  let VINTERP = 1;
55}
56
57class VINTERP_Real <VOP_Pseudo ps, int EncodingFamily> :
58  VOP3_Real <ps, EncodingFamily> {
59  let VINTERP = 1;
60}
61
62def VOP3_VINTERP_F32 : VOPProfile<[f32, f32, f32, f32]> {
63  let HasOpSel = 0;
64  let HasModifiers = 1;
65
66  let Src0Mod = FPVRegInputMods;
67  let Src1Mod = FPVRegInputMods;
68  let Src2Mod = FPVRegInputMods;
69
70  let Outs64 = (outs VGPR_32:$vdst);
71  let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
72                   Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
73                   Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
74                   clampmod:$clamp,
75                   wait_exp:$waitexp);
76
77  let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$waitexp";
78}
79
80class VOP3_VINTERP_F16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
81  let HasOpSel = 1;
82  let HasModifiers = 1;
83
84  let Src0Mod = FPVRegInputMods;
85  let Src1Mod = FPVRegInputMods;
86  let Src2Mod = FPVRegInputMods;
87
88  let Outs64 = (outs VGPR_32:$vdst);
89  let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
90                   Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
91                   Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
92                   clampmod:$clamp, op_sel0:$op_sel,
93                   wait_exp:$waitexp);
94
95  let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$op_sel$waitexp";
96}
97
98//===----------------------------------------------------------------------===//
99// VINTERP Pseudo Instructions
100//===----------------------------------------------------------------------===//
101
102let SubtargetPredicate = isGFX11Plus in {
103
104let Uses = [M0, EXEC, MODE] in {
105def V_INTERP_P10_F32_inreg : VINTERP_Pseudo <"v_interp_p10_f32", VOP3_VINTERP_F32>;
106def V_INTERP_P2_F32_inreg : VINTERP_Pseudo <"v_interp_p2_f32", VOP3_VINTERP_F32>;
107def V_INTERP_P10_F16_F32_inreg :
108  VINTERP_Pseudo <"v_interp_p10_f16_f32", VOP3_VINTERP_F16<[f32, f32, f32, f32]>>;
109def V_INTERP_P2_F16_F32_inreg :
110  VINTERP_Pseudo <"v_interp_p2_f16_f32", VOP3_VINTERP_F16<[f16, f32, f32, f32]>>;
111} // Uses = [M0, EXEC, MODE]
112
113let Uses = [M0, EXEC] in {
114def V_INTERP_P10_RTZ_F16_F32_inreg :
115  VINTERP_Pseudo <"v_interp_p10_rtz_f16_f32", VOP3_VINTERP_F16<[f32, f32, f32, f32]>>;
116def V_INTERP_P2_RTZ_F16_F32_inreg :
117  VINTERP_Pseudo <"v_interp_p2_rtz_f16_f32", VOP3_VINTERP_F16<[f16, f32, f32, f32]>>;
118} // Uses = [M0, EXEC]
119
120} // SubtargetPredicate = isGFX11Plus
121
122class VInterpF32Pat <SDPatternOperator op, Instruction inst> : GCNPat <
123   (f32 (op
124      (VINTERPMods f32:$src0, i32:$src0_modifiers),
125      (VINTERPMods f32:$src1, i32:$src1_modifiers),
126      (VINTERPMods f32:$src2, i32:$src2_modifiers))),
127    (inst $src0_modifiers, $src0,
128          $src1_modifiers, $src1,
129          $src2_modifiers, $src2,
130          0, /* clamp */
131          7) /* wait_exp */
132>;
133
134def VINTERP_OPSEL {
135  int LOW = 0;
136  int HIGH = 0xa;
137}
138
139class VInterpF16Pat <SDPatternOperator op, Instruction inst,
140                     ValueType dst_type, bit high,
141                     list<ComplexPattern> pat> : GCNPat <
142   (dst_type (op
143      (pat[0] f32:$src0, i32:$src0_modifiers),
144      (pat[1] f32:$src1, i32:$src1_modifiers),
145      (pat[2] f32:$src2, i32:$src2_modifiers),
146      !if(high, (i1 -1), (i1 0)))),
147    (inst $src0_modifiers, $src0,
148          $src1_modifiers, $src1,
149          $src2_modifiers, $src2,
150          0, /* clamp */
151          /* op_sel = 0 */
152          7) /* wait_exp */
153>;
154
155multiclass VInterpF16Pat <SDPatternOperator op, Instruction inst,
156                          ValueType dst_type, list<ComplexPattern> high_pat> {
157  def : VInterpF16Pat<op, inst, dst_type, 0,
158                      [VINTERPMods, VINTERPMods, VINTERPMods]>;
159  def : VInterpF16Pat<op, inst, dst_type, 1, high_pat>;
160}
161
162def : VInterpF32Pat<int_amdgcn_interp_inreg_p10, V_INTERP_P10_F32_inreg>;
163def : VInterpF32Pat<int_amdgcn_interp_inreg_p2, V_INTERP_P2_F32_inreg>;
164defm : VInterpF16Pat<int_amdgcn_interp_inreg_p10_f16,
165                     V_INTERP_P10_F16_F32_inreg, f32,
166                     [VINTERPModsHi, VINTERPMods, VINTERPModsHi]>;
167defm : VInterpF16Pat<int_amdgcn_interp_inreg_p2_f16,
168                     V_INTERP_P2_F16_F32_inreg, f16,
169                     [VINTERPModsHi, VINTERPMods, VINTERPMods]>;
170
171//===----------------------------------------------------------------------===//
172// VINTERP Real Instructions
173//===----------------------------------------------------------------------===//
174
175let AssemblerPredicate = isGFX11Plus, DecoderNamespace = "GFX11" in {
176  multiclass VINTERP_Real_gfx11 <bits<7> op> {
177    def _gfx11 :
178      VINTERP_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX11>,
179      VINTERPe_gfx11<op, !cast<VOP3_Pseudo>(NAME).Pfl>;
180  }
181}
182
183defm V_INTERP_P10_F32_inreg  : VINTERP_Real_gfx11<0x000>;
184defm V_INTERP_P2_F32_inreg  : VINTERP_Real_gfx11<0x001>;
185defm V_INTERP_P10_F16_F32_inreg  : VINTERP_Real_gfx11<0x002>;
186defm V_INTERP_P2_F16_F32_inreg  : VINTERP_Real_gfx11<0x003>;
187defm V_INTERP_P10_RTZ_F16_F32_inreg  : VINTERP_Real_gfx11<0x004>;
188defm V_INTERP_P2_RTZ_F16_F32_inreg  : VINTERP_Real_gfx11<0x005>;
189