xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp (revision 924226fba12cc9a228c73b956e1b7fa24c60b055)
1 //===-- AMDGPUPALMetadata.cpp - Accumulate and print AMDGPU PAL metadata  -===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 ///
11 /// This class has methods called by AMDGPUAsmPrinter to accumulate and print
12 /// the PAL metadata.
13 //
14 //===----------------------------------------------------------------------===//
15 //
16 
17 #include "AMDGPUPALMetadata.h"
18 #include "AMDGPUPTNote.h"
19 #include "SIDefines.h"
20 #include "llvm/BinaryFormat/ELF.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/IR/Constants.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/AMDGPUMetadata.h"
25 #include "llvm/Support/EndianStream.h"
26 
27 using namespace llvm;
28 using namespace llvm::AMDGPU;
29 
30 // Read the PAL metadata from IR metadata, where it was put by the frontend.
31 void AMDGPUPALMetadata::readFromIR(Module &M) {
32   auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata.msgpack");
33   if (NamedMD && NamedMD->getNumOperands()) {
34     // This is the new msgpack format for metadata. It is a NamedMD containing
35     // an MDTuple containing an MDString containing the msgpack data.
36     BlobType = ELF::NT_AMDGPU_METADATA;
37     auto MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0));
38     if (MDN && MDN->getNumOperands()) {
39       if (auto MDS = dyn_cast<MDString>(MDN->getOperand(0)))
40         setFromMsgPackBlob(MDS->getString());
41     }
42     return;
43   }
44   BlobType = ELF::NT_AMD_PAL_METADATA;
45   NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
46   if (!NamedMD || !NamedMD->getNumOperands()) {
47     // Emit msgpack metadata by default
48     BlobType = ELF::NT_AMDGPU_METADATA;
49     return;
50   }
51   // This is the old reg=value pair format for metadata. It is a NamedMD
52   // containing an MDTuple containing a number of MDNodes each of which is an
53   // integer value, and each two integer values forms a key=value pair that we
54   // store as Registers[key]=value in the map.
55   auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
56   if (!Tuple)
57     return;
58   for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
59     auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
60     auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
61     if (!Key || !Val)
62       continue;
63     setRegister(Key->getZExtValue(), Val->getZExtValue());
64   }
65 }
66 
67 // Set PAL metadata from a binary blob from the applicable .note record.
68 // Returns false if bad format.  Blob must remain valid for the lifetime of the
69 // Metadata.
70 bool AMDGPUPALMetadata::setFromBlob(unsigned Type, StringRef Blob) {
71   BlobType = Type;
72   if (Type == ELF::NT_AMD_PAL_METADATA)
73     return setFromLegacyBlob(Blob);
74   return setFromMsgPackBlob(Blob);
75 }
76 
77 // Set PAL metadata from legacy (array of key=value pairs) blob.
78 bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) {
79   auto Data = reinterpret_cast<const uint32_t *>(Blob.data());
80   for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I)
81     setRegister(Data[I * 2], Data[I * 2 + 1]);
82   return true;
83 }
84 
85 // Set PAL metadata from msgpack blob.
86 bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) {
87   msgpack::Reader Reader(Blob);
88   return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false);
89 }
90 
91 // Given the calling convention, calculate the register number for rsrc1. In
92 // principle the register number could change in future hardware, but we know
93 // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
94 // we can use fixed values.
95 static unsigned getRsrc1Reg(CallingConv::ID CC) {
96   switch (CC) {
97   default:
98     return PALMD::R_2E12_COMPUTE_PGM_RSRC1;
99   case CallingConv::AMDGPU_LS:
100     return PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS;
101   case CallingConv::AMDGPU_HS:
102     return PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS;
103   case CallingConv::AMDGPU_ES:
104     return PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES;
105   case CallingConv::AMDGPU_GS:
106     return PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS;
107   case CallingConv::AMDGPU_VS:
108     return PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS;
109   case CallingConv::AMDGPU_PS:
110     return PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS;
111   }
112 }
113 
114 // Calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
115 // with a constant offset to access any non-register shader-specific PAL
116 // metadata key.
117 static unsigned getScratchSizeKey(CallingConv::ID CC) {
118   switch (CC) {
119   case CallingConv::AMDGPU_PS:
120     return PALMD::Key::PS_SCRATCH_SIZE;
121   case CallingConv::AMDGPU_VS:
122     return PALMD::Key::VS_SCRATCH_SIZE;
123   case CallingConv::AMDGPU_GS:
124     return PALMD::Key::GS_SCRATCH_SIZE;
125   case CallingConv::AMDGPU_ES:
126     return PALMD::Key::ES_SCRATCH_SIZE;
127   case CallingConv::AMDGPU_HS:
128     return PALMD::Key::HS_SCRATCH_SIZE;
129   case CallingConv::AMDGPU_LS:
130     return PALMD::Key::LS_SCRATCH_SIZE;
131   default:
132     return PALMD::Key::CS_SCRATCH_SIZE;
133   }
134 }
135 
136 // Set the rsrc1 register in the metadata for a particular shader stage.
137 // In fact this ORs the value into any previous setting of the register.
138 void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, unsigned Val) {
139   setRegister(getRsrc1Reg(CC), Val);
140 }
141 
142 // Set the rsrc2 register in the metadata for a particular shader stage.
143 // In fact this ORs the value into any previous setting of the register.
144 void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, unsigned Val) {
145   setRegister(getRsrc1Reg(CC) + 1, Val);
146 }
147 
148 // Set the SPI_PS_INPUT_ENA register in the metadata.
149 // In fact this ORs the value into any previous setting of the register.
150 void AMDGPUPALMetadata::setSpiPsInputEna(unsigned Val) {
151   setRegister(PALMD::R_A1B3_SPI_PS_INPUT_ENA, Val);
152 }
153 
154 // Set the SPI_PS_INPUT_ADDR register in the metadata.
155 // In fact this ORs the value into any previous setting of the register.
156 void AMDGPUPALMetadata::setSpiPsInputAddr(unsigned Val) {
157   setRegister(PALMD::R_A1B4_SPI_PS_INPUT_ADDR, Val);
158 }
159 
160 // Get a register from the metadata, or 0 if not currently set.
161 unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) {
162   auto Regs = getRegisters();
163   auto It = Regs.find(MsgPackDoc.getNode(Reg));
164   if (It == Regs.end())
165     return 0;
166   auto N = It->second;
167   if (N.getKind() != msgpack::Type::UInt)
168     return 0;
169   return N.getUInt();
170 }
171 
172 // Set a register in the metadata.
173 // In fact this ORs the value into any previous setting of the register.
174 void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) {
175   if (!isLegacy()) {
176     // In the new MsgPack format, ignore register numbered >= 0x10000000. It
177     // is a PAL ABI pseudo-register in the old non-MsgPack format.
178     if (Reg >= 0x10000000)
179       return;
180   }
181   auto &N = getRegisters()[MsgPackDoc.getNode(Reg)];
182   if (N.getKind() == msgpack::Type::UInt)
183     Val |= N.getUInt();
184   N = N.getDocument()->getNode(Val);
185 }
186 
187 // Set the entry point name for one shader.
188 void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) {
189   if (isLegacy())
190     return;
191   // Msgpack format.
192   getHwStage(CC)[".entry_point"] = MsgPackDoc.getNode(Name, /*Copy=*/true);
193 }
194 
195 // Set the number of used vgprs in the metadata. This is an optional
196 // advisory record for logging etc; wave dispatch actually uses the rsrc1
197 // register for the shader stage to determine the number of vgprs to
198 // allocate.
199 void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, unsigned Val) {
200   if (isLegacy()) {
201     // Old non-msgpack format.
202     unsigned NumUsedVgprsKey = getScratchSizeKey(CC) +
203                                PALMD::Key::VS_NUM_USED_VGPRS -
204                                PALMD::Key::VS_SCRATCH_SIZE;
205     setRegister(NumUsedVgprsKey, Val);
206     return;
207   }
208   // Msgpack format.
209   getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(Val);
210 }
211 
212 // Set the number of used sgprs in the metadata. This is an optional advisory
213 // record for logging etc; wave dispatch actually uses the rsrc1 register for
214 // the shader stage to determine the number of sgprs to allocate.
215 void AMDGPUPALMetadata::setNumUsedSgprs(CallingConv::ID CC, unsigned Val) {
216   if (isLegacy()) {
217     // Old non-msgpack format.
218     unsigned NumUsedSgprsKey = getScratchSizeKey(CC) +
219                                PALMD::Key::VS_NUM_USED_SGPRS -
220                                PALMD::Key::VS_SCRATCH_SIZE;
221     setRegister(NumUsedSgprsKey, Val);
222     return;
223   }
224   // Msgpack format.
225   getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(Val);
226 }
227 
228 // Set the scratch size in the metadata.
229 void AMDGPUPALMetadata::setScratchSize(CallingConv::ID CC, unsigned Val) {
230   if (isLegacy()) {
231     // Old non-msgpack format.
232     setRegister(getScratchSizeKey(CC), Val);
233     return;
234   }
235   // Msgpack format.
236   getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(Val);
237 }
238 
239 // Set the stack frame size of a function in the metadata.
240 void AMDGPUPALMetadata::setFunctionScratchSize(const MachineFunction &MF,
241                                                unsigned Val) {
242   auto Node = getShaderFunction(MF.getFunction().getName());
243   Node[".stack_frame_size_in_bytes"] = MsgPackDoc.getNode(Val);
244 }
245 
246 // Set the amount of LDS used in bytes in the metadata.
247 void AMDGPUPALMetadata::setFunctionLdsSize(const MachineFunction &MF,
248                                            unsigned Val) {
249   auto Node = getShaderFunction(MF.getFunction().getName());
250   Node[".lds_size"] = MsgPackDoc.getNode(Val);
251 }
252 
253 // Set the number of used vgprs in the metadata.
254 void AMDGPUPALMetadata::setFunctionNumUsedVgprs(const MachineFunction &MF,
255                                                 unsigned Val) {
256   auto Node = getShaderFunction(MF.getFunction().getName());
257   Node[".vgpr_count"] = MsgPackDoc.getNode(Val);
258 }
259 
260 // Set the number of used vgprs in the metadata.
261 void AMDGPUPALMetadata::setFunctionNumUsedSgprs(const MachineFunction &MF,
262                                                 unsigned Val) {
263   auto Node = getShaderFunction(MF.getFunction().getName());
264   Node[".sgpr_count"] = MsgPackDoc.getNode(Val);
265 }
266 
267 // Set the hardware register bit in PAL metadata to enable wave32 on the
268 // shader of the given calling convention.
269 void AMDGPUPALMetadata::setWave32(unsigned CC) {
270   switch (CC) {
271   case CallingConv::AMDGPU_HS:
272     setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_HS_W32_EN(1));
273     break;
274   case CallingConv::AMDGPU_GS:
275     setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_GS_W32_EN(1));
276     break;
277   case CallingConv::AMDGPU_VS:
278     setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_VS_W32_EN(1));
279     break;
280   case CallingConv::AMDGPU_PS:
281     setRegister(PALMD::R_A1B6_SPI_PS_IN_CONTROL, S_0286D8_PS_W32_EN(1));
282     break;
283   case CallingConv::AMDGPU_CS:
284     setRegister(PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR,
285                 S_00B800_CS_W32_EN(1));
286     break;
287   }
288 }
289 
290 // Convert a register number to name, for display by toString().
291 // Returns nullptr if none.
292 static const char *getRegisterName(unsigned RegNum) {
293   // Table of registers.
294   static const struct RegInfo {
295     unsigned Num;
296     const char *Name;
297   } RegInfoTable[] = {
298       // Registers that code generation sets/modifies metadata for.
299       {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS, "SPI_SHADER_PGM_RSRC1_VS"},
300       {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1, "SPI_SHADER_PGM_RSRC2_VS"},
301       {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, "SPI_SHADER_PGM_RSRC1_LS"},
302       {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, "SPI_SHADER_PGM_RSRC2_LS"},
303       {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, "SPI_SHADER_PGM_RSRC1_HS"},
304       {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, "SPI_SHADER_PGM_RSRC2_HS"},
305       {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, "SPI_SHADER_PGM_RSRC1_ES"},
306       {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"},
307       {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"},
308       {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"},
309       {PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, "COMPUTE_DISPATCH_INITIATOR"},
310       {PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"},
311       {PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"},
312       {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"},
313       {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"},
314       {PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"},
315       {PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"},
316       {PALMD::R_A1B6_SPI_PS_IN_CONTROL, "SPI_PS_IN_CONTROL"},
317       {PALMD::R_A2D5_VGT_SHADER_STAGES_EN, "VGT_SHADER_STAGES_EN"},
318 
319       // Registers not known to code generation.
320       {0x2c07, "SPI_SHADER_PGM_RSRC3_PS"},
321       {0x2c46, "SPI_SHADER_PGM_RSRC3_VS"},
322       {0x2c87, "SPI_SHADER_PGM_RSRC3_GS"},
323       {0x2cc7, "SPI_SHADER_PGM_RSRC3_ES"},
324       {0x2d07, "SPI_SHADER_PGM_RSRC3_HS"},
325       {0x2d47, "SPI_SHADER_PGM_RSRC3_LS"},
326 
327       {0xa1c3, "SPI_SHADER_POS_FORMAT"},
328       {0xa1b1, "SPI_VS_OUT_CONFIG"},
329       {0xa207, "PA_CL_VS_OUT_CNTL"},
330       {0xa204, "PA_CL_CLIP_CNTL"},
331       {0xa206, "PA_CL_VTE_CNTL"},
332       {0xa2f9, "PA_SU_VTX_CNTL"},
333       {0xa293, "PA_SC_MODE_CNTL_1"},
334       {0xa2a1, "VGT_PRIMITIVEID_EN"},
335       {0x2c81, "SPI_SHADER_PGM_RSRC4_GS"},
336       {0x2e18, "COMPUTE_TMPRING_SIZE"},
337       {0xa1b5, "SPI_INTERP_CONTROL_0"},
338       {0xa1ba, "SPI_TMPRING_SIZE"},
339       {0xa1c4, "SPI_SHADER_Z_FORMAT"},
340       {0xa1c5, "SPI_SHADER_COL_FORMAT"},
341       {0xa203, "DB_SHADER_CONTROL"},
342       {0xa08f, "CB_SHADER_MASK"},
343       {0xa191, "SPI_PS_INPUT_CNTL_0"},
344       {0xa192, "SPI_PS_INPUT_CNTL_1"},
345       {0xa193, "SPI_PS_INPUT_CNTL_2"},
346       {0xa194, "SPI_PS_INPUT_CNTL_3"},
347       {0xa195, "SPI_PS_INPUT_CNTL_4"},
348       {0xa196, "SPI_PS_INPUT_CNTL_5"},
349       {0xa197, "SPI_PS_INPUT_CNTL_6"},
350       {0xa198, "SPI_PS_INPUT_CNTL_7"},
351       {0xa199, "SPI_PS_INPUT_CNTL_8"},
352       {0xa19a, "SPI_PS_INPUT_CNTL_9"},
353       {0xa19b, "SPI_PS_INPUT_CNTL_10"},
354       {0xa19c, "SPI_PS_INPUT_CNTL_11"},
355       {0xa19d, "SPI_PS_INPUT_CNTL_12"},
356       {0xa19e, "SPI_PS_INPUT_CNTL_13"},
357       {0xa19f, "SPI_PS_INPUT_CNTL_14"},
358       {0xa1a0, "SPI_PS_INPUT_CNTL_15"},
359       {0xa1a1, "SPI_PS_INPUT_CNTL_16"},
360       {0xa1a2, "SPI_PS_INPUT_CNTL_17"},
361       {0xa1a3, "SPI_PS_INPUT_CNTL_18"},
362       {0xa1a4, "SPI_PS_INPUT_CNTL_19"},
363       {0xa1a5, "SPI_PS_INPUT_CNTL_20"},
364       {0xa1a6, "SPI_PS_INPUT_CNTL_21"},
365       {0xa1a7, "SPI_PS_INPUT_CNTL_22"},
366       {0xa1a8, "SPI_PS_INPUT_CNTL_23"},
367       {0xa1a9, "SPI_PS_INPUT_CNTL_24"},
368       {0xa1aa, "SPI_PS_INPUT_CNTL_25"},
369       {0xa1ab, "SPI_PS_INPUT_CNTL_26"},
370       {0xa1ac, "SPI_PS_INPUT_CNTL_27"},
371       {0xa1ad, "SPI_PS_INPUT_CNTL_28"},
372       {0xa1ae, "SPI_PS_INPUT_CNTL_29"},
373       {0xa1af, "SPI_PS_INPUT_CNTL_30"},
374       {0xa1b0, "SPI_PS_INPUT_CNTL_31"},
375 
376       {0xa2ce, "VGT_GS_MAX_VERT_OUT"},
377       {0xa2ab, "VGT_ESGS_RING_ITEMSIZE"},
378       {0xa290, "VGT_GS_MODE"},
379       {0xa291, "VGT_GS_ONCHIP_CNTL"},
380       {0xa2d7, "VGT_GS_VERT_ITEMSIZE"},
381       {0xa2d8, "VGT_GS_VERT_ITEMSIZE_1"},
382       {0xa2d9, "VGT_GS_VERT_ITEMSIZE_2"},
383       {0xa2da, "VGT_GS_VERT_ITEMSIZE_3"},
384       {0xa298, "VGT_GSVS_RING_OFFSET_1"},
385       {0xa299, "VGT_GSVS_RING_OFFSET_2"},
386       {0xa29a, "VGT_GSVS_RING_OFFSET_3"},
387 
388       {0xa2e4, "VGT_GS_INSTANCE_CNT"},
389       {0xa297, "VGT_GS_PER_VS"},
390       {0xa29b, "VGT_GS_OUT_PRIM_TYPE"},
391       {0xa2ac, "VGT_GSVS_RING_ITEMSIZE"},
392 
393       {0xa2ad, "VGT_REUSE_OFF"},
394       {0xa1b8, "SPI_BARYC_CNTL"},
395 
396       {0x2c4c, "SPI_SHADER_USER_DATA_VS_0"},
397       {0x2c4d, "SPI_SHADER_USER_DATA_VS_1"},
398       {0x2c4e, "SPI_SHADER_USER_DATA_VS_2"},
399       {0x2c4f, "SPI_SHADER_USER_DATA_VS_3"},
400       {0x2c50, "SPI_SHADER_USER_DATA_VS_4"},
401       {0x2c51, "SPI_SHADER_USER_DATA_VS_5"},
402       {0x2c52, "SPI_SHADER_USER_DATA_VS_6"},
403       {0x2c53, "SPI_SHADER_USER_DATA_VS_7"},
404       {0x2c54, "SPI_SHADER_USER_DATA_VS_8"},
405       {0x2c55, "SPI_SHADER_USER_DATA_VS_9"},
406       {0x2c56, "SPI_SHADER_USER_DATA_VS_10"},
407       {0x2c57, "SPI_SHADER_USER_DATA_VS_11"},
408       {0x2c58, "SPI_SHADER_USER_DATA_VS_12"},
409       {0x2c59, "SPI_SHADER_USER_DATA_VS_13"},
410       {0x2c5a, "SPI_SHADER_USER_DATA_VS_14"},
411       {0x2c5b, "SPI_SHADER_USER_DATA_VS_15"},
412       {0x2c5c, "SPI_SHADER_USER_DATA_VS_16"},
413       {0x2c5d, "SPI_SHADER_USER_DATA_VS_17"},
414       {0x2c5e, "SPI_SHADER_USER_DATA_VS_18"},
415       {0x2c5f, "SPI_SHADER_USER_DATA_VS_19"},
416       {0x2c60, "SPI_SHADER_USER_DATA_VS_20"},
417       {0x2c61, "SPI_SHADER_USER_DATA_VS_21"},
418       {0x2c62, "SPI_SHADER_USER_DATA_VS_22"},
419       {0x2c63, "SPI_SHADER_USER_DATA_VS_23"},
420       {0x2c64, "SPI_SHADER_USER_DATA_VS_24"},
421       {0x2c65, "SPI_SHADER_USER_DATA_VS_25"},
422       {0x2c66, "SPI_SHADER_USER_DATA_VS_26"},
423       {0x2c67, "SPI_SHADER_USER_DATA_VS_27"},
424       {0x2c68, "SPI_SHADER_USER_DATA_VS_28"},
425       {0x2c69, "SPI_SHADER_USER_DATA_VS_29"},
426       {0x2c6a, "SPI_SHADER_USER_DATA_VS_30"},
427       {0x2c6b, "SPI_SHADER_USER_DATA_VS_31"},
428 
429       {0x2c8c, "SPI_SHADER_USER_DATA_GS_0"},
430       {0x2c8d, "SPI_SHADER_USER_DATA_GS_1"},
431       {0x2c8e, "SPI_SHADER_USER_DATA_GS_2"},
432       {0x2c8f, "SPI_SHADER_USER_DATA_GS_3"},
433       {0x2c90, "SPI_SHADER_USER_DATA_GS_4"},
434       {0x2c91, "SPI_SHADER_USER_DATA_GS_5"},
435       {0x2c92, "SPI_SHADER_USER_DATA_GS_6"},
436       {0x2c93, "SPI_SHADER_USER_DATA_GS_7"},
437       {0x2c94, "SPI_SHADER_USER_DATA_GS_8"},
438       {0x2c95, "SPI_SHADER_USER_DATA_GS_9"},
439       {0x2c96, "SPI_SHADER_USER_DATA_GS_10"},
440       {0x2c97, "SPI_SHADER_USER_DATA_GS_11"},
441       {0x2c98, "SPI_SHADER_USER_DATA_GS_12"},
442       {0x2c99, "SPI_SHADER_USER_DATA_GS_13"},
443       {0x2c9a, "SPI_SHADER_USER_DATA_GS_14"},
444       {0x2c9b, "SPI_SHADER_USER_DATA_GS_15"},
445       {0x2c9c, "SPI_SHADER_USER_DATA_GS_16"},
446       {0x2c9d, "SPI_SHADER_USER_DATA_GS_17"},
447       {0x2c9e, "SPI_SHADER_USER_DATA_GS_18"},
448       {0x2c9f, "SPI_SHADER_USER_DATA_GS_19"},
449       {0x2ca0, "SPI_SHADER_USER_DATA_GS_20"},
450       {0x2ca1, "SPI_SHADER_USER_DATA_GS_21"},
451       {0x2ca2, "SPI_SHADER_USER_DATA_GS_22"},
452       {0x2ca3, "SPI_SHADER_USER_DATA_GS_23"},
453       {0x2ca4, "SPI_SHADER_USER_DATA_GS_24"},
454       {0x2ca5, "SPI_SHADER_USER_DATA_GS_25"},
455       {0x2ca6, "SPI_SHADER_USER_DATA_GS_26"},
456       {0x2ca7, "SPI_SHADER_USER_DATA_GS_27"},
457       {0x2ca8, "SPI_SHADER_USER_DATA_GS_28"},
458       {0x2ca9, "SPI_SHADER_USER_DATA_GS_29"},
459       {0x2caa, "SPI_SHADER_USER_DATA_GS_30"},
460       {0x2cab, "SPI_SHADER_USER_DATA_GS_31"},
461 
462       {0x2ccc, "SPI_SHADER_USER_DATA_ES_0"},
463       {0x2ccd, "SPI_SHADER_USER_DATA_ES_1"},
464       {0x2cce, "SPI_SHADER_USER_DATA_ES_2"},
465       {0x2ccf, "SPI_SHADER_USER_DATA_ES_3"},
466       {0x2cd0, "SPI_SHADER_USER_DATA_ES_4"},
467       {0x2cd1, "SPI_SHADER_USER_DATA_ES_5"},
468       {0x2cd2, "SPI_SHADER_USER_DATA_ES_6"},
469       {0x2cd3, "SPI_SHADER_USER_DATA_ES_7"},
470       {0x2cd4, "SPI_SHADER_USER_DATA_ES_8"},
471       {0x2cd5, "SPI_SHADER_USER_DATA_ES_9"},
472       {0x2cd6, "SPI_SHADER_USER_DATA_ES_10"},
473       {0x2cd7, "SPI_SHADER_USER_DATA_ES_11"},
474       {0x2cd8, "SPI_SHADER_USER_DATA_ES_12"},
475       {0x2cd9, "SPI_SHADER_USER_DATA_ES_13"},
476       {0x2cda, "SPI_SHADER_USER_DATA_ES_14"},
477       {0x2cdb, "SPI_SHADER_USER_DATA_ES_15"},
478       {0x2cdc, "SPI_SHADER_USER_DATA_ES_16"},
479       {0x2cdd, "SPI_SHADER_USER_DATA_ES_17"},
480       {0x2cde, "SPI_SHADER_USER_DATA_ES_18"},
481       {0x2cdf, "SPI_SHADER_USER_DATA_ES_19"},
482       {0x2ce0, "SPI_SHADER_USER_DATA_ES_20"},
483       {0x2ce1, "SPI_SHADER_USER_DATA_ES_21"},
484       {0x2ce2, "SPI_SHADER_USER_DATA_ES_22"},
485       {0x2ce3, "SPI_SHADER_USER_DATA_ES_23"},
486       {0x2ce4, "SPI_SHADER_USER_DATA_ES_24"},
487       {0x2ce5, "SPI_SHADER_USER_DATA_ES_25"},
488       {0x2ce6, "SPI_SHADER_USER_DATA_ES_26"},
489       {0x2ce7, "SPI_SHADER_USER_DATA_ES_27"},
490       {0x2ce8, "SPI_SHADER_USER_DATA_ES_28"},
491       {0x2ce9, "SPI_SHADER_USER_DATA_ES_29"},
492       {0x2cea, "SPI_SHADER_USER_DATA_ES_30"},
493       {0x2ceb, "SPI_SHADER_USER_DATA_ES_31"},
494 
495       {0x2c0c, "SPI_SHADER_USER_DATA_PS_0"},
496       {0x2c0d, "SPI_SHADER_USER_DATA_PS_1"},
497       {0x2c0e, "SPI_SHADER_USER_DATA_PS_2"},
498       {0x2c0f, "SPI_SHADER_USER_DATA_PS_3"},
499       {0x2c10, "SPI_SHADER_USER_DATA_PS_4"},
500       {0x2c11, "SPI_SHADER_USER_DATA_PS_5"},
501       {0x2c12, "SPI_SHADER_USER_DATA_PS_6"},
502       {0x2c13, "SPI_SHADER_USER_DATA_PS_7"},
503       {0x2c14, "SPI_SHADER_USER_DATA_PS_8"},
504       {0x2c15, "SPI_SHADER_USER_DATA_PS_9"},
505       {0x2c16, "SPI_SHADER_USER_DATA_PS_10"},
506       {0x2c17, "SPI_SHADER_USER_DATA_PS_11"},
507       {0x2c18, "SPI_SHADER_USER_DATA_PS_12"},
508       {0x2c19, "SPI_SHADER_USER_DATA_PS_13"},
509       {0x2c1a, "SPI_SHADER_USER_DATA_PS_14"},
510       {0x2c1b, "SPI_SHADER_USER_DATA_PS_15"},
511       {0x2c1c, "SPI_SHADER_USER_DATA_PS_16"},
512       {0x2c1d, "SPI_SHADER_USER_DATA_PS_17"},
513       {0x2c1e, "SPI_SHADER_USER_DATA_PS_18"},
514       {0x2c1f, "SPI_SHADER_USER_DATA_PS_19"},
515       {0x2c20, "SPI_SHADER_USER_DATA_PS_20"},
516       {0x2c21, "SPI_SHADER_USER_DATA_PS_21"},
517       {0x2c22, "SPI_SHADER_USER_DATA_PS_22"},
518       {0x2c23, "SPI_SHADER_USER_DATA_PS_23"},
519       {0x2c24, "SPI_SHADER_USER_DATA_PS_24"},
520       {0x2c25, "SPI_SHADER_USER_DATA_PS_25"},
521       {0x2c26, "SPI_SHADER_USER_DATA_PS_26"},
522       {0x2c27, "SPI_SHADER_USER_DATA_PS_27"},
523       {0x2c28, "SPI_SHADER_USER_DATA_PS_28"},
524       {0x2c29, "SPI_SHADER_USER_DATA_PS_29"},
525       {0x2c2a, "SPI_SHADER_USER_DATA_PS_30"},
526       {0x2c2b, "SPI_SHADER_USER_DATA_PS_31"},
527 
528       {0x2e40, "COMPUTE_USER_DATA_0"},
529       {0x2e41, "COMPUTE_USER_DATA_1"},
530       {0x2e42, "COMPUTE_USER_DATA_2"},
531       {0x2e43, "COMPUTE_USER_DATA_3"},
532       {0x2e44, "COMPUTE_USER_DATA_4"},
533       {0x2e45, "COMPUTE_USER_DATA_5"},
534       {0x2e46, "COMPUTE_USER_DATA_6"},
535       {0x2e47, "COMPUTE_USER_DATA_7"},
536       {0x2e48, "COMPUTE_USER_DATA_8"},
537       {0x2e49, "COMPUTE_USER_DATA_9"},
538       {0x2e4a, "COMPUTE_USER_DATA_10"},
539       {0x2e4b, "COMPUTE_USER_DATA_11"},
540       {0x2e4c, "COMPUTE_USER_DATA_12"},
541       {0x2e4d, "COMPUTE_USER_DATA_13"},
542       {0x2e4e, "COMPUTE_USER_DATA_14"},
543       {0x2e4f, "COMPUTE_USER_DATA_15"},
544 
545       {0x2e07, "COMPUTE_NUM_THREAD_X"},
546       {0x2e08, "COMPUTE_NUM_THREAD_Y"},
547       {0x2e09, "COMPUTE_NUM_THREAD_Z"},
548       {0xa2db, "VGT_TF_PARAM"},
549       {0xa2d6, "VGT_LS_HS_CONFIG"},
550       {0xa287, "VGT_HOS_MIN_TESS_LEVEL"},
551       {0xa286, "VGT_HOS_MAX_TESS_LEVEL"},
552       {0xa2f8, "PA_SC_AA_CONFIG"},
553       {0xa310, "PA_SC_SHADER_CONTROL"},
554       {0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"},
555 
556       {0x2d0c, "SPI_SHADER_USER_DATA_HS_0"},
557       {0x2d0d, "SPI_SHADER_USER_DATA_HS_1"},
558       {0x2d0e, "SPI_SHADER_USER_DATA_HS_2"},
559       {0x2d0f, "SPI_SHADER_USER_DATA_HS_3"},
560       {0x2d10, "SPI_SHADER_USER_DATA_HS_4"},
561       {0x2d11, "SPI_SHADER_USER_DATA_HS_5"},
562       {0x2d12, "SPI_SHADER_USER_DATA_HS_6"},
563       {0x2d13, "SPI_SHADER_USER_DATA_HS_7"},
564       {0x2d14, "SPI_SHADER_USER_DATA_HS_8"},
565       {0x2d15, "SPI_SHADER_USER_DATA_HS_9"},
566       {0x2d16, "SPI_SHADER_USER_DATA_HS_10"},
567       {0x2d17, "SPI_SHADER_USER_DATA_HS_11"},
568       {0x2d18, "SPI_SHADER_USER_DATA_HS_12"},
569       {0x2d19, "SPI_SHADER_USER_DATA_HS_13"},
570       {0x2d1a, "SPI_SHADER_USER_DATA_HS_14"},
571       {0x2d1b, "SPI_SHADER_USER_DATA_HS_15"},
572       {0x2d1c, "SPI_SHADER_USER_DATA_HS_16"},
573       {0x2d1d, "SPI_SHADER_USER_DATA_HS_17"},
574       {0x2d1e, "SPI_SHADER_USER_DATA_HS_18"},
575       {0x2d1f, "SPI_SHADER_USER_DATA_HS_19"},
576       {0x2d20, "SPI_SHADER_USER_DATA_HS_20"},
577       {0x2d21, "SPI_SHADER_USER_DATA_HS_21"},
578       {0x2d22, "SPI_SHADER_USER_DATA_HS_22"},
579       {0x2d23, "SPI_SHADER_USER_DATA_HS_23"},
580       {0x2d24, "SPI_SHADER_USER_DATA_HS_24"},
581       {0x2d25, "SPI_SHADER_USER_DATA_HS_25"},
582       {0x2d26, "SPI_SHADER_USER_DATA_HS_26"},
583       {0x2d27, "SPI_SHADER_USER_DATA_HS_27"},
584       {0x2d28, "SPI_SHADER_USER_DATA_HS_28"},
585       {0x2d29, "SPI_SHADER_USER_DATA_HS_29"},
586       {0x2d2a, "SPI_SHADER_USER_DATA_HS_30"},
587       {0x2d2b, "SPI_SHADER_USER_DATA_HS_31"},
588 
589       {0x2d4c, "SPI_SHADER_USER_DATA_LS_0"},
590       {0x2d4d, "SPI_SHADER_USER_DATA_LS_1"},
591       {0x2d4e, "SPI_SHADER_USER_DATA_LS_2"},
592       {0x2d4f, "SPI_SHADER_USER_DATA_LS_3"},
593       {0x2d50, "SPI_SHADER_USER_DATA_LS_4"},
594       {0x2d51, "SPI_SHADER_USER_DATA_LS_5"},
595       {0x2d52, "SPI_SHADER_USER_DATA_LS_6"},
596       {0x2d53, "SPI_SHADER_USER_DATA_LS_7"},
597       {0x2d54, "SPI_SHADER_USER_DATA_LS_8"},
598       {0x2d55, "SPI_SHADER_USER_DATA_LS_9"},
599       {0x2d56, "SPI_SHADER_USER_DATA_LS_10"},
600       {0x2d57, "SPI_SHADER_USER_DATA_LS_11"},
601       {0x2d58, "SPI_SHADER_USER_DATA_LS_12"},
602       {0x2d59, "SPI_SHADER_USER_DATA_LS_13"},
603       {0x2d5a, "SPI_SHADER_USER_DATA_LS_14"},
604       {0x2d5b, "SPI_SHADER_USER_DATA_LS_15"},
605 
606       {0xa2aa, "IA_MULTI_VGT_PARAM"},
607       {0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"},
608       {0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"},
609       {0xa2e5, "VGT_STRMOUT_CONFIG"},
610       {0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"},
611       {0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"},
612       {0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"},
613       {0xa2c1, "VGT_STRMOUT_VTX_STRIDE_3"},
614       {0xa316, "VGT_VERTEX_REUSE_BLOCK_CNTL"},
615 
616       {0x2e28, "COMPUTE_PGM_RSRC3"},
617       {0x2e2a, "COMPUTE_SHADER_CHKSUM"},
618       {0x2e24, "COMPUTE_USER_ACCUM_0"},
619       {0x2e25, "COMPUTE_USER_ACCUM_1"},
620       {0x2e26, "COMPUTE_USER_ACCUM_2"},
621       {0x2e27, "COMPUTE_USER_ACCUM_3"},
622       {0xa1ff, "GE_MAX_OUTPUT_PER_SUBGROUP"},
623       {0xa2d3, "GE_NGG_SUBGRP_CNTL"},
624       {0xc25f, "GE_STEREO_CNTL"},
625       {0xc262, "GE_USER_VGPR_EN"},
626       {0xc258, "IA_MULTI_VGT_PARAM_PIPED"},
627       {0xa210, "PA_STEREO_CNTL"},
628       {0xa1c2, "SPI_SHADER_IDX_FORMAT"},
629       {0x2c80, "SPI_SHADER_PGM_CHKSUM_GS"},
630       {0x2d00, "SPI_SHADER_PGM_CHKSUM_HS"},
631       {0x2c06, "SPI_SHADER_PGM_CHKSUM_PS"},
632       {0x2c45, "SPI_SHADER_PGM_CHKSUM_VS"},
633       {0x2c88, "SPI_SHADER_PGM_LO_GS"},
634       {0x2cb2, "SPI_SHADER_USER_ACCUM_ESGS_0"},
635       {0x2cb3, "SPI_SHADER_USER_ACCUM_ESGS_1"},
636       {0x2cb4, "SPI_SHADER_USER_ACCUM_ESGS_2"},
637       {0x2cb5, "SPI_SHADER_USER_ACCUM_ESGS_3"},
638       {0x2d32, "SPI_SHADER_USER_ACCUM_LSHS_0"},
639       {0x2d33, "SPI_SHADER_USER_ACCUM_LSHS_1"},
640       {0x2d34, "SPI_SHADER_USER_ACCUM_LSHS_2"},
641       {0x2d35, "SPI_SHADER_USER_ACCUM_LSHS_3"},
642       {0x2c32, "SPI_SHADER_USER_ACCUM_PS_0"},
643       {0x2c33, "SPI_SHADER_USER_ACCUM_PS_1"},
644       {0x2c34, "SPI_SHADER_USER_ACCUM_PS_2"},
645       {0x2c35, "SPI_SHADER_USER_ACCUM_PS_3"},
646       {0x2c72, "SPI_SHADER_USER_ACCUM_VS_0"},
647       {0x2c73, "SPI_SHADER_USER_ACCUM_VS_1"},
648       {0x2c74, "SPI_SHADER_USER_ACCUM_VS_2"},
649       {0x2c75, "SPI_SHADER_USER_ACCUM_VS_3"},
650 
651       {0, nullptr}};
652   auto Entry = RegInfoTable;
653   for (; Entry->Num && Entry->Num != RegNum; ++Entry)
654     ;
655   return Entry->Name;
656 }
657 
658 // Convert the accumulated PAL metadata into an asm directive.
659 void AMDGPUPALMetadata::toString(std::string &String) {
660   String.clear();
661   if (!BlobType)
662     return;
663   raw_string_ostream Stream(String);
664   if (isLegacy()) {
665     if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil)
666       return;
667     // Old linear reg=val format.
668     Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' ';
669     auto Regs = getRegisters();
670     for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
671       if (I != Regs.begin())
672         Stream << ',';
673       unsigned Reg = I->first.getUInt();
674       unsigned Val = I->second.getUInt();
675       Stream << "0x" << Twine::utohexstr(Reg) << ",0x" << Twine::utohexstr(Val);
676     }
677     Stream << '\n';
678     return;
679   }
680 
681   // New msgpack-based format -- output as YAML (with unsigned numbers in hex),
682   // but first change the registers map to use names.
683   MsgPackDoc.setHexMode();
684   auto &RegsObj = refRegisters();
685   auto OrigRegs = RegsObj.getMap();
686   RegsObj = MsgPackDoc.getMapNode();
687   for (auto I : OrigRegs) {
688     auto Key = I.first;
689     if (const char *RegName = getRegisterName(Key.getUInt())) {
690       std::string KeyName = Key.toString();
691       KeyName += " (";
692       KeyName += RegName;
693       KeyName += ')';
694       Key = MsgPackDoc.getNode(KeyName, /*Copy=*/true);
695     }
696     RegsObj.getMap()[Key] = I.second;
697   }
698 
699   // Output as YAML.
700   Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n';
701   MsgPackDoc.toYAML(Stream);
702   Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n';
703 
704   // Restore original registers map.
705   RegsObj = OrigRegs;
706 }
707 
708 // Convert the accumulated PAL metadata into a binary blob for writing as
709 // a .note record of the specified AMD type. Returns an empty blob if
710 // there is no PAL metadata,
711 void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) {
712   if (Type == ELF::NT_AMD_PAL_METADATA)
713     toLegacyBlob(Blob);
714   else if (Type)
715     toMsgPackBlob(Blob);
716 }
717 
718 void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) {
719   Blob.clear();
720   auto Registers = getRegisters();
721   if (Registers.getMap().empty())
722     return;
723   raw_string_ostream OS(Blob);
724   support::endian::Writer EW(OS, support::endianness::little);
725   for (auto I : Registers.getMap()) {
726     EW.write(uint32_t(I.first.getUInt()));
727     EW.write(uint32_t(I.second.getUInt()));
728   }
729 }
730 
731 void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) {
732   Blob.clear();
733   MsgPackDoc.writeToBlob(Blob);
734 }
735 
736 // Set PAL metadata from YAML text. Returns false if failed.
737 bool AMDGPUPALMetadata::setFromString(StringRef S) {
738   BlobType = ELF::NT_AMDGPU_METADATA;
739   if (!MsgPackDoc.fromYAML(S))
740     return false;
741 
742   // In the registers map, some keys may be of the form "0xa191
743   // (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a
744   // string. We need to turn it into a number.
745   auto &RegsObj = refRegisters();
746   auto OrigRegs = RegsObj;
747   RegsObj = MsgPackDoc.getMapNode();
748   Registers = RegsObj.getMap();
749   bool Ok = true;
750   for (auto I : OrigRegs.getMap()) {
751     auto Key = I.first;
752     if (Key.getKind() == msgpack::Type::String) {
753       StringRef S = Key.getString();
754       uint64_t Val;
755       if (S.consumeInteger(0, Val)) {
756         Ok = false;
757         errs() << "Unrecognized PAL metadata register key '" << S << "'\n";
758         continue;
759       }
760       Key = MsgPackDoc.getNode(uint64_t(Val));
761     }
762     Registers.getMap()[Key] = I.second;
763   }
764   return Ok;
765 }
766 
767 // Reference (create if necessary) the node for the registers map.
768 msgpack::DocNode &AMDGPUPALMetadata::refRegisters() {
769   auto &N =
770       MsgPackDoc.getRoot()
771           .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
772           .getArray(/*Convert=*/true)[0]
773           .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".registers")];
774   N.getMap(/*Convert=*/true);
775   return N;
776 }
777 
778 // Get (create if necessary) the registers map.
779 msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() {
780   if (Registers.isEmpty())
781     Registers = refRegisters();
782   return Registers.getMap();
783 }
784 
785 // Reference (create if necessary) the node for the shader functions map.
786 msgpack::DocNode &AMDGPUPALMetadata::refShaderFunctions() {
787   auto &N =
788       MsgPackDoc.getRoot()
789           .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
790           .getArray(/*Convert=*/true)[0]
791           .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".shader_functions")];
792   N.getMap(/*Convert=*/true);
793   return N;
794 }
795 
796 // Get (create if necessary) the shader functions map.
797 msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunctions() {
798   if (ShaderFunctions.isEmpty())
799     ShaderFunctions = refShaderFunctions();
800   return ShaderFunctions.getMap();
801 }
802 
803 // Get (create if necessary) a function in the shader functions map.
804 msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunction(StringRef Name) {
805   auto Functions = getShaderFunctions();
806   return Functions[Name].getMap(/*Convert=*/true);
807 }
808 
809 // Return the PAL metadata hardware shader stage name.
810 static const char *getStageName(CallingConv::ID CC) {
811   switch (CC) {
812   case CallingConv::AMDGPU_PS:
813     return ".ps";
814   case CallingConv::AMDGPU_VS:
815     return ".vs";
816   case CallingConv::AMDGPU_GS:
817     return ".gs";
818   case CallingConv::AMDGPU_ES:
819     return ".es";
820   case CallingConv::AMDGPU_HS:
821     return ".hs";
822   case CallingConv::AMDGPU_LS:
823     return ".ls";
824   case CallingConv::AMDGPU_Gfx:
825     llvm_unreachable("Callable shader has no hardware stage");
826   default:
827     return ".cs";
828   }
829 }
830 
831 // Get (create if necessary) the .hardware_stages entry for the given calling
832 // convention.
833 msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) {
834   if (HwStages.isEmpty())
835     HwStages = MsgPackDoc.getRoot()
836                    .getMap(/*Convert=*/true)["amdpal.pipelines"]
837                    .getArray(/*Convert=*/true)[0]
838                    .getMap(/*Convert=*/true)[".hardware_stages"]
839                    .getMap(/*Convert=*/true);
840   return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true);
841 }
842 
843 // Get .note record vendor name of metadata blob to be emitted.
844 const char *AMDGPUPALMetadata::getVendor() const {
845   return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3;
846 }
847 
848 // Get .note record type of metadata blob to be emitted:
849 // ELF::NT_AMD_PAL_METADATA (legacy key=val format), or
850 // ELF::NT_AMDGPU_METADATA (MsgPack format), or
851 // 0 (no PAL metadata).
852 unsigned AMDGPUPALMetadata::getType() const {
853   return BlobType;
854 }
855 
856 // Return whether the blob type is legacy PAL metadata.
857 bool AMDGPUPALMetadata::isLegacy() const {
858   return BlobType == ELF::NT_AMD_PAL_METADATA;
859 }
860 
861 // Set legacy PAL metadata format.
862 void AMDGPUPALMetadata::setLegacy() {
863   BlobType = ELF::NT_AMD_PAL_METADATA;
864 }
865 
866 // Erase all PAL metadata.
867 void AMDGPUPALMetadata::reset() {
868   MsgPackDoc.clear();
869   Registers = MsgPackDoc.getEmptyNode();
870   HwStages = MsgPackDoc.getEmptyNode();
871 }
872