1 //===-- AMDGPUPALMetadata.cpp - Accumulate and print AMDGPU PAL metadata -===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// 11 /// This class has methods called by AMDGPUAsmPrinter to accumulate and print 12 /// the PAL metadata. 13 // 14 //===----------------------------------------------------------------------===// 15 // 16 17 #include "AMDGPUPALMetadata.h" 18 #include "AMDGPUPTNote.h" 19 #include "SIDefines.h" 20 #include "llvm/BinaryFormat/ELF.h" 21 #include "llvm/IR/Constants.h" 22 #include "llvm/IR/Module.h" 23 #include "llvm/MC/MCExpr.h" 24 #include "llvm/Support/AMDGPUMetadata.h" 25 #include "llvm/Support/EndianStream.h" 26 #include "llvm/Support/VersionTuple.h" 27 28 using namespace llvm; 29 using namespace llvm::AMDGPU; 30 31 // Return the PAL metadata hardware shader stage name. 32 static const char *getStageName(CallingConv::ID CC) { 33 switch (CC) { 34 case CallingConv::AMDGPU_PS: 35 return ".ps"; 36 case CallingConv::AMDGPU_VS: 37 return ".vs"; 38 case CallingConv::AMDGPU_GS: 39 return ".gs"; 40 case CallingConv::AMDGPU_ES: 41 return ".es"; 42 case CallingConv::AMDGPU_HS: 43 return ".hs"; 44 case CallingConv::AMDGPU_LS: 45 return ".ls"; 46 case CallingConv::AMDGPU_Gfx: 47 llvm_unreachable("Callable shader has no hardware stage"); 48 default: 49 return ".cs"; 50 } 51 } 52 53 // Read the PAL metadata from IR metadata, where it was put by the frontend. 54 void AMDGPUPALMetadata::readFromIR(Module &M) { 55 auto *NamedMD = M.getNamedMetadata("amdgpu.pal.metadata.msgpack"); 56 if (NamedMD && NamedMD->getNumOperands()) { 57 // This is the new msgpack format for metadata. It is a NamedMD containing 58 // an MDTuple containing an MDString containing the msgpack data. 59 BlobType = ELF::NT_AMDGPU_METADATA; 60 auto *MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0)); 61 if (MDN && MDN->getNumOperands()) { 62 if (auto *MDS = dyn_cast<MDString>(MDN->getOperand(0))) 63 setFromMsgPackBlob(MDS->getString()); 64 } 65 return; 66 } 67 BlobType = ELF::NT_AMD_PAL_METADATA; 68 NamedMD = M.getNamedMetadata("amdgpu.pal.metadata"); 69 if (!NamedMD || !NamedMD->getNumOperands()) { 70 // Emit msgpack metadata by default 71 BlobType = ELF::NT_AMDGPU_METADATA; 72 return; 73 } 74 // This is the old reg=value pair format for metadata. It is a NamedMD 75 // containing an MDTuple containing a number of MDNodes each of which is an 76 // integer value, and each two integer values forms a key=value pair that we 77 // store as Registers[key]=value in the map. 78 auto *Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0)); 79 if (!Tuple) 80 return; 81 for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) { 82 auto *Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I)); 83 auto *Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1)); 84 if (!Key || !Val) 85 continue; 86 setRegister(Key->getZExtValue(), Val->getZExtValue()); 87 } 88 } 89 90 // Set PAL metadata from a binary blob from the applicable .note record. 91 // Returns false if bad format. Blob must remain valid for the lifetime of the 92 // Metadata. 93 bool AMDGPUPALMetadata::setFromBlob(unsigned Type, StringRef Blob) { 94 BlobType = Type; 95 if (Type == ELF::NT_AMD_PAL_METADATA) 96 return setFromLegacyBlob(Blob); 97 return setFromMsgPackBlob(Blob); 98 } 99 100 // Set PAL metadata from legacy (array of key=value pairs) blob. 101 bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) { 102 const auto *Data = reinterpret_cast<const uint32_t *>(Blob.data()); 103 for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I) 104 setRegister(Data[I * 2], Data[I * 2 + 1]); 105 return true; 106 } 107 108 // Set PAL metadata from msgpack blob. 109 bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) { 110 return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false); 111 } 112 113 // Given the calling convention, calculate the register number for rsrc1. In 114 // principle the register number could change in future hardware, but we know 115 // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so 116 // we can use fixed values. 117 static unsigned getRsrc1Reg(CallingConv::ID CC) { 118 switch (CC) { 119 default: 120 return PALMD::R_2E12_COMPUTE_PGM_RSRC1; 121 case CallingConv::AMDGPU_LS: 122 return PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS; 123 case CallingConv::AMDGPU_HS: 124 return PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS; 125 case CallingConv::AMDGPU_ES: 126 return PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES; 127 case CallingConv::AMDGPU_GS: 128 return PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS; 129 case CallingConv::AMDGPU_VS: 130 return PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS; 131 case CallingConv::AMDGPU_PS: 132 return PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS; 133 } 134 } 135 136 // Calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used 137 // with a constant offset to access any non-register shader-specific PAL 138 // metadata key. 139 static unsigned getScratchSizeKey(CallingConv::ID CC) { 140 switch (CC) { 141 case CallingConv::AMDGPU_PS: 142 return PALMD::Key::PS_SCRATCH_SIZE; 143 case CallingConv::AMDGPU_VS: 144 return PALMD::Key::VS_SCRATCH_SIZE; 145 case CallingConv::AMDGPU_GS: 146 return PALMD::Key::GS_SCRATCH_SIZE; 147 case CallingConv::AMDGPU_ES: 148 return PALMD::Key::ES_SCRATCH_SIZE; 149 case CallingConv::AMDGPU_HS: 150 return PALMD::Key::HS_SCRATCH_SIZE; 151 case CallingConv::AMDGPU_LS: 152 return PALMD::Key::LS_SCRATCH_SIZE; 153 default: 154 return PALMD::Key::CS_SCRATCH_SIZE; 155 } 156 } 157 158 // Set the rsrc1 register in the metadata for a particular shader stage. 159 // In fact this ORs the value into any previous setting of the register. 160 void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, unsigned Val) { 161 setRegister(getRsrc1Reg(CC), Val); 162 } 163 164 void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, const MCExpr *Val, 165 MCContext &Ctx) { 166 setRegister(getRsrc1Reg(CC), Val, Ctx); 167 } 168 169 // Set the rsrc2 register in the metadata for a particular shader stage. 170 // In fact this ORs the value into any previous setting of the register. 171 void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, unsigned Val) { 172 setRegister(getRsrc1Reg(CC) + 1, Val); 173 } 174 175 void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, const MCExpr *Val, 176 MCContext &Ctx) { 177 setRegister(getRsrc1Reg(CC) + 1, Val, Ctx); 178 } 179 180 // Set the SPI_PS_INPUT_ENA register in the metadata. 181 // In fact this ORs the value into any previous setting of the register. 182 void AMDGPUPALMetadata::setSpiPsInputEna(unsigned Val) { 183 setRegister(PALMD::R_A1B3_SPI_PS_INPUT_ENA, Val); 184 } 185 186 // Set the SPI_PS_INPUT_ADDR register in the metadata. 187 // In fact this ORs the value into any previous setting of the register. 188 void AMDGPUPALMetadata::setSpiPsInputAddr(unsigned Val) { 189 setRegister(PALMD::R_A1B4_SPI_PS_INPUT_ADDR, Val); 190 } 191 192 // Get a register from the metadata, or 0 if not currently set. 193 unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) { 194 auto Regs = getRegisters(); 195 auto It = Regs.find(MsgPackDoc.getNode(Reg)); 196 if (It == Regs.end()) 197 return 0; 198 auto N = It->second; 199 if (N.getKind() != msgpack::Type::UInt) 200 return 0; 201 return N.getUInt(); 202 } 203 204 // Set a register in the metadata. 205 // In fact this ORs the value into any previous setting of the register. 206 void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) { 207 if (!isLegacy()) { 208 // In the new MsgPack format, ignore register numbered >= 0x10000000. It 209 // is a PAL ABI pseudo-register in the old non-MsgPack format. 210 if (Reg >= 0x10000000) 211 return; 212 } 213 auto &N = getRegisters()[MsgPackDoc.getNode(Reg)]; 214 if (N.getKind() == msgpack::Type::UInt) 215 Val |= N.getUInt(); 216 N = N.getDocument()->getNode(Val); 217 } 218 219 // Set a register in the metadata. 220 // In fact this ORs the value into any previous setting of the register. 221 void AMDGPUPALMetadata::setRegister(unsigned Reg, const MCExpr *Val, 222 MCContext &Ctx) { 223 if (!isLegacy()) { 224 // In the new MsgPack format, ignore register numbered >= 0x10000000. It 225 // is a PAL ABI pseudo-register in the old non-MsgPack format. 226 if (Reg >= 0x10000000) 227 return; 228 } 229 auto &N = getRegisters()[MsgPackDoc.getNode(Reg)]; 230 auto [ExprIt, Inserted] = REM.try_emplace(Reg); 231 232 if (!Inserted) { 233 Val = MCBinaryExpr::createOr(Val, ExprIt->getSecond(), Ctx); 234 // This conditional may be redundant most of the time, but the alternate 235 // setRegister(unsigned, unsigned) could've been called while the 236 // conditional returns true (i.e., Reg exists in REM). 237 if (N.getKind() == msgpack::Type::UInt) { 238 const MCExpr *NExpr = MCConstantExpr::create(N.getUInt(), Ctx); 239 Val = MCBinaryExpr::createOr(Val, NExpr, Ctx); 240 } 241 } else if (N.getKind() == msgpack::Type::UInt) { 242 const MCExpr *NExpr = MCConstantExpr::create(N.getUInt(), Ctx); 243 Val = MCBinaryExpr::createOr(Val, NExpr, Ctx); 244 } else { 245 // Default to uint64_t 0 so additional calls to setRegister will allow 246 // propagate ORs. 247 N = (uint64_t)0; 248 } 249 ExprIt->second = Val; 250 DelayedExprs.assignDocNode(N, msgpack::Type::UInt, Val); 251 } 252 253 // Set the entry point name for one shader. 254 void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) { 255 if (isLegacy()) 256 return; 257 // Msgpack format. 258 // Entry point is updated to .entry_point_symbol and is set to the function 259 // name 260 getHwStage(CC)[".entry_point_symbol"] = 261 MsgPackDoc.getNode(Name, /*Copy=*/true); 262 263 // For PAL version 3.6 and above, entry_point is no longer required. 264 if (getPALVersion() < VersionTuple(3, 6)) { 265 // Set .entry_point which is defined to be _amdgpu_<stage>_main and 266 // _amdgpu_cs_main for non-shader functions. 267 SmallString<16> EPName("_amdgpu_"); 268 raw_svector_ostream EPNameOS(EPName); 269 EPNameOS << getStageName(CC) + 1 << "_main"; 270 getHwStage(CC)[".entry_point"] = 271 MsgPackDoc.getNode(EPNameOS.str(), /*Copy=*/true); 272 } 273 } 274 275 // Set the number of used vgprs in the metadata. This is an optional 276 // advisory record for logging etc; wave dispatch actually uses the rsrc1 277 // register for the shader stage to determine the number of vgprs to 278 // allocate. 279 void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, unsigned Val) { 280 if (isLegacy()) { 281 // Old non-msgpack format. 282 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) + 283 PALMD::Key::VS_NUM_USED_VGPRS - 284 PALMD::Key::VS_SCRATCH_SIZE; 285 setRegister(NumUsedVgprsKey, Val); 286 return; 287 } 288 // Msgpack format. 289 getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(Val); 290 } 291 292 void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, const MCExpr *Val, 293 MCContext &Ctx) { 294 if (isLegacy()) { 295 // Old non-msgpack format. 296 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) + 297 PALMD::Key::VS_NUM_USED_VGPRS - 298 PALMD::Key::VS_SCRATCH_SIZE; 299 setRegister(NumUsedVgprsKey, Val, Ctx); 300 return; 301 } 302 // Msgpack format. 303 setHwStage(CC, ".vgpr_count", msgpack::Type::UInt, Val); 304 } 305 306 // Set the number of used agprs in the metadata. 307 void AMDGPUPALMetadata::setNumUsedAgprs(CallingConv::ID CC, unsigned Val) { 308 getHwStage(CC)[".agpr_count"] = Val; 309 } 310 311 void AMDGPUPALMetadata::setNumUsedAgprs(unsigned CC, const MCExpr *Val) { 312 setHwStage(CC, ".agpr_count", msgpack::Type::UInt, Val); 313 } 314 315 // Set the number of used sgprs in the metadata. This is an optional advisory 316 // record for logging etc; wave dispatch actually uses the rsrc1 register for 317 // the shader stage to determine the number of sgprs to allocate. 318 void AMDGPUPALMetadata::setNumUsedSgprs(CallingConv::ID CC, unsigned Val) { 319 if (isLegacy()) { 320 // Old non-msgpack format. 321 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) + 322 PALMD::Key::VS_NUM_USED_SGPRS - 323 PALMD::Key::VS_SCRATCH_SIZE; 324 setRegister(NumUsedSgprsKey, Val); 325 return; 326 } 327 // Msgpack format. 328 getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(Val); 329 } 330 331 void AMDGPUPALMetadata::setNumUsedSgprs(unsigned CC, const MCExpr *Val, 332 MCContext &Ctx) { 333 if (isLegacy()) { 334 // Old non-msgpack format. 335 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) + 336 PALMD::Key::VS_NUM_USED_SGPRS - 337 PALMD::Key::VS_SCRATCH_SIZE; 338 setRegister(NumUsedSgprsKey, Val, Ctx); 339 return; 340 } 341 // Msgpack format. 342 setHwStage(CC, ".sgpr_count", msgpack::Type::UInt, Val); 343 } 344 345 // Set the scratch size in the metadata. 346 void AMDGPUPALMetadata::setScratchSize(CallingConv::ID CC, unsigned Val) { 347 if (isLegacy()) { 348 // Old non-msgpack format. 349 setRegister(getScratchSizeKey(CC), Val); 350 return; 351 } 352 // Msgpack format. 353 getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(Val); 354 } 355 356 void AMDGPUPALMetadata::setScratchSize(unsigned CC, const MCExpr *Val, 357 MCContext &Ctx) { 358 if (isLegacy()) { 359 // Old non-msgpack format. 360 setRegister(getScratchSizeKey(CC), Val, Ctx); 361 return; 362 } 363 // Msgpack format. 364 setHwStage(CC, ".scratch_memory_size", msgpack::Type::UInt, Val); 365 } 366 367 // Set the stack frame size of a function in the metadata. 368 void AMDGPUPALMetadata::setFunctionScratchSize(StringRef FnName, unsigned Val) { 369 auto Node = getShaderFunction(FnName); 370 Node[".stack_frame_size_in_bytes"] = MsgPackDoc.getNode(Val); 371 Node[".backend_stack_size"] = MsgPackDoc.getNode(Val); 372 } 373 374 // Set the amount of LDS used in bytes in the metadata. 375 void AMDGPUPALMetadata::setFunctionLdsSize(StringRef FnName, unsigned Val) { 376 auto Node = getShaderFunction(FnName); 377 Node[".lds_size"] = MsgPackDoc.getNode(Val); 378 } 379 380 // Set the number of used vgprs in the metadata. 381 void AMDGPUPALMetadata::setFunctionNumUsedVgprs(StringRef FnName, 382 unsigned Val) { 383 auto Node = getShaderFunction(FnName); 384 Node[".vgpr_count"] = MsgPackDoc.getNode(Val); 385 } 386 387 void AMDGPUPALMetadata::setFunctionNumUsedVgprs(StringRef FnName, 388 const MCExpr *Val) { 389 auto Node = getShaderFunction(FnName); 390 DelayedExprs.assignDocNode(Node[".vgpr_count"], msgpack::Type::UInt, Val); 391 } 392 393 // Set the number of used vgprs in the metadata. 394 void AMDGPUPALMetadata::setFunctionNumUsedSgprs(StringRef FnName, 395 unsigned Val) { 396 auto Node = getShaderFunction(FnName); 397 Node[".sgpr_count"] = MsgPackDoc.getNode(Val); 398 } 399 400 void AMDGPUPALMetadata::setFunctionNumUsedSgprs(StringRef FnName, 401 const MCExpr *Val) { 402 auto Node = getShaderFunction(FnName); 403 DelayedExprs.assignDocNode(Node[".sgpr_count"], msgpack::Type::UInt, Val); 404 } 405 406 // Set the hardware register bit in PAL metadata to enable wave32 on the 407 // shader of the given calling convention. 408 void AMDGPUPALMetadata::setWave32(unsigned CC) { 409 switch (CC) { 410 case CallingConv::AMDGPU_HS: 411 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_HS_W32_EN(1)); 412 break; 413 case CallingConv::AMDGPU_GS: 414 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_GS_W32_EN(1)); 415 break; 416 case CallingConv::AMDGPU_VS: 417 setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_VS_W32_EN(1)); 418 break; 419 case CallingConv::AMDGPU_PS: 420 setRegister(PALMD::R_A1B6_SPI_PS_IN_CONTROL, S_0286D8_PS_W32_EN(1)); 421 break; 422 case CallingConv::AMDGPU_CS: 423 setRegister(PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, 424 S_00B800_CS_W32_EN(1)); 425 break; 426 } 427 } 428 429 // Convert a register number to name, for display by toString(). 430 // Returns nullptr if none. 431 static const char *getRegisterName(unsigned RegNum) { 432 // Table of registers. 433 static const struct RegInfo { 434 unsigned Num; 435 const char *Name; 436 } RegInfoTable[] = { 437 // Registers that code generation sets/modifies metadata for. 438 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS, "SPI_SHADER_PGM_RSRC1_VS"}, 439 {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1, "SPI_SHADER_PGM_RSRC2_VS"}, 440 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, "SPI_SHADER_PGM_RSRC1_LS"}, 441 {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, "SPI_SHADER_PGM_RSRC2_LS"}, 442 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, "SPI_SHADER_PGM_RSRC1_HS"}, 443 {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, "SPI_SHADER_PGM_RSRC2_HS"}, 444 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, "SPI_SHADER_PGM_RSRC1_ES"}, 445 {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"}, 446 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"}, 447 {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"}, 448 {PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, "COMPUTE_DISPATCH_INITIATOR"}, 449 {PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"}, 450 {PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"}, 451 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"}, 452 {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"}, 453 {PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"}, 454 {PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"}, 455 {PALMD::R_A1B6_SPI_PS_IN_CONTROL, "SPI_PS_IN_CONTROL"}, 456 {PALMD::R_A2D5_VGT_SHADER_STAGES_EN, "VGT_SHADER_STAGES_EN"}, 457 458 // Registers not known to code generation. 459 {0x2c07, "SPI_SHADER_PGM_RSRC3_PS"}, 460 {0x2c46, "SPI_SHADER_PGM_RSRC3_VS"}, 461 {0x2c87, "SPI_SHADER_PGM_RSRC3_GS"}, 462 {0x2cc7, "SPI_SHADER_PGM_RSRC3_ES"}, 463 {0x2d07, "SPI_SHADER_PGM_RSRC3_HS"}, 464 {0x2d47, "SPI_SHADER_PGM_RSRC3_LS"}, 465 466 {0xa1c3, "SPI_SHADER_POS_FORMAT"}, 467 {0xa1b1, "SPI_VS_OUT_CONFIG"}, 468 {0xa207, "PA_CL_VS_OUT_CNTL"}, 469 {0xa204, "PA_CL_CLIP_CNTL"}, 470 {0xa206, "PA_CL_VTE_CNTL"}, 471 {0xa2f9, "PA_SU_VTX_CNTL"}, 472 {0xa293, "PA_SC_MODE_CNTL_1"}, 473 {0xa2a1, "VGT_PRIMITIVEID_EN"}, 474 {0x2c81, "SPI_SHADER_PGM_RSRC4_GS"}, 475 {0x2e18, "COMPUTE_TMPRING_SIZE"}, 476 {0xa1b5, "SPI_INTERP_CONTROL_0"}, 477 {0xa1ba, "SPI_TMPRING_SIZE"}, 478 {0xa1c4, "SPI_SHADER_Z_FORMAT"}, 479 {0xa1c5, "SPI_SHADER_COL_FORMAT"}, 480 {0xa203, "DB_SHADER_CONTROL"}, 481 {0xa08f, "CB_SHADER_MASK"}, 482 {0xa191, "SPI_PS_INPUT_CNTL_0"}, 483 {0xa192, "SPI_PS_INPUT_CNTL_1"}, 484 {0xa193, "SPI_PS_INPUT_CNTL_2"}, 485 {0xa194, "SPI_PS_INPUT_CNTL_3"}, 486 {0xa195, "SPI_PS_INPUT_CNTL_4"}, 487 {0xa196, "SPI_PS_INPUT_CNTL_5"}, 488 {0xa197, "SPI_PS_INPUT_CNTL_6"}, 489 {0xa198, "SPI_PS_INPUT_CNTL_7"}, 490 {0xa199, "SPI_PS_INPUT_CNTL_8"}, 491 {0xa19a, "SPI_PS_INPUT_CNTL_9"}, 492 {0xa19b, "SPI_PS_INPUT_CNTL_10"}, 493 {0xa19c, "SPI_PS_INPUT_CNTL_11"}, 494 {0xa19d, "SPI_PS_INPUT_CNTL_12"}, 495 {0xa19e, "SPI_PS_INPUT_CNTL_13"}, 496 {0xa19f, "SPI_PS_INPUT_CNTL_14"}, 497 {0xa1a0, "SPI_PS_INPUT_CNTL_15"}, 498 {0xa1a1, "SPI_PS_INPUT_CNTL_16"}, 499 {0xa1a2, "SPI_PS_INPUT_CNTL_17"}, 500 {0xa1a3, "SPI_PS_INPUT_CNTL_18"}, 501 {0xa1a4, "SPI_PS_INPUT_CNTL_19"}, 502 {0xa1a5, "SPI_PS_INPUT_CNTL_20"}, 503 {0xa1a6, "SPI_PS_INPUT_CNTL_21"}, 504 {0xa1a7, "SPI_PS_INPUT_CNTL_22"}, 505 {0xa1a8, "SPI_PS_INPUT_CNTL_23"}, 506 {0xa1a9, "SPI_PS_INPUT_CNTL_24"}, 507 {0xa1aa, "SPI_PS_INPUT_CNTL_25"}, 508 {0xa1ab, "SPI_PS_INPUT_CNTL_26"}, 509 {0xa1ac, "SPI_PS_INPUT_CNTL_27"}, 510 {0xa1ad, "SPI_PS_INPUT_CNTL_28"}, 511 {0xa1ae, "SPI_PS_INPUT_CNTL_29"}, 512 {0xa1af, "SPI_PS_INPUT_CNTL_30"}, 513 {0xa1b0, "SPI_PS_INPUT_CNTL_31"}, 514 515 {0xa2ce, "VGT_GS_MAX_VERT_OUT"}, 516 {0xa2ab, "VGT_ESGS_RING_ITEMSIZE"}, 517 {0xa290, "VGT_GS_MODE"}, 518 {0xa291, "VGT_GS_ONCHIP_CNTL"}, 519 {0xa2d7, "VGT_GS_VERT_ITEMSIZE"}, 520 {0xa2d8, "VGT_GS_VERT_ITEMSIZE_1"}, 521 {0xa2d9, "VGT_GS_VERT_ITEMSIZE_2"}, 522 {0xa2da, "VGT_GS_VERT_ITEMSIZE_3"}, 523 {0xa298, "VGT_GSVS_RING_OFFSET_1"}, 524 {0xa299, "VGT_GSVS_RING_OFFSET_2"}, 525 {0xa29a, "VGT_GSVS_RING_OFFSET_3"}, 526 527 {0xa2e4, "VGT_GS_INSTANCE_CNT"}, 528 {0xa297, "VGT_GS_PER_VS"}, 529 {0xa29b, "VGT_GS_OUT_PRIM_TYPE"}, 530 {0xa2ac, "VGT_GSVS_RING_ITEMSIZE"}, 531 532 {0xa2ad, "VGT_REUSE_OFF"}, 533 {0xa1b8, "SPI_BARYC_CNTL"}, 534 535 {0x2c4c, "SPI_SHADER_USER_DATA_VS_0"}, 536 {0x2c4d, "SPI_SHADER_USER_DATA_VS_1"}, 537 {0x2c4e, "SPI_SHADER_USER_DATA_VS_2"}, 538 {0x2c4f, "SPI_SHADER_USER_DATA_VS_3"}, 539 {0x2c50, "SPI_SHADER_USER_DATA_VS_4"}, 540 {0x2c51, "SPI_SHADER_USER_DATA_VS_5"}, 541 {0x2c52, "SPI_SHADER_USER_DATA_VS_6"}, 542 {0x2c53, "SPI_SHADER_USER_DATA_VS_7"}, 543 {0x2c54, "SPI_SHADER_USER_DATA_VS_8"}, 544 {0x2c55, "SPI_SHADER_USER_DATA_VS_9"}, 545 {0x2c56, "SPI_SHADER_USER_DATA_VS_10"}, 546 {0x2c57, "SPI_SHADER_USER_DATA_VS_11"}, 547 {0x2c58, "SPI_SHADER_USER_DATA_VS_12"}, 548 {0x2c59, "SPI_SHADER_USER_DATA_VS_13"}, 549 {0x2c5a, "SPI_SHADER_USER_DATA_VS_14"}, 550 {0x2c5b, "SPI_SHADER_USER_DATA_VS_15"}, 551 {0x2c5c, "SPI_SHADER_USER_DATA_VS_16"}, 552 {0x2c5d, "SPI_SHADER_USER_DATA_VS_17"}, 553 {0x2c5e, "SPI_SHADER_USER_DATA_VS_18"}, 554 {0x2c5f, "SPI_SHADER_USER_DATA_VS_19"}, 555 {0x2c60, "SPI_SHADER_USER_DATA_VS_20"}, 556 {0x2c61, "SPI_SHADER_USER_DATA_VS_21"}, 557 {0x2c62, "SPI_SHADER_USER_DATA_VS_22"}, 558 {0x2c63, "SPI_SHADER_USER_DATA_VS_23"}, 559 {0x2c64, "SPI_SHADER_USER_DATA_VS_24"}, 560 {0x2c65, "SPI_SHADER_USER_DATA_VS_25"}, 561 {0x2c66, "SPI_SHADER_USER_DATA_VS_26"}, 562 {0x2c67, "SPI_SHADER_USER_DATA_VS_27"}, 563 {0x2c68, "SPI_SHADER_USER_DATA_VS_28"}, 564 {0x2c69, "SPI_SHADER_USER_DATA_VS_29"}, 565 {0x2c6a, "SPI_SHADER_USER_DATA_VS_30"}, 566 {0x2c6b, "SPI_SHADER_USER_DATA_VS_31"}, 567 568 {0x2c8c, "SPI_SHADER_USER_DATA_GS_0"}, 569 {0x2c8d, "SPI_SHADER_USER_DATA_GS_1"}, 570 {0x2c8e, "SPI_SHADER_USER_DATA_GS_2"}, 571 {0x2c8f, "SPI_SHADER_USER_DATA_GS_3"}, 572 {0x2c90, "SPI_SHADER_USER_DATA_GS_4"}, 573 {0x2c91, "SPI_SHADER_USER_DATA_GS_5"}, 574 {0x2c92, "SPI_SHADER_USER_DATA_GS_6"}, 575 {0x2c93, "SPI_SHADER_USER_DATA_GS_7"}, 576 {0x2c94, "SPI_SHADER_USER_DATA_GS_8"}, 577 {0x2c95, "SPI_SHADER_USER_DATA_GS_9"}, 578 {0x2c96, "SPI_SHADER_USER_DATA_GS_10"}, 579 {0x2c97, "SPI_SHADER_USER_DATA_GS_11"}, 580 {0x2c98, "SPI_SHADER_USER_DATA_GS_12"}, 581 {0x2c99, "SPI_SHADER_USER_DATA_GS_13"}, 582 {0x2c9a, "SPI_SHADER_USER_DATA_GS_14"}, 583 {0x2c9b, "SPI_SHADER_USER_DATA_GS_15"}, 584 {0x2c9c, "SPI_SHADER_USER_DATA_GS_16"}, 585 {0x2c9d, "SPI_SHADER_USER_DATA_GS_17"}, 586 {0x2c9e, "SPI_SHADER_USER_DATA_GS_18"}, 587 {0x2c9f, "SPI_SHADER_USER_DATA_GS_19"}, 588 {0x2ca0, "SPI_SHADER_USER_DATA_GS_20"}, 589 {0x2ca1, "SPI_SHADER_USER_DATA_GS_21"}, 590 {0x2ca2, "SPI_SHADER_USER_DATA_GS_22"}, 591 {0x2ca3, "SPI_SHADER_USER_DATA_GS_23"}, 592 {0x2ca4, "SPI_SHADER_USER_DATA_GS_24"}, 593 {0x2ca5, "SPI_SHADER_USER_DATA_GS_25"}, 594 {0x2ca6, "SPI_SHADER_USER_DATA_GS_26"}, 595 {0x2ca7, "SPI_SHADER_USER_DATA_GS_27"}, 596 {0x2ca8, "SPI_SHADER_USER_DATA_GS_28"}, 597 {0x2ca9, "SPI_SHADER_USER_DATA_GS_29"}, 598 {0x2caa, "SPI_SHADER_USER_DATA_GS_30"}, 599 {0x2cab, "SPI_SHADER_USER_DATA_GS_31"}, 600 601 {0x2ccc, "SPI_SHADER_USER_DATA_ES_0"}, 602 {0x2ccd, "SPI_SHADER_USER_DATA_ES_1"}, 603 {0x2cce, "SPI_SHADER_USER_DATA_ES_2"}, 604 {0x2ccf, "SPI_SHADER_USER_DATA_ES_3"}, 605 {0x2cd0, "SPI_SHADER_USER_DATA_ES_4"}, 606 {0x2cd1, "SPI_SHADER_USER_DATA_ES_5"}, 607 {0x2cd2, "SPI_SHADER_USER_DATA_ES_6"}, 608 {0x2cd3, "SPI_SHADER_USER_DATA_ES_7"}, 609 {0x2cd4, "SPI_SHADER_USER_DATA_ES_8"}, 610 {0x2cd5, "SPI_SHADER_USER_DATA_ES_9"}, 611 {0x2cd6, "SPI_SHADER_USER_DATA_ES_10"}, 612 {0x2cd7, "SPI_SHADER_USER_DATA_ES_11"}, 613 {0x2cd8, "SPI_SHADER_USER_DATA_ES_12"}, 614 {0x2cd9, "SPI_SHADER_USER_DATA_ES_13"}, 615 {0x2cda, "SPI_SHADER_USER_DATA_ES_14"}, 616 {0x2cdb, "SPI_SHADER_USER_DATA_ES_15"}, 617 {0x2cdc, "SPI_SHADER_USER_DATA_ES_16"}, 618 {0x2cdd, "SPI_SHADER_USER_DATA_ES_17"}, 619 {0x2cde, "SPI_SHADER_USER_DATA_ES_18"}, 620 {0x2cdf, "SPI_SHADER_USER_DATA_ES_19"}, 621 {0x2ce0, "SPI_SHADER_USER_DATA_ES_20"}, 622 {0x2ce1, "SPI_SHADER_USER_DATA_ES_21"}, 623 {0x2ce2, "SPI_SHADER_USER_DATA_ES_22"}, 624 {0x2ce3, "SPI_SHADER_USER_DATA_ES_23"}, 625 {0x2ce4, "SPI_SHADER_USER_DATA_ES_24"}, 626 {0x2ce5, "SPI_SHADER_USER_DATA_ES_25"}, 627 {0x2ce6, "SPI_SHADER_USER_DATA_ES_26"}, 628 {0x2ce7, "SPI_SHADER_USER_DATA_ES_27"}, 629 {0x2ce8, "SPI_SHADER_USER_DATA_ES_28"}, 630 {0x2ce9, "SPI_SHADER_USER_DATA_ES_29"}, 631 {0x2cea, "SPI_SHADER_USER_DATA_ES_30"}, 632 {0x2ceb, "SPI_SHADER_USER_DATA_ES_31"}, 633 634 {0x2c0c, "SPI_SHADER_USER_DATA_PS_0"}, 635 {0x2c0d, "SPI_SHADER_USER_DATA_PS_1"}, 636 {0x2c0e, "SPI_SHADER_USER_DATA_PS_2"}, 637 {0x2c0f, "SPI_SHADER_USER_DATA_PS_3"}, 638 {0x2c10, "SPI_SHADER_USER_DATA_PS_4"}, 639 {0x2c11, "SPI_SHADER_USER_DATA_PS_5"}, 640 {0x2c12, "SPI_SHADER_USER_DATA_PS_6"}, 641 {0x2c13, "SPI_SHADER_USER_DATA_PS_7"}, 642 {0x2c14, "SPI_SHADER_USER_DATA_PS_8"}, 643 {0x2c15, "SPI_SHADER_USER_DATA_PS_9"}, 644 {0x2c16, "SPI_SHADER_USER_DATA_PS_10"}, 645 {0x2c17, "SPI_SHADER_USER_DATA_PS_11"}, 646 {0x2c18, "SPI_SHADER_USER_DATA_PS_12"}, 647 {0x2c19, "SPI_SHADER_USER_DATA_PS_13"}, 648 {0x2c1a, "SPI_SHADER_USER_DATA_PS_14"}, 649 {0x2c1b, "SPI_SHADER_USER_DATA_PS_15"}, 650 {0x2c1c, "SPI_SHADER_USER_DATA_PS_16"}, 651 {0x2c1d, "SPI_SHADER_USER_DATA_PS_17"}, 652 {0x2c1e, "SPI_SHADER_USER_DATA_PS_18"}, 653 {0x2c1f, "SPI_SHADER_USER_DATA_PS_19"}, 654 {0x2c20, "SPI_SHADER_USER_DATA_PS_20"}, 655 {0x2c21, "SPI_SHADER_USER_DATA_PS_21"}, 656 {0x2c22, "SPI_SHADER_USER_DATA_PS_22"}, 657 {0x2c23, "SPI_SHADER_USER_DATA_PS_23"}, 658 {0x2c24, "SPI_SHADER_USER_DATA_PS_24"}, 659 {0x2c25, "SPI_SHADER_USER_DATA_PS_25"}, 660 {0x2c26, "SPI_SHADER_USER_DATA_PS_26"}, 661 {0x2c27, "SPI_SHADER_USER_DATA_PS_27"}, 662 {0x2c28, "SPI_SHADER_USER_DATA_PS_28"}, 663 {0x2c29, "SPI_SHADER_USER_DATA_PS_29"}, 664 {0x2c2a, "SPI_SHADER_USER_DATA_PS_30"}, 665 {0x2c2b, "SPI_SHADER_USER_DATA_PS_31"}, 666 667 {0x2e40, "COMPUTE_USER_DATA_0"}, 668 {0x2e41, "COMPUTE_USER_DATA_1"}, 669 {0x2e42, "COMPUTE_USER_DATA_2"}, 670 {0x2e43, "COMPUTE_USER_DATA_3"}, 671 {0x2e44, "COMPUTE_USER_DATA_4"}, 672 {0x2e45, "COMPUTE_USER_DATA_5"}, 673 {0x2e46, "COMPUTE_USER_DATA_6"}, 674 {0x2e47, "COMPUTE_USER_DATA_7"}, 675 {0x2e48, "COMPUTE_USER_DATA_8"}, 676 {0x2e49, "COMPUTE_USER_DATA_9"}, 677 {0x2e4a, "COMPUTE_USER_DATA_10"}, 678 {0x2e4b, "COMPUTE_USER_DATA_11"}, 679 {0x2e4c, "COMPUTE_USER_DATA_12"}, 680 {0x2e4d, "COMPUTE_USER_DATA_13"}, 681 {0x2e4e, "COMPUTE_USER_DATA_14"}, 682 {0x2e4f, "COMPUTE_USER_DATA_15"}, 683 684 {0x2e07, "COMPUTE_NUM_THREAD_X"}, 685 {0x2e08, "COMPUTE_NUM_THREAD_Y"}, 686 {0x2e09, "COMPUTE_NUM_THREAD_Z"}, 687 {0xa2db, "VGT_TF_PARAM"}, 688 {0xa2d6, "VGT_LS_HS_CONFIG"}, 689 {0xa287, "VGT_HOS_MIN_TESS_LEVEL"}, 690 {0xa286, "VGT_HOS_MAX_TESS_LEVEL"}, 691 {0xa2f8, "PA_SC_AA_CONFIG"}, 692 {0xa310, "PA_SC_SHADER_CONTROL"}, 693 {0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"}, 694 695 {0x2d0c, "SPI_SHADER_USER_DATA_HS_0"}, 696 {0x2d0d, "SPI_SHADER_USER_DATA_HS_1"}, 697 {0x2d0e, "SPI_SHADER_USER_DATA_HS_2"}, 698 {0x2d0f, "SPI_SHADER_USER_DATA_HS_3"}, 699 {0x2d10, "SPI_SHADER_USER_DATA_HS_4"}, 700 {0x2d11, "SPI_SHADER_USER_DATA_HS_5"}, 701 {0x2d12, "SPI_SHADER_USER_DATA_HS_6"}, 702 {0x2d13, "SPI_SHADER_USER_DATA_HS_7"}, 703 {0x2d14, "SPI_SHADER_USER_DATA_HS_8"}, 704 {0x2d15, "SPI_SHADER_USER_DATA_HS_9"}, 705 {0x2d16, "SPI_SHADER_USER_DATA_HS_10"}, 706 {0x2d17, "SPI_SHADER_USER_DATA_HS_11"}, 707 {0x2d18, "SPI_SHADER_USER_DATA_HS_12"}, 708 {0x2d19, "SPI_SHADER_USER_DATA_HS_13"}, 709 {0x2d1a, "SPI_SHADER_USER_DATA_HS_14"}, 710 {0x2d1b, "SPI_SHADER_USER_DATA_HS_15"}, 711 {0x2d1c, "SPI_SHADER_USER_DATA_HS_16"}, 712 {0x2d1d, "SPI_SHADER_USER_DATA_HS_17"}, 713 {0x2d1e, "SPI_SHADER_USER_DATA_HS_18"}, 714 {0x2d1f, "SPI_SHADER_USER_DATA_HS_19"}, 715 {0x2d20, "SPI_SHADER_USER_DATA_HS_20"}, 716 {0x2d21, "SPI_SHADER_USER_DATA_HS_21"}, 717 {0x2d22, "SPI_SHADER_USER_DATA_HS_22"}, 718 {0x2d23, "SPI_SHADER_USER_DATA_HS_23"}, 719 {0x2d24, "SPI_SHADER_USER_DATA_HS_24"}, 720 {0x2d25, "SPI_SHADER_USER_DATA_HS_25"}, 721 {0x2d26, "SPI_SHADER_USER_DATA_HS_26"}, 722 {0x2d27, "SPI_SHADER_USER_DATA_HS_27"}, 723 {0x2d28, "SPI_SHADER_USER_DATA_HS_28"}, 724 {0x2d29, "SPI_SHADER_USER_DATA_HS_29"}, 725 {0x2d2a, "SPI_SHADER_USER_DATA_HS_30"}, 726 {0x2d2b, "SPI_SHADER_USER_DATA_HS_31"}, 727 728 {0x2d4c, "SPI_SHADER_USER_DATA_LS_0"}, 729 {0x2d4d, "SPI_SHADER_USER_DATA_LS_1"}, 730 {0x2d4e, "SPI_SHADER_USER_DATA_LS_2"}, 731 {0x2d4f, "SPI_SHADER_USER_DATA_LS_3"}, 732 {0x2d50, "SPI_SHADER_USER_DATA_LS_4"}, 733 {0x2d51, "SPI_SHADER_USER_DATA_LS_5"}, 734 {0x2d52, "SPI_SHADER_USER_DATA_LS_6"}, 735 {0x2d53, "SPI_SHADER_USER_DATA_LS_7"}, 736 {0x2d54, "SPI_SHADER_USER_DATA_LS_8"}, 737 {0x2d55, "SPI_SHADER_USER_DATA_LS_9"}, 738 {0x2d56, "SPI_SHADER_USER_DATA_LS_10"}, 739 {0x2d57, "SPI_SHADER_USER_DATA_LS_11"}, 740 {0x2d58, "SPI_SHADER_USER_DATA_LS_12"}, 741 {0x2d59, "SPI_SHADER_USER_DATA_LS_13"}, 742 {0x2d5a, "SPI_SHADER_USER_DATA_LS_14"}, 743 {0x2d5b, "SPI_SHADER_USER_DATA_LS_15"}, 744 745 {0xa2aa, "IA_MULTI_VGT_PARAM"}, 746 {0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"}, 747 {0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"}, 748 {0xa2e5, "VGT_STRMOUT_CONFIG"}, 749 {0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"}, 750 {0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"}, 751 {0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"}, 752 {0xa2c1, "VGT_STRMOUT_VTX_STRIDE_3"}, 753 {0xa316, "VGT_VERTEX_REUSE_BLOCK_CNTL"}, 754 755 {0x2e28, "COMPUTE_PGM_RSRC3"}, 756 {0x2e2a, "COMPUTE_SHADER_CHKSUM"}, 757 {0x2e24, "COMPUTE_USER_ACCUM_0"}, 758 {0x2e25, "COMPUTE_USER_ACCUM_1"}, 759 {0x2e26, "COMPUTE_USER_ACCUM_2"}, 760 {0x2e27, "COMPUTE_USER_ACCUM_3"}, 761 {0xa1ff, "GE_MAX_OUTPUT_PER_SUBGROUP"}, 762 {0xa2d3, "GE_NGG_SUBGRP_CNTL"}, 763 {0xc25f, "GE_STEREO_CNTL"}, 764 {0xc262, "GE_USER_VGPR_EN"}, 765 {0xc258, "IA_MULTI_VGT_PARAM_PIPED"}, 766 {0xa210, "PA_STEREO_CNTL"}, 767 {0xa1c2, "SPI_SHADER_IDX_FORMAT"}, 768 {0x2c80, "SPI_SHADER_PGM_CHKSUM_GS"}, 769 {0x2d00, "SPI_SHADER_PGM_CHKSUM_HS"}, 770 {0x2c06, "SPI_SHADER_PGM_CHKSUM_PS"}, 771 {0x2c45, "SPI_SHADER_PGM_CHKSUM_VS"}, 772 {0x2c88, "SPI_SHADER_PGM_LO_GS"}, 773 {0x2cb2, "SPI_SHADER_USER_ACCUM_ESGS_0"}, 774 {0x2cb3, "SPI_SHADER_USER_ACCUM_ESGS_1"}, 775 {0x2cb4, "SPI_SHADER_USER_ACCUM_ESGS_2"}, 776 {0x2cb5, "SPI_SHADER_USER_ACCUM_ESGS_3"}, 777 {0x2d32, "SPI_SHADER_USER_ACCUM_LSHS_0"}, 778 {0x2d33, "SPI_SHADER_USER_ACCUM_LSHS_1"}, 779 {0x2d34, "SPI_SHADER_USER_ACCUM_LSHS_2"}, 780 {0x2d35, "SPI_SHADER_USER_ACCUM_LSHS_3"}, 781 {0x2c32, "SPI_SHADER_USER_ACCUM_PS_0"}, 782 {0x2c33, "SPI_SHADER_USER_ACCUM_PS_1"}, 783 {0x2c34, "SPI_SHADER_USER_ACCUM_PS_2"}, 784 {0x2c35, "SPI_SHADER_USER_ACCUM_PS_3"}, 785 {0x2c72, "SPI_SHADER_USER_ACCUM_VS_0"}, 786 {0x2c73, "SPI_SHADER_USER_ACCUM_VS_1"}, 787 {0x2c74, "SPI_SHADER_USER_ACCUM_VS_2"}, 788 {0x2c75, "SPI_SHADER_USER_ACCUM_VS_3"}, 789 790 {0, nullptr}}; 791 const auto *Entry = RegInfoTable; 792 for (; Entry->Num && Entry->Num != RegNum; ++Entry) 793 ; 794 return Entry->Name; 795 } 796 797 // Convert the accumulated PAL metadata into an asm directive. 798 void AMDGPUPALMetadata::toString(std::string &String) { 799 String.clear(); 800 if (!BlobType) 801 return; 802 ResolvedAll = DelayedExprs.resolveDelayedExpressions(); 803 raw_string_ostream Stream(String); 804 if (isLegacy()) { 805 if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil) 806 return; 807 // Old linear reg=val format. 808 Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' '; 809 auto Regs = getRegisters(); 810 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) { 811 if (I != Regs.begin()) 812 Stream << ','; 813 unsigned Reg = I->first.getUInt(); 814 unsigned Val = I->second.getUInt(); 815 Stream << "0x" << Twine::utohexstr(Reg) << ",0x" << Twine::utohexstr(Val); 816 } 817 Stream << '\n'; 818 return; 819 } 820 821 // New msgpack-based format -- output as YAML (with unsigned numbers in hex), 822 // but first change the registers map to use names. 823 MsgPackDoc.setHexMode(); 824 auto &RegsObj = refRegisters(); 825 auto OrigRegs = RegsObj.getMap(); 826 RegsObj = MsgPackDoc.getMapNode(); 827 for (auto I : OrigRegs) { 828 auto Key = I.first; 829 if (const char *RegName = getRegisterName(Key.getUInt())) { 830 std::string KeyName = Key.toString(); 831 KeyName += " ("; 832 KeyName += RegName; 833 KeyName += ')'; 834 Key = MsgPackDoc.getNode(KeyName, /*Copy=*/true); 835 } 836 RegsObj.getMap()[Key] = I.second; 837 } 838 839 // Output as YAML. 840 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n'; 841 MsgPackDoc.toYAML(Stream); 842 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n'; 843 844 // Restore original registers map. 845 RegsObj = OrigRegs; 846 } 847 848 // Convert the accumulated PAL metadata into a binary blob for writing as 849 // a .note record of the specified AMD type. Returns an empty blob if 850 // there is no PAL metadata, 851 void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) { 852 ResolvedAll = DelayedExprs.resolveDelayedExpressions(); 853 if (Type == ELF::NT_AMD_PAL_METADATA) 854 toLegacyBlob(Blob); 855 else if (Type) 856 toMsgPackBlob(Blob); 857 } 858 859 void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) { 860 Blob.clear(); 861 auto Registers = getRegisters(); 862 if (Registers.getMap().empty()) 863 return; 864 raw_string_ostream OS(Blob); 865 support::endian::Writer EW(OS, llvm::endianness::little); 866 for (auto I : Registers.getMap()) { 867 EW.write(uint32_t(I.first.getUInt())); 868 EW.write(uint32_t(I.second.getUInt())); 869 } 870 } 871 872 void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) { 873 Blob.clear(); 874 MsgPackDoc.writeToBlob(Blob); 875 } 876 877 // Set PAL metadata from YAML text. Returns false if failed. 878 bool AMDGPUPALMetadata::setFromString(StringRef S) { 879 BlobType = ELF::NT_AMDGPU_METADATA; 880 if (!MsgPackDoc.fromYAML(S)) 881 return false; 882 883 // In the registers map, some keys may be of the form "0xa191 884 // (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a 885 // string. We need to turn it into a number. 886 auto &RegsObj = refRegisters(); 887 auto OrigRegs = RegsObj; 888 RegsObj = MsgPackDoc.getMapNode(); 889 Registers = RegsObj.getMap(); 890 bool Ok = true; 891 for (auto I : OrigRegs.getMap()) { 892 auto Key = I.first; 893 if (Key.getKind() == msgpack::Type::String) { 894 StringRef S = Key.getString(); 895 uint64_t Val; 896 if (S.consumeInteger(0, Val)) { 897 Ok = false; 898 errs() << "Unrecognized PAL metadata register key '" << S << "'\n"; 899 continue; 900 } 901 Key = MsgPackDoc.getNode(Val); 902 } 903 Registers.getMap()[Key] = I.second; 904 } 905 return Ok; 906 } 907 908 // Reference (create if necessary) the node for the registers map. 909 msgpack::DocNode &AMDGPUPALMetadata::refRegisters() { 910 auto &N = 911 MsgPackDoc.getRoot() 912 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")] 913 .getArray(/*Convert=*/true)[0] 914 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".registers")]; 915 N.getMap(/*Convert=*/true); 916 return N; 917 } 918 919 // Get (create if necessary) the registers map. 920 msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() { 921 if (Registers.isEmpty()) 922 Registers = refRegisters(); 923 return Registers.getMap(); 924 } 925 926 // Reference (create if necessary) the node for the shader functions map. 927 msgpack::DocNode &AMDGPUPALMetadata::refShaderFunctions() { 928 auto &N = 929 MsgPackDoc.getRoot() 930 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")] 931 .getArray(/*Convert=*/true)[0] 932 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".shader_functions")]; 933 N.getMap(/*Convert=*/true); 934 return N; 935 } 936 937 // Get (create if necessary) the shader functions map. 938 msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunctions() { 939 if (ShaderFunctions.isEmpty()) 940 ShaderFunctions = refShaderFunctions(); 941 return ShaderFunctions.getMap(); 942 } 943 944 // Get (create if necessary) a function in the shader functions map. 945 msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunction(StringRef Name) { 946 auto Functions = getShaderFunctions(); 947 return Functions[Name].getMap(/*Convert=*/true); 948 } 949 950 msgpack::DocNode &AMDGPUPALMetadata::refComputeRegisters() { 951 auto &N = 952 MsgPackDoc.getRoot() 953 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")] 954 .getArray(/*Convert=*/true)[0] 955 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".compute_registers")]; 956 N.getMap(/*Convert=*/true); 957 return N; 958 } 959 960 msgpack::MapDocNode AMDGPUPALMetadata::getComputeRegisters() { 961 if (ComputeRegisters.isEmpty()) 962 ComputeRegisters = refComputeRegisters(); 963 return ComputeRegisters.getMap(); 964 } 965 966 msgpack::DocNode &AMDGPUPALMetadata::refGraphicsRegisters() { 967 auto &N = 968 MsgPackDoc.getRoot() 969 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")] 970 .getArray(/*Convert=*/true)[0] 971 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".graphics_registers")]; 972 N.getMap(/*Convert=*/true); 973 return N; 974 } 975 976 msgpack::MapDocNode AMDGPUPALMetadata::getGraphicsRegisters() { 977 if (GraphicsRegisters.isEmpty()) 978 GraphicsRegisters = refGraphicsRegisters(); 979 return GraphicsRegisters.getMap(); 980 } 981 982 msgpack::DocNode &AMDGPUPALMetadata::refHwStage() { 983 auto &N = 984 MsgPackDoc.getRoot() 985 .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")] 986 .getArray(/*Convert=*/true)[0] 987 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".hardware_stages")]; 988 N.getMap(/*Convert=*/true); 989 return N; 990 } 991 992 // Get (create if necessary) the .hardware_stages entry for the given calling 993 // convention. 994 msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) { 995 if (HwStages.isEmpty()) 996 HwStages = refHwStage(); 997 return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true); 998 } 999 1000 // Get .note record vendor name of metadata blob to be emitted. 1001 const char *AMDGPUPALMetadata::getVendor() const { 1002 return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3; 1003 } 1004 1005 // Get .note record type of metadata blob to be emitted: 1006 // ELF::NT_AMD_PAL_METADATA (legacy key=val format), or 1007 // ELF::NT_AMDGPU_METADATA (MsgPack format), or 1008 // 0 (no PAL metadata). 1009 unsigned AMDGPUPALMetadata::getType() const { 1010 return BlobType; 1011 } 1012 1013 // Return whether the blob type is legacy PAL metadata. 1014 bool AMDGPUPALMetadata::isLegacy() const { 1015 return BlobType == ELF::NT_AMD_PAL_METADATA; 1016 } 1017 1018 // Set legacy PAL metadata format. 1019 void AMDGPUPALMetadata::setLegacy() { 1020 BlobType = ELF::NT_AMD_PAL_METADATA; 1021 } 1022 1023 // Erase all PAL metadata. 1024 void AMDGPUPALMetadata::reset() { 1025 MsgPackDoc.clear(); 1026 REM.clear(); 1027 DelayedExprs.clear(); 1028 Registers = MsgPackDoc.getEmptyNode(); 1029 HwStages = MsgPackDoc.getEmptyNode(); 1030 ShaderFunctions = MsgPackDoc.getEmptyNode(); 1031 } 1032 1033 bool AMDGPUPALMetadata::resolvedAllMCExpr() { 1034 return ResolvedAll && DelayedExprs.empty(); 1035 } 1036 1037 unsigned AMDGPUPALMetadata::getPALVersion(unsigned idx) { 1038 assert(idx < 2 && 1039 "illegal index to PAL version - should be 0 (major) or 1 (minor)"); 1040 if (!VersionChecked) { 1041 if (Version.isEmpty()) { 1042 auto &M = MsgPackDoc.getRoot().getMap(/*Convert=*/true); 1043 auto I = M.find(MsgPackDoc.getNode("amdpal.version")); 1044 if (I != M.end()) 1045 Version = I->second; 1046 } 1047 VersionChecked = true; 1048 } 1049 if (Version.isEmpty()) 1050 // Default to 2.6 if there's no version info 1051 return idx ? 6 : 2; 1052 return Version.getArray()[idx].getUInt(); 1053 } 1054 1055 unsigned AMDGPUPALMetadata::getPALMajorVersion() { return getPALVersion(0); } 1056 1057 unsigned AMDGPUPALMetadata::getPALMinorVersion() { return getPALVersion(1); } 1058 1059 VersionTuple AMDGPUPALMetadata::getPALVersion() { 1060 return VersionTuple(getPALVersion(0), getPALVersion(1)); 1061 } 1062 1063 // Set the field in a given .hardware_stages entry 1064 void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, unsigned Val) { 1065 getHwStage(CC)[field] = Val; 1066 } 1067 1068 void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, bool Val) { 1069 getHwStage(CC)[field] = Val; 1070 } 1071 1072 void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, 1073 msgpack::Type Type, const MCExpr *Val) { 1074 DelayedExprs.assignDocNode(getHwStage(CC)[field], Type, Val); 1075 } 1076 1077 void AMDGPUPALMetadata::setComputeRegisters(StringRef field, unsigned Val) { 1078 getComputeRegisters()[field] = Val; 1079 } 1080 1081 void AMDGPUPALMetadata::setComputeRegisters(StringRef field, bool Val) { 1082 getComputeRegisters()[field] = Val; 1083 } 1084 1085 msgpack::DocNode *AMDGPUPALMetadata::refComputeRegister(StringRef field) { 1086 auto M = getComputeRegisters(); 1087 auto I = M.find(field); 1088 return I == M.end() ? nullptr : &I->second; 1089 } 1090 1091 bool AMDGPUPALMetadata::checkComputeRegisters(StringRef field, unsigned Val) { 1092 if (auto *N = refComputeRegister(field)) 1093 return N->getUInt() == Val; 1094 return false; 1095 } 1096 1097 bool AMDGPUPALMetadata::checkComputeRegisters(StringRef field, bool Val) { 1098 if (auto *N = refComputeRegister(field)) 1099 return N->getBool() == Val; 1100 return false; 1101 } 1102 1103 void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field, unsigned Val) { 1104 getGraphicsRegisters()[field] = Val; 1105 } 1106 1107 void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field, bool Val) { 1108 getGraphicsRegisters()[field] = Val; 1109 } 1110 1111 void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field1, StringRef field2, 1112 unsigned Val) { 1113 getGraphicsRegisters()[field1].getMap(true)[field2] = Val; 1114 } 1115 1116 void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field1, StringRef field2, 1117 bool Val) { 1118 getGraphicsRegisters()[field1].getMap(true)[field2] = Val; 1119 } 1120