xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp (revision a7623790fb345e6dc986dfd31df0ace115e6f2e4)
1 //===-- AMDGPUAsmUtils.cpp - AsmParser/InstPrinter common -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 #include "AMDGPUAsmUtils.h"
9 
10 namespace llvm {
11 namespace AMDGPU {
12 namespace SendMsg {
13 
14 // This must be in sync with llvm::AMDGPU::SendMsg::Id enum members, see SIDefines.h.
15 const char* const IdSymbolic[] = {
16   nullptr,
17   "MSG_INTERRUPT",
18   "MSG_GS",
19   "MSG_GS_DONE",
20   nullptr,
21   nullptr,
22   nullptr,
23   nullptr,
24   nullptr,
25   "MSG_GS_ALLOC_REQ",
26   "MSG_GET_DOORBELL",
27   nullptr,
28   nullptr,
29   nullptr,
30   nullptr,
31   "MSG_SYSMSG"
32 };
33 
34 // These two must be in sync with llvm::AMDGPU::SendMsg::Op enum members, see SIDefines.h.
35 const char* const OpSysSymbolic[] = {
36   nullptr,
37   "SYSMSG_OP_ECC_ERR_INTERRUPT",
38   "SYSMSG_OP_REG_RD",
39   "SYSMSG_OP_HOST_TRAP_ACK",
40   "SYSMSG_OP_TTRACE_PC"
41 };
42 
43 const char* const OpGsSymbolic[] = {
44   "GS_OP_NOP",
45   "GS_OP_CUT",
46   "GS_OP_EMIT",
47   "GS_OP_EMIT_CUT"
48 };
49 
50 } // namespace SendMsg
51 
52 namespace Hwreg {
53 
54 // This must be in sync with llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_/LAST_, see SIDefines.h.
55 const char* const IdSymbolic[] = {
56   nullptr,
57   "HW_REG_MODE",
58   "HW_REG_STATUS",
59   "HW_REG_TRAPSTS",
60   "HW_REG_HW_ID",
61   "HW_REG_GPR_ALLOC",
62   "HW_REG_LDS_ALLOC",
63   "HW_REG_IB_STS",
64   nullptr,
65   nullptr,
66   nullptr,
67   nullptr,
68   nullptr,
69   nullptr,
70   nullptr,
71   "HW_REG_SH_MEM_BASES",
72   "HW_REG_TBA_LO",
73   "HW_REG_TBA_HI",
74   "HW_REG_TMA_LO",
75   "HW_REG_TMA_HI",
76   "HW_REG_FLAT_SCR_LO",
77   "HW_REG_FLAT_SCR_HI",
78   "HW_REG_XNACK_MASK",
79   nullptr, // HW_ID1, no predictable values
80   nullptr, // HW_ID2, no predictable values
81   "HW_REG_POPS_PACKER",
82   nullptr,
83   nullptr,
84   nullptr,
85   "HW_REG_SHADER_CYCLES"
86 };
87 
88 } // namespace Hwreg
89 
90 namespace Swizzle {
91 
92 // This must be in sync with llvm::AMDGPU::Swizzle::Id enum members, see SIDefines.h.
93 const char* const IdSymbolic[] = {
94   "QUAD_PERM",
95   "BITMASK_PERM",
96   "SWAP",
97   "REVERSE",
98   "BROADCAST",
99 };
100 
101 } // namespace Swizzle
102 
103 namespace VGPRIndexMode {
104 
105 // This must be in sync with llvm::AMDGPU::VGPRIndexMode::Id enum members, see SIDefines.h.
106 const char* const IdSymbolic[] = {
107   "SRC0",
108   "SRC1",
109   "SRC2",
110   "DST",
111 };
112 
113 } // namespace VGPRIndexMode
114 
115 } // namespace AMDGPU
116 } // namespace llvm
117