1//===-- SISchedule.td - SI Scheduling definitions -------------------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// MachineModel definitions for Southern Islands (SI) 10// 11//===----------------------------------------------------------------------===// 12 13def : PredicateProlog<[{ 14 const SIInstrInfo *TII = 15 static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo()); 16 (void)TII; 17}]>; 18 19def WriteBranch : SchedWrite; 20def WriteExport : SchedWrite; 21def WriteLDS : SchedWrite; 22def WriteSALU : SchedWrite; 23def WriteSMEM : SchedWrite; 24def WriteVMEM : SchedWrite; 25def WriteBarrier : SchedWrite; 26 27def MIVGPRRead : SchedRead; 28def MIMFMARead : SchedRead; 29 30// Normal 16 or 32 bit VALU instructions 31def Write32Bit : SchedWrite; 32// Conversion to or from F32 (but not converting F64 to or from F32) 33def WriteFloatCvt : SchedWrite; 34// F16 or F32 transcendental instructions (these are quarter rate) 35def WriteTrans32 : SchedWrite; 36// Other quarter rate VALU instructions 37def WriteQuarterRate32 : SchedWrite; 38 39def WriteFloatFMA : SchedWrite; 40 41// Slow quarter rate f64 instruction. 42def WriteDouble : SchedWrite; 43 44// half rate f64 instruction (same as v_add_f64) 45def WriteDoubleAdd : SchedWrite; 46 47// Conversion to or from f64 instruction 48def WriteDoubleCvt : SchedWrite; 49 50// F64 "transcendental" (actually only reciprocal and/or square root) 51// instructions 52def WriteTrans64 : SchedWrite; 53 54// Half rate 64-bit instructions. 55def Write64Bit : SchedWrite; 56 57// Integer multiplications. 58def WriteIntMul : SchedWrite; 59 60// mAI multipass instructions. 61def Write2PassMAI : SchedWrite; 62def Write8PassMAI : SchedWrite; 63def Write16PassMAI : SchedWrite; 64def Write4PassDGEMM : SchedWrite; 65def Write8PassDGEMM : SchedWrite; 66 67// FIXME: Should there be a class for instructions which are VALU 68// instructions and have VALU rates, but write to the SALU (i.e. VOPC 69// instructions) 70 71class SISchedMachineModel : SchedMachineModel { 72 let CompleteModel = 1; 73 // MicroOpBufferSize = 1 means that instructions will always be added 74 // the ready queue when they become available. This exposes them 75 // to the register pressure analysis. 76 let MicroOpBufferSize = 1; 77 let IssueWidth = 1; 78 let PostRAScheduler = 1; 79 80 // FIXME:Approximate 2 * branch cost. Try to hack around bad 81 // early-ifcvt heuristics. These need improvement to avoid the OOE 82 // heuristics. 83 int MispredictPenalty = 20; 84} 85 86def SIFullSpeedModel : SISchedMachineModel; 87def SIQuarterSpeedModel : SISchedMachineModel; 88def SIDPFullSpeedModel : SISchedMachineModel; 89def GFX10SpeedModel : SISchedMachineModel; 90 91// XXX: Are the resource counts correct? 92def HWBranch : ProcResource<1> { 93 let BufferSize = 1; 94} 95def HWExport : ProcResource<1> { 96 let BufferSize = 7; // Taken from S_WAITCNT 97} 98def HWLGKM : ProcResource<1> { 99 let BufferSize = 31; // Taken from S_WAITCNT 100} 101def HWSALU : ProcResource<1> { 102 let BufferSize = 1; 103} 104def HWVMEM : ProcResource<1> { 105 let BufferSize = 15; // Taken from S_WAITCNT 106} 107def HWVALU : ProcResource<1> { 108 let BufferSize = 1; 109} 110def HWTransVALU : ProcResource<1> { // Transcendental VALU 111 let BufferSize = 1; 112} 113def HWRC : ProcResource<1> { // Register destination cache 114 let BufferSize = 1; 115} 116def HWXDL : ProcResource<1> { // MFMA CU 117 let BufferSize = 0; 118} 119 120class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources, 121 int latency> : WriteRes<write, resources> { 122 let Latency = latency; 123} 124 125class HWVALUWriteRes<SchedWrite write, int latency> : 126 HWWriteRes<write, [HWVALU], latency>; 127 128def PredMIReadVGPR : SchedPredicate<[{TII->hasVGPRUses(*MI)}]>; 129 130def MIReadVGPR : SchedReadVariant<[ 131 SchedVar<PredMIReadVGPR, [MIVGPRRead]>, 132 SchedVar<NoSchedPred, [ReadDefault]>]>; 133 134// The latency numbers are taken from AMD Accelerated Parallel Processing 135// guide. They may not be accurate. 136 137// The latency values are 1 / (operations / cycle) / 4. 138multiclass SICommonWriteRes { 139 140 def : HWWriteRes<WriteBranch, [HWBranch], 8>; 141 def : HWWriteRes<WriteExport, [HWExport], 4>; 142 def : HWWriteRes<WriteLDS, [HWLGKM], 5>; // Can be between 2 and 64 143 def : HWWriteRes<WriteSALU, [HWSALU], 1>; 144 def : HWWriteRes<WriteSMEM, [HWLGKM], 5>; 145 def : HWWriteRes<WriteVMEM, [HWVMEM], 80>; 146 def : HWWriteRes<WriteBarrier, [HWBranch], 500>; // XXX: Guessed ??? 147 148 def : HWVALUWriteRes<Write32Bit, 1>; 149 def : HWVALUWriteRes<WriteFloatCvt, 4>; 150 def : HWVALUWriteRes<WriteTrans32, 4>; 151 def : HWVALUWriteRes<WriteQuarterRate32, 4>; 152 153 def : HWVALUWriteRes<Write4PassDGEMM, 4>; 154 def : HWVALUWriteRes<Write8PassDGEMM, 16>; 155 156 let ResourceCycles = [2] in 157 def : HWWriteRes<Write2PassMAI, [HWXDL], 2>; 158 let ResourceCycles = [8] in 159 def : HWWriteRes<Write8PassMAI, [HWXDL], 8>; 160 let ResourceCycles = [16] in 161 def : HWWriteRes<Write16PassMAI, [HWXDL], 16>; 162 163 def : ReadAdvance<MIVGPRRead, -2>; 164 165 // Technically mfma reads can be from 0 to 4 cycles but that does not make 166 // sense to model because its register setup is huge. In particular if we 167 // properly model read advance as -2 for a vgpr read it will result in a 168 // bad scheduling of acc writes before that mfma. To avoid it we would 169 // need to consume 2 or 4 more vgprs to be initialized before the acc 170 // write sequence. Just assume worst case here. 171 def : ReadAdvance<MIMFMARead, -4>; 172} 173 174def PredIsVGPR32Copy : SchedPredicate<[{TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32}]>; 175def PredIsVGPR64Copy : SchedPredicate<[{TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32}]>; 176def WriteCopy : SchedWriteVariant<[ 177 SchedVar<PredIsVGPR32Copy, [Write32Bit]>, 178 SchedVar<PredIsVGPR64Copy, [Write64Bit]>, 179 SchedVar<NoSchedPred, [WriteSALU]>]>; 180 181let SchedModel = SIFullSpeedModel in { 182 183defm : SICommonWriteRes; 184 185def : HWVALUWriteRes<Write64Bit, 2>; 186def : HWVALUWriteRes<WriteIntMul, 4>; 187def : HWVALUWriteRes<WriteFloatFMA, 1>; 188def : HWVALUWriteRes<WriteDouble, 4>; 189def : HWVALUWriteRes<WriteDoubleAdd, 2>; 190def : HWVALUWriteRes<WriteDoubleCvt, 4>; 191def : HWVALUWriteRes<WriteTrans64, 4>; 192 193def : InstRW<[WriteCopy], (instrs COPY)>; 194 195} // End SchedModel = SIFullSpeedModel 196 197let SchedModel = SIQuarterSpeedModel in { 198 199defm : SICommonWriteRes; 200 201def : HWVALUWriteRes<Write64Bit, 2>; 202def : HWVALUWriteRes<WriteIntMul, 4>; 203def : HWVALUWriteRes<WriteFloatFMA, 16>; 204def : HWVALUWriteRes<WriteDouble, 16>; 205def : HWVALUWriteRes<WriteDoubleAdd, 8>; 206def : HWVALUWriteRes<WriteDoubleCvt, 4>; 207def : HWVALUWriteRes<WriteTrans64, 16>; 208 209def : InstRW<[WriteCopy], (instrs COPY)>; 210def : InstRW<[Write64Bit, MIReadVGPR], (instregex "^V_ACCVGPR_WRITE_B32_e64$")>; 211def : InstRW<[Write2PassMAI, MIMFMARead], (instregex "^V_MFMA_..._4X4X")>; 212def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_MFMA_..._16X16X")>; 213def : InstRW<[Write16PassMAI, MIMFMARead], (instregex "^V_MFMA_..._32X32X")>; 214 215} // End SchedModel = SIQuarterSpeedModel 216 217let SchedModel = SIDPFullSpeedModel in { 218 219defm : SICommonWriteRes; 220 221def : HWVALUWriteRes<WriteFloatFMA, 1>; 222def : HWVALUWriteRes<WriteDouble, 1>; 223def : HWVALUWriteRes<WriteDoubleAdd, 1>; 224def : HWVALUWriteRes<WriteDoubleCvt, 1>; 225def : HWVALUWriteRes<WriteTrans64, 4>; 226def : HWVALUWriteRes<WriteIntMul, 1>; 227def : HWVALUWriteRes<Write64Bit, 1>; 228 229def : InstRW<[WriteCopy], (instrs COPY)>; 230def : InstRW<[Write64Bit], (instregex "^V_ACCVGPR_WRITE_B32_e64$")>; 231def : InstRW<[Write2PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_4X4X")>; 232def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_16X16X")>; 233def : InstRW<[Write16PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_32X32X")>; 234def : InstRW<[Write4PassDGEMM, MIMFMARead], (instregex "^V_MFMA_.64_4X4X")>; 235def : InstRW<[Write8PassDGEMM, MIMFMARead], (instregex "^V_MFMA_.64_16X16X")>; 236 237} // End SchedModel = SIDPFullSpeedModel 238 239let SchedModel = GFX10SpeedModel in { 240 241// The latency values are 1 / (operations / cycle). 242// Add 1 stall cycle for VGPR read. 243def : HWWriteRes<Write32Bit, [HWVALU, HWRC], 5>; 244def : HWWriteRes<WriteFloatCvt, [HWVALU, HWRC], 5>; 245def : HWWriteRes<Write64Bit, [HWVALU, HWRC], 6>; 246def : HWWriteRes<WriteTrans32, [HWTransVALU, HWRC], 10>; 247def : HWWriteRes<WriteQuarterRate32, [HWVALU, HWRC], 8>; 248def : HWWriteRes<WriteFloatFMA, [HWVALU, HWRC], 5>; 249def : HWWriteRes<WriteDouble, [HWVALU, HWRC], 22>; 250def : HWWriteRes<WriteDoubleAdd, [HWVALU, HWRC], 22>; 251def : HWWriteRes<WriteDoubleCvt, [HWVALU, HWRC], 22>; 252def : HWWriteRes<WriteIntMul, [HWVALU, HWRC], 8>; 253def : HWWriteRes<WriteTrans64, [HWVALU, HWTransVALU, HWRC], 24>; 254 255def : HWWriteRes<WriteBranch, [HWBranch], 32>; 256def : HWWriteRes<WriteExport, [HWExport, HWRC], 16>; 257def : HWWriteRes<WriteLDS, [HWLGKM, HWRC], 20>; 258def : HWWriteRes<WriteSALU, [HWSALU, HWRC], 2>; 259def : HWWriteRes<WriteSMEM, [HWLGKM, HWRC], 20>; 260def : HWWriteRes<WriteVMEM, [HWVMEM, HWRC], 320>; 261def : HWWriteRes<WriteBarrier, [HWBranch], 2000>; 262 263def : InstRW<[WriteCopy], (instrs COPY)>; 264 265} // End SchedModel = GFX10SpeedModel 266