1//===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Subregister declarations 11//===----------------------------------------------------------------------===// 12 13let Namespace = "AMDGPU" in { 14 15def lo16 : SubRegIndex<16, 0>; 16def hi16 : SubRegIndex<16, 16>; 17 18foreach Index = 0...31 in { 19 def sub#Index : SubRegIndex<32, !shl(Index, 5)>; 20} 21 22foreach Index = 1...31 in { 23 def sub#Index#_lo16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), lo16>; 24 def sub#Index#_hi16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), hi16>; 25} 26 27foreach Size = {2...6,8,16} in { 28 foreach Index = !range(!sub(33, Size)) in { 29 def !interleave(!foreach(cur, !range(Size), "sub"#!add(cur, Index)), "_") : 30 SubRegIndex<!mul(Size, 32), !shl(Index, 5)> { 31 let CoveringSubRegIndices = 32 !foreach(cur, !range(Size), !cast<SubRegIndex>(sub#!add(cur, Index))); 33 } 34 } 35} 36 37} 38 39//===----------------------------------------------------------------------===// 40// Helpers 41//===----------------------------------------------------------------------===// 42 43class getSubRegs<int size> { 44 list<SubRegIndex> ret2 = [sub0, sub1]; 45 list<SubRegIndex> ret3 = [sub0, sub1, sub2]; 46 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3]; 47 list<SubRegIndex> ret5 = [sub0, sub1, sub2, sub3, sub4]; 48 list<SubRegIndex> ret6 = [sub0, sub1, sub2, sub3, sub4, sub5]; 49 list<SubRegIndex> ret7 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6]; 50 list<SubRegIndex> ret8 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7]; 51 list<SubRegIndex> ret9 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7, sub8]; 52 list<SubRegIndex> ret10 = [sub0, sub1, sub2, sub3, 53 sub4, sub5, sub6, sub7, 54 sub8, sub9]; 55 list<SubRegIndex> ret11 = [sub0, sub1, sub2, sub3, 56 sub4, sub5, sub6, sub7, 57 sub8, sub9, sub10]; 58 list<SubRegIndex> ret12 = [sub0, sub1, sub2, sub3, 59 sub4, sub5, sub6, sub7, 60 sub8, sub9, sub10, sub11]; 61 list<SubRegIndex> ret16 = [sub0, sub1, sub2, sub3, 62 sub4, sub5, sub6, sub7, 63 sub8, sub9, sub10, sub11, 64 sub12, sub13, sub14, sub15]; 65 list<SubRegIndex> ret32 = [sub0, sub1, sub2, sub3, 66 sub4, sub5, sub6, sub7, 67 sub8, sub9, sub10, sub11, 68 sub12, sub13, sub14, sub15, 69 sub16, sub17, sub18, sub19, 70 sub20, sub21, sub22, sub23, 71 sub24, sub25, sub26, sub27, 72 sub28, sub29, sub30, sub31]; 73 74 list<SubRegIndex> ret = !if(!eq(size, 2), ret2, 75 !if(!eq(size, 3), ret3, 76 !if(!eq(size, 4), ret4, 77 !if(!eq(size, 5), ret5, 78 !if(!eq(size, 6), ret6, 79 !if(!eq(size, 7), ret7, 80 !if(!eq(size, 8), ret8, 81 !if(!eq(size, 9), ret9, 82 !if(!eq(size, 10), ret10, 83 !if(!eq(size, 11), ret11, 84 !if(!eq(size, 12), ret12, 85 !if(!eq(size, 16), ret16, 86 ret32)))))))))))); 87} 88 89// Generates list of sequential register tuple names. 90// E.g. RegSeq<3,2,2,"s">.ret -> [ "s[0:1]", "s[2:3]" ] 91class RegSeqNames<int last_reg, int stride, int size, string prefix, 92 int start = 0> { 93 int next = !add(start, stride); 94 int end_reg = !add(start, size, -1); 95 list<string> ret = 96 !if(!le(end_reg, last_reg), 97 !listconcat([prefix # "[" # start # ":" # end_reg # "]"], 98 RegSeqNames<last_reg, stride, size, prefix, next>.ret), 99 []); 100} 101 102// Generates list of dags for register tuples. 103class RegSeqDags<RegisterClass RC, int last_reg, int stride, int size, 104 int start = 0> { 105 dag trunc_rc = (trunc RC, 106 !if(!and(!eq(stride, 1), !eq(start, 0)), 107 !sub(!add(last_reg, 2), size), 108 !add(last_reg, 1))); 109 list<dag> ret = 110 !if(!lt(start, size), 111 !listconcat([(add (decimate (shl trunc_rc, start), stride))], 112 RegSeqDags<RC, last_reg, stride, size, !add(start, 1)>.ret), 113 []); 114} 115 116class SIRegisterTuples<list<SubRegIndex> Indices, RegisterClass RC, 117 int last_reg, int stride, int size, string prefix> : 118 RegisterTuples<Indices, 119 RegSeqDags<RC, last_reg, stride, size>.ret, 120 RegSeqNames<last_reg, stride, size, prefix>.ret>; 121 122//===----------------------------------------------------------------------===// 123// Declarations that describe the SI registers 124//===----------------------------------------------------------------------===// 125class SIReg <string n, bits<8> regIdx = 0, bit isAGPROrVGPR = 0, 126 bit isHi = 0> : Register<n> { 127 let Namespace = "AMDGPU"; 128 129 // These are generic helper values we use to form actual register 130 // codes. They should not be assumed to match any particular register 131 // encodings on any particular subtargets. 132 let HWEncoding{7-0} = regIdx; 133 let HWEncoding{8} = isAGPROrVGPR; 134 let HWEncoding{9} = isHi; 135 136 int Index = !cast<int>(regIdx); 137} 138 139// For register classes that use TSFlags. 140class SIRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList> 141 : RegisterClass <n, rTypes, Align, rList> { 142 // For vector register classes. 143 field bit HasVGPR = 0; 144 field bit HasAGPR = 0; 145 146 // For scalar register classes. 147 field bit HasSGPR = 0; 148 149 // Alignment of the first register in tuple (in 32-bit units). 150 field int RegTupleAlignUnits = 1; 151 152 // These need to be kept in sync with the enum SIRCFlags. 153 let TSFlags{1-0} = RegTupleAlignUnits; 154 let TSFlags{2} = HasVGPR; 155 let TSFlags{3} = HasAGPR; 156 let TSFlags{4} = HasSGPR; 157} 158 159multiclass SIRegLoHi16 <string n, bits<8> regIdx, bit ArtificialHigh = 1, 160 bit isAGPROrVGPR = 0> { 161 def _LO16 : SIReg<n#".l", regIdx, isAGPROrVGPR>; 162 def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx, isAGPROrVGPR, 163 /* isHi */ 1> { 164 let isArtificial = ArtificialHigh; 165 } 166 def "" : RegisterWithSubRegs<n, [!cast<Register>(NAME#"_LO16"), 167 !cast<Register>(NAME#"_HI16")]> { 168 let Namespace = "AMDGPU"; 169 let SubRegIndices = [lo16, hi16]; 170 let CoveredBySubRegs = !not(ArtificialHigh); 171 let HWEncoding{7-0} = regIdx; 172 let HWEncoding{8} = isAGPROrVGPR; 173 174 int Index = !cast<int>(regIdx); 175 } 176} 177 178// Special Registers 179defm VCC_LO : SIRegLoHi16<"vcc_lo", 106>; 180defm VCC_HI : SIRegLoHi16<"vcc_hi", 107>; 181 182// Pseudo-registers: Used as placeholders during isel and immediately 183// replaced, never seeing the verifier. 184def PRIVATE_RSRC_REG : SIReg<"private_rsrc", 0>; 185def FP_REG : SIReg<"fp", 0>; 186def SP_REG : SIReg<"sp", 0>; 187 188// Pseudo-register to represent the program-counter DWARF register. 189def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 16]> { 190 // There is no physical register corresponding to a "program counter", but 191 // we need to encode the concept in debug information in order to represent 192 // things like the return value in unwind information. 193 let isArtificial = 1; 194} 195 196// VCC for 64-bit instructions 197def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> { 198 let Namespace = "AMDGPU"; 199 let SubRegIndices = [sub0, sub1]; 200 let HWEncoding = VCC_LO.HWEncoding; 201} 202 203defm EXEC_LO : SIRegLoHi16<"exec_lo", 126>, DwarfRegNum<[1, 1]>; 204defm EXEC_HI : SIRegLoHi16<"exec_hi", 127>; 205 206def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> { 207 let Namespace = "AMDGPU"; 208 let SubRegIndices = [sub0, sub1]; 209 let HWEncoding = EXEC_LO.HWEncoding; 210} 211 212// 32-bit real registers, for MC only. 213// May be used with both 32-bit and 64-bit operands. 214defm SRC_VCCZ : SIRegLoHi16<"src_vccz", 251>; 215defm SRC_EXECZ : SIRegLoHi16<"src_execz", 252>; 216defm SRC_SCC : SIRegLoHi16<"src_scc", 253>; 217 218// 1-bit pseudo register, for codegen only. 219// Should never be emitted. 220def SCC : SIReg<"scc">; 221 222// Encoding changes between subtarget generations. 223// See also Utils/AMDGPUBaseInfo.cpp MAP_REG2REG. 224defm M0_gfxpre11 : SIRegLoHi16 <"m0", 124>; 225defm M0_gfx11plus : SIRegLoHi16 <"m0", 125>; 226defm M0 : SIRegLoHi16 <"m0", 0>; 227 228defm SGPR_NULL_gfxpre11 : SIRegLoHi16 <"null", 125>; 229defm SGPR_NULL_gfx11plus : SIRegLoHi16 <"null", 124>; 230let isConstant = true in { 231defm SGPR_NULL : SIRegLoHi16 <"null", 0>; 232defm SGPR_NULL_HI : SIRegLoHi16 <"", 0>; 233} // isConstant = true 234 235def SGPR_NULL64 : 236 RegisterWithSubRegs<"null", [SGPR_NULL, SGPR_NULL_HI]> { 237 let Namespace = "AMDGPU"; 238 let SubRegIndices = [sub0, sub1]; 239 let HWEncoding = SGPR_NULL.HWEncoding; 240 let isConstant = true; 241} 242 243// Aperture registers are 64 bit registers with a LO/HI 32 bit. 244// HI 32 bit cannot be used, and LO 32 is used by instructions 245// with 32 bit sources. 246// 247// Note that the low 32 bits are essentially useless as they 248// don't contain the lower 32 bits of the address - they are in 249// the high 32 bits. The lower 32 bits are always zero (for base) or 250// -1 (for limit). Since we cannot access the high 32 bits, when we 251// need them, we need to do a 64 bit load and extract the bits manually. 252multiclass ApertureRegister<string name, bits<8> regIdx> { 253 let isConstant = true in { 254 // FIXME: We shouldn't need to define subregisters for these (nor add them to any 16 bit 255 // register classes), but if we don't it seems to confuse the TableGen 256 // backend and we end up with a lot of weird register pressure sets and classes. 257 defm _LO : SIRegLoHi16 <name, regIdx>; 258 defm _HI : SIRegLoHi16 <"", regIdx>; 259 260 def "" : RegisterWithSubRegs<name, [!cast<Register>(NAME#_LO), !cast<Register>(NAME#_HI)]> { 261 let Namespace = "AMDGPU"; 262 let SubRegIndices = [sub0, sub1]; 263 let HWEncoding = !cast<Register>(NAME#_LO).HWEncoding; 264 } 265 } // isConstant = true 266} 267 268defm SRC_SHARED_BASE : ApertureRegister<"src_shared_base", 235>; 269defm SRC_SHARED_LIMIT : ApertureRegister<"src_shared_limit", 236>; 270defm SRC_PRIVATE_BASE : ApertureRegister<"src_private_base", 237>; 271defm SRC_PRIVATE_LIMIT : ApertureRegister<"src_private_limit", 238>; 272 273defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>; 274 275// Not addressable 276def MODE : SIReg <"mode", 0>; 277 278def LDS_DIRECT : SIReg <"src_lds_direct", 254> { 279 // There is no physical register corresponding to this. This is an 280 // encoding value in a source field, which will ultimately trigger a 281 // read from m0. 282 let isArtificial = 1; 283} 284 285defm XNACK_MASK_LO : SIRegLoHi16<"xnack_mask_lo", 104>; 286defm XNACK_MASK_HI : SIRegLoHi16<"xnack_mask_hi", 105>; 287 288def XNACK_MASK : 289 RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]> { 290 let Namespace = "AMDGPU"; 291 let SubRegIndices = [sub0, sub1]; 292 let HWEncoding = XNACK_MASK_LO.HWEncoding; 293} 294 295// Trap handler registers 296defm TBA_LO : SIRegLoHi16<"tba_lo", 108>; 297defm TBA_HI : SIRegLoHi16<"tba_hi", 109>; 298 299def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]> { 300 let Namespace = "AMDGPU"; 301 let SubRegIndices = [sub0, sub1]; 302 let HWEncoding = TBA_LO.HWEncoding; 303} 304 305defm TMA_LO : SIRegLoHi16<"tma_lo", 110>; 306defm TMA_HI : SIRegLoHi16<"tma_hi", 111>; 307 308def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]> { 309 let Namespace = "AMDGPU"; 310 let SubRegIndices = [sub0, sub1]; 311 let HWEncoding = TMA_LO.HWEncoding; 312} 313 314foreach Index = 0...15 in { 315 defm TTMP#Index#_vi : SIRegLoHi16<"ttmp"#Index, !add(112, Index)>; 316 defm TTMP#Index#_gfx9plus : SIRegLoHi16<"ttmp"#Index, !add(108, Index)>; 317 defm TTMP#Index : SIRegLoHi16<"ttmp"#Index, 0>; 318} 319 320multiclass FLAT_SCR_LOHI_m <string n, bits<8> ci_e, bits<8> vi_e> { 321 defm _ci : SIRegLoHi16<n, ci_e>; 322 defm _vi : SIRegLoHi16<n, vi_e>; 323 defm "" : SIRegLoHi16<n, 0>; 324} 325 326class FlatReg <Register lo, Register hi, bits<16> encoding> : 327 RegisterWithSubRegs<"flat_scratch", [lo, hi]> { 328 let Namespace = "AMDGPU"; 329 let SubRegIndices = [sub0, sub1]; 330 let HWEncoding = encoding; 331} 332 333defm FLAT_SCR_LO : FLAT_SCR_LOHI_m<"flat_scratch_lo", 104, 102>; // Offset in units of 256-bytes. 334defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes. 335 336def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>; 337def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>; 338def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>; 339 340// SGPR registers 341foreach Index = 0...105 in { 342 defm SGPR#Index : 343 SIRegLoHi16 <"s"#Index, Index>, 344 DwarfRegNum<[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)), 345 !if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>; 346} 347 348// VGPR registers 349foreach Index = 0...255 in { 350 defm VGPR#Index : 351 SIRegLoHi16 <"v"#Index, Index, 0, 1>, 352 DwarfRegNum<[!add(Index, 2560), !add(Index, 1536)]>; 353} 354 355// AccVGPR registers 356foreach Index = 0...255 in { 357 defm AGPR#Index : 358 SIRegLoHi16 <"a"#Index, Index, 1, 1>, 359 DwarfRegNum<[!add(Index, 3072), !add(Index, 2048)]>; 360} 361 362//===----------------------------------------------------------------------===// 363// Groupings using register classes and tuples 364//===----------------------------------------------------------------------===// 365 366def SCC_CLASS : SIRegisterClass<"AMDGPU", [i1], 1, (add SCC)> { 367 let CopyCost = -1; 368 let isAllocatable = 0; 369 let HasSGPR = 1; 370 let BaseClassOrder = 10000; 371} 372 373def M0_CLASS : SIRegisterClass<"AMDGPU", [i32], 32, (add M0)> { 374 let CopyCost = 1; 375 let isAllocatable = 0; 376 let HasSGPR = 1; 377} 378 379def M0_CLASS_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16, (add M0_LO16)> { 380 let CopyCost = 1; 381 let Size = 16; 382 let isAllocatable = 0; 383 let HasSGPR = 1; 384} 385 386// TODO: Do we need to set DwarfRegAlias on register tuples? 387 388def SGPR_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16, 389 (add (sequence "SGPR%u_LO16", 0, 105))> { 390 let AllocationPriority = 0; 391 let Size = 16; 392 let GeneratePressureSet = 0; 393 let HasSGPR = 1; 394} 395 396def SGPR_HI16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16, 397 (add (sequence "SGPR%u_HI16", 0, 105))> { 398 let isAllocatable = 0; 399 let Size = 16; 400 let GeneratePressureSet = 0; 401 let HasSGPR = 1; 402} 403 404// SGPR 32-bit registers 405def SGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32, 406 (add (sequence "SGPR%u", 0, 105))> { 407 // Give all SGPR classes higher priority than VGPR classes, because 408 // we want to spill SGPRs to VGPRs. 409 let AllocationPriority = 0; 410 let GeneratePressureSet = 0; 411 let HasSGPR = 1; 412} 413 414// SGPR 64-bit registers 415def SGPR_64Regs : SIRegisterTuples<getSubRegs<2>.ret, SGPR_32, 105, 2, 2, "s">; 416 417// SGPR 96-bit registers. 418def SGPR_96Regs : SIRegisterTuples<getSubRegs<3>.ret, SGPR_32, 105, 4, 3, "s">; 419 420// SGPR 128-bit registers 421def SGPR_128Regs : SIRegisterTuples<getSubRegs<4>.ret, SGPR_32, 105, 4, 4, "s">; 422 423// SGPR 160-bit registers. No operations use these, but for symmetry with 160-bit VGPRs. 424def SGPR_160Regs : SIRegisterTuples<getSubRegs<5>.ret, SGPR_32, 105, 4, 5, "s">; 425 426// SGPR 192-bit registers. No operations use these, but for symmetry with 192-bit VGPRs. 427def SGPR_192Regs : SIRegisterTuples<getSubRegs<6>.ret, SGPR_32, 105, 4, 6, "s">; 428 429// SGPR 224-bit registers. No operations use these, but for symmetry with 224-bit VGPRs. 430def SGPR_224Regs : SIRegisterTuples<getSubRegs<7>.ret, SGPR_32, 105, 4, 7, "s">; 431 432// SGPR 256-bit registers 433def SGPR_256Regs : SIRegisterTuples<getSubRegs<8>.ret, SGPR_32, 105, 4, 8, "s">; 434 435// SGPR 288-bit registers. No operations use these, but for symmetry with 288-bit VGPRs. 436def SGPR_288Regs : SIRegisterTuples<getSubRegs<9>.ret, SGPR_32, 105, 4, 9, "s">; 437 438// SGPR 320-bit registers. No operations use these, but for symmetry with 320-bit VGPRs. 439def SGPR_320Regs : SIRegisterTuples<getSubRegs<10>.ret, SGPR_32, 105, 4, 10, "s">; 440 441// SGPR 352-bit registers. No operations use these, but for symmetry with 352-bit VGPRs. 442def SGPR_352Regs : SIRegisterTuples<getSubRegs<11>.ret, SGPR_32, 105, 4, 11, "s">; 443 444// SGPR 384-bit registers. No operations use these, but for symmetry with 384-bit VGPRs. 445def SGPR_384Regs : SIRegisterTuples<getSubRegs<12>.ret, SGPR_32, 105, 4, 12, "s">; 446 447// SGPR 512-bit registers 448def SGPR_512Regs : SIRegisterTuples<getSubRegs<16>.ret, SGPR_32, 105, 4, 16, "s">; 449 450// SGPR 1024-bit registers 451def SGPR_1024Regs : SIRegisterTuples<getSubRegs<32>.ret, SGPR_32, 105, 4, 32, "s">; 452 453// Trap handler TMP 32-bit registers 454def TTMP_32 : SIRegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16, v2bf16], 32, 455 (add (sequence "TTMP%u", 0, 15))> { 456 let isAllocatable = 0; 457 let HasSGPR = 1; 458} 459 460// Trap handler TMP 16-bit registers 461def TTMP_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16, 462 (add (sequence "TTMP%u_LO16", 0, 15))> { 463 let Size = 16; 464 let isAllocatable = 0; 465 let HasSGPR = 1; 466} 467 468// Trap handler TMP 64-bit registers 469def TTMP_64Regs : SIRegisterTuples<getSubRegs<2>.ret, TTMP_32, 15, 2, 2, "ttmp">; 470 471// Trap handler TMP 96-bit registers 472def TTMP_96Regs : SIRegisterTuples<getSubRegs<3>.ret, TTMP_32, 15, 3, 3, "ttmp">; 473 474// Trap handler TMP 128-bit registers 475def TTMP_128Regs : SIRegisterTuples<getSubRegs<4>.ret, TTMP_32, 15, 4, 4, "ttmp">; 476 477// Trap handler TMP 160-bit registers 478def TTMP_160Regs : SIRegisterTuples<getSubRegs<5>.ret, TTMP_32, 15, 4, 5, "ttmp">; 479 480// Trap handler TMP 192-bit registers 481def TTMP_192Regs : SIRegisterTuples<getSubRegs<6>.ret, TTMP_32, 15, 4, 6, "ttmp">; 482 483// Trap handler TMP 224-bit registers 484def TTMP_224Regs : SIRegisterTuples<getSubRegs<7>.ret, TTMP_32, 15, 4, 7, "ttmp">; 485 486// Trap handler TMP 256-bit registers 487def TTMP_256Regs : SIRegisterTuples<getSubRegs<8>.ret, TTMP_32, 15, 4, 8, "ttmp">; 488 489// Trap handler TMP 288-bit registers 490def TTMP_288Regs : SIRegisterTuples<getSubRegs<9>.ret, TTMP_32, 15, 4, 9, "ttmp">; 491 492// Trap handler TMP 320-bit registers 493def TTMP_320Regs : SIRegisterTuples<getSubRegs<10>.ret, TTMP_32, 15, 4, 10, "ttmp">; 494 495// Trap handler TMP 352-bit registers 496def TTMP_352Regs : SIRegisterTuples<getSubRegs<11>.ret, TTMP_32, 15, 4, 11, "ttmp">; 497 498// Trap handler TMP 384-bit registers 499def TTMP_384Regs : SIRegisterTuples<getSubRegs<12>.ret, TTMP_32, 15, 4, 12, "ttmp">; 500 501// Trap handler TMP 512-bit registers 502def TTMP_512Regs : SIRegisterTuples<getSubRegs<16>.ret, TTMP_32, 15, 4, 16, "ttmp">; 503 504class TmpRegTuplesBase<int index, int size, 505 list<Register> subRegs, 506 list<SubRegIndex> indices = getSubRegs<size>.ret, 507 int index1 = !add(index, size, -1), 508 string name = "ttmp["#index#":"#index1#"]"> : 509 RegisterWithSubRegs<name, subRegs> { 510 let HWEncoding = subRegs[0].HWEncoding; 511 let SubRegIndices = indices; 512} 513 514class TmpRegTuples<string tgt, 515 int size, 516 int index0, 517 int index1 = !add(index0, 1), 518 int index2 = !add(index0, !if(!eq(size, 2), 1, 2)), 519 int index3 = !add(index0, !if(!eq(size, 2), 1, 3)), 520 int index4 = !add(index0, !if(!eq(size, 8), 4, 1)), 521 int index5 = !add(index0, !if(!eq(size, 8), 5, 1)), 522 int index6 = !add(index0, !if(!eq(size, 8), 6, 1)), 523 int index7 = !add(index0, !if(!eq(size, 8), 7, 1)), 524 Register r0 = !cast<Register>("TTMP"#index0#tgt), 525 Register r1 = !cast<Register>("TTMP"#index1#tgt), 526 Register r2 = !cast<Register>("TTMP"#index2#tgt), 527 Register r3 = !cast<Register>("TTMP"#index3#tgt), 528 Register r4 = !cast<Register>("TTMP"#index4#tgt), 529 Register r5 = !cast<Register>("TTMP"#index5#tgt), 530 Register r6 = !cast<Register>("TTMP"#index6#tgt), 531 Register r7 = !cast<Register>("TTMP"#index7#tgt)> : 532 TmpRegTuplesBase<index0, size, 533 !if(!eq(size, 2), [r0, r1], 534 !if(!eq(size, 4), [r0, r1, r2, r3], 535 [r0, r1, r2, r3, r4, r5, r6, r7])), 536 getSubRegs<size>.ret>; 537 538foreach Index = {0, 2, 4, 6, 8, 10, 12, 14} in { 539 def TTMP#Index#_TTMP#!add(Index,1)#_vi : TmpRegTuples<"_vi", 2, Index>; 540 def TTMP#Index#_TTMP#!add(Index,1)#_gfx9plus : TmpRegTuples<"_gfx9plus", 2, Index>; 541} 542 543foreach Index = {0, 4, 8, 12} in { 544 def TTMP#Index#_TTMP#!add(Index,1)# 545 _TTMP#!add(Index,2)# 546 _TTMP#!add(Index,3)#_vi : TmpRegTuples<"_vi", 4, Index>; 547 def TTMP#Index#_TTMP#!add(Index,1)# 548 _TTMP#!add(Index,2)# 549 _TTMP#!add(Index,3)#_gfx9plus : TmpRegTuples<"_gfx9plus", 4, Index>; 550} 551 552foreach Index = {0, 4, 8} in { 553 def TTMP#Index#_TTMP#!add(Index,1)# 554 _TTMP#!add(Index,2)# 555 _TTMP#!add(Index,3)# 556 _TTMP#!add(Index,4)# 557 _TTMP#!add(Index,5)# 558 _TTMP#!add(Index,6)# 559 _TTMP#!add(Index,7)#_vi : TmpRegTuples<"_vi", 8, Index>; 560 def TTMP#Index#_TTMP#!add(Index,1)# 561 _TTMP#!add(Index,2)# 562 _TTMP#!add(Index,3)# 563 _TTMP#!add(Index,4)# 564 _TTMP#!add(Index,5)# 565 _TTMP#!add(Index,6)# 566 _TTMP#!add(Index,7)#_gfx9plus : TmpRegTuples<"_gfx9plus", 8, Index>; 567} 568 569def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_vi : 570 TmpRegTuplesBase<0, 16, 571 [TTMP0_vi, TTMP1_vi, TTMP2_vi, TTMP3_vi, 572 TTMP4_vi, TTMP5_vi, TTMP6_vi, TTMP7_vi, 573 TTMP8_vi, TTMP9_vi, TTMP10_vi, TTMP11_vi, 574 TTMP12_vi, TTMP13_vi, TTMP14_vi, TTMP15_vi]>; 575 576def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_gfx9plus : 577 TmpRegTuplesBase<0, 16, 578 [TTMP0_gfx9plus, TTMP1_gfx9plus, TTMP2_gfx9plus, TTMP3_gfx9plus, 579 TTMP4_gfx9plus, TTMP5_gfx9plus, TTMP6_gfx9plus, TTMP7_gfx9plus, 580 TTMP8_gfx9plus, TTMP9_gfx9plus, TTMP10_gfx9plus, TTMP11_gfx9plus, 581 TTMP12_gfx9plus, TTMP13_gfx9plus, TTMP14_gfx9plus, TTMP15_gfx9plus]>; 582 583class RegisterTypes<list<ValueType> reg_types> { 584 list<ValueType> types = reg_types; 585} 586 587def Reg16Types : RegisterTypes<[i16, f16, bf16]>; 588def Reg32Types : RegisterTypes<[i32, f32, v2i16, v2f16, v2bf16, p2, p3, p5, p6]>; 589 590let HasVGPR = 1 in { 591// VOP3 and VINTERP can access 256 lo and 256 hi registers. 592def VGPR_16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16, 593 (add (interleave (sequence "VGPR%u_LO16", 0, 255), 594 (sequence "VGPR%u_HI16", 0, 255)))> { 595 let AllocationPriority = 2; 596 let Size = 16; 597 let GeneratePressureSet = 0; 598 599 // This is the base class for VGPR{128..255}_{LO16,HI16}. 600 let BaseClassOrder = 17; 601} 602 603// VOP1/2/C can access the First 128 lo and 128 hi registers. 604// The order of registers in the class determines order of allocation, so it is 605// important to interleave lo and hi registers. 606def VGPR_16_Lo128 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16, 607 (add (interleave (sequence "VGPR%u_LO16", 0, 127), 608 (sequence "VGPR%u_HI16", 0, 127)))> { 609 let Size = 16; 610 let GeneratePressureSet = 0; 611 let isAllocatable = 0; 612 613 // This is the base class for VGPR{0..127}_{LO16,HI16}. 614 let BaseClassOrder = 16; 615} 616 617// VGPR 32-bit registers 618// i16/f16 only on VI+ 619def VGPR_32 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32, 620 (add (sequence "VGPR%u", 0, 255))> { 621 let AllocationPriority = 0; 622 let Size = 32; 623 let Weight = 1; 624 let BaseClassOrder = 32; 625} 626 627// Identical to VGPR_32 except it only contains the low 128 (Lo128) registers. 628def VGPR_32_Lo128 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32, 629 (add (sequence "VGPR%u", 0, 127))> { 630 let AllocationPriority = 0; 631 let GeneratePressureSet = 0; 632 let Size = 32; 633 let Weight = 1; 634} 635} // End HasVGPR = 1 636 637// VGPR 64-bit registers 638def VGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, VGPR_32, 255, 1, 2, "v">; 639 640// VGPR 96-bit registers 641def VGPR_96 : SIRegisterTuples<getSubRegs<3>.ret, VGPR_32, 255, 1, 3, "v">; 642 643// VGPR 128-bit registers 644def VGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, VGPR_32, 255, 1, 4, "v">; 645 646// VGPR 160-bit registers 647def VGPR_160 : SIRegisterTuples<getSubRegs<5>.ret, VGPR_32, 255, 1, 5, "v">; 648 649// VGPR 192-bit registers 650def VGPR_192 : SIRegisterTuples<getSubRegs<6>.ret, VGPR_32, 255, 1, 6, "v">; 651 652// VGPR 224-bit registers 653def VGPR_224 : SIRegisterTuples<getSubRegs<7>.ret, VGPR_32, 255, 1, 7, "v">; 654 655// VGPR 256-bit registers 656def VGPR_256 : SIRegisterTuples<getSubRegs<8>.ret, VGPR_32, 255, 1, 8, "v">; 657 658// VGPR 288-bit registers 659def VGPR_288 : SIRegisterTuples<getSubRegs<9>.ret, VGPR_32, 255, 1, 9, "v">; 660 661// VGPR 320-bit registers 662def VGPR_320 : SIRegisterTuples<getSubRegs<10>.ret, VGPR_32, 255, 1, 10, "v">; 663 664// VGPR 352-bit registers 665def VGPR_352 : SIRegisterTuples<getSubRegs<11>.ret, VGPR_32, 255, 1, 11, "v">; 666 667// VGPR 384-bit registers 668def VGPR_384 : SIRegisterTuples<getSubRegs<12>.ret, VGPR_32, 255, 1, 12, "v">; 669 670// VGPR 512-bit registers 671def VGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, VGPR_32, 255, 1, 16, "v">; 672 673// VGPR 1024-bit registers 674def VGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, VGPR_32, 255, 1, 32, "v">; 675 676let HasAGPR = 1 in { 677def AGPR_LO16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16, 678 (add (sequence "AGPR%u_LO16", 0, 255))> { 679 let isAllocatable = 0; 680 let Size = 16; 681 let GeneratePressureSet = 0; 682 let BaseClassOrder = 16; 683} 684 685// AccVGPR 32-bit registers 686def AGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32, 687 (add (sequence "AGPR%u", 0, 255))> { 688 let AllocationPriority = 0; 689 let Size = 32; 690 let Weight = 1; 691 let BaseClassOrder = 32; 692} 693} // End HasAGPR = 1 694 695// AGPR 64-bit registers 696def AGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, AGPR_32, 255, 1, 2, "a">; 697 698// AGPR 96-bit registers 699def AGPR_96 : SIRegisterTuples<getSubRegs<3>.ret, AGPR_32, 255, 1, 3, "a">; 700 701// AGPR 128-bit registers 702def AGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, AGPR_32, 255, 1, 4, "a">; 703 704// AGPR 160-bit registers 705def AGPR_160 : SIRegisterTuples<getSubRegs<5>.ret, AGPR_32, 255, 1, 5, "a">; 706 707// AGPR 192-bit registers 708def AGPR_192 : SIRegisterTuples<getSubRegs<6>.ret, AGPR_32, 255, 1, 6, "a">; 709 710// AGPR 224-bit registers 711def AGPR_224 : SIRegisterTuples<getSubRegs<7>.ret, AGPR_32, 255, 1, 7, "a">; 712 713// AGPR 256-bit registers 714def AGPR_256 : SIRegisterTuples<getSubRegs<8>.ret, AGPR_32, 255, 1, 8, "a">; 715 716// AGPR 288-bit registers 717def AGPR_288 : SIRegisterTuples<getSubRegs<9>.ret, AGPR_32, 255, 1, 9, "a">; 718 719// AGPR 320-bit registers 720def AGPR_320 : SIRegisterTuples<getSubRegs<10>.ret, AGPR_32, 255, 1, 10, "a">; 721 722// AGPR 352-bit registers 723def AGPR_352 : SIRegisterTuples<getSubRegs<11>.ret, AGPR_32, 255, 1, 11, "a">; 724 725// AGPR 384-bit registers 726def AGPR_384 : SIRegisterTuples<getSubRegs<12>.ret, AGPR_32, 255, 1, 12, "a">; 727 728// AGPR 512-bit registers 729def AGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, AGPR_32, 255, 1, 16, "a">; 730 731// AGPR 1024-bit registers 732def AGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, AGPR_32, 255, 1, 32, "a">; 733 734//===----------------------------------------------------------------------===// 735// Register classes used as source and destination 736//===----------------------------------------------------------------------===// 737 738def Pseudo_SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32, 739 (add FP_REG, SP_REG)> { 740 let isAllocatable = 0; 741 let CopyCost = -1; 742 let HasSGPR = 1; 743 let BaseClassOrder = 10000; 744} 745 746def Pseudo_SReg_128 : SIRegisterClass<"AMDGPU", [v4i32, v2i64, v2f64, v8i16, v8f16, v8bf16], 32, 747 (add PRIVATE_RSRC_REG)> { 748 let isAllocatable = 0; 749 let CopyCost = -1; 750 let HasSGPR = 1; 751 let BaseClassOrder = 10000; 752} 753 754def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32], 32, 755 (add LDS_DIRECT)> { 756 let isAllocatable = 0; 757 let CopyCost = -1; 758} 759 760let GeneratePressureSet = 0, HasSGPR = 1 in { 761// Subset of SReg_32 without M0 for SMRD instructions and alike. 762// See comments in SIInstructions.td for more info. 763def SReg_32_XM0_XEXEC : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, i1], 32, 764 (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI, 765 SGPR_NULL, SGPR_NULL_HI, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE_LO, 766 SRC_SHARED_LIMIT_LO, SRC_PRIVATE_BASE_LO, SRC_PRIVATE_LIMIT_LO, SRC_SHARED_BASE_HI, 767 SRC_SHARED_LIMIT_HI, SRC_PRIVATE_BASE_HI, SRC_PRIVATE_LIMIT_HI, SRC_POPS_EXITING_WAVE_ID, 768 SRC_VCCZ, SRC_EXECZ, SRC_SCC)> { 769 let AllocationPriority = 0; 770} 771 772def SReg_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16, 773 (add SGPR_LO16, VCC_LO_LO16, VCC_HI_LO16, FLAT_SCR_LO_LO16, FLAT_SCR_HI_LO16, 774 XNACK_MASK_LO_LO16, XNACK_MASK_HI_LO16, SGPR_NULL_LO16, SGPR_NULL_HI_LO16, TTMP_LO16, 775 TMA_LO_LO16, TMA_HI_LO16, TBA_LO_LO16, TBA_HI_LO16, SRC_SHARED_BASE_LO_LO16, 776 SRC_SHARED_LIMIT_LO_LO16, SRC_PRIVATE_BASE_LO_LO16, SRC_PRIVATE_LIMIT_LO_LO16, 777 SRC_SHARED_BASE_HI_LO16, SRC_SHARED_LIMIT_HI_LO16, SRC_PRIVATE_BASE_HI_LO16, 778 SRC_PRIVATE_LIMIT_HI_LO16, SRC_POPS_EXITING_WAVE_ID_LO16, SRC_VCCZ_LO16, 779 SRC_EXECZ_LO16, SRC_SCC_LO16, EXEC_LO_LO16, EXEC_HI_LO16, M0_CLASS_LO16)> { 780 let Size = 16; 781 let isAllocatable = 0; 782 let BaseClassOrder = 16; 783} 784 785def SReg_32_XEXEC : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, i1], 32, 786 (add SReg_32_XM0_XEXEC, M0_CLASS)> { 787 let AllocationPriority = 0; 788} 789 790def SReg_32_XEXEC_HI : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, i1], 32, 791 (add SReg_32_XEXEC, EXEC_LO)> { 792 let AllocationPriority = 0; 793} 794 795def SReg_32_XM0 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, i1], 32, 796 (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> { 797 let AllocationPriority = 0; 798} 799 800} // End GeneratePressureSet = 0 801 802// Register class for all scalar registers (SGPRs + Special Registers) 803def SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, i1], 32, 804 (add SReg_32_XM0, M0_CLASS)> { 805 let AllocationPriority = 0; 806 let HasSGPR = 1; 807 let BaseClassOrder = 32; 808} 809 810let GeneratePressureSet = 0 in { 811def SRegOrLds_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32, 812 (add SReg_32, LDS_DIRECT_CLASS)> { 813 let isAllocatable = 0; 814 let HasSGPR = 1; 815} 816 817def SGPR_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16, v4bf16], 32, 818 (add SGPR_64Regs)> { 819 let CopyCost = 1; 820 let AllocationPriority = 1; 821 let HasSGPR = 1; 822} 823 824// CCR (call clobbered registers) SGPR 64-bit registers 825def CCR_SGPR_64 : SIRegisterClass<"AMDGPU", SGPR_64.RegTypes, 32, (add (trunc SGPR_64, 15))> { 826 let CopyCost = SGPR_64.CopyCost; 827 let AllocationPriority = SGPR_64.AllocationPriority; 828 let HasSGPR = 1; 829} 830 831// Call clobbered 64-bit SGPRs for AMDGPU_Gfx CC 832def Gfx_CCR_SGPR_64 : SIRegisterClass<"AMDGPU", SGPR_64.RegTypes, 32, 833 (add (trunc (shl SGPR_64, 18), 14))> { // s[36:37]-s[s62:63] 834 let CopyCost = SGPR_64.CopyCost; 835 let AllocationPriority = SGPR_64.AllocationPriority; 836 let HasSGPR = 1; 837} 838 839def TTMP_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, f64, v4i16, v4f16, v4bf16], 32, 840 (add TTMP_64Regs)> { 841 let isAllocatable = 0; 842 let HasSGPR = 1; 843} 844 845def SReg_64_XEXEC : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16, v4bf16], 32, 846 (add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, SGPR_NULL64, SRC_SHARED_BASE, 847 SRC_SHARED_LIMIT, SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT, TTMP_64, TBA, TMA)> { 848 let CopyCost = 1; 849 let AllocationPriority = 1; 850 let HasSGPR = 1; 851} 852 853def SReg_64 : SIRegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16, v4bf16], 32, 854 (add SReg_64_XEXEC, EXEC)> { 855 let CopyCost = 1; 856 let AllocationPriority = 1; 857 let HasSGPR = 1; 858 let BaseClassOrder = 64; 859} 860 861def SReg_1_XEXEC : SIRegisterClass<"AMDGPU", [i1], 32, 862 (add SReg_64_XEXEC, SReg_32_XEXEC)> { 863 let CopyCost = 1; 864 let isAllocatable = 0; 865 let HasSGPR = 1; 866} 867 868def SReg_1 : SIRegisterClass<"AMDGPU", [i1], 32, 869 (add SReg_1_XEXEC, EXEC, EXEC_LO, EXEC_HI)> { 870 let CopyCost = 1; 871 let isAllocatable = 0; 872 let HasSGPR = 1; 873} 874 875multiclass SRegClass<int numRegs, 876 list<ValueType> regTypes, 877 SIRegisterTuples regList, 878 SIRegisterTuples ttmpList = regList, 879 int copyCost = !sra(!add(numRegs, 1), 1)> { 880 defvar hasTTMP = !ne(regList, ttmpList); 881 defvar suffix = !cast<string>(!mul(numRegs, 32)); 882 defvar sgprName = !strconcat("SGPR_", suffix); 883 defvar ttmpName = !strconcat("TTMP_", suffix); 884 885 let AllocationPriority = !sub(numRegs, 1), CopyCost = copyCost, HasSGPR = 1 in { 886 def "" # sgprName : SIRegisterClass<"AMDGPU", regTypes, 32, (add regList)> { 887 } 888 889 if hasTTMP then { 890 def "" # ttmpName : SIRegisterClass<"AMDGPU", regTypes, 32, (add ttmpList)> { 891 let isAllocatable = 0; 892 } 893 } 894 895 def SReg_ # suffix : 896 SIRegisterClass<"AMDGPU", regTypes, 32, 897 !con(!dag(add, [!cast<RegisterClass>(sgprName)], ["sgpr"]), 898 !if(hasTTMP, 899 !dag(add, [!cast<RegisterClass>(ttmpName)], ["ttmp"]), 900 (add)))> { 901 let isAllocatable = 0; 902 let BaseClassOrder = !mul(numRegs, 32); 903 } 904 } 905} 906 907defm "" : SRegClass<3, [v3i32, v3f32], SGPR_96Regs, TTMP_96Regs>; 908defm "" : SRegClass<4, [v4i32, v4f32, v2i64, v2f64, v8i16, v8f16, v8bf16], SGPR_128Regs, TTMP_128Regs>; 909defm "" : SRegClass<5, [v5i32, v5f32], SGPR_160Regs, TTMP_160Regs>; 910defm "" : SRegClass<6, [v6i32, v6f32, v3i64, v3f64], SGPR_192Regs, TTMP_192Regs>; 911defm "" : SRegClass<7, [v7i32, v7f32], SGPR_224Regs, TTMP_224Regs>; 912defm "" : SRegClass<8, [v8i32, v8f32, v4i64, v4f64, v16i16, v16f16, v16bf16], SGPR_256Regs, TTMP_256Regs>; 913defm "" : SRegClass<9, [v9i32, v9f32], SGPR_288Regs, TTMP_288Regs>; 914defm "" : SRegClass<10, [v10i32, v10f32], SGPR_320Regs, TTMP_320Regs>; 915defm "" : SRegClass<11, [v11i32, v11f32], SGPR_352Regs, TTMP_352Regs>; 916defm "" : SRegClass<12, [v12i32, v12f32], SGPR_384Regs, TTMP_384Regs>; 917 918let GlobalPriority = true in { 919defm "" : SRegClass<16, [v16i32, v16f32, v8i64, v8f64, v32i16, v32f16, v32bf16], SGPR_512Regs, TTMP_512Regs>; 920defm "" : SRegClass<32, [v32i32, v32f32, v16i64, v16f64], SGPR_1024Regs>; 921} 922 923def VRegOrLds_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32, 924 (add VGPR_32, LDS_DIRECT_CLASS)> { 925 let isAllocatable = 0; 926 let HasVGPR = 1; 927} 928 929// Register class for all vector registers (VGPRs + Interpolation Registers) 930class VRegClassBase<int numRegs, list<ValueType> regTypes, dag regList> : 931 SIRegisterClass<"AMDGPU", regTypes, 32, regList> { 932 let Size = !mul(numRegs, 32); 933 934 // Requires n v_mov_b32 to copy 935 let CopyCost = numRegs; 936 let AllocationPriority = !sub(numRegs, 1); 937 let Weight = numRegs; 938} 939 940// Define a register tuple class, along with one requiring an even 941// aligned base register. 942multiclass VRegClass<int numRegs, list<ValueType> regTypes, dag regList> { 943 let HasVGPR = 1 in { 944 // Define the regular class. 945 def "" : VRegClassBase<numRegs, regTypes, regList> { 946 let BaseClassOrder = !mul(numRegs, 32); 947 } 948 949 // Define 2-aligned variant 950 def _Align2 : VRegClassBase<numRegs, regTypes, (decimate regList, 2)> { 951 // Give aligned class higher priority in base class resolution 952 let BaseClassOrder = !sub(!mul(numRegs, 32), 1); 953 let RegTupleAlignUnits = 2; 954 } 955 } 956} 957 958defm VReg_64 : VRegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4bf16, v4i16, p0, p1, p4], 959 (add VGPR_64)>; 960defm VReg_96 : VRegClass<3, [v3i32, v3f32], (add VGPR_96)>; 961defm VReg_128 : VRegClass<4, [v4i32, v4f32, v2i64, v2f64, v8i16, v8f16, v8bf16], (add VGPR_128)>; 962defm VReg_160 : VRegClass<5, [v5i32, v5f32], (add VGPR_160)>; 963 964defm VReg_192 : VRegClass<6, [v6i32, v6f32, v3i64, v3f64], (add VGPR_192)>; 965defm VReg_224 : VRegClass<7, [v7i32, v7f32], (add VGPR_224)>; 966defm VReg_256 : VRegClass<8, [v8i32, v8f32, v4i64, v4f64, v16i16, v16f16, v16bf16], (add VGPR_256)>; 967defm VReg_288 : VRegClass<9, [v9i32, v9f32], (add VGPR_288)>; 968defm VReg_320 : VRegClass<10, [v10i32, v10f32], (add VGPR_320)>; 969defm VReg_352 : VRegClass<11, [v11i32, v11f32], (add VGPR_352)>; 970defm VReg_384 : VRegClass<12, [v12i32, v12f32], (add VGPR_384)>; 971 972let GlobalPriority = true in { 973defm VReg_512 : VRegClass<16, [v16i32, v16f32, v8i64, v8f64, v32i16, v32f16, v32bf16], (add VGPR_512)>; 974defm VReg_1024 : VRegClass<32, [v32i32, v32f32, v16i64, v16f64], (add VGPR_1024)>; 975} 976 977multiclass ARegClass<int numRegs, list<ValueType> regTypes, dag regList> { 978 let CopyCost = !add(numRegs, numRegs, 1), HasAGPR = 1 in { 979 // Define the regular class. 980 def "" : VRegClassBase<numRegs, regTypes, regList> { 981 let BaseClassOrder = !mul(numRegs, 32); 982 } 983 984 // Define 2-aligned variant 985 def _Align2 : VRegClassBase<numRegs, regTypes, (decimate regList, 2)> { 986 // Give aligned class higher priority in base class resolution 987 let BaseClassOrder = !sub(!mul(numRegs, 32), 1); 988 let RegTupleAlignUnits = 2; 989 } 990 } 991} 992 993defm AReg_64 : ARegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16], 994 (add AGPR_64)>; 995defm AReg_96 : ARegClass<3, [v3i32, v3f32], (add AGPR_96)>; 996defm AReg_128 : ARegClass<4, [v4i32, v4f32, v2i64, v2f64, v8i16, v8f16, v8bf16], (add AGPR_128)>; 997defm AReg_160 : ARegClass<5, [v5i32, v5f32], (add AGPR_160)>; 998defm AReg_192 : ARegClass<6, [v6i32, v6f32, v3i64, v3f64], (add AGPR_192)>; 999defm AReg_224 : ARegClass<7, [v7i32, v7f32], (add AGPR_224)>; 1000defm AReg_256 : ARegClass<8, [v8i32, v8f32, v4i64, v4f64], (add AGPR_256)>; 1001defm AReg_288 : ARegClass<9, [v9i32, v9f32], (add AGPR_288)>; 1002defm AReg_320 : ARegClass<10, [v10i32, v10f32], (add AGPR_320)>; 1003defm AReg_352 : ARegClass<11, [v11i32, v11f32], (add AGPR_352)>; 1004defm AReg_384 : ARegClass<12, [v12i32, v12f32], (add AGPR_384)>; 1005 1006let GlobalPriority = true in { 1007defm AReg_512 : ARegClass<16, [v16i32, v16f32, v8i64, v8f64], (add AGPR_512)>; 1008defm AReg_1024 : ARegClass<32, [v32i32, v32f32, v16i64, v16f64], (add AGPR_1024)>; 1009} 1010 1011} // End GeneratePressureSet = 0 1012 1013let GeneratePressureSet = 0 in { 1014// No register should ever be allocated using VReg_1. This is a hack for 1015// SelectionDAG that should always be lowered by SILowerI1Copies. TableGen 1016// sorts register classes based on the number of registers in them so this is 1017// sorted to the end and not preferred over VGPR_32. 1018def VReg_1 : SIRegisterClass<"AMDGPU", [i1], 32, (add)> { 1019 let Size = 1; 1020 let HasVGPR = 1; 1021} 1022 1023def VS_16 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16, 1024 (add VGPR_16, SReg_32, LDS_DIRECT_CLASS)> { 1025 let isAllocatable = 0; 1026 let HasVGPR = 1; 1027} 1028 1029def VS_16_Lo128 : SIRegisterClass<"AMDGPU", Reg16Types.types, 16, 1030 (add VGPR_16_Lo128, SReg_32, LDS_DIRECT_CLASS)> { 1031 let isAllocatable = 0; 1032 let HasVGPR = 1; 1033} 1034 1035def VS_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32, 1036 (add VGPR_32, SReg_32, LDS_DIRECT_CLASS)> { 1037 let isAllocatable = 0; 1038 let HasVGPR = 1; 1039 let HasSGPR = 1; 1040} 1041 1042def VS_32_Lo128 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32, 1043 (add VGPR_32_Lo128, SReg_32, LDS_DIRECT_CLASS)> { 1044 let isAllocatable = 0; 1045 let HasVGPR = 1; 1046 let HasSGPR = 1; 1047} 1048 1049def VS_64 : SIRegisterClass<"AMDGPU", [i64, f64, v2f32], 32, (add VReg_64, SReg_64)> { 1050 let isAllocatable = 0; 1051 let HasVGPR = 1; 1052 let HasSGPR = 1; 1053} 1054 1055def AV_32 : SIRegisterClass<"AMDGPU", VGPR_32.RegTypes, 32, (add VGPR_32, AGPR_32)> { 1056 let HasVGPR = 1; 1057 let HasAGPR = 1; 1058} 1059} // End GeneratePressureSet = 0 1060 1061// Define a register tuple class, along with one requiring an even 1062// aligned base register. 1063multiclass AVRegClass<int numRegs, list<ValueType> regTypes, 1064 dag vregList, dag aregList> { 1065 let HasVGPR = 1, HasAGPR = 1 in { 1066 // Define the regular class. 1067 def "" : VRegClassBase<numRegs, regTypes, (add vregList, aregList)>; 1068 1069 // Define 2-aligned variant 1070 def _Align2 : VRegClassBase<numRegs, regTypes, 1071 (add (decimate vregList, 2), 1072 (decimate aregList, 2))> { 1073 let RegTupleAlignUnits = 2; 1074 } 1075 } 1076} 1077 1078defm AV_64 : AVRegClass<2, VReg_64.RegTypes, (add VGPR_64), (add AGPR_64)>; 1079defm AV_96 : AVRegClass<3, VReg_96.RegTypes, (add VGPR_96), (add AGPR_96)>; 1080defm AV_128 : AVRegClass<4, VReg_128.RegTypes, (add VGPR_128), (add AGPR_128)>; 1081defm AV_160 : AVRegClass<5, VReg_160.RegTypes, (add VGPR_160), (add AGPR_160)>; 1082defm AV_192 : AVRegClass<6, VReg_192.RegTypes, (add VGPR_192), (add AGPR_192)>; 1083defm AV_224 : AVRegClass<7, VReg_224.RegTypes, (add VGPR_224), (add AGPR_224)>; 1084defm AV_256 : AVRegClass<8, VReg_256.RegTypes, (add VGPR_256), (add AGPR_256)>; 1085defm AV_288 : AVRegClass<9, VReg_288.RegTypes, (add VGPR_288), (add AGPR_288)>; 1086defm AV_320 : AVRegClass<10, VReg_320.RegTypes, (add VGPR_320), (add AGPR_320)>; 1087defm AV_352 : AVRegClass<11, VReg_352.RegTypes, (add VGPR_352), (add AGPR_352)>; 1088defm AV_384 : AVRegClass<12, VReg_384.RegTypes, (add VGPR_384), (add AGPR_384)>; 1089 1090let GlobalPriority = true in { 1091defm AV_512 : AVRegClass<16, VReg_512.RegTypes, (add VGPR_512), (add AGPR_512)>; 1092defm AV_1024 : AVRegClass<32, VReg_1024.RegTypes, (add VGPR_1024), (add AGPR_1024)>; 1093} 1094 1095//===----------------------------------------------------------------------===// 1096// Register operands 1097//===----------------------------------------------------------------------===// 1098 1099class RegImmMatcher<string name> : AsmOperandClass { 1100 let Name = name; 1101 let RenderMethod = "addRegOrImmOperands"; 1102} 1103 1104class RegOrImmOperand <string RegisterClassName, string OperandTypeName, 1105 string ParserMatchClassName, string decoderImmSize> 1106 : RegisterOperand<!cast<RegisterClass>(RegisterClassName)> { 1107 let OperandNamespace = "AMDGPU"; 1108 let OperandType = OperandTypeName; 1109 let ParserMatchClass = RegImmMatcher<ParserMatchClassName>; 1110 let DecoderMethod = "decodeOperand_" # RegisterClassName # decoderImmSize; 1111 } 1112 1113class RegOrB16 <string RegisterClass, string OperandTypePrefix> 1114 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_INT16", 1115 !subst("_b16", "B16", NAME), "_Imm16">; 1116 1117class RegOrF16 <string RegisterClass, string OperandTypePrefix> 1118 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP16", 1119 !subst("_f16", "F16", NAME), "_Imm16">; 1120 1121class RegOrB16T <string RegisterClass, string OperandTypePrefix> 1122 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_INT16", 1123 !subst("_b16", "B16", NAME), "_Imm16"> { 1124 let EncoderMethod = "getMachineOpValueT16"; 1125} 1126 1127class RegOrF16T <string RegisterClass, string OperandTypePrefix> 1128 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP16", 1129 !subst("_f16", "F16", NAME), "_Imm16"> { 1130 let EncoderMethod = "getMachineOpValueT16"; 1131} 1132 1133class RegOrB16_Lo128T <string RegisterClass, string OperandTypePrefix> 1134 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_INT16", 1135 !subst("_b16_Lo128", "B16_Lo128", NAME), "_Imm16"> { 1136 let EncoderMethod = "getMachineOpValueT16Lo128"; 1137} 1138 1139class RegOrF16_Lo128T <string RegisterClass, string OperandTypePrefix> 1140 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP16", 1141 !subst("_f16_Lo128", "F16_Lo128", NAME), "_Imm16"> { 1142 let EncoderMethod = "getMachineOpValueT16Lo128"; 1143} 1144 1145class RegOrB32 <string RegisterClass, string OperandTypePrefix> 1146 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_INT32", 1147 !subst("_b32", "B32", NAME), "_Imm32">; 1148 1149class RegOrF32 <string RegisterClass, string OperandTypePrefix> 1150 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP32", 1151 !subst("_f32", "F32", NAME), "_Imm32">; 1152 1153class RegOrV2B16 <string RegisterClass, string OperandTypePrefix> 1154 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_V2INT16", 1155 !subst("_v2b16", "V2B16", NAME), "_ImmV2I16">; 1156 1157class RegOrV2F16 <string RegisterClass, string OperandTypePrefix> 1158 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_V2FP16", 1159 !subst("_v2f16", "V2F16", NAME), "_ImmV2F16">; 1160 1161class RegOrF64 <string RegisterClass, string OperandTypePrefix> 1162 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP64", 1163 !subst("_f64", "F64", NAME), "_Imm64">; 1164 1165class RegOrB64 <string RegisterClass, string OperandTypePrefix> 1166 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_INT64", 1167 !subst("_b64", "B64", NAME), "_Imm64">; 1168 1169class RegOrV2F32 <string RegisterClass, string OperandTypePrefix> 1170 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_V2FP32", 1171 !subst("_v2f32", "V2FP32", NAME), "_Imm32">; 1172 1173class RegOrV2B32 <string RegisterClass, string OperandTypePrefix> 1174 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_V2INT32", 1175 !subst("_v2b32", "V2INT32", NAME), "_Imm32">; 1176 1177// For VOP1,2,C True16 instructions. _Lo128 use first 128 32-bit VGPRs only. 1178class RegOrB16_Lo128 <string RegisterClass, string OperandTypePrefix> 1179 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_INT16", 1180 !subst("_b16_Lo128", "B16_Lo128", NAME), "_Imm16">; 1181 1182class RegOrF16_Lo128 <string RegisterClass, string OperandTypePrefix> 1183 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP16", 1184 !subst("_f16_Lo128", "F16_Lo128", NAME), "_Imm16">; 1185 1186// Deferred operands 1187class RegOrF16_Deferred <string RegisterClass, string OperandTypePrefix> 1188 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP16_DEFERRED", 1189 !subst("_f16_Deferred", "F16", NAME), "_Deferred_Imm16">; 1190 1191class RegOrF32_Deferred <string RegisterClass, string OperandTypePrefix> 1192 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP32_DEFERRED", 1193 !subst("_f32_Deferred", "F32", NAME), "_Deferred_Imm32">; 1194 1195class RegOrF16_Lo128_Deferred <string RegisterClass, 1196 string OperandTypePrefix> 1197 : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_FP16_DEFERRED", 1198 !subst("_f16_Lo128_Deferred", "F16_Lo128", NAME), 1199 "_Deferred_Imm16">; 1200 1201//===----------------------------------------------------------------------===// 1202// SSrc_* Operands with an SGPR or a 32-bit immediate 1203//===----------------------------------------------------------------------===// 1204 1205def SSrc_b16 : RegOrB16 <"SReg_32", "OPERAND_REG_IMM">; 1206def SSrc_f16 : RegOrF16 <"SReg_32", "OPERAND_REG_IMM">; 1207def SSrc_b32 : RegOrB32 <"SReg_32", "OPERAND_REG_IMM">; 1208def SSrc_f32 : RegOrF32 <"SReg_32", "OPERAND_REG_IMM">; 1209def SSrc_b64 : RegOrB64 <"SReg_64", "OPERAND_REG_IMM">; 1210 1211def SSrcOrLds_b32 : RegOrB32 <"SRegOrLds_32", "OPERAND_REG_IMM">; 1212 1213//===----------------------------------------------------------------------===// 1214// SSrc_32_Deferred Operands with an SGPR or a 32-bit immediate for use with 1215// FMAMK/FMAAK 1216//===----------------------------------------------------------------------===// 1217 1218def SSrc_f32_Deferred : RegOrF32_Deferred<"SReg_32", "OPERAND_REG_IMM">; 1219 1220//===----------------------------------------------------------------------===// 1221// SCSrc_* Operands with an SGPR or a inline constant 1222//===----------------------------------------------------------------------===// 1223 1224def SCSrc_b32 : RegOrB32 <"SReg_32", "OPERAND_REG_INLINE_C">; 1225def SCSrc_b64 : RegOrB64 <"SReg_64", "OPERAND_REG_INLINE_C">; 1226 1227//===----------------------------------------------------------------------===// 1228// VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate 1229//===----------------------------------------------------------------------===// 1230 1231// The current and temporary future default used case for VOP3. 1232def VSrc_b16 : RegOrB16 <"VS_32", "OPERAND_REG_IMM">; 1233def VSrc_f16 : RegOrF16 <"VS_32", "OPERAND_REG_IMM">; 1234 1235// True16 VOP3 operands. 1236def VSrcT_b16 : RegOrB16T <"VS_16", "OPERAND_REG_IMM"> { 1237 let DecoderMethod = "decodeOperand_VSrcT16"; 1238} 1239def VSrcT_f16 : RegOrF16T <"VS_16", "OPERAND_REG_IMM"> { 1240 let DecoderMethod = "decodeOperand_VSrcT16"; 1241} 1242 1243// True16 VOP1/2/C operands. 1244def VSrcT_b16_Lo128 : RegOrB16_Lo128T <"VS_16_Lo128", "OPERAND_REG_IMM"> { 1245 let DecoderMethod = "decodeOperand_VSrcT16_Lo128"; 1246} 1247def VSrcT_f16_Lo128 : RegOrF16_Lo128T <"VS_16_Lo128", "OPERAND_REG_IMM"> { 1248 let DecoderMethod = "decodeOperand_VSrcT16_Lo128"; 1249} 1250 1251// The current and temporary future default used case for fake VOP1/2/C. 1252def VSrcFake16_b16_Lo128 : RegOrB16_Lo128 <"VS_32_Lo128", "OPERAND_REG_IMM">; 1253def VSrcFake16_f16_Lo128 : RegOrF16_Lo128 <"VS_32_Lo128", "OPERAND_REG_IMM">; 1254 1255def VSrc_b32 : RegOrB32 <"VS_32", "OPERAND_REG_IMM">; 1256def VSrc_f32 : RegOrF32 <"VS_32", "OPERAND_REG_IMM">; 1257def VSrc_v2b16 : RegOrV2B16 <"VS_32", "OPERAND_REG_IMM">; 1258def VSrc_v2f16 : RegOrV2F16 <"VS_32", "OPERAND_REG_IMM">; 1259def VSrc_b64 : RegOrB64 <"VS_64", "OPERAND_REG_IMM">; 1260def VSrc_f64 : RegOrF64 <"VS_64", "OPERAND_REG_IMM"> { 1261 let DecoderMethod = "decodeOperand_VSrc_f64"; 1262} 1263def VSrc_v2b32 : RegOrV2B32 <"VS_64", "OPERAND_REG_IMM">; 1264def VSrc_v2f32 : RegOrV2F32 <"VS_64", "OPERAND_REG_IMM">; 1265 1266//===----------------------------------------------------------------------===// 1267// VSrc_*_Deferred Operands with an SGPR, VGPR or a 32-bit immediate for use 1268// with FMAMK/FMAAK 1269//===----------------------------------------------------------------------===// 1270 1271def VSrc_f16_Deferred : RegOrF16_Deferred<"VS_32", "OPERAND_REG_IMM">; 1272def VSrc_f32_Deferred : RegOrF32_Deferred<"VS_32", "OPERAND_REG_IMM">; 1273 1274def VSrcFake16_f16_Lo128_Deferred : RegOrF16_Lo128_Deferred<"VS_32_Lo128", 1275 "OPERAND_REG_IMM">; 1276 1277//===----------------------------------------------------------------------===// 1278// VRegSrc_* Operands with a VGPR 1279//===----------------------------------------------------------------------===// 1280 1281// This is for operands with the enum(9), VSrc encoding restriction, 1282// but only allows VGPRs. 1283def VRegSrc_32 : RegisterOperand<VGPR_32> { 1284 let DecoderMethod = "decodeOperand_VGPR_32"; 1285} 1286 1287def VRegSrc_64 : RegisterOperand<VReg_64> { 1288 let DecoderMethod = "decodeOperand_VReg_64"; 1289} 1290 1291def VRegSrc_128 : RegisterOperand<VReg_128> { 1292 let DecoderMethod = "decodeOperand_VReg_128"; 1293} 1294 1295def VRegSrc_256 : RegisterOperand<VReg_256> { 1296 let DecoderMethod = "decodeOperand_VReg_256"; 1297} 1298 1299def VRegOrLdsSrc_32 : RegisterOperand<VRegOrLds_32> { 1300 let DecoderMethod = "decodeOperand_VRegOrLds_32"; 1301} 1302 1303//===----------------------------------------------------------------------===// 1304// VGPRSrc_* 1305//===----------------------------------------------------------------------===// 1306 1307// An 8-bit RegisterOperand wrapper for a VGPR 1308def VGPRSrc_32 : RegisterOperand<VGPR_32> { 1309 let DecoderMethod = "DecodeVGPR_32RegisterClass"; 1310} 1311def VGPRSrc_32_Lo128 : RegisterOperand<VGPR_32_Lo128> { 1312 let DecoderMethod = "DecodeVGPR_32RegisterClass"; 1313} 1314 1315def VGPRSrc_16_Lo128 : RegisterOperand<VGPR_16_Lo128> { 1316 let DecoderMethod = "DecodeVGPR_16_Lo128RegisterClass"; 1317 let EncoderMethod = "getMachineOpValueT16Lo128"; 1318} 1319 1320//===----------------------------------------------------------------------===// 1321// ASrc_* Operands with an AccVGPR 1322//===----------------------------------------------------------------------===// 1323 1324def ARegSrc_32 : RegisterOperand<AGPR_32> { 1325 let DecoderMethod = "decodeOperand_AGPR_32"; 1326 let EncoderMethod = "getAVOperandEncoding"; 1327} 1328 1329//===----------------------------------------------------------------------===// 1330// VCSrc_* Operands with an SGPR, VGPR or an inline constant 1331//===----------------------------------------------------------------------===// 1332 1333def VCSrc_b16 : RegOrB16 <"VS_32", "OPERAND_REG_INLINE_C">; 1334def VCSrc_f16 : RegOrF16 <"VS_32", "OPERAND_REG_INLINE_C">; 1335def VCSrc_b32 : RegOrB32 <"VS_32", "OPERAND_REG_INLINE_C">; 1336def VCSrc_f32 : RegOrF32 <"VS_32", "OPERAND_REG_INLINE_C">; 1337def VCSrc_v2b16 : RegOrV2B16 <"VS_32", "OPERAND_REG_INLINE_C">; 1338def VCSrc_v2f16 : RegOrV2F16 <"VS_32", "OPERAND_REG_INLINE_C">; 1339 1340//===----------------------------------------------------------------------===// 1341// VISrc_* Operands with a VGPR or an inline constant 1342//===----------------------------------------------------------------------===// 1343 1344def VISrc_64_f16 : RegOrF16 <"VReg_64", "OPERAND_REG_INLINE_C">; 1345def VISrc_64_b32 : RegOrB32 <"VReg_64", "OPERAND_REG_INLINE_C">; 1346def VISrc_64_f64 : RegOrF64 <"VReg_64", "OPERAND_REG_INLINE_C">; 1347def VISrc_128_f16 : RegOrF16 <"VReg_128", "OPERAND_REG_INLINE_C">; 1348def VISrc_128_b32 : RegOrB32 <"VReg_128", "OPERAND_REG_INLINE_C">; 1349def VISrc_128_f32 : RegOrF32 <"VReg_128", "OPERAND_REG_INLINE_C">; 1350def VISrc_256_b32 : RegOrB32 <"VReg_256", "OPERAND_REG_INLINE_C">; 1351def VISrc_256_f32 : RegOrF32 <"VReg_256", "OPERAND_REG_INLINE_C">; 1352def VISrc_256_f64 : RegOrF64 <"VReg_256", "OPERAND_REG_INLINE_C">; 1353def VISrc_512_b32 : RegOrB32 <"VReg_512", "OPERAND_REG_INLINE_C">; 1354def VISrc_512_f32 : RegOrF32 <"VReg_512", "OPERAND_REG_INLINE_C">; 1355def VISrc_1024_b32 : RegOrB32 <"VReg_1024", "OPERAND_REG_INLINE_C">; 1356def VISrc_1024_f32 : RegOrF32 <"VReg_1024", "OPERAND_REG_INLINE_C">; 1357 1358//===----------------------------------------------------------------------===// 1359// AVSrc_*, AVDst_*, AVLdSt_* Operands with an AGPR or VGPR 1360//===----------------------------------------------------------------------===// 1361 1362def AVSrc_32 : RegisterOperand<AV_32> { 1363 let DecoderMethod = "decodeOperand_AV_32"; 1364 let EncoderMethod = "getAVOperandEncoding"; 1365} 1366 1367def AVSrc_64 : RegisterOperand<AV_64> { 1368 let DecoderMethod = "decodeOperand_AV_64"; 1369 let EncoderMethod = "getAVOperandEncoding"; 1370} 1371 1372def AVSrc_128 : RegisterOperand<AV_128> { 1373 let DecoderMethod = "decodeOperand_AV_128"; 1374 let EncoderMethod = "getAVOperandEncoding"; 1375} 1376 1377def AVDst_128 : RegisterOperand<AV_128> { 1378 let DecoderMethod = "DecodeAVDst_128RegisterClass"; 1379 let EncoderMethod = "getAVOperandEncoding"; 1380} 1381 1382def AVDst_512 : RegisterOperand<AV_512> { 1383 let DecoderMethod = "DecodeAVDst_512RegisterClass"; 1384 let EncoderMethod = "getAVOperandEncoding"; 1385} 1386 1387def AVLdSt_32 : RegisterOperand<AV_32> { 1388 let DecoderMethod = "DecodeAVLdSt_32RegisterClass"; 1389 let EncoderMethod = "getAVOperandEncoding"; 1390} 1391 1392def AVLdSt_64 : RegisterOperand<AV_64> { 1393 let DecoderMethod = "DecodeAVLdSt_64RegisterClass"; 1394 let EncoderMethod = "getAVOperandEncoding"; 1395} 1396 1397def AVLdSt_96 : RegisterOperand<AV_96> { 1398 let DecoderMethod = "DecodeAVLdSt_96RegisterClass"; 1399 let EncoderMethod = "getAVOperandEncoding"; 1400} 1401 1402def AVLdSt_128 : RegisterOperand<AV_128> { 1403 let DecoderMethod = "DecodeAVLdSt_128RegisterClass"; 1404 let EncoderMethod = "getAVOperandEncoding"; 1405} 1406 1407def AVLdSt_160 : RegisterOperand<AV_160> { 1408 let DecoderMethod = "DecodeAVLdSt_160RegisterClass"; 1409 let EncoderMethod = "getAVOperandEncoding"; 1410} 1411 1412//===----------------------------------------------------------------------===// 1413// ACSrc_* Operands with an AGPR or an inline constant 1414//===----------------------------------------------------------------------===// 1415 1416def AISrc_64_f64 : RegOrF64 <"AReg_64", "OPERAND_REG_INLINE_AC">; 1417def AISrc_128_f32 : RegOrF32 <"AReg_128", "OPERAND_REG_INLINE_AC">; 1418def AISrc_128_b32 : RegOrB32 <"AReg_128", "OPERAND_REG_INLINE_AC">; 1419def AISrc_256_f64 : RegOrF64 <"AReg_256", "OPERAND_REG_INLINE_AC">; 1420def AISrc_512_f32 : RegOrF32 <"AReg_512", "OPERAND_REG_INLINE_AC">; 1421def AISrc_512_b32 : RegOrB32 <"AReg_512", "OPERAND_REG_INLINE_AC">; 1422def AISrc_1024_f32 : RegOrF32 <"AReg_1024", "OPERAND_REG_INLINE_AC">; 1423def AISrc_1024_b32 : RegOrB32 <"AReg_1024", "OPERAND_REG_INLINE_AC">; 1424