1//===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Helpers 11//===----------------------------------------------------------------------===// 12 13class getSubRegs<int size> { 14 list<SubRegIndex> ret2 = [sub0, sub1]; 15 list<SubRegIndex> ret3 = [sub0, sub1, sub2]; 16 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3]; 17 list<SubRegIndex> ret5 = [sub0, sub1, sub2, sub3, sub4]; 18 list<SubRegIndex> ret8 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7]; 19 list<SubRegIndex> ret16 = [sub0, sub1, sub2, sub3, 20 sub4, sub5, sub6, sub7, 21 sub8, sub9, sub10, sub11, 22 sub12, sub13, sub14, sub15]; 23 list<SubRegIndex> ret32 = [sub0, sub1, sub2, sub3, 24 sub4, sub5, sub6, sub7, 25 sub8, sub9, sub10, sub11, 26 sub12, sub13, sub14, sub15, 27 sub16, sub17, sub18, sub19, 28 sub20, sub21, sub22, sub23, 29 sub24, sub25, sub26, sub27, 30 sub28, sub29, sub30, sub31]; 31 32 list<SubRegIndex> ret = !if(!eq(size, 2), ret2, 33 !if(!eq(size, 3), ret3, 34 !if(!eq(size, 4), ret4, 35 !if(!eq(size, 5), ret5, 36 !if(!eq(size, 8), ret8, 37 !if(!eq(size, 16), ret16, ret32)))))); 38} 39 40// Generates list of sequential register tuple names. 41// E.g. RegSeq<3,2,2,"s">.ret -> [ "s[0:1]", "s[2:3]" ] 42class RegSeqNames<int last_reg, int stride, int size, string prefix, 43 int start = 0> { 44 int next = !add(start, stride); 45 int end_reg = !add(!add(start, size), -1); 46 list<string> ret = 47 !if(!le(end_reg, last_reg), 48 !listconcat([prefix # "[" # start # ":" # end_reg # "]"], 49 RegSeqNames<last_reg, stride, size, prefix, next>.ret), 50 []); 51} 52 53// Generates list of dags for register tupless. 54class RegSeqDags<RegisterClass RC, int last_reg, int stride, int size, 55 int start = 0> { 56 dag trunc_rc = (trunc RC, 57 !if(!and(!eq(stride, 1), !eq(start, 0)), 58 !add(!add(last_reg, 2), !mul(size, -1)), 59 !add(last_reg, 1))); 60 list<dag> ret = 61 !if(!lt(start, size), 62 !listconcat([(add (decimate (shl trunc_rc, start), stride))], 63 RegSeqDags<RC, last_reg, stride, size, !add(start, 1)>.ret), 64 []); 65} 66 67class SIRegisterTuples<list<SubRegIndex> Indices, RegisterClass RC, 68 int last_reg, int stride, int size, string prefix> : 69 RegisterTuples<Indices, 70 RegSeqDags<RC, last_reg, stride, size>.ret, 71 RegSeqNames<last_reg, stride, size, prefix>.ret>; 72 73//===----------------------------------------------------------------------===// 74// Declarations that describe the SI registers 75//===----------------------------------------------------------------------===// 76class SIReg <string n, bits<16> regIdx = 0> : 77 Register<n>, 78 DwarfRegNum<[!cast<int>(HWEncoding)]> { 79 let Namespace = "AMDGPU"; 80 81 // This is the not yet the complete register encoding. An additional 82 // bit is set for VGPRs. 83 let HWEncoding = regIdx; 84} 85 86// Special Registers 87def VCC_LO : SIReg<"vcc_lo", 106>; 88def VCC_HI : SIReg<"vcc_hi", 107>; 89 90// Pseudo-registers: Used as placeholders during isel and immediately 91// replaced, never seeing the verifier. 92def PRIVATE_RSRC_REG : SIReg<"private_rsrc", 0>; 93def FP_REG : SIReg<"fp", 0>; 94def SP_REG : SIReg<"sp", 0>; 95def SCRATCH_WAVE_OFFSET_REG : SIReg<"scratch_wave_offset", 0>; 96 97// VCC for 64-bit instructions 98def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]>, 99 DwarfRegAlias<VCC_LO> { 100 let Namespace = "AMDGPU"; 101 let SubRegIndices = [sub0, sub1]; 102 let HWEncoding = 106; 103} 104 105def EXEC_LO : SIReg<"exec_lo", 126>; 106def EXEC_HI : SIReg<"exec_hi", 127>; 107 108def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, 109 DwarfRegAlias<EXEC_LO> { 110 let Namespace = "AMDGPU"; 111 let SubRegIndices = [sub0, sub1]; 112 let HWEncoding = 126; 113} 114 115// 32-bit real registers, for MC only. 116// May be used with both 32-bit and 64-bit operands. 117def SRC_VCCZ : SIReg<"src_vccz", 251>; 118def SRC_EXECZ : SIReg<"src_execz", 252>; 119def SRC_SCC : SIReg<"src_scc", 253>; 120 121// 1-bit pseudo register, for codegen only. 122// Should never be emitted. 123def SCC : SIReg<"scc">; 124 125def M0 : SIReg <"m0", 124>; 126def SGPR_NULL : SIReg<"null", 125>; 127 128def SRC_SHARED_BASE : SIReg<"src_shared_base", 235>; 129def SRC_SHARED_LIMIT : SIReg<"src_shared_limit", 236>; 130def SRC_PRIVATE_BASE : SIReg<"src_private_base", 237>; 131def SRC_PRIVATE_LIMIT : SIReg<"src_private_limit", 238>; 132def SRC_POPS_EXITING_WAVE_ID : SIReg<"src_pops_exiting_wave_id", 239>; 133 134def LDS_DIRECT : SIReg <"src_lds_direct", 254>; 135 136def XNACK_MASK_LO : SIReg<"xnack_mask_lo", 104>; 137def XNACK_MASK_HI : SIReg<"xnack_mask_hi", 105>; 138 139def XNACK_MASK : RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]>, 140 DwarfRegAlias<XNACK_MASK_LO> { 141 let Namespace = "AMDGPU"; 142 let SubRegIndices = [sub0, sub1]; 143 let HWEncoding = 104; 144} 145 146// Trap handler registers 147def TBA_LO : SIReg<"tba_lo", 108>; 148def TBA_HI : SIReg<"tba_hi", 109>; 149 150def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]>, 151 DwarfRegAlias<TBA_LO> { 152 let Namespace = "AMDGPU"; 153 let SubRegIndices = [sub0, sub1]; 154 let HWEncoding = 108; 155} 156 157def TMA_LO : SIReg<"tma_lo", 110>; 158def TMA_HI : SIReg<"tma_hi", 111>; 159 160def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]>, 161 DwarfRegAlias<TMA_LO> { 162 let Namespace = "AMDGPU"; 163 let SubRegIndices = [sub0, sub1]; 164 let HWEncoding = 110; 165} 166 167foreach Index = 0-15 in { 168 def TTMP#Index#_vi : SIReg<"ttmp"#Index, !add(112, Index)>; 169 def TTMP#Index#_gfx9_gfx10 : SIReg<"ttmp"#Index, !add(108, Index)>; 170 def TTMP#Index : SIReg<"ttmp"#Index, 0>; 171} 172 173multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> { 174 def _ci : SIReg<n, ci_e>; 175 def _vi : SIReg<n, vi_e>; 176 def "" : SIReg<n, 0>; 177} 178 179class FlatReg <Register lo, Register hi, bits<16> encoding> : 180 RegisterWithSubRegs<"flat_scratch", [lo, hi]>, 181 DwarfRegAlias<lo> { 182 let Namespace = "AMDGPU"; 183 let SubRegIndices = [sub0, sub1]; 184 let HWEncoding = encoding; 185} 186 187defm FLAT_SCR_LO : FLAT_SCR_LOHI_m<"flat_scratch_lo", 104, 102>; // Offset in units of 256-bytes. 188defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes. 189 190def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>; 191def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>; 192def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>; 193 194// SGPR registers 195foreach Index = 0-105 in { 196 def SGPR#Index : SIReg <"s"#Index, Index>; 197} 198 199// VGPR registers 200foreach Index = 0-255 in { 201 def VGPR#Index : SIReg <"v"#Index, Index> { 202 let HWEncoding{8} = 1; 203 } 204} 205 206// AccVGPR registers 207foreach Index = 0-255 in { 208 def AGPR#Index : SIReg <"a"#Index, Index> { 209 let HWEncoding{8} = 1; 210 } 211} 212 213//===----------------------------------------------------------------------===// 214// Groupings using register classes and tuples 215//===----------------------------------------------------------------------===// 216 217def SCC_CLASS : RegisterClass<"AMDGPU", [i1], 1, (add SCC)> { 218 let CopyCost = -1; 219 let isAllocatable = 0; 220} 221 222def M0_CLASS : RegisterClass<"AMDGPU", [i32], 32, (add M0)> { 223 let CopyCost = 1; 224 let isAllocatable = 0; 225} 226 227// TODO: Do we need to set DwarfRegAlias on register tuples? 228 229// SGPR 32-bit registers 230def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 231 (add (sequence "SGPR%u", 0, 105))> { 232 // Give all SGPR classes higher priority than VGPR classes, because 233 // we want to spill SGPRs to VGPRs. 234 let AllocationPriority = 9; 235} 236 237// SGPR 64-bit registers 238def SGPR_64Regs : SIRegisterTuples<getSubRegs<2>.ret, SGPR_32, 105, 2, 2, "s">; 239 240// SGPR 96-bit registers. No operations use these, but for symmetry with 96-bit VGPRs. 241def SGPR_96Regs : SIRegisterTuples<getSubRegs<3>.ret, SGPR_32, 105, 3, 3, "s">; 242 243// SGPR 128-bit registers 244def SGPR_128Regs : SIRegisterTuples<getSubRegs<4>.ret, SGPR_32, 105, 4, 4, "s">; 245 246// SGPR 160-bit registers. No operations use these, but for symmetry with 160-bit VGPRs. 247def SGPR_160Regs : SIRegisterTuples<getSubRegs<5>.ret, SGPR_32, 105, 4, 5, "s">; 248 249// SGPR 256-bit registers 250def SGPR_256Regs : SIRegisterTuples<getSubRegs<8>.ret, SGPR_32, 105, 4, 8, "s">; 251 252// SGPR 512-bit registers 253def SGPR_512Regs : SIRegisterTuples<getSubRegs<16>.ret, SGPR_32, 105, 4, 16, "s">; 254 255// SGPR 1024-bit registers 256def SGPR_1024Regs : SIRegisterTuples<getSubRegs<32>.ret, SGPR_32, 105, 4, 32, "s">; 257 258// Trap handler TMP 32-bit registers 259def TTMP_32 : RegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32, 260 (add (sequence "TTMP%u", 0, 15))> { 261 let isAllocatable = 0; 262} 263 264// Trap handler TMP 64-bit registers 265def TTMP_64Regs : SIRegisterTuples<getSubRegs<2>.ret, TTMP_32, 15, 2, 2, "ttmp">; 266 267// Trap handler TMP 128-bit registers 268def TTMP_128Regs : SIRegisterTuples<getSubRegs<4>.ret, TTMP_32, 15, 4, 4, "ttmp">; 269 270def TTMP_256Regs : SIRegisterTuples<getSubRegs<8>.ret, TTMP_32, 15, 4, 8, "ttmp">; 271 272def TTMP_512Regs : SIRegisterTuples<getSubRegs<16>.ret, TTMP_32, 15, 4, 16, "ttmp">; 273 274class TmpRegTuplesBase<int index, int size, 275 list<Register> subRegs, 276 list<SubRegIndex> indices = getSubRegs<size>.ret, 277 int index1 = !add(index, !add(size, -1)), 278 string name = "ttmp["#index#":"#index1#"]"> : 279 RegisterWithSubRegs<name, subRegs> { 280 let HWEncoding = subRegs[0].HWEncoding; 281 let SubRegIndices = indices; 282} 283 284class TmpRegTuples<string tgt, 285 int size, 286 int index0, 287 int index1 = !add(index0, 1), 288 int index2 = !add(index0, !if(!eq(size, 2), 1, 2)), 289 int index3 = !add(index0, !if(!eq(size, 2), 1, 3)), 290 int index4 = !add(index0, !if(!eq(size, 8), 4, 1)), 291 int index5 = !add(index0, !if(!eq(size, 8), 5, 1)), 292 int index6 = !add(index0, !if(!eq(size, 8), 6, 1)), 293 int index7 = !add(index0, !if(!eq(size, 8), 7, 1)), 294 Register r0 = !cast<Register>("TTMP"#index0#tgt), 295 Register r1 = !cast<Register>("TTMP"#index1#tgt), 296 Register r2 = !cast<Register>("TTMP"#index2#tgt), 297 Register r3 = !cast<Register>("TTMP"#index3#tgt), 298 Register r4 = !cast<Register>("TTMP"#index4#tgt), 299 Register r5 = !cast<Register>("TTMP"#index5#tgt), 300 Register r6 = !cast<Register>("TTMP"#index6#tgt), 301 Register r7 = !cast<Register>("TTMP"#index7#tgt)> : 302 TmpRegTuplesBase<index0, size, 303 !if(!eq(size, 2), [r0, r1], 304 !if(!eq(size, 4), [r0, r1, r2, r3], 305 [r0, r1, r2, r3, r4, r5, r6, r7])), 306 getSubRegs<size>.ret>; 307 308foreach Index = {0, 2, 4, 6, 8, 10, 12, 14} in { 309 def TTMP#Index#_TTMP#!add(Index,1)#_vi : TmpRegTuples<"_vi", 2, Index>; 310 def TTMP#Index#_TTMP#!add(Index,1)#_gfx9_gfx10 : TmpRegTuples<"_gfx9_gfx10", 2, Index>; 311} 312 313foreach Index = {0, 4, 8, 12} in { 314 def TTMP#Index#_TTMP#!add(Index,1)# 315 _TTMP#!add(Index,2)# 316 _TTMP#!add(Index,3)#_vi : TmpRegTuples<"_vi", 4, Index>; 317 def TTMP#Index#_TTMP#!add(Index,1)# 318 _TTMP#!add(Index,2)# 319 _TTMP#!add(Index,3)#_gfx9_gfx10 : TmpRegTuples<"_gfx9_gfx10", 4, Index>; 320} 321 322foreach Index = {0, 4, 8} in { 323 def TTMP#Index#_TTMP#!add(Index,1)# 324 _TTMP#!add(Index,2)# 325 _TTMP#!add(Index,3)# 326 _TTMP#!add(Index,4)# 327 _TTMP#!add(Index,5)# 328 _TTMP#!add(Index,6)# 329 _TTMP#!add(Index,7)#_vi : TmpRegTuples<"_vi", 8, Index>; 330 def TTMP#Index#_TTMP#!add(Index,1)# 331 _TTMP#!add(Index,2)# 332 _TTMP#!add(Index,3)# 333 _TTMP#!add(Index,4)# 334 _TTMP#!add(Index,5)# 335 _TTMP#!add(Index,6)# 336 _TTMP#!add(Index,7)#_gfx9_gfx10 : TmpRegTuples<"_gfx9_gfx10", 8, Index>; 337} 338 339def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_vi : 340 TmpRegTuplesBase<0, 16, 341 [TTMP0_vi, TTMP1_vi, TTMP2_vi, TTMP3_vi, 342 TTMP4_vi, TTMP5_vi, TTMP6_vi, TTMP7_vi, 343 TTMP8_vi, TTMP9_vi, TTMP10_vi, TTMP11_vi, 344 TTMP12_vi, TTMP13_vi, TTMP14_vi, TTMP15_vi]>; 345 346def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_gfx9_gfx10 : 347 TmpRegTuplesBase<0, 16, 348 [TTMP0_gfx9_gfx10, TTMP1_gfx9_gfx10, TTMP2_gfx9_gfx10, TTMP3_gfx9_gfx10, 349 TTMP4_gfx9_gfx10, TTMP5_gfx9_gfx10, TTMP6_gfx9_gfx10, TTMP7_gfx9_gfx10, 350 TTMP8_gfx9_gfx10, TTMP9_gfx9_gfx10, TTMP10_gfx9_gfx10, TTMP11_gfx9_gfx10, 351 TTMP12_gfx9_gfx10, TTMP13_gfx9_gfx10, TTMP14_gfx9_gfx10, TTMP15_gfx9_gfx10]>; 352 353class RegisterTypes<list<ValueType> reg_types> { 354 list<ValueType> types = reg_types; 355} 356 357def Reg16Types : RegisterTypes<[i16, f16]>; 358def Reg32Types : RegisterTypes<[i32, f32, v2i16, v2f16, p2, p3, p5, p6]>; 359 360 361// VGPR 32-bit registers 362// i16/f16 only on VI+ 363def VGPR_32 : RegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32, 364 (add (sequence "VGPR%u", 0, 255))> { 365 let AllocationPriority = 1; 366 let Size = 32; 367} 368 369// VGPR 64-bit registers 370def VGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, VGPR_32, 255, 1, 2, "v">; 371 372// VGPR 96-bit registers 373def VGPR_96 : SIRegisterTuples<getSubRegs<3>.ret, VGPR_32, 255, 1, 3, "v">; 374 375// VGPR 128-bit registers 376def VGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, VGPR_32, 255, 1, 4, "v">; 377 378// VGPR 160-bit registers 379def VGPR_160 : SIRegisterTuples<getSubRegs<5>.ret, VGPR_32, 255, 1, 5, "v">; 380 381// VGPR 256-bit registers 382def VGPR_256 : SIRegisterTuples<getSubRegs<8>.ret, VGPR_32, 255, 1, 8, "v">; 383 384// VGPR 512-bit registers 385def VGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, VGPR_32, 255, 1, 16, "v">; 386 387// VGPR 1024-bit registers 388def VGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, VGPR_32, 255, 1, 32, "v">; 389 390// AccVGPR 32-bit registers 391def AGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 392 (add (sequence "AGPR%u", 0, 255))> { 393 let AllocationPriority = 1; 394 let Size = 32; 395} 396 397// AGPR 64-bit registers 398def AGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, AGPR_32, 255, 1, 2, "a">; 399 400// AGPR 128-bit registers 401def AGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, AGPR_32, 255, 1, 4, "a">; 402 403// AGPR 512-bit registers 404def AGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, AGPR_32, 255, 1, 16, "a">; 405 406// AGPR 1024-bit registers 407def AGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, AGPR_32, 255, 1, 32, "a">; 408 409//===----------------------------------------------------------------------===// 410// Register classes used as source and destination 411//===----------------------------------------------------------------------===// 412 413def Pseudo_SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 414 (add FP_REG, SP_REG, SCRATCH_WAVE_OFFSET_REG)> { 415 let isAllocatable = 0; 416 let CopyCost = -1; 417} 418 419def Pseudo_SReg_128 : RegisterClass<"AMDGPU", [v4i32, v2i64, v2f64], 32, 420 (add PRIVATE_RSRC_REG)> { 421 let isAllocatable = 0; 422 let CopyCost = -1; 423} 424 425def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 426 (add LDS_DIRECT)> { 427 let isAllocatable = 0; 428 let CopyCost = -1; 429} 430 431// Subset of SReg_32 without M0 for SMRD instructions and alike. 432// See comments in SIInstructions.td for more info. 433def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 434 (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI, 435 SGPR_NULL, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT, 436 SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT, SRC_POPS_EXITING_WAVE_ID, 437 SRC_VCCZ, SRC_EXECZ, SRC_SCC)> { 438 let AllocationPriority = 10; 439} 440 441def SReg_32_XEXEC_HI : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 442 (add SReg_32_XM0_XEXEC, EXEC_LO, M0_CLASS)> { 443 let AllocationPriority = 10; 444} 445 446def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 447 (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> { 448 let AllocationPriority = 10; 449} 450 451// Register class for all scalar registers (SGPRs + Special Registers) 452def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 453 (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI)> { 454 let AllocationPriority = 10; 455} 456 457def SRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, 458 (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI, LDS_DIRECT_CLASS)> { 459 let isAllocatable = 0; 460} 461 462def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32, 463 (add SGPR_64Regs)> { 464 let CopyCost = 1; 465 let AllocationPriority = 11; 466} 467 468// CCR (call clobbered registers) SGPR 64-bit registers 469def CCR_SGPR_64 : RegisterClass<"AMDGPU", SGPR_64.RegTypes, 32, 470 (add (trunc SGPR_64, 16))> { 471 let CopyCost = SGPR_64.CopyCost; 472 let AllocationPriority = SGPR_64.AllocationPriority; 473} 474 475def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, v4i16, v4f16], 32, 476 (add TTMP_64Regs)> { 477 let isAllocatable = 0; 478} 479 480def SReg_64_XEXEC : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32, 481 (add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, TTMP_64, TBA, TMA)> { 482 let CopyCost = 1; 483 let AllocationPriority = 13; 484} 485 486def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32, 487 (add SReg_64_XEXEC, EXEC)> { 488 let CopyCost = 1; 489 let AllocationPriority = 13; 490} 491 492def SReg_1_XEXEC : RegisterClass<"AMDGPU", [i1], 32, 493 (add SReg_64_XEXEC, SReg_32_XM0_XEXEC)> { 494 let CopyCost = 1; 495 let isAllocatable = 0; 496} 497 498def SReg_1 : RegisterClass<"AMDGPU", [i1], 32, 499 (add SReg_1_XEXEC, EXEC, EXEC_LO)> { 500 let CopyCost = 1; 501 let isAllocatable = 0; 502} 503 504// Requires 2 s_mov_b64 to copy 505let CopyCost = 2 in { 506 507// There are no 3-component scalar instructions, but this is needed 508// for symmetry with VGPRs. 509def SGPR_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32, 510 (add SGPR_96Regs)> { 511 let AllocationPriority = 14; 512} 513 514def SReg_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32, 515 (add SGPR_96)> { 516 let AllocationPriority = 14; 517} 518 519def SGPR_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64], 32, 520 (add SGPR_128Regs)> { 521 let AllocationPriority = 15; 522} 523 524def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64], 32, 525 (add TTMP_128Regs)> { 526 let isAllocatable = 0; 527} 528 529def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32, 530 (add SGPR_128, TTMP_128)> { 531 let AllocationPriority = 15; 532 let isAllocatable = 0; 533} 534 535} // End CopyCost = 2 536 537// There are no 5-component scalar instructions, but this is needed 538// for symmetry with VGPRs. 539def SGPR_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32, 540 (add SGPR_160Regs)> { 541 let AllocationPriority = 16; 542} 543 544def SReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32, 545 (add SGPR_160)> { 546 let AllocationPriority = 16; 547} 548 549def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256Regs)> { 550 let AllocationPriority = 17; 551} 552 553def TTMP_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add TTMP_256Regs)> { 554 let isAllocatable = 0; 555} 556 557def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, 558 (add SGPR_256, TTMP_256)> { 559 // Requires 4 s_mov_b64 to copy 560 let CopyCost = 4; 561 let AllocationPriority = 17; 562} 563 564def SGPR_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, 565 (add SGPR_512Regs)> { 566 let AllocationPriority = 18; 567} 568 569def TTMP_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, 570 (add TTMP_512Regs)> { 571 let isAllocatable = 0; 572} 573 574def SReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, 575 (add SGPR_512, TTMP_512)> { 576 // Requires 8 s_mov_b64 to copy 577 let CopyCost = 8; 578 let AllocationPriority = 18; 579} 580 581def VRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 582 (add VGPR_32, LDS_DIRECT_CLASS)> { 583 let isAllocatable = 0; 584} 585 586def SGPR_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, 587 (add SGPR_1024Regs)> { 588 let AllocationPriority = 19; 589} 590 591def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, 592 (add SGPR_1024)> { 593 let CopyCost = 16; 594 let AllocationPriority = 19; 595} 596 597// Register class for all vector registers (VGPRs + Interploation Registers) 598def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32, v4f16, v4i16, p0, p1, p4], 32, 599 (add VGPR_64)> { 600 let Size = 64; 601 602 // Requires 2 v_mov_b32 to copy 603 let CopyCost = 2; 604 let AllocationPriority = 2; 605} 606 607def VReg_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32, (add VGPR_96)> { 608 let Size = 96; 609 610 // Requires 3 v_mov_b32 to copy 611 let CopyCost = 3; 612 let AllocationPriority = 3; 613} 614 615def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32, 616 (add VGPR_128)> { 617 let Size = 128; 618 619 // Requires 4 v_mov_b32 to copy 620 let CopyCost = 4; 621 let AllocationPriority = 4; 622} 623 624def VReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32, 625 (add VGPR_160)> { 626 let Size = 160; 627 628 // Requires 5 v_mov_b32 to copy 629 let CopyCost = 5; 630 let AllocationPriority = 5; 631} 632 633def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, 634 (add VGPR_256)> { 635 let Size = 256; 636 let CopyCost = 8; 637 let AllocationPriority = 6; 638} 639 640def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, 641 (add VGPR_512)> { 642 let Size = 512; 643 let CopyCost = 16; 644 let AllocationPriority = 7; 645} 646 647def VReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, 648 (add VGPR_1024)> { 649 let Size = 1024; 650 let CopyCost = 32; 651 let AllocationPriority = 8; 652} 653 654def AReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32, v4f16, v4i16], 32, 655 (add AGPR_64)> { 656 let Size = 64; 657 658 let CopyCost = 5; 659 let AllocationPriority = 2; 660} 661 662def AReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32, 663 (add AGPR_128)> { 664 let Size = 128; 665 666 // Requires 4 v_accvgpr_write and 4 v_accvgpr_read to copy + burn 1 vgpr 667 let CopyCost = 9; 668 let AllocationPriority = 4; 669} 670 671def AReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, 672 (add AGPR_512)> { 673 let Size = 512; 674 let CopyCost = 33; 675 let AllocationPriority = 7; 676} 677 678def AReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, 679 (add AGPR_1024)> { 680 let Size = 1024; 681 let CopyCost = 65; 682 let AllocationPriority = 8; 683} 684 685def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> { 686 let Size = 1; 687} 688 689def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 690 (add VGPR_32, SReg_32, LDS_DIRECT_CLASS)> { 691 let isAllocatable = 0; 692} 693 694def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> { 695 let isAllocatable = 0; 696} 697 698def AV_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, 699 (add AGPR_32, VGPR_32)> { 700 let isAllocatable = 0; 701} 702 703def AV_64 : RegisterClass<"AMDGPU", [i64, f64, v4f16], 32, 704 (add AReg_64, VReg_64)> { 705 let isAllocatable = 0; 706} 707 708//===----------------------------------------------------------------------===// 709// Register operands 710//===----------------------------------------------------------------------===// 711 712class RegImmMatcher<string name> : AsmOperandClass { 713 let Name = name; 714 let RenderMethod = "addRegOrImmOperands"; 715} 716 717multiclass SIRegOperand32 <string rc, string MatchName, string opType, 718 string rc_suffix = "_32"> { 719 let OperandNamespace = "AMDGPU" in { 720 def _b16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 721 let OperandType = opType#"_INT16"; 722 let ParserMatchClass = RegImmMatcher<MatchName#"B16">; 723 let DecoderMethod = "decodeOperand_VSrc16"; 724 } 725 726 def _f16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 727 let OperandType = opType#"_FP16"; 728 let ParserMatchClass = RegImmMatcher<MatchName#"F16">; 729 let DecoderMethod = "decodeOperand_" # rc # "_16"; 730 } 731 732 def _b32 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 733 let OperandType = opType#"_INT32"; 734 let ParserMatchClass = RegImmMatcher<MatchName#"B32">; 735 let DecoderMethod = "decodeOperand_" # rc # rc_suffix; 736 } 737 738 def _f32 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 739 let OperandType = opType#"_FP32"; 740 let ParserMatchClass = RegImmMatcher<MatchName#"F32">; 741 let DecoderMethod = "decodeOperand_" # rc # rc_suffix; 742 } 743 744 def _v2b16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 745 let OperandType = opType#"_V2INT16"; 746 let ParserMatchClass = RegImmMatcher<MatchName#"V2B16">; 747 let DecoderMethod = "decodeOperand_VSrcV216"; 748 } 749 750 def _v2f16 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { 751 let OperandType = opType#"_V2FP16"; 752 let ParserMatchClass = RegImmMatcher<MatchName#"V2F16">; 753 let DecoderMethod = "decodeOperand_VSrcV216"; 754 } 755 } 756} 757 758multiclass SIRegOperand <string rc, string MatchName, string opType> : 759 SIRegOperand32<rc, MatchName, opType> { 760 let OperandNamespace = "AMDGPU" in { 761 def _b64 : RegisterOperand<!cast<RegisterClass>(rc#"_64")> { 762 let OperandType = opType#"_INT64"; 763 let ParserMatchClass = RegImmMatcher<MatchName#"B64">; 764 } 765 766 def _f64 : RegisterOperand<!cast<RegisterClass>(rc#"_64")> { 767 let OperandType = opType#"_FP64"; 768 let ParserMatchClass = RegImmMatcher<MatchName#"F64">; 769 } 770 } 771} 772 773// FIXME: 64-bit sources can sometimes use 32-bit constants. 774multiclass RegImmOperand <string rc, string MatchName> 775 : SIRegOperand<rc, MatchName, "OPERAND_REG_IMM">; 776 777multiclass RegInlineOperand <string rc, string MatchName> 778 : SIRegOperand<rc, MatchName, "OPERAND_REG_INLINE_C">; 779 780multiclass RegInlineOperand32 <string rc, string MatchName, 781 string rc_suffix = "_32"> 782 : SIRegOperand32<rc, MatchName, "OPERAND_REG_INLINE_C", rc_suffix>; 783 784multiclass RegInlineOperandAC <string rc, string MatchName, 785 string rc_suffix = "_32"> 786 : SIRegOperand32<rc, MatchName, "OPERAND_REG_INLINE_AC", rc_suffix>; 787 788//===----------------------------------------------------------------------===// 789// SSrc_* Operands with an SGPR or a 32-bit immediate 790//===----------------------------------------------------------------------===// 791 792defm SSrc : RegImmOperand<"SReg", "SSrc">; 793 794def SSrcOrLds_b32 : RegisterOperand<SRegOrLds_32> { 795 let OperandNamespace = "AMDGPU"; 796 let OperandType = "OPERAND_REG_IMM_INT32"; 797 let ParserMatchClass = RegImmMatcher<"SSrcOrLdsB32">; 798} 799 800//===----------------------------------------------------------------------===// 801// SCSrc_* Operands with an SGPR or a inline constant 802//===----------------------------------------------------------------------===// 803 804defm SCSrc : RegInlineOperand<"SReg", "SCSrc"> ; 805 806//===----------------------------------------------------------------------===// 807// VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate 808//===----------------------------------------------------------------------===// 809 810defm VSrc : RegImmOperand<"VS", "VSrc">; 811 812def VSrc_128 : RegisterOperand<VReg_128> { 813 let DecoderMethod = "DecodeVS_128RegisterClass"; 814} 815 816//===----------------------------------------------------------------------===// 817// VSrc_* Operands with an VGPR 818//===----------------------------------------------------------------------===// 819 820// This is for operands with the enum(9), VSrc encoding restriction, 821// but only allows VGPRs. 822def VRegSrc_32 : RegisterOperand<VGPR_32> { 823 //let ParserMatchClass = RegImmMatcher<"VRegSrc32">; 824 let DecoderMethod = "DecodeVS_32RegisterClass"; 825} 826 827//===----------------------------------------------------------------------===// 828// ASrc_* Operands with an AccVGPR 829//===----------------------------------------------------------------------===// 830 831def ARegSrc_32 : RegisterOperand<AGPR_32> { 832 let DecoderMethod = "DecodeAGPR_32RegisterClass"; 833 let EncoderMethod = "getAVOperandEncoding"; 834} 835 836//===----------------------------------------------------------------------===// 837// VCSrc_* Operands with an SGPR, VGPR or an inline constant 838//===----------------------------------------------------------------------===// 839 840defm VCSrc : RegInlineOperand<"VS", "VCSrc">; 841 842//===----------------------------------------------------------------------===// 843// VISrc_* Operands with a VGPR or an inline constant 844//===----------------------------------------------------------------------===// 845 846defm VISrc : RegInlineOperand32<"VGPR", "VISrc">; 847 848//===----------------------------------------------------------------------===// 849// AVSrc_* Operands with an AGPR or VGPR 850//===----------------------------------------------------------------------===// 851 852def AVSrc_32 : RegisterOperand<AV_32> { 853 let DecoderMethod = "DecodeAV_32RegisterClass"; 854 let EncoderMethod = "getAVOperandEncoding"; 855} 856 857def AVSrc_64 : RegisterOperand<AV_64> { 858 let DecoderMethod = "DecodeAV_64RegisterClass"; 859 let EncoderMethod = "getAVOperandEncoding"; 860} 861 862//===----------------------------------------------------------------------===// 863// ACSrc_* Operands with an AGPR or an inline constant 864//===----------------------------------------------------------------------===// 865 866defm AISrc : RegInlineOperandAC<"AGPR", "AISrc">; 867defm AISrc_128 : RegInlineOperandAC<"AReg", "AISrc_128", "_128">; 868defm AISrc_512 : RegInlineOperandAC<"AReg", "AISrc_512", "_512">; 869defm AISrc_1024 : RegInlineOperandAC<"AReg", "AISrc_1024", "_1024">; 870