1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// Interface definition for SIRegisterInfo 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H 15 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H 16 17 #define GET_REGINFO_HEADER 18 #include "AMDGPUGenRegisterInfo.inc" 19 20 #include "SIDefines.h" 21 22 namespace llvm { 23 24 class GCNSubtarget; 25 class LiveIntervals; 26 class LivePhysRegs; 27 class RegisterBank; 28 struct SGPRSpillBuilder; 29 30 class SIRegisterInfo final : public AMDGPUGenRegisterInfo { 31 private: 32 const GCNSubtarget &ST; 33 bool SpillSGPRToVGPR; 34 bool isWave32; 35 BitVector RegPressureIgnoredUnits; 36 37 /// Sub reg indexes for getRegSplitParts. 38 /// First index represents subreg size from 1 to 16 DWORDs. 39 /// The inner vector is sorted by bit offset. 40 /// Provided a register can be fully split with given subregs, 41 /// all elements of the inner vector combined give a full lane mask. 42 static std::array<std::vector<int16_t>, 16> RegSplitParts; 43 44 // Table representing sub reg of given width and offset. 45 // First index is subreg size: 32, 64, 96, 128, 160, 192, 224, 256, 512. 46 // Second index is 32 different dword offsets. 47 static std::array<std::array<uint16_t, 32>, 9> SubRegFromChannelTable; 48 49 void reserveRegisterTuples(BitVector &, MCRegister Reg) const; 50 51 public: 52 SIRegisterInfo(const GCNSubtarget &ST); 53 54 struct SpilledReg { 55 Register VGPR; 56 int Lane = -1; 57 58 SpilledReg() = default; 59 SpilledReg(Register R, int L) : VGPR(R), Lane(L) {} 60 61 bool hasLane() { return Lane != -1; } 62 bool hasReg() { return VGPR != 0; } 63 }; 64 65 /// \returns the sub reg enum value for the given \p Channel 66 /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0) 67 static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs = 1); 68 69 bool spillSGPRToVGPR() const { 70 return SpillSGPRToVGPR; 71 } 72 73 /// Return the end register initially reserved for the scratch buffer in case 74 /// spilling is needed. 75 MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const; 76 77 BitVector getReservedRegs(const MachineFunction &MF) const override; 78 bool isAsmClobberable(const MachineFunction &MF, 79 MCRegister PhysReg) const override; 80 81 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override; 82 const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const; 83 const uint32_t *getCallPreservedMask(const MachineFunction &MF, 84 CallingConv::ID) const override; 85 const uint32_t *getNoPreservedMask() const override; 86 87 // Stack access is very expensive. CSRs are also the high registers, and we 88 // want to minimize the number of used registers. 89 unsigned getCSRFirstUseCost() const override { 90 return 100; 91 } 92 93 const TargetRegisterClass * 94 getLargestLegalSuperClass(const TargetRegisterClass *RC, 95 const MachineFunction &MF) const override; 96 97 Register getFrameRegister(const MachineFunction &MF) const override; 98 99 bool hasBasePointer(const MachineFunction &MF) const; 100 Register getBaseRegister() const; 101 102 bool shouldRealignStack(const MachineFunction &MF) const override; 103 bool requiresRegisterScavenging(const MachineFunction &Fn) const override; 104 105 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override; 106 bool requiresFrameIndexReplacementScavenging( 107 const MachineFunction &MF) const override; 108 bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override; 109 110 int64_t getScratchInstrOffset(const MachineInstr *MI) const; 111 112 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 113 int Idx) const override; 114 115 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; 116 117 Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, 118 int64_t Offset) const override; 119 120 void resolveFrameIndex(MachineInstr &MI, Register BaseReg, 121 int64_t Offset) const override; 122 123 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, 124 int64_t Offset) const override; 125 126 const TargetRegisterClass *getPointerRegClass( 127 const MachineFunction &MF, unsigned Kind = 0) const override; 128 129 /// Returns a legal register class to copy a register in the specified class 130 /// to or from. If it is possible to copy the register directly without using 131 /// a cross register class copy, return the specified RC. Returns NULL if it 132 /// is not possible to copy between two registers of the specified class. 133 const TargetRegisterClass * 134 getCrossCopyRegClass(const TargetRegisterClass *RC) const override; 135 136 void buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, int Offset, 137 bool IsLoad, bool IsKill = true) const; 138 139 /// If \p OnlyToVGPR is true, this will only succeed if this 140 bool spillSGPR(MachineBasicBlock::iterator MI, 141 int FI, RegScavenger *RS, 142 LiveIntervals *LIS = nullptr, 143 bool OnlyToVGPR = false) const; 144 145 bool restoreSGPR(MachineBasicBlock::iterator MI, 146 int FI, RegScavenger *RS, 147 LiveIntervals *LIS = nullptr, 148 bool OnlyToVGPR = false) const; 149 150 bool spillEmergencySGPR(MachineBasicBlock::iterator MI, 151 MachineBasicBlock &RestoreMBB, Register SGPR, 152 RegScavenger *RS) const; 153 154 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, 155 unsigned FIOperandNum, 156 RegScavenger *RS) const override; 157 158 bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, 159 int FI, RegScavenger *RS, 160 LiveIntervals *LIS = nullptr) const; 161 162 StringRef getRegAsmName(MCRegister Reg) const override; 163 164 // Pseudo regs are not allowed 165 unsigned getHWRegIndex(MCRegister Reg) const { 166 return getEncodingValue(Reg) & 0xff; 167 } 168 169 LLVM_READONLY 170 const TargetRegisterClass *getVGPRClassForBitWidth(unsigned BitWidth) const; 171 172 LLVM_READONLY 173 const TargetRegisterClass *getAGPRClassForBitWidth(unsigned BitWidth) const; 174 175 LLVM_READONLY 176 const TargetRegisterClass * 177 getVectorSuperClassForBitWidth(unsigned BitWidth) const; 178 179 LLVM_READONLY 180 static const TargetRegisterClass *getSGPRClassForBitWidth(unsigned BitWidth); 181 182 /// Return the 'base' register class for this register. 183 /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc. 184 const TargetRegisterClass *getPhysRegClass(MCRegister Reg) const; 185 186 /// \returns true if this class contains only SGPR registers 187 static bool isSGPRClass(const TargetRegisterClass *RC) { 188 return hasSGPRs(RC) && !hasVGPRs(RC) && !hasAGPRs(RC); 189 } 190 191 /// \returns true if this class ID contains only SGPR registers 192 bool isSGPRClassID(unsigned RCID) const { 193 return isSGPRClass(getRegClass(RCID)); 194 } 195 196 bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const; 197 198 /// \returns true if this class contains only VGPR registers 199 static bool isVGPRClass(const TargetRegisterClass *RC) { 200 return hasVGPRs(RC) && !hasAGPRs(RC) && !hasSGPRs(RC); 201 } 202 203 /// \returns true if this class contains only AGPR registers 204 static bool isAGPRClass(const TargetRegisterClass *RC) { 205 return hasAGPRs(RC) && !hasVGPRs(RC) && !hasSGPRs(RC); 206 } 207 208 /// \returns true only if this class contains both VGPR and AGPR registers 209 bool isVectorSuperClass(const TargetRegisterClass *RC) const { 210 return hasVGPRs(RC) && hasAGPRs(RC) && !hasSGPRs(RC); 211 } 212 213 /// \returns true only if this class contains both VGPR and SGPR registers 214 bool isVSSuperClass(const TargetRegisterClass *RC) const { 215 return hasVGPRs(RC) && hasSGPRs(RC) && !hasAGPRs(RC); 216 } 217 218 /// \returns true if this class contains VGPR registers. 219 static bool hasVGPRs(const TargetRegisterClass *RC) { 220 return RC->TSFlags & SIRCFlags::HasVGPR; 221 } 222 223 /// \returns true if this class contains AGPR registers. 224 static bool hasAGPRs(const TargetRegisterClass *RC) { 225 return RC->TSFlags & SIRCFlags::HasAGPR; 226 } 227 228 /// \returns true if this class contains SGPR registers. 229 static bool hasSGPRs(const TargetRegisterClass *RC) { 230 return RC->TSFlags & SIRCFlags::HasSGPR; 231 } 232 233 /// \returns true if this class contains any vector registers. 234 static bool hasVectorRegisters(const TargetRegisterClass *RC) { 235 return hasVGPRs(RC) || hasAGPRs(RC); 236 } 237 238 /// \returns A VGPR reg class with the same width as \p SRC 239 const TargetRegisterClass * 240 getEquivalentVGPRClass(const TargetRegisterClass *SRC) const; 241 242 /// \returns An AGPR reg class with the same width as \p SRC 243 const TargetRegisterClass * 244 getEquivalentAGPRClass(const TargetRegisterClass *SRC) const; 245 246 /// \returns A SGPR reg class with the same width as \p SRC 247 const TargetRegisterClass * 248 getEquivalentSGPRClass(const TargetRegisterClass *VRC) const; 249 250 /// \returns The canonical register class that is used for a sub-register of 251 /// \p RC for the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC 252 /// will be returned. 253 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC, 254 unsigned SubIdx) const; 255 256 /// Returns a register class which is compatible with \p SuperRC, such that a 257 /// subregister exists with class \p SubRC with subregister index \p 258 /// SubIdx. If this is impossible (e.g., an unaligned subregister index within 259 /// a register tuple), return null. 260 const TargetRegisterClass * 261 getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, 262 const TargetRegisterClass *SubRC, 263 unsigned SubIdx) const; 264 265 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, 266 unsigned DefSubReg, 267 const TargetRegisterClass *SrcRC, 268 unsigned SrcSubReg) const override; 269 270 /// \returns True if operands defined with this operand type can accept 271 /// a literal constant (i.e. any 32-bit immediate). 272 bool opCanUseLiteralConstant(unsigned OpType) const; 273 274 /// \returns True if operands defined with this operand type can accept 275 /// an inline constant. i.e. An integer value in the range (-16, 64) or 276 /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f. 277 bool opCanUseInlineConstant(unsigned OpType) const; 278 279 MCRegister findUnusedRegister(const MachineRegisterInfo &MRI, 280 const TargetRegisterClass *RC, 281 const MachineFunction &MF, 282 bool ReserveHighestVGPR = false) const; 283 284 const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI, 285 Register Reg) const; 286 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const; 287 bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const; 288 bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const { 289 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); 290 } 291 292 bool isConstantPhysReg(MCRegister PhysReg) const override; 293 294 bool isDivergentRegClass(const TargetRegisterClass *RC) const override { 295 return !isSGPRClass(RC); 296 } 297 298 ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC, 299 unsigned EltSize) const; 300 301 bool shouldCoalesce(MachineInstr *MI, 302 const TargetRegisterClass *SrcRC, 303 unsigned SubReg, 304 const TargetRegisterClass *DstRC, 305 unsigned DstSubReg, 306 const TargetRegisterClass *NewRC, 307 LiveIntervals &LIS) const override; 308 309 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 310 MachineFunction &MF) const override; 311 312 unsigned getRegPressureSetLimit(const MachineFunction &MF, 313 unsigned Idx) const override; 314 315 const int *getRegUnitPressureSets(unsigned RegUnit) const override; 316 317 MCRegister getReturnAddressReg(const MachineFunction &MF) const; 318 319 const TargetRegisterClass * 320 getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank) const; 321 322 const TargetRegisterClass * 323 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const { 324 return getRegClassForSizeOnBank(Ty.getSizeInBits(), Bank); 325 } 326 327 const TargetRegisterClass * 328 getConstrainedRegClassForOperand(const MachineOperand &MO, 329 const MachineRegisterInfo &MRI) const override; 330 331 const TargetRegisterClass *getBoolRC() const { 332 return isWave32 ? &AMDGPU::SReg_32RegClass 333 : &AMDGPU::SReg_64RegClass; 334 } 335 336 const TargetRegisterClass *getWaveMaskRegClass() const { 337 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass 338 : &AMDGPU::SReg_64_XEXECRegClass; 339 } 340 341 // Return the appropriate register class to use for 64-bit VGPRs for the 342 // subtarget. 343 const TargetRegisterClass *getVGPR64Class() const; 344 345 MCRegister getVCC() const; 346 347 MCRegister getExec() const; 348 349 const TargetRegisterClass *getRegClass(unsigned RCID) const; 350 351 // Find reaching register definition 352 MachineInstr *findReachingDef(Register Reg, unsigned SubReg, 353 MachineInstr &Use, 354 MachineRegisterInfo &MRI, 355 LiveIntervals *LIS) const; 356 357 const uint32_t *getAllVGPRRegMask() const; 358 const uint32_t *getAllAGPRRegMask() const; 359 const uint32_t *getAllVectorRegMask() const; 360 const uint32_t *getAllAllocatableSRegMask() const; 361 362 // \returns number of 32 bit registers covered by a \p LM 363 static unsigned getNumCoveredRegs(LaneBitmask LM) { 364 // The assumption is that every lo16 subreg is an even bit and every hi16 365 // is an adjacent odd bit or vice versa. 366 uint64_t Mask = LM.getAsInteger(); 367 uint64_t Even = Mask & 0xAAAAAAAAAAAAAAAAULL; 368 Mask = (Even >> 1) | Mask; 369 uint64_t Odd = Mask & 0x5555555555555555ULL; 370 return countPopulation(Odd); 371 } 372 373 // \returns a DWORD offset of a \p SubReg 374 unsigned getChannelFromSubReg(unsigned SubReg) const { 375 return SubReg ? (getSubRegIdxOffset(SubReg) + 31) / 32 : 0; 376 } 377 378 // \returns a DWORD size of a \p SubReg 379 unsigned getNumChannelsFromSubReg(unsigned SubReg) const { 380 return getNumCoveredRegs(getSubRegIndexLaneMask(SubReg)); 381 } 382 383 // For a given 16 bit \p Reg \returns a 32 bit register holding it. 384 // \returns \p Reg otherwise. 385 MCPhysReg get32BitRegister(MCPhysReg Reg) const; 386 387 // Returns true if a given register class is properly aligned for 388 // the subtarget. 389 bool isProperlyAlignedRC(const TargetRegisterClass &RC) const; 390 391 // Given \p RC returns corresponding aligned register class if required 392 // by the subtarget. 393 const TargetRegisterClass * 394 getProperlyAlignedRC(const TargetRegisterClass *RC) const; 395 396 /// Return all SGPR128 which satisfy the waves per execution unit requirement 397 /// of the subtarget. 398 ArrayRef<MCPhysReg> getAllSGPR128(const MachineFunction &MF) const; 399 400 /// Return all SGPR64 which satisfy the waves per execution unit requirement 401 /// of the subtarget. 402 ArrayRef<MCPhysReg> getAllSGPR64(const MachineFunction &MF) const; 403 404 /// Return all SGPR32 which satisfy the waves per execution unit requirement 405 /// of the subtarget. 406 ArrayRef<MCPhysReg> getAllSGPR32(const MachineFunction &MF) const; 407 408 // Insert spill or restore instructions. 409 // When lowering spill pseudos, the RegScavenger should be set. 410 // For creating spill instructions during frame lowering, where no scavenger 411 // is available, LiveRegs can be used. 412 void buildSpillLoadStore(MachineBasicBlock &MBB, 413 MachineBasicBlock::iterator MI, const DebugLoc &DL, 414 unsigned LoadStoreOp, int Index, Register ValueReg, 415 bool ValueIsKill, MCRegister ScratchOffsetReg, 416 int64_t InstrOffset, MachineMemOperand *MMO, 417 RegScavenger *RS, 418 LivePhysRegs *LiveRegs = nullptr) const; 419 }; 420 421 } // End namespace llvm 422 423 #endif 424